mbed official
mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
Diff: targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h
- Revision:
- 187:0387e8f68319
- Parent:
- 165:e614a9f1c9e2
--- a/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h Fri Jun 22 16:45:37 2018 +0100
+++ b/targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h Thu Sep 06 13:40:20 2018 +0100
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f1xx_hal_eth.h
* @author MCD Application Team
- * @version V1.1.0
- * @date 14-April-2017
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -33,14 +31,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F1xx_HAL_ETH_H
#define __STM32F1xx_HAL_ETH_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -49,12 +47,12 @@
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
-#if defined (STM32F107xC)
+#if defined (STM32F107xC)
/** @addtogroup ETH
* @{
- */
-
+ */
+
/** @addtogroup ETH_Private_Macros
* @{
*/
@@ -266,7 +264,7 @@
((BUFFER) == ETH_DMARXDESC_BUFFER2))
#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
((FLAG) == ETH_PMT_FLAG_MPR))
-#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
+#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U))
#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
@@ -355,18 +353,18 @@
/* ETHERNET Missed frames counter Shift */
#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U
- /**
- * @}
- */
+/**
+ * @}
+ */
-/* Exported types ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
/** @defgroup ETH_Exported_Types ETH Exported Types
* @{
*/
-/**
- * @brief HAL State structures definition
- */
+/**
+ * @brief HAL State structures definition
+ */
typedef enum
{
HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
@@ -379,10 +377,10 @@
HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */
HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
-}HAL_ETH_StateTypeDef;
+} HAL_ETH_StateTypeDef;
-/**
- * @brief ETH Init Structure definition
+/**
+ * @brief ETH Init Structure definition
*/
typedef struct
@@ -397,34 +395,34 @@
uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
This parameter can be a value of @ref ETH_Duplex_Mode */
-
+
uint16_t PhyAddress; /*!< Ethernet PHY address.
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
-
+
uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
-
+
uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
This parameter can be a value of @ref ETH_Rx_Mode */
-
- uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
+
+ uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
This parameter can be a value of @ref ETH_Checksum_Mode */
-
- uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
+
+ uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface.
This parameter can be a value of @ref ETH_Media_Interface */
} ETH_InitTypeDef;
- /**
- * @brief ETH MAC Configuration Structure definition
- */
+/**
+ * @brief ETH MAC Configuration Structure definition
+ */
typedef struct
{
uint32_t Watchdog; /*!< Selects or not the Watchdog timer
When enabled, the MAC allows no more then 2048 bytes to be received.
When disabled, the MAC can receive up to 16384 bytes.
- This parameter can be a value of @ref ETH_Watchdog */
+ This parameter can be a value of @ref ETH_Watchdog */
uint32_t Jabber; /*!< Selects or not Jabber timer
When enabled, the MAC allows no more then 2048 bytes to be sent.
@@ -432,7 +430,7 @@
This parameter can be a value of @ref ETH_Jabber */
uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
- This parameter can be a value of @ref ETH_Inter_Frame_Gap */
+ This parameter can be a value of @ref ETH_Inter_Frame_Gap */
uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
This parameter can be a value of @ref ETH_Carrier_Sense */
@@ -440,62 +438,62 @@
uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
in Half-Duplex mode.
- This parameter can be a value of @ref ETH_Receive_Own */
+ This parameter can be a value of @ref ETH_Receive_Own */
uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
- This parameter can be a value of @ref ETH_Loop_Back_Mode */
+ This parameter can be a value of @ref ETH_Loop_Back_Mode */
uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
- This parameter can be a value of @ref ETH_Checksum_Offload */
+ This parameter can be a value of @ref ETH_Checksum_Offload */
uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
when a collision occurs (Half-Duplex mode).
This parameter can be a value of @ref ETH_Retry_Transmission */
uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
- This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
+ This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
This parameter can be a value of @ref ETH_Back_Off_Limit */
uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
- This parameter can be a value of @ref ETH_Deferral_Check */
+ This parameter can be a value of @ref ETH_Deferral_Check */
uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
- This parameter can be a value of @ref ETH_Receive_All */
+ This parameter can be a value of @ref ETH_Receive_All */
uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
This parameter can be a value of @ref ETH_Source_Addr_Filter */
uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
- This parameter can be a value of @ref ETH_Pass_Control_Frames */
+ This parameter can be a value of @ref ETH_Pass_Control_Frames */
uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
- This parameter can be a value of @ref ETH_Destination_Addr_Filter */
+ This parameter can be a value of @ref ETH_Destination_Addr_Filter */
uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
This parameter can be a value of @ref ETH_Promiscuous_Mode */
uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
+ This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
- This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
+ This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
- This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
+ This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */
- uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
+ uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */
uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
- This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
+ This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
automatic retransmission of PAUSE Frame.
@@ -503,7 +501,7 @@
uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
unicast address and unique multicast address).
- This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
+ This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
disable its transmitter for a specified time (Pause Time)
@@ -511,33 +509,33 @@
uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
or the MAC back-pressure operation (Half-Duplex mode)
- This parameter can be a value of @ref ETH_Transmit_Flow_Control */
+ This parameter can be a value of @ref ETH_Transmit_Flow_Control */
uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
comparison and filtering.
- This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
+ This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
} ETH_MACInitTypeDef;
-/**
- * @brief ETH DMA Configuration Structure definition
+/**
+ * @brief ETH DMA Configuration Structure definition
*/
typedef struct
{
- uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
- This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
+ uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
+ This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
- This parameter can be a value of @ref ETH_Receive_Store_Forward */
+ This parameter can be a value of @ref ETH_Receive_Store_Forward */
uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
- This parameter can be a value of @ref ETH_Flush_Received_Frame */
+ This parameter can be a value of @ref ETH_Flush_Received_Frame */
uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
- This parameter can be a value of @ref ETH_Transmit_Store_Forward */
+ This parameter can be a value of @ref ETH_Transmit_Store_Forward */
uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
@@ -563,7 +561,7 @@
This parameter can be a value of @ref ETH_Fixed_Burst */
uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
- This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
+ This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
@@ -572,70 +570,70 @@
This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
- This parameter can be a value of @ref ETH_DMA_Arbitration */
+ This parameter can be a value of @ref ETH_DMA_Arbitration */
} ETH_DMAInitTypeDef;
-/**
+/**
* @brief ETH DMA Descriptors data structure definition
- */
+ */
-typedef struct
+typedef struct
{
__IO uint32_t Status; /*!< Status */
-
+
uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
-
+
uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
-
+
uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
} ETH_DMADescTypeDef;
-/**
+/**
* @brief Received Frame Informations structure definition
- */
-typedef struct
+ */
+typedef struct
{
ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
-
+
ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
-
+
uint32_t SegCount; /*!< Segment count */
-
+
uint32_t length; /*!< Frame length */
-
+
uint32_t buffer; /*!< Frame buffer */
} ETH_DMARxFrameInfos;
-/**
- * @brief ETH Handle Structure definition
+/**
+ * @brief ETH Handle Structure definition
*/
-
+
typedef struct
{
ETH_TypeDef *Instance; /*!< Register base address */
-
+
ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
-
+
uint32_t LinkStatus; /*!< Ethernet link status */
-
+
ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
-
+
ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
-
+
ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
-
+
__IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
-
+
HAL_LockTypeDef Lock; /*!< ETH Lock */
} ETH_HandleTypeDef;
- /**
- * @}
- */
+/**
+ * @}
+ */
/* Exported constants --------------------------------------------------------*/
/** @defgroup ETH_Exported_Constants ETH Exported Constants
@@ -644,72 +642,72 @@
/** @defgroup ETH_Buffers_setting ETH Buffers setting
* @{
- */
+ */
#define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define ETH_CRC 4U /*!< Ethernet CRC */
-#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
+#define ETH_EXTRA 2U /*!< Extra bytes in some cases */
#define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */
#define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */
#define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */
-#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */
- /* Ethernet driver receive buffers are organized in a chained linked-list, when
- an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
- to the driver receive buffers memory.
+/* Ethernet driver receive buffers are organized in a chained linked-list, when
+ an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
+ to the driver receive buffers memory.
- Depending on the size of the received ethernet packet and the size of
- each ethernet driver receive buffer, the received packet can take one or more
- ethernet driver receive buffer.
+ Depending on the size of the received ethernet packet and the size of
+ each ethernet driver receive buffer, the received packet can take one or more
+ ethernet driver receive buffer.
- In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
- and the total count of the driver receive buffers ETH_RXBUFNB.
+ In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
+ and the total count of the driver receive buffers ETH_RXBUFNB.
- The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
+ The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
packet */
#ifndef ETH_RX_BUF_SIZE
- #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
#endif
-/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
+/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
#ifndef ETH_RXBUFNB
- #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
#endif
- /* Ethernet driver transmit buffers are organized in a chained linked-list, when
- an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
- driver transmit buffers memory to the TxFIFO.
+/* Ethernet driver transmit buffers are organized in a chained linked-list, when
+ an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
+ driver transmit buffers memory to the TxFIFO.
- Depending on the size of the Ethernet packet to be transmitted and the size of
- each ethernet driver transmit buffer, the packet to be transmitted can take
- one or more ethernet driver transmit buffer.
+ Depending on the size of the Ethernet packet to be transmitted and the size of
+ each ethernet driver transmit buffer, the packet to be transmitted can take
+ one or more ethernet driver transmit buffer.
- In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
- and the total count of the driver transmit buffers ETH_TXBUFNB.
+ In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
+ and the total count of the driver transmit buffers ETH_TXBUFNB.
- The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
- example, they can be reconfigured in the application layer to fit the application
- needs */
+ The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
+ example, they can be reconfigured in the application layer to fit the application
+ needs */
/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
packet */
-#ifndef ETH_TX_BUF_SIZE
- #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
+#ifndef ETH_TX_BUF_SIZE
+#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
#endif
-/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
+/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
#ifndef ETH_TXBUFNB
- #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
+#define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
#endif
- /**
- * @}
- */
+/**
+ * @}
+ */
/** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
* @{
@@ -728,9 +726,9 @@
-----------------------------------------------------------------------------------------------
*/
-/**
+/**
* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
- */
+ */
#define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
#define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */
#define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */
@@ -739,10 +737,10 @@
#define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */
#define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */
#define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */
-#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
-#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
-#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
+#define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */
+#define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
+#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
#define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */
#define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */
#define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */
@@ -761,25 +759,25 @@
#define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */
#define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */
-/**
+/**
* @brief Bit definition of TDES1 register
- */
+ */
#define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */
#define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */
-/**
+/**
* @brief Bit definition of TDES2 register
- */
+ */
#define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-/**
+/**
* @brief Bit definition of TDES3 register
- */
+ */
#define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
- */
+ */
/** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
* @{
*/
@@ -797,9 +795,9 @@
---------------------------------------------------------------------------------------------------------------------
*/
-/**
+/**
* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
- */
+ */
#define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */
#define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */
#define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */
@@ -810,8 +808,8 @@
#define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */
#define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */
#define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */
-#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
-#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
+#define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */
+#define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
#define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */
#define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */
#define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
@@ -820,40 +818,40 @@
#define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */
#define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
-/**
+/**
* @brief Bit definition of RDES1 register
- */
+ */
#define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */
#define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */
#define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */
#define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */
#define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */
-/**
- * @brief Bit definition of RDES2 register
- */
+/**
+ * @brief Bit definition of RDES2 register
+ */
#define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */
-/**
- * @brief Bit definition of RDES3 register
- */
+/**
+ * @brief Bit definition of RDES3 register
+ */
#define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */
/**
* @}
*/
- /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
- * @{
- */
+/** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
+ * @{
+ */
#define ETH_AUTONEGOTIATION_ENABLE 0x00000001U
#define ETH_AUTONEGOTIATION_DISABLE 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Speed ETH Speed
+/** @defgroup ETH_Speed ETH Speed
* @{
- */
+ */
#define ETH_SPEED_10M 0x00000000U
#define ETH_SPEED_100M 0x00004000U
@@ -862,7 +860,7 @@
*/
/** @defgroup ETH_Duplex_Mode ETH Duplex Mode
* @{
- */
+ */
#define ETH_MODE_FULLDUPLEX 0x00000800U
#define ETH_MODE_HALFDUPLEX 0x00000000U
/**
@@ -870,7 +868,7 @@
*/
/** @defgroup ETH_Rx_Mode ETH Rx Mode
* @{
- */
+ */
#define ETH_RXPOLLING_MODE 0x00000000U
#define ETH_RXINTERRUPT_MODE 0x00000001U
/**
@@ -879,7 +877,7 @@
/** @defgroup ETH_Checksum_Mode ETH Checksum Mode
* @{
- */
+ */
#define ETH_CHECKSUM_BY_HARDWARE 0x00000000U
#define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U
/**
@@ -888,7 +886,7 @@
/** @defgroup ETH_Media_Interface ETH Media Interface
* @{
- */
+ */
#define ETH_MEDIA_INTERFACE_MII 0x00000000U
#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
@@ -898,7 +896,7 @@
/** @defgroup ETH_Watchdog ETH Watchdog
* @{
- */
+ */
#define ETH_WATCHDOG_ENABLE 0x00000000U
#define ETH_WATCHDOG_DISABLE 0x00800000U
/**
@@ -907,16 +905,16 @@
/** @defgroup ETH_Jabber ETH Jabber
* @{
- */
+ */
#define ETH_JABBER_ENABLE 0x00000000U
#define ETH_JABBER_DISABLE 0x00400000U
/**
* @}
*/
-/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
+/** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
* @{
- */
+ */
#define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */
#define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */
#define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */
@@ -931,25 +929,25 @@
/** @defgroup ETH_Carrier_Sense ETH Carrier Sense
* @{
- */
+ */
#define ETH_CARRIERSENCE_ENABLE 0x00000000U
#define ETH_CARRIERSENCE_DISABLE 0x00010000U
/**
* @}
*/
-/** @defgroup ETH_Receive_Own ETH Receive Own
+/** @defgroup ETH_Receive_Own ETH Receive Own
* @{
- */
+ */
#define ETH_RECEIVEOWN_ENABLE 0x00000000U
#define ETH_RECEIVEOWN_DISABLE 0x00002000U
/**
* @}
*/
-/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
+/** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
* @{
- */
+ */
#define ETH_LOOPBACKMODE_ENABLE 0x00001000U
#define ETH_LOOPBACKMODE_DISABLE 0x00000000U
/**
@@ -958,7 +956,7 @@
/** @defgroup ETH_Checksum_Offload ETH Checksum Offload
* @{
- */
+ */
#define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U
#define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U
/**
@@ -967,7 +965,7 @@
/** @defgroup ETH_Retry_Transmission ETH Retry Transmission
* @{
- */
+ */
#define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U
#define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U
/**
@@ -976,7 +974,7 @@
/** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
* @{
- */
+ */
#define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U
#define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U
/**
@@ -985,7 +983,7 @@
/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
* @{
- */
+ */
#define ETH_BACKOFFLIMIT_10 0x00000000U
#define ETH_BACKOFFLIMIT_8 0x00000020U
#define ETH_BACKOFFLIMIT_4 0x00000040U
@@ -1005,7 +1003,7 @@
/** @defgroup ETH_Receive_All ETH Receive All
* @{
- */
+ */
#define ETH_RECEIVEALL_ENABLE 0x80000000U
#define ETH_RECEIVEAll_DISABLE 0x00000000U
/**
@@ -1014,7 +1012,7 @@
/** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
* @{
- */
+ */
#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U
#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U
#define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U
@@ -1024,17 +1022,17 @@
/** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
* @{
- */
+ */
#define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */
#define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */
-#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
+#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */
/**
* @}
*/
/** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
* @{
- */
+ */
#define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U
#define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U
/**
@@ -1043,7 +1041,7 @@
/** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
* @{
- */
+ */
#define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U
#define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U
/**
@@ -1052,7 +1050,7 @@
/** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
* @{
- */
+ */
#define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U
#define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U
/**
@@ -1061,7 +1059,7 @@
/** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
* @{
- */
+ */
#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U
#define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U
#define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U
@@ -1072,7 +1070,7 @@
/** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
* @{
- */
+ */
#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U
#define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U
#define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U
@@ -1080,9 +1078,9 @@
* @}
*/
-/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
+/** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
* @{
- */
+ */
#define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U
#define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U
/**
@@ -1091,7 +1089,7 @@
/** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
* @{
- */
+ */
#define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */
#define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */
@@ -1102,7 +1100,7 @@
/** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
* @{
- */
+ */
#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U
#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U
/**
@@ -1111,7 +1109,7 @@
/** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
* @{
- */
+ */
#define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U
#define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U
/**
@@ -1120,7 +1118,7 @@
/** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
* @{
- */
+ */
#define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U
#define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U
/**
@@ -1129,7 +1127,7 @@
/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
* @{
- */
+ */
#define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U
#define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U
/**
@@ -1138,7 +1136,7 @@
/** @defgroup ETH_MAC_addresses ETH MAC addresses
* @{
- */
+ */
#define ETH_MAC_ADDRESS0 0x00000000U
#define ETH_MAC_ADDRESS1 0x00000008U
#define ETH_MAC_ADDRESS2 0x00000010U
@@ -1147,9 +1145,9 @@
* @}
*/
-/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
+/** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
* @{
- */
+ */
#define ETH_MAC_ADDRESSFILTER_SA 0x00000000U
#define ETH_MAC_ADDRESSFILTER_DA 0x00000008U
/**
@@ -1158,7 +1156,7 @@
/** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
* @{
- */
+ */
#define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */
#define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */
#define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */
@@ -1171,7 +1169,7 @@
/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
* @{
- */
+ */
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U
#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U
/**
@@ -1180,7 +1178,7 @@
/** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
* @{
- */
+ */
#define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U
#define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U
/**
@@ -1189,7 +1187,7 @@
/** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
* @{
- */
+ */
#define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U
#define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U
/**
@@ -1198,7 +1196,7 @@
/** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
* @{
- */
+ */
#define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U
#define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U
/**
@@ -1207,7 +1205,7 @@
/** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
* @{
- */
+ */
#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
@@ -1222,7 +1220,7 @@
/** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
* @{
- */
+ */
#define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U
#define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U
/**
@@ -1231,7 +1229,7 @@
/** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
* @{
- */
+ */
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U
#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U
/**
@@ -1240,7 +1238,7 @@
/** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
* @{
- */
+ */
#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
@@ -1251,16 +1249,16 @@
/** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
* @{
- */
+ */
#define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U
#define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U
/**
* @}
*/
-/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
+/** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
* @{
- */
+ */
#define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U
#define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U
/**
@@ -1269,7 +1267,7 @@
/** @defgroup ETH_Fixed_Burst ETH Fixed Burst
* @{
- */
+ */
#define ETH_FIXEDBURST_ENABLE 0x00010000U
#define ETH_FIXEDBURST_DISABLE 0x00000000U
/**
@@ -1278,7 +1276,7 @@
/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
* @{
- */
+ */
#define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
@@ -1297,7 +1295,7 @@
/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
* @{
- */
+ */
#define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
@@ -1317,7 +1315,7 @@
/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
* @{
- */
+ */
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U
#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U
@@ -1329,7 +1327,7 @@
/** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
* @{
- */
+ */
#define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */
#define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */
/**
@@ -1338,7 +1336,7 @@
/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
* @{
- */
+ */
#define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */
#define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */
#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
@@ -1347,9 +1345,9 @@
* @}
*/
-/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
+/** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
* @{
- */
+ */
#define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */
#define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */
/**
@@ -1358,7 +1356,7 @@
/** @defgroup ETH_PMT_Flags ETH PMT Flags
* @{
- */
+ */
#define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */
#define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */
#define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */
@@ -1368,7 +1366,7 @@
/** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
* @{
- */
+ */
#define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */
#define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */
#define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */
@@ -1388,7 +1386,7 @@
/** @defgroup ETH_MAC_Flags ETH MAC Flags
* @{
- */
+ */
#define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */
#define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */
#define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */
@@ -1400,7 +1398,7 @@
/** @defgroup ETH_DMA_Flags ETH DMA Flags
* @{
- */
+ */
#define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
#define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
@@ -1426,9 +1424,9 @@
* @}
*/
-/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
* @{
- */
+ */
#define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */
#define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */
#define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */
@@ -1438,9 +1436,9 @@
* @}
*/
-/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
* @{
- */
+ */
#define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */
#define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */
#define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */
@@ -1463,9 +1461,9 @@
* @}
*/
-/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
+/** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
* @{
- */
+ */
#define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */
#define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */
#define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */
@@ -1475,12 +1473,12 @@
/**
* @}
- */
+ */
-/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
+/** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
* @{
- */
+ */
#define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */
#define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */
#define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */
@@ -1494,16 +1492,16 @@
/** @defgroup ETH_DMA_overflow ETH DMA overflow
* @{
- */
+ */
#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */
#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */
/**
* @}
- */
+ */
/** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
* @{
- */
+ */
#define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */
/**
@@ -1519,14 +1517,14 @@
* @brief macros to handle interrupts and specific clock configurations
* @{
*/
-
+
/** @brief Reset ETH handle state
* @param __HANDLE__: specifies the ETH handle.
* @retval None
*/
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
-/**
+/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
* @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag of TDES0 to check.
@@ -1565,7 +1563,7 @@
/**
* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @retval The Transmit descriptor collision counter value.
*/
#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
@@ -1579,21 +1577,21 @@
/**
* @brief Enables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
/**
* @brief Disables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
/**
* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
* This parameter can be one of the following values:
* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
@@ -1606,40 +1604,40 @@
/**
* @brief Enables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
/**
* @brief Disables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
/**
* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
/**
* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__: ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
-/**
+/**
* @brief Enables the specified ETHERNET MAC interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
- * @arg ETH_MAC_IT_PMT : PMT interrupt
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_PMT : PMT interrupt
* @retval None
*/
#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
@@ -1650,7 +1648,7 @@
* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
- * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
+ * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
* @arg ETH_MAC_IT_PMT : PMT interrupt
* @retval None
*/
@@ -1689,16 +1687,16 @@
* @param __HANDLE__: ETH Handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
- * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
- * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
- * @arg ETH_MAC_FLAG_MMC : MMC flag
- * @arg ETH_MAC_FLAG_PMT : PMT flag
+ * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
+ * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
+ * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
+ * @arg ETH_MAC_FLAG_MMC : MMC flag
+ * @arg ETH_MAC_FLAG_PMT : PMT flag
* @retval The state of ETHERNET MAC flag.
*/
#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
-/**
+/**
* @brief Enables the specified ETHERNET DMA interrupts.
* @param __HANDLE__ : ETH Handle
* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
@@ -1754,12 +1752,12 @@
/**
* @brief Set the DMA Receive status watchdog timer register value
* @param __HANDLE__: ETH Handle
- * @param __VALUE__: DMA Receive status watchdog timer register value
+ * @param __VALUE__: DMA Receive status watchdog timer register value
* @retval None
*/
#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
-/**
+/**
* @brief Enables any unicast packet filtered by the MAC address
* recognition to be a wake-up frame.
* @param __HANDLE__: ETH Handle.
@@ -1822,14 +1820,14 @@
* @param __HANDLE__: ETH Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
- * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
- * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
+ * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
+ * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
* @retval The new state of ETHERNET PMT Flag (SET or RESET).
*/
#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
-/**
+/**
* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
* @param __HANDLE__: ETH Handle.
* @retval None
@@ -1897,9 +1895,9 @@
* @brief Enables the specified ETHERNET MMC Rx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
@@ -1908,9 +1906,9 @@
* @brief Disables the specified ETHERNET MMC Rx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
- * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
+ * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
* @retval None
*/
@@ -1919,10 +1917,10 @@
* @brief Enables the specified ETHERNET MMC Tx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
* @retval None
*/
#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
@@ -1931,10 +1929,10 @@
* @brief Disables the specified ETHERNET MMC Tx interrupts.
* @param __HANDLE__: ETH Handle.
* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
- * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
+ * This parameter can be one of the following values:
+ * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
+ * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
* @retval None
*/
#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
@@ -2039,7 +2037,7 @@
HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
-HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
+HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount);
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
/**
@@ -2078,7 +2076,7 @@
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
/**
* @}
- */
+ */
/* Peripheral State functions ************************************************/
@@ -2102,7 +2100,7 @@
/**
* @}
*/
-
+
#ifdef __cplusplus
}
#endif
