mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ramfunc.c@189:f392fc9709a3, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 22:31:08 2019 +0000
- Revision:
- 189:f392fc9709a3
- Parent:
- 184:08ed48f1de7f
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /** |
<> | 149:156823d33999 | 2 | ****************************************************************************** |
<> | 149:156823d33999 | 3 | * @file stm32l1xx_hal_flash_ramfunc.c |
<> | 149:156823d33999 | 4 | * @author MCD Application Team |
<> | 149:156823d33999 | 5 | * @brief FLASH RAMFUNC driver. |
<> | 149:156823d33999 | 6 | * This file provides a Flash firmware functions which should be |
<> | 149:156823d33999 | 7 | * executed from internal SRAM |
<> | 149:156823d33999 | 8 | * |
<> | 149:156823d33999 | 9 | * @verbatim |
<> | 149:156823d33999 | 10 | |
<> | 149:156823d33999 | 11 | *** ARM Compiler *** |
<> | 149:156823d33999 | 12 | -------------------- |
<> | 149:156823d33999 | 13 | [..] RAM functions are defined using the toolchain options. |
<> | 149:156823d33999 | 14 | Functions that are be executed in RAM should reside in a separate |
<> | 149:156823d33999 | 15 | source module. Using the 'Options for File' dialog you can simply change |
<> | 149:156823d33999 | 16 | the 'Code / Const' area of a module to a memory space in physical RAM. |
<> | 149:156823d33999 | 17 | Available memory areas are declared in the 'Target' tab of the |
<> | 149:156823d33999 | 18 | Options for Target' dialog. |
<> | 149:156823d33999 | 19 | |
<> | 149:156823d33999 | 20 | *** ICCARM Compiler *** |
<> | 149:156823d33999 | 21 | ----------------------- |
<> | 149:156823d33999 | 22 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc". |
<> | 149:156823d33999 | 23 | |
<> | 149:156823d33999 | 24 | *** GNU Compiler *** |
<> | 149:156823d33999 | 25 | -------------------- |
<> | 149:156823d33999 | 26 | [..] RAM functions are defined using a specific toolchain attribute |
<> | 149:156823d33999 | 27 | "__attribute__((section(".RamFunc")))". |
<> | 149:156823d33999 | 28 | |
<> | 149:156823d33999 | 29 | @endverbatim |
<> | 149:156823d33999 | 30 | ****************************************************************************** |
<> | 149:156823d33999 | 31 | * @attention |
<> | 149:156823d33999 | 32 | * |
AnnaBridge | 184:08ed48f1de7f | 33 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 149:156823d33999 | 34 | * |
<> | 149:156823d33999 | 35 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 149:156823d33999 | 36 | * are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 37 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 149:156823d33999 | 38 | * this list of conditions and the following disclaimer. |
<> | 149:156823d33999 | 39 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 149:156823d33999 | 40 | * this list of conditions and the following disclaimer in the documentation |
<> | 149:156823d33999 | 41 | * and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 42 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 149:156823d33999 | 43 | * may be used to endorse or promote products derived from this software |
<> | 149:156823d33999 | 44 | * without specific prior written permission. |
<> | 149:156823d33999 | 45 | * |
<> | 149:156823d33999 | 46 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 149:156823d33999 | 47 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 149:156823d33999 | 48 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 149:156823d33999 | 49 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 149:156823d33999 | 50 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 149:156823d33999 | 51 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 149:156823d33999 | 52 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 149:156823d33999 | 53 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 149:156823d33999 | 54 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 149:156823d33999 | 55 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 56 | * |
<> | 149:156823d33999 | 57 | ****************************************************************************** |
<> | 149:156823d33999 | 58 | */ |
<> | 149:156823d33999 | 59 | |
<> | 149:156823d33999 | 60 | /* Includes ------------------------------------------------------------------*/ |
<> | 149:156823d33999 | 61 | #include "stm32l1xx_hal.h" |
<> | 149:156823d33999 | 62 | |
<> | 149:156823d33999 | 63 | /** @addtogroup STM32L1xx_HAL_Driver |
<> | 149:156823d33999 | 64 | * @{ |
<> | 149:156823d33999 | 65 | */ |
<> | 149:156823d33999 | 66 | |
<> | 149:156823d33999 | 67 | #ifdef HAL_FLASH_MODULE_ENABLED |
<> | 149:156823d33999 | 68 | |
<> | 149:156823d33999 | 69 | /** @addtogroup FLASH |
<> | 149:156823d33999 | 70 | * @{ |
<> | 149:156823d33999 | 71 | */ |
<> | 149:156823d33999 | 72 | /** @addtogroup FLASH_Private_Variables |
<> | 149:156823d33999 | 73 | * @{ |
<> | 149:156823d33999 | 74 | */ |
<> | 149:156823d33999 | 75 | extern FLASH_ProcessTypeDef pFlash; |
<> | 149:156823d33999 | 76 | /** |
<> | 149:156823d33999 | 77 | * @} |
<> | 149:156823d33999 | 78 | */ |
<> | 149:156823d33999 | 79 | |
<> | 149:156823d33999 | 80 | /** |
<> | 149:156823d33999 | 81 | * @} |
<> | 149:156823d33999 | 82 | */ |
<> | 149:156823d33999 | 83 | |
<> | 149:156823d33999 | 84 | /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC |
<> | 149:156823d33999 | 85 | * @brief FLASH functions executed from RAM |
<> | 149:156823d33999 | 86 | * @{ |
<> | 149:156823d33999 | 87 | */ |
<> | 149:156823d33999 | 88 | |
<> | 149:156823d33999 | 89 | |
<> | 149:156823d33999 | 90 | /* Private typedef -----------------------------------------------------------*/ |
<> | 149:156823d33999 | 91 | /* Private define ------------------------------------------------------------*/ |
<> | 149:156823d33999 | 92 | /* Private macro -------------------------------------------------------------*/ |
<> | 149:156823d33999 | 93 | /* Private variables ---------------------------------------------------------*/ |
<> | 149:156823d33999 | 94 | /* Private function prototypes -----------------------------------------------*/ |
<> | 149:156823d33999 | 95 | /** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions |
<> | 149:156823d33999 | 96 | * @{ |
<> | 149:156823d33999 | 97 | */ |
<> | 149:156823d33999 | 98 | |
<> | 149:156823d33999 | 99 | static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); |
<> | 149:156823d33999 | 100 | static __RAM_FUNC FLASHRAM_SetErrorCode(void); |
<> | 149:156823d33999 | 101 | |
<> | 149:156823d33999 | 102 | /** |
<> | 149:156823d33999 | 103 | * @} |
<> | 149:156823d33999 | 104 | */ |
<> | 149:156823d33999 | 105 | |
<> | 149:156823d33999 | 106 | /* Private functions ---------------------------------------------------------*/ |
<> | 149:156823d33999 | 107 | |
<> | 149:156823d33999 | 108 | /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions |
<> | 149:156823d33999 | 109 | * |
<> | 149:156823d33999 | 110 | @verbatim |
<> | 149:156823d33999 | 111 | =============================================================================== |
<> | 149:156823d33999 | 112 | ##### ramfunc functions ##### |
<> | 149:156823d33999 | 113 | =============================================================================== |
<> | 149:156823d33999 | 114 | [..] |
<> | 149:156823d33999 | 115 | This subsection provides a set of functions that should be executed from RAM |
<> | 149:156823d33999 | 116 | transfers. |
<> | 149:156823d33999 | 117 | |
<> | 149:156823d33999 | 118 | @endverbatim |
<> | 149:156823d33999 | 119 | * @{ |
<> | 149:156823d33999 | 120 | */ |
<> | 149:156823d33999 | 121 | |
<> | 149:156823d33999 | 122 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions |
<> | 149:156823d33999 | 123 | * @{ |
<> | 149:156823d33999 | 124 | */ |
<> | 149:156823d33999 | 125 | |
<> | 149:156823d33999 | 126 | /** |
<> | 149:156823d33999 | 127 | * @brief Enable the power down mode during RUN mode. |
<> | 149:156823d33999 | 128 | * @note This function can be used only when the user code is running from Internal SRAM. |
<> | 149:156823d33999 | 129 | * @retval HAL status |
<> | 149:156823d33999 | 130 | */ |
<> | 149:156823d33999 | 131 | __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) |
<> | 149:156823d33999 | 132 | { |
<> | 149:156823d33999 | 133 | /* Enable the Power Down in Run mode*/ |
<> | 149:156823d33999 | 134 | __HAL_FLASH_POWER_DOWN_ENABLE(); |
<> | 149:156823d33999 | 135 | |
<> | 149:156823d33999 | 136 | return HAL_OK; |
<> | 149:156823d33999 | 137 | } |
<> | 149:156823d33999 | 138 | |
<> | 149:156823d33999 | 139 | /** |
<> | 149:156823d33999 | 140 | * @brief Disable the power down mode during RUN mode. |
<> | 149:156823d33999 | 141 | * @note This function can be used only when the user code is running from Internal SRAM. |
<> | 149:156823d33999 | 142 | * @retval HAL status |
<> | 149:156823d33999 | 143 | */ |
<> | 149:156823d33999 | 144 | __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) |
<> | 149:156823d33999 | 145 | { |
<> | 149:156823d33999 | 146 | /* Disable the Power Down in Run mode*/ |
<> | 149:156823d33999 | 147 | __HAL_FLASH_POWER_DOWN_DISABLE(); |
<> | 149:156823d33999 | 148 | |
<> | 149:156823d33999 | 149 | return HAL_OK; |
<> | 149:156823d33999 | 150 | } |
<> | 149:156823d33999 | 151 | |
<> | 149:156823d33999 | 152 | /** |
<> | 149:156823d33999 | 153 | * @} |
<> | 149:156823d33999 | 154 | */ |
<> | 149:156823d33999 | 155 | |
<> | 149:156823d33999 | 156 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions |
<> | 149:156823d33999 | 157 | * |
<> | 149:156823d33999 | 158 | @verbatim |
<> | 149:156823d33999 | 159 | @endverbatim |
<> | 149:156823d33999 | 160 | * @{ |
<> | 149:156823d33999 | 161 | */ |
<> | 149:156823d33999 | 162 | |
<> | 149:156823d33999 | 163 | #if defined(FLASH_PECR_PARALLBANK) |
<> | 149:156823d33999 | 164 | /** |
<> | 149:156823d33999 | 165 | * @brief Erases a specified 2 pages in program memory in parallel. |
<> | 149:156823d33999 | 166 | * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. |
<> | 149:156823d33999 | 167 | * To correctly run this function, the @ref HAL_FLASH_Unlock() function |
<> | 149:156823d33999 | 168 | * must be called before. |
<> | 149:156823d33999 | 169 | * Call the @ref HAL_FLASH_Lock() to disable the flash memory access |
<> | 149:156823d33999 | 170 | * (recommended to protect the FLASH memory against possible unwanted operation). |
<> | 149:156823d33999 | 171 | * @param Page_Address1: The page address in program memory to be erased in |
<> | 149:156823d33999 | 172 | * the first Bank (BANK1). This parameter should be between FLASH_BASE |
<> | 149:156823d33999 | 173 | * and FLASH_BANK1_END. |
<> | 149:156823d33999 | 174 | * @param Page_Address2: The page address in program memory to be erased in |
<> | 149:156823d33999 | 175 | * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE |
<> | 149:156823d33999 | 176 | * and FLASH_BANK2_END. |
<> | 149:156823d33999 | 177 | * @note A Page is erased in the Program memory only if the address to load |
<> | 149:156823d33999 | 178 | * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes). |
<> | 149:156823d33999 | 179 | * @retval HAL status |
<> | 149:156823d33999 | 180 | */ |
<> | 149:156823d33999 | 181 | __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) |
<> | 149:156823d33999 | 182 | { |
<> | 149:156823d33999 | 183 | HAL_StatusTypeDef status = HAL_OK; |
<> | 149:156823d33999 | 184 | |
<> | 149:156823d33999 | 185 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 186 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 187 | |
<> | 149:156823d33999 | 188 | if(status == HAL_OK) |
<> | 149:156823d33999 | 189 | { |
<> | 149:156823d33999 | 190 | /* Proceed to erase the page */ |
<> | 149:156823d33999 | 191 | SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
<> | 149:156823d33999 | 192 | SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); |
<> | 149:156823d33999 | 193 | SET_BIT(FLASH->PECR, FLASH_PECR_PROG); |
<> | 149:156823d33999 | 194 | |
<> | 149:156823d33999 | 195 | /* Write 00000000h to the first word of the first program page to erase */ |
AnnaBridge | 184:08ed48f1de7f | 196 | *(__IO uint32_t *)Page_Address1 = 0x00000000U; |
<> | 149:156823d33999 | 197 | /* Write 00000000h to the first word of the second program page to erase */ |
AnnaBridge | 184:08ed48f1de7f | 198 | *(__IO uint32_t *)Page_Address2 = 0x00000000U; |
<> | 149:156823d33999 | 199 | |
<> | 149:156823d33999 | 200 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 201 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 202 | |
<> | 149:156823d33999 | 203 | /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ |
<> | 149:156823d33999 | 204 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); |
<> | 149:156823d33999 | 205 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); |
<> | 149:156823d33999 | 206 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
<> | 149:156823d33999 | 207 | } |
<> | 149:156823d33999 | 208 | /* Return the Erase Status */ |
<> | 149:156823d33999 | 209 | return status; |
<> | 149:156823d33999 | 210 | } |
<> | 149:156823d33999 | 211 | |
<> | 149:156823d33999 | 212 | /** |
<> | 149:156823d33999 | 213 | * @brief Program 2 half pages in program memory in parallel (half page size is 32 Words). |
<> | 149:156823d33999 | 214 | * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices. |
<> | 149:156823d33999 | 215 | * @param Address1: specifies the first address to be written in the first bank |
<> | 149:156823d33999 | 216 | * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE). |
<> | 149:156823d33999 | 217 | * @param pBuffer1: pointer to the buffer containing the data to be written |
<> | 149:156823d33999 | 218 | * to the first half page in the first bank. |
<> | 149:156823d33999 | 219 | * @param Address2: specifies the second address to be written in the second bank |
<> | 149:156823d33999 | 220 | * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE). |
<> | 149:156823d33999 | 221 | * @param pBuffer2: pointer to the buffer containing the data to be written |
<> | 149:156823d33999 | 222 | * to the second half page in the second bank. |
<> | 149:156823d33999 | 223 | * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function |
<> | 149:156823d33999 | 224 | * must be called before. |
<> | 149:156823d33999 | 225 | * Call the @ref HAL_FLASH_Lock() to disable the flash memory access |
<> | 149:156823d33999 | 226 | * (recommended to protect the FLASH memory against possible unwanted operation). |
<> | 149:156823d33999 | 227 | * @note Half page write is possible only from SRAM. |
<> | 149:156823d33999 | 228 | * @note If there are more than 32 words to write, after 32 words another |
<> | 149:156823d33999 | 229 | * Half Page programming operation starts and has to be finished. |
<> | 149:156823d33999 | 230 | * @note A half page is written to the program memory only if the first |
<> | 149:156823d33999 | 231 | * address to load is the start address of a half page (multiple of 128 |
<> | 149:156823d33999 | 232 | * bytes) and the 31 remaining words to load are in the same half page. |
<> | 149:156823d33999 | 233 | * @note During the Program memory half page write all read operations are |
<> | 149:156823d33999 | 234 | * forbidden (this includes DMA read operations and debugger read |
<> | 149:156823d33999 | 235 | * operations such as breakpoints, periodic updates, etc.). |
<> | 149:156823d33999 | 236 | * @note If a PGAERR is set during a Program memory half page write, the |
<> | 149:156823d33999 | 237 | * complete write operation is aborted. Software should then reset the |
<> | 149:156823d33999 | 238 | * FPRG and PROG/DATA bits and restart the write operation from the |
<> | 149:156823d33999 | 239 | * beginning. |
<> | 149:156823d33999 | 240 | * @retval HAL status |
<> | 149:156823d33999 | 241 | */ |
<> | 149:156823d33999 | 242 | __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) |
<> | 149:156823d33999 | 243 | { |
AnnaBridge | 184:08ed48f1de7f | 244 | uint32_t count = 0U; |
<> | 149:156823d33999 | 245 | HAL_StatusTypeDef status = HAL_OK; |
<> | 149:156823d33999 | 246 | |
AnnaBridge | 184:08ed48f1de7f | 247 | /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) |
<> | 149:156823d33999 | 248 | This bit prevents the interruption of multicycle instructions and therefore |
<> | 149:156823d33999 | 249 | will increase the interrupt latency. of Cortex-M3. */ |
<> | 149:156823d33999 | 250 | SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 251 | |
<> | 149:156823d33999 | 252 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 253 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 254 | |
<> | 149:156823d33999 | 255 | if(status == HAL_OK) |
<> | 149:156823d33999 | 256 | { |
<> | 149:156823d33999 | 257 | /* Proceed to program the new half page */ |
<> | 149:156823d33999 | 258 | SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
<> | 149:156823d33999 | 259 | SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
<> | 149:156823d33999 | 260 | SET_BIT(FLASH->PECR, FLASH_PECR_PROG); |
<> | 149:156823d33999 | 261 | |
<> | 149:156823d33999 | 262 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 263 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 264 | if(status == HAL_OK) |
<> | 149:156823d33999 | 265 | { |
<> | 149:156823d33999 | 266 | /* Disable all IRQs */ |
<> | 149:156823d33999 | 267 | __disable_irq(); |
<> | 149:156823d33999 | 268 | |
<> | 149:156823d33999 | 269 | /* Write the first half page directly with 32 different words */ |
AnnaBridge | 184:08ed48f1de7f | 270 | while(count < 32U) |
<> | 149:156823d33999 | 271 | { |
<> | 149:156823d33999 | 272 | *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1; |
<> | 149:156823d33999 | 273 | pBuffer1++; |
<> | 149:156823d33999 | 274 | count ++; |
<> | 149:156823d33999 | 275 | } |
<> | 149:156823d33999 | 276 | |
<> | 149:156823d33999 | 277 | /* Write the second half page directly with 32 different words */ |
AnnaBridge | 184:08ed48f1de7f | 278 | count = 0U; |
AnnaBridge | 184:08ed48f1de7f | 279 | while(count < 32U) |
<> | 149:156823d33999 | 280 | { |
<> | 149:156823d33999 | 281 | *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2; |
<> | 149:156823d33999 | 282 | pBuffer2++; |
<> | 149:156823d33999 | 283 | count ++; |
<> | 149:156823d33999 | 284 | } |
<> | 149:156823d33999 | 285 | |
<> | 149:156823d33999 | 286 | /* Enable IRQs */ |
<> | 149:156823d33999 | 287 | __enable_irq(); |
<> | 149:156823d33999 | 288 | |
<> | 149:156823d33999 | 289 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 290 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 291 | } |
<> | 149:156823d33999 | 292 | |
<> | 149:156823d33999 | 293 | /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ |
<> | 149:156823d33999 | 294 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); |
<> | 149:156823d33999 | 295 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
<> | 149:156823d33999 | 296 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); |
<> | 149:156823d33999 | 297 | } |
<> | 149:156823d33999 | 298 | |
<> | 149:156823d33999 | 299 | CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 300 | |
<> | 149:156823d33999 | 301 | /* Return the Write Status */ |
<> | 149:156823d33999 | 302 | return status; |
<> | 149:156823d33999 | 303 | } |
<> | 149:156823d33999 | 304 | #endif /* FLASH_PECR_PARALLBANK */ |
<> | 149:156823d33999 | 305 | |
<> | 149:156823d33999 | 306 | /** |
<> | 149:156823d33999 | 307 | * @brief Program a half page in program memory. |
<> | 149:156823d33999 | 308 | * @param Address: specifies the address to be written. |
<> | 149:156823d33999 | 309 | * @param pBuffer: pointer to the buffer containing the data to be written to |
<> | 149:156823d33999 | 310 | * the half page. |
<> | 149:156823d33999 | 311 | * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function |
<> | 149:156823d33999 | 312 | * must be called before. |
<> | 149:156823d33999 | 313 | * Call the @ref HAL_FLASH_Lock() to disable the flash memory access |
<> | 149:156823d33999 | 314 | * (recommended to protect the FLASH memory against possible unwanted operation) |
<> | 149:156823d33999 | 315 | * @note Half page write is possible only from SRAM. |
<> | 149:156823d33999 | 316 | * @note If there are more than 32 words to write, after 32 words another |
<> | 149:156823d33999 | 317 | * Half Page programming operation starts and has to be finished. |
<> | 149:156823d33999 | 318 | * @note A half page is written to the program memory only if the first |
<> | 149:156823d33999 | 319 | * address to load is the start address of a half page (multiple of 128 |
<> | 149:156823d33999 | 320 | * bytes) and the 31 remaining words to load are in the same half page. |
<> | 149:156823d33999 | 321 | * @note During the Program memory half page write all read operations are |
<> | 149:156823d33999 | 322 | * forbidden (this includes DMA read operations and debugger read |
<> | 149:156823d33999 | 323 | * operations such as breakpoints, periodic updates, etc.). |
<> | 149:156823d33999 | 324 | * @note If a PGAERR is set during a Program memory half page write, the |
<> | 149:156823d33999 | 325 | * complete write operation is aborted. Software should then reset the |
<> | 149:156823d33999 | 326 | * FPRG and PROG/DATA bits and restart the write operation from the |
<> | 149:156823d33999 | 327 | * beginning. |
<> | 149:156823d33999 | 328 | * @retval HAL status |
<> | 149:156823d33999 | 329 | */ |
<> | 149:156823d33999 | 330 | __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer) |
<> | 149:156823d33999 | 331 | { |
AnnaBridge | 184:08ed48f1de7f | 332 | uint32_t count = 0U; |
<> | 149:156823d33999 | 333 | HAL_StatusTypeDef status = HAL_OK; |
<> | 149:156823d33999 | 334 | |
AnnaBridge | 184:08ed48f1de7f | 335 | /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) |
<> | 149:156823d33999 | 336 | This bit prevents the interruption of multicycle instructions and therefore |
<> | 149:156823d33999 | 337 | will increase the interrupt latency. of Cortex-M3. */ |
<> | 149:156823d33999 | 338 | SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 339 | |
<> | 149:156823d33999 | 340 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 341 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 342 | |
<> | 149:156823d33999 | 343 | if(status == HAL_OK) |
<> | 149:156823d33999 | 344 | { |
<> | 149:156823d33999 | 345 | /* Proceed to program the new half page */ |
<> | 149:156823d33999 | 346 | SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
<> | 149:156823d33999 | 347 | SET_BIT(FLASH->PECR, FLASH_PECR_PROG); |
<> | 149:156823d33999 | 348 | |
<> | 149:156823d33999 | 349 | /* Disable all IRQs */ |
<> | 149:156823d33999 | 350 | __disable_irq(); |
<> | 149:156823d33999 | 351 | |
<> | 149:156823d33999 | 352 | /* Write one half page directly with 32 different words */ |
AnnaBridge | 184:08ed48f1de7f | 353 | while(count < 32U) |
<> | 149:156823d33999 | 354 | { |
<> | 149:156823d33999 | 355 | *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer; |
<> | 149:156823d33999 | 356 | pBuffer++; |
<> | 149:156823d33999 | 357 | count ++; |
<> | 149:156823d33999 | 358 | } |
<> | 149:156823d33999 | 359 | |
AnnaBridge | 184:08ed48f1de7f | 360 | /* Wait for last operation to be completed */ |
AnnaBridge | 184:08ed48f1de7f | 361 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
AnnaBridge | 184:08ed48f1de7f | 362 | |
<> | 149:156823d33999 | 363 | /* Enable IRQs */ |
<> | 149:156823d33999 | 364 | __enable_irq(); |
<> | 149:156823d33999 | 365 | |
<> | 149:156823d33999 | 366 | /* If the write operation is completed, disable the PROG and FPRG bits */ |
<> | 149:156823d33999 | 367 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); |
<> | 149:156823d33999 | 368 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
<> | 149:156823d33999 | 369 | } |
<> | 149:156823d33999 | 370 | |
<> | 149:156823d33999 | 371 | CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 372 | |
<> | 149:156823d33999 | 373 | /* Return the Write Status */ |
<> | 149:156823d33999 | 374 | return status; |
<> | 149:156823d33999 | 375 | } |
<> | 149:156823d33999 | 376 | |
<> | 149:156823d33999 | 377 | /** |
<> | 149:156823d33999 | 378 | * @} |
<> | 149:156823d33999 | 379 | */ |
<> | 149:156823d33999 | 380 | |
<> | 149:156823d33999 | 381 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions |
<> | 149:156823d33999 | 382 | * @brief Peripheral errors functions |
<> | 149:156823d33999 | 383 | * |
<> | 149:156823d33999 | 384 | @verbatim |
<> | 149:156823d33999 | 385 | =============================================================================== |
<> | 149:156823d33999 | 386 | ##### Peripheral errors functions ##### |
<> | 149:156823d33999 | 387 | =============================================================================== |
<> | 149:156823d33999 | 388 | [..] |
<> | 149:156823d33999 | 389 | This subsection permit to get in run-time errors of the FLASH peripheral. |
<> | 149:156823d33999 | 390 | |
<> | 149:156823d33999 | 391 | @endverbatim |
<> | 149:156823d33999 | 392 | * @{ |
<> | 149:156823d33999 | 393 | */ |
<> | 149:156823d33999 | 394 | |
<> | 149:156823d33999 | 395 | /** |
<> | 149:156823d33999 | 396 | * @brief Get the specific FLASH errors flag. |
<> | 149:156823d33999 | 397 | * @param Error pointer is the error value. It can be a mixed of: |
<> | 149:156823d33999 | 398 | @if STM32L100xB |
<> | 149:156823d33999 | 399 | @elif STM32L100xBA |
<> | 149:156823d33999 | 400 | * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
<> | 149:156823d33999 | 401 | @elif STM32L151xB |
<> | 149:156823d33999 | 402 | @elif STM32L151xBA |
<> | 149:156823d33999 | 403 | * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
<> | 149:156823d33999 | 404 | @elif STM32L152xB |
<> | 149:156823d33999 | 405 | @elif STM32L152xBA |
<> | 149:156823d33999 | 406 | * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
<> | 149:156823d33999 | 407 | @elif STM32L100xC |
<> | 149:156823d33999 | 408 | * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
<> | 149:156823d33999 | 409 | * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error |
<> | 149:156823d33999 | 410 | @elif STM32L151xC |
<> | 149:156823d33999 | 411 | * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
<> | 149:156823d33999 | 412 | * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error |
<> | 149:156823d33999 | 413 | @elif STM32L152xC |
<> | 149:156823d33999 | 414 | * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
<> | 149:156823d33999 | 415 | * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error |
<> | 149:156823d33999 | 416 | @elif STM32L162xC |
<> | 149:156823d33999 | 417 | * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP) |
<> | 149:156823d33999 | 418 | * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error |
<> | 149:156823d33999 | 419 | @else |
<> | 149:156823d33999 | 420 | * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error |
<> | 149:156823d33999 | 421 | @endif |
<> | 149:156823d33999 | 422 | * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag |
<> | 149:156823d33999 | 423 | * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag |
<> | 149:156823d33999 | 424 | * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag |
<> | 149:156823d33999 | 425 | * @retval HAL Status |
<> | 149:156823d33999 | 426 | */ |
<> | 149:156823d33999 | 427 | __RAM_FUNC HAL_FLASHEx_GetError(uint32_t * Error) |
<> | 149:156823d33999 | 428 | { |
<> | 149:156823d33999 | 429 | *Error = pFlash.ErrorCode; |
<> | 149:156823d33999 | 430 | return HAL_OK; |
<> | 149:156823d33999 | 431 | } |
<> | 149:156823d33999 | 432 | |
<> | 149:156823d33999 | 433 | /** |
<> | 149:156823d33999 | 434 | * @} |
<> | 149:156823d33999 | 435 | */ |
<> | 149:156823d33999 | 436 | |
<> | 149:156823d33999 | 437 | /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions |
<> | 149:156823d33999 | 438 | * |
<> | 149:156823d33999 | 439 | * @{ |
<> | 149:156823d33999 | 440 | */ |
<> | 149:156823d33999 | 441 | |
<> | 149:156823d33999 | 442 | /** |
<> | 149:156823d33999 | 443 | * @brief Erase a double word in data memory. |
<> | 149:156823d33999 | 444 | * @param Address: specifies the address to be erased. |
<> | 149:156823d33999 | 445 | * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function |
<> | 149:156823d33999 | 446 | * must be called before. |
<> | 149:156823d33999 | 447 | * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access |
<> | 149:156823d33999 | 448 | * and Flash program erase control register access(recommended to protect |
<> | 149:156823d33999 | 449 | * the DATA_EEPROM against possible unwanted operation). |
<> | 149:156823d33999 | 450 | * @note Data memory double word erase is possible only from SRAM. |
<> | 149:156823d33999 | 451 | * @note A double word is erased to the data memory only if the first address |
<> | 149:156823d33999 | 452 | * to load is the start address of a double word (multiple of 8 bytes). |
<> | 149:156823d33999 | 453 | * @note During the Data memory double word erase, all read operations are |
<> | 149:156823d33999 | 454 | * forbidden (this includes DMA read operations and debugger read |
<> | 149:156823d33999 | 455 | * operations such as breakpoints, periodic updates, etc.). |
<> | 149:156823d33999 | 456 | * @retval HAL status |
<> | 149:156823d33999 | 457 | */ |
<> | 149:156823d33999 | 458 | |
<> | 149:156823d33999 | 459 | __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address) |
<> | 149:156823d33999 | 460 | { |
<> | 149:156823d33999 | 461 | HAL_StatusTypeDef status = HAL_OK; |
<> | 149:156823d33999 | 462 | |
AnnaBridge | 184:08ed48f1de7f | 463 | /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) |
<> | 149:156823d33999 | 464 | This bit prevents the interruption of multicycle instructions and therefore |
<> | 149:156823d33999 | 465 | will increase the interrupt latency. of Cortex-M3. */ |
<> | 149:156823d33999 | 466 | SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 467 | |
<> | 149:156823d33999 | 468 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 469 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 470 | |
<> | 149:156823d33999 | 471 | if(status == HAL_OK) |
<> | 149:156823d33999 | 472 | { |
<> | 149:156823d33999 | 473 | /* If the previous operation is completed, proceed to erase the next double word */ |
<> | 149:156823d33999 | 474 | /* Set the ERASE bit */ |
<> | 149:156823d33999 | 475 | SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); |
<> | 149:156823d33999 | 476 | |
<> | 149:156823d33999 | 477 | /* Set DATA bit */ |
<> | 149:156823d33999 | 478 | SET_BIT(FLASH->PECR, FLASH_PECR_DATA); |
<> | 149:156823d33999 | 479 | |
<> | 149:156823d33999 | 480 | /* Write 00000000h to the 2 words to erase */ |
AnnaBridge | 184:08ed48f1de7f | 481 | *(__IO uint32_t *)Address = 0x00000000U; |
AnnaBridge | 184:08ed48f1de7f | 482 | Address += 4U; |
AnnaBridge | 184:08ed48f1de7f | 483 | *(__IO uint32_t *)Address = 0x00000000U; |
<> | 149:156823d33999 | 484 | |
<> | 149:156823d33999 | 485 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 486 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 487 | |
<> | 149:156823d33999 | 488 | /* If the erase operation is completed, disable the ERASE and DATA bits */ |
<> | 149:156823d33999 | 489 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); |
<> | 149:156823d33999 | 490 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA); |
<> | 149:156823d33999 | 491 | } |
<> | 149:156823d33999 | 492 | |
<> | 149:156823d33999 | 493 | CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 494 | |
<> | 149:156823d33999 | 495 | /* Return the erase status */ |
<> | 149:156823d33999 | 496 | return status; |
<> | 149:156823d33999 | 497 | } |
<> | 149:156823d33999 | 498 | |
<> | 149:156823d33999 | 499 | /** |
<> | 149:156823d33999 | 500 | * @brief Write a double word in data memory without erase. |
<> | 149:156823d33999 | 501 | * @param Address: specifies the address to be written. |
<> | 149:156823d33999 | 502 | * @param Data: specifies the data to be written. |
<> | 149:156823d33999 | 503 | * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function |
<> | 149:156823d33999 | 504 | * must be called before. |
<> | 149:156823d33999 | 505 | * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access |
<> | 149:156823d33999 | 506 | * and Flash program erase control register access(recommended to protect |
<> | 149:156823d33999 | 507 | * the DATA_EEPROM against possible unwanted operation). |
<> | 149:156823d33999 | 508 | * @note Data memory double word write is possible only from SRAM. |
<> | 149:156823d33999 | 509 | * @note A data memory double word is written to the data memory only if the |
<> | 149:156823d33999 | 510 | * first address to load is the start address of a double word (multiple |
<> | 149:156823d33999 | 511 | * of double word). |
<> | 149:156823d33999 | 512 | * @note During the Data memory double word write, all read operations are |
<> | 149:156823d33999 | 513 | * forbidden (this includes DMA read operations and debugger read |
<> | 149:156823d33999 | 514 | * operations such as breakpoints, periodic updates, etc.). |
<> | 149:156823d33999 | 515 | * @retval HAL status |
<> | 149:156823d33999 | 516 | */ |
<> | 149:156823d33999 | 517 | __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data) |
<> | 149:156823d33999 | 518 | { |
<> | 149:156823d33999 | 519 | HAL_StatusTypeDef status = HAL_OK; |
<> | 149:156823d33999 | 520 | |
AnnaBridge | 184:08ed48f1de7f | 521 | /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008U) |
<> | 149:156823d33999 | 522 | This bit prevents the interruption of multicycle instructions and therefore |
<> | 149:156823d33999 | 523 | will increase the interrupt latency. of Cortex-M3. */ |
<> | 149:156823d33999 | 524 | SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 525 | |
<> | 149:156823d33999 | 526 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 527 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 528 | |
<> | 149:156823d33999 | 529 | if(status == HAL_OK) |
<> | 149:156823d33999 | 530 | { |
<> | 149:156823d33999 | 531 | /* If the previous operation is completed, proceed to program the new data*/ |
<> | 149:156823d33999 | 532 | SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
<> | 149:156823d33999 | 533 | SET_BIT(FLASH->PECR, FLASH_PECR_DATA); |
<> | 149:156823d33999 | 534 | |
<> | 149:156823d33999 | 535 | /* Write the 2 words */ |
<> | 149:156823d33999 | 536 | *(__IO uint32_t *)Address = (uint32_t) Data; |
AnnaBridge | 184:08ed48f1de7f | 537 | Address += 4U; |
<> | 149:156823d33999 | 538 | *(__IO uint32_t *)Address = (uint32_t) (Data >> 32); |
<> | 149:156823d33999 | 539 | |
<> | 149:156823d33999 | 540 | /* Wait for last operation to be completed */ |
<> | 149:156823d33999 | 541 | status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); |
<> | 149:156823d33999 | 542 | |
<> | 149:156823d33999 | 543 | /* If the write operation is completed, disable the FPRG and DATA bits */ |
<> | 149:156823d33999 | 544 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); |
<> | 149:156823d33999 | 545 | CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA); |
<> | 149:156823d33999 | 546 | } |
<> | 149:156823d33999 | 547 | |
<> | 149:156823d33999 | 548 | CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk); |
<> | 149:156823d33999 | 549 | |
<> | 149:156823d33999 | 550 | /* Return the Write Status */ |
<> | 149:156823d33999 | 551 | return status; |
<> | 149:156823d33999 | 552 | } |
<> | 149:156823d33999 | 553 | |
<> | 149:156823d33999 | 554 | /** |
<> | 149:156823d33999 | 555 | * @} |
<> | 149:156823d33999 | 556 | */ |
<> | 149:156823d33999 | 557 | |
<> | 149:156823d33999 | 558 | /** |
<> | 149:156823d33999 | 559 | * @} |
<> | 149:156823d33999 | 560 | */ |
<> | 149:156823d33999 | 561 | |
<> | 149:156823d33999 | 562 | /** @addtogroup FLASH_RAMFUNC_Private_Functions |
<> | 149:156823d33999 | 563 | * @{ |
<> | 149:156823d33999 | 564 | */ |
<> | 149:156823d33999 | 565 | |
<> | 149:156823d33999 | 566 | /** |
<> | 149:156823d33999 | 567 | * @brief Set the specific FLASH error flag. |
<> | 149:156823d33999 | 568 | * @retval HAL Status |
<> | 149:156823d33999 | 569 | */ |
<> | 149:156823d33999 | 570 | static __RAM_FUNC FLASHRAM_SetErrorCode(void) |
<> | 149:156823d33999 | 571 | { |
AnnaBridge | 184:08ed48f1de7f | 572 | uint32_t flags = 0U; |
<> | 149:156823d33999 | 573 | |
<> | 149:156823d33999 | 574 | if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) |
<> | 149:156823d33999 | 575 | { |
<> | 149:156823d33999 | 576 | pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; |
<> | 149:156823d33999 | 577 | flags |= FLASH_FLAG_WRPERR; |
<> | 149:156823d33999 | 578 | } |
<> | 149:156823d33999 | 579 | if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) |
<> | 149:156823d33999 | 580 | { |
<> | 149:156823d33999 | 581 | pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; |
<> | 149:156823d33999 | 582 | flags |= FLASH_FLAG_PGAERR; |
<> | 149:156823d33999 | 583 | } |
<> | 149:156823d33999 | 584 | if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) |
<> | 149:156823d33999 | 585 | { |
<> | 149:156823d33999 | 586 | pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; |
<> | 149:156823d33999 | 587 | flags |= FLASH_FLAG_OPTVERR; |
<> | 149:156823d33999 | 588 | } |
<> | 149:156823d33999 | 589 | |
<> | 149:156823d33999 | 590 | #if defined(FLASH_SR_RDERR) |
<> | 149:156823d33999 | 591 | if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) |
<> | 149:156823d33999 | 592 | { |
<> | 149:156823d33999 | 593 | pFlash.ErrorCode |= HAL_FLASH_ERROR_RD; |
<> | 149:156823d33999 | 594 | flags |= FLASH_FLAG_RDERR; |
<> | 149:156823d33999 | 595 | } |
<> | 149:156823d33999 | 596 | #endif /* FLASH_SR_RDERR */ |
<> | 149:156823d33999 | 597 | #if defined(FLASH_SR_OPTVERRUSR) |
<> | 149:156823d33999 | 598 | if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR)) |
<> | 149:156823d33999 | 599 | { |
<> | 149:156823d33999 | 600 | pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR; |
<> | 149:156823d33999 | 601 | flags |= FLASH_FLAG_OPTVERRUSR; |
<> | 149:156823d33999 | 602 | } |
<> | 149:156823d33999 | 603 | #endif /* FLASH_SR_OPTVERRUSR */ |
<> | 149:156823d33999 | 604 | |
<> | 149:156823d33999 | 605 | /* Clear FLASH error pending bits */ |
<> | 149:156823d33999 | 606 | __HAL_FLASH_CLEAR_FLAG(flags); |
<> | 149:156823d33999 | 607 | |
<> | 149:156823d33999 | 608 | return HAL_OK; |
<> | 149:156823d33999 | 609 | } |
<> | 149:156823d33999 | 610 | |
<> | 149:156823d33999 | 611 | /** |
<> | 149:156823d33999 | 612 | * @brief Wait for a FLASH operation to complete. |
<> | 149:156823d33999 | 613 | * @param Timeout: maximum flash operationtimeout |
<> | 149:156823d33999 | 614 | * @retval HAL status |
<> | 149:156823d33999 | 615 | */ |
<> | 149:156823d33999 | 616 | static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) |
<> | 149:156823d33999 | 617 | { |
<> | 149:156823d33999 | 618 | /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. |
<> | 149:156823d33999 | 619 | Even if the FLASH operation fails, the BUSY flag will be reset and an error |
<> | 149:156823d33999 | 620 | flag will be set */ |
<> | 149:156823d33999 | 621 | |
AnnaBridge | 184:08ed48f1de7f | 622 | while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00U)) |
<> | 149:156823d33999 | 623 | { |
<> | 149:156823d33999 | 624 | Timeout--; |
<> | 149:156823d33999 | 625 | } |
<> | 149:156823d33999 | 626 | |
AnnaBridge | 184:08ed48f1de7f | 627 | if(Timeout == 0x00U) |
<> | 149:156823d33999 | 628 | { |
<> | 149:156823d33999 | 629 | return HAL_TIMEOUT; |
<> | 149:156823d33999 | 630 | } |
<> | 149:156823d33999 | 631 | |
<> | 149:156823d33999 | 632 | /* Check FLASH End of Operation flag */ |
<> | 149:156823d33999 | 633 | if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) |
<> | 149:156823d33999 | 634 | { |
<> | 149:156823d33999 | 635 | /* Clear FLASH End of Operation pending bit */ |
<> | 149:156823d33999 | 636 | __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); |
<> | 149:156823d33999 | 637 | } |
<> | 149:156823d33999 | 638 | |
<> | 149:156823d33999 | 639 | if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) || |
<> | 149:156823d33999 | 640 | __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) || |
<> | 149:156823d33999 | 641 | #if defined(FLASH_SR_RDERR) |
<> | 149:156823d33999 | 642 | __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) || |
<> | 149:156823d33999 | 643 | #endif /* FLASH_SR_RDERR */ |
<> | 149:156823d33999 | 644 | #if defined(FLASH_SR_OPTVERRUSR) |
<> | 149:156823d33999 | 645 | __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) || |
<> | 149:156823d33999 | 646 | #endif /* FLASH_SR_OPTVERRUSR */ |
<> | 149:156823d33999 | 647 | __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) |
<> | 149:156823d33999 | 648 | { |
<> | 149:156823d33999 | 649 | /*Save the error code*/ |
<> | 149:156823d33999 | 650 | FLASHRAM_SetErrorCode(); |
<> | 149:156823d33999 | 651 | return HAL_ERROR; |
<> | 149:156823d33999 | 652 | } |
<> | 149:156823d33999 | 653 | |
<> | 149:156823d33999 | 654 | /* There is no error flag set */ |
<> | 149:156823d33999 | 655 | return HAL_OK; |
<> | 149:156823d33999 | 656 | } |
<> | 149:156823d33999 | 657 | |
<> | 149:156823d33999 | 658 | /** |
<> | 149:156823d33999 | 659 | * @} |
<> | 149:156823d33999 | 660 | */ |
<> | 149:156823d33999 | 661 | |
<> | 149:156823d33999 | 662 | /** |
<> | 149:156823d33999 | 663 | * @} |
<> | 149:156823d33999 | 664 | */ |
<> | 149:156823d33999 | 665 | |
<> | 149:156823d33999 | 666 | #endif /* HAL_FLASH_MODULE_ENABLED */ |
<> | 149:156823d33999 | 667 | /** |
<> | 149:156823d33999 | 668 | * @} |
<> | 149:156823d33999 | 669 | */ |
<> | 149:156823d33999 | 670 | |
<> | 149:156823d33999 | 671 | |
<> | 149:156823d33999 | 672 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |