mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_flash_ramfunc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
184:08ed48f1de7f
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_flash_ramfunc.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief FLASH RAMFUNC driver.
<> 149:156823d33999 8 * This file provides a Flash firmware functions which should be
<> 149:156823d33999 9 * executed from internal SRAM
<> 149:156823d33999 10 *
<> 149:156823d33999 11 * @verbatim
<> 149:156823d33999 12
<> 149:156823d33999 13 *** ARM Compiler ***
<> 149:156823d33999 14 --------------------
<> 149:156823d33999 15 [..] RAM functions are defined using the toolchain options.
<> 149:156823d33999 16 Functions that are be executed in RAM should reside in a separate
<> 149:156823d33999 17 source module. Using the 'Options for File' dialog you can simply change
<> 149:156823d33999 18 the 'Code / Const' area of a module to a memory space in physical RAM.
<> 149:156823d33999 19 Available memory areas are declared in the 'Target' tab of the
<> 149:156823d33999 20 Options for Target' dialog.
<> 149:156823d33999 21
<> 149:156823d33999 22 *** ICCARM Compiler ***
<> 149:156823d33999 23 -----------------------
<> 149:156823d33999 24 [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
<> 149:156823d33999 25
<> 149:156823d33999 26 *** GNU Compiler ***
<> 149:156823d33999 27 --------------------
<> 149:156823d33999 28 [..] RAM functions are defined using a specific toolchain attribute
<> 149:156823d33999 29 "__attribute__((section(".RamFunc")))".
<> 149:156823d33999 30
<> 149:156823d33999 31 @endverbatim
<> 149:156823d33999 32 ******************************************************************************
<> 149:156823d33999 33 * @attention
<> 149:156823d33999 34 *
<> 149:156823d33999 35 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 36 *
<> 149:156823d33999 37 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 38 * are permitted provided that the following conditions are met:
<> 149:156823d33999 39 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 40 * this list of conditions and the following disclaimer.
<> 149:156823d33999 41 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 42 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 43 * and/or other materials provided with the distribution.
<> 149:156823d33999 44 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 45 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 46 * without specific prior written permission.
<> 149:156823d33999 47 *
<> 149:156823d33999 48 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 49 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 50 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 51 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 52 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 53 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 54 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 55 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 56 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 57 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 58 *
<> 149:156823d33999 59 ******************************************************************************
<> 149:156823d33999 60 */
<> 149:156823d33999 61
<> 149:156823d33999 62 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 63 #include "stm32l1xx_hal.h"
<> 149:156823d33999 64
<> 149:156823d33999 65 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 66 * @{
<> 149:156823d33999 67 */
<> 149:156823d33999 68
<> 149:156823d33999 69 #ifdef HAL_FLASH_MODULE_ENABLED
<> 149:156823d33999 70
<> 149:156823d33999 71 /** @addtogroup FLASH
<> 149:156823d33999 72 * @{
<> 149:156823d33999 73 */
<> 149:156823d33999 74 /** @addtogroup FLASH_Private_Variables
<> 149:156823d33999 75 * @{
<> 149:156823d33999 76 */
<> 149:156823d33999 77 extern FLASH_ProcessTypeDef pFlash;
<> 149:156823d33999 78 /**
<> 149:156823d33999 79 * @}
<> 149:156823d33999 80 */
<> 149:156823d33999 81
<> 149:156823d33999 82 /**
<> 149:156823d33999 83 * @}
<> 149:156823d33999 84 */
<> 149:156823d33999 85
<> 149:156823d33999 86 /** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
<> 149:156823d33999 87 * @brief FLASH functions executed from RAM
<> 149:156823d33999 88 * @{
<> 149:156823d33999 89 */
<> 149:156823d33999 90
<> 149:156823d33999 91
<> 149:156823d33999 92 /* Private typedef -----------------------------------------------------------*/
<> 149:156823d33999 93 /* Private define ------------------------------------------------------------*/
<> 149:156823d33999 94 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 95 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 96 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 97 /** @defgroup FLASH_RAMFUNC_Private_Functions FLASH RAM Private Functions
<> 149:156823d33999 98 * @{
<> 149:156823d33999 99 */
<> 149:156823d33999 100
<> 149:156823d33999 101 static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
<> 149:156823d33999 102 static __RAM_FUNC FLASHRAM_SetErrorCode(void);
<> 149:156823d33999 103
<> 149:156823d33999 104 /**
<> 149:156823d33999 105 * @}
<> 149:156823d33999 106 */
<> 149:156823d33999 107
<> 149:156823d33999 108 /* Private functions ---------------------------------------------------------*/
<> 149:156823d33999 109
<> 149:156823d33999 110 /** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH RAM Exported Functions
<> 149:156823d33999 111 *
<> 149:156823d33999 112 @verbatim
<> 149:156823d33999 113 ===============================================================================
<> 149:156823d33999 114 ##### ramfunc functions #####
<> 149:156823d33999 115 ===============================================================================
<> 149:156823d33999 116 [..]
<> 149:156823d33999 117 This subsection provides a set of functions that should be executed from RAM
<> 149:156823d33999 118 transfers.
<> 149:156823d33999 119
<> 149:156823d33999 120 @endverbatim
<> 149:156823d33999 121 * @{
<> 149:156823d33999 122 */
<> 149:156823d33999 123
<> 149:156823d33999 124 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions
<> 149:156823d33999 125 * @{
<> 149:156823d33999 126 */
<> 149:156823d33999 127
<> 149:156823d33999 128 /**
<> 149:156823d33999 129 * @brief Enable the power down mode during RUN mode.
<> 149:156823d33999 130 * @note This function can be used only when the user code is running from Internal SRAM.
<> 149:156823d33999 131 * @retval HAL status
<> 149:156823d33999 132 */
<> 149:156823d33999 133 __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
<> 149:156823d33999 134 {
<> 149:156823d33999 135 /* Enable the Power Down in Run mode*/
<> 149:156823d33999 136 __HAL_FLASH_POWER_DOWN_ENABLE();
<> 149:156823d33999 137
<> 149:156823d33999 138 return HAL_OK;
<> 149:156823d33999 139 }
<> 149:156823d33999 140
<> 149:156823d33999 141 /**
<> 149:156823d33999 142 * @brief Disable the power down mode during RUN mode.
<> 149:156823d33999 143 * @note This function can be used only when the user code is running from Internal SRAM.
<> 149:156823d33999 144 * @retval HAL status
<> 149:156823d33999 145 */
<> 149:156823d33999 146 __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
<> 149:156823d33999 147 {
<> 149:156823d33999 148 /* Disable the Power Down in Run mode*/
<> 149:156823d33999 149 __HAL_FLASH_POWER_DOWN_DISABLE();
<> 149:156823d33999 150
<> 149:156823d33999 151 return HAL_OK;
<> 149:156823d33999 152 }
<> 149:156823d33999 153
<> 149:156823d33999 154 /**
<> 149:156823d33999 155 * @}
<> 149:156823d33999 156 */
<> 149:156823d33999 157
<> 149:156823d33999 158 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group2 Programming and erasing operation functions
<> 149:156823d33999 159 *
<> 149:156823d33999 160 @verbatim
<> 149:156823d33999 161 @endverbatim
<> 149:156823d33999 162 * @{
<> 149:156823d33999 163 */
<> 149:156823d33999 164
<> 149:156823d33999 165 #if defined(FLASH_PECR_PARALLBANK)
<> 149:156823d33999 166 /**
<> 149:156823d33999 167 * @brief Erases a specified 2 pages in program memory in parallel.
<> 149:156823d33999 168 * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
<> 149:156823d33999 169 * To correctly run this function, the @ref HAL_FLASH_Unlock() function
<> 149:156823d33999 170 * must be called before.
<> 149:156823d33999 171 * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
<> 149:156823d33999 172 * (recommended to protect the FLASH memory against possible unwanted operation).
<> 149:156823d33999 173 * @param Page_Address1: The page address in program memory to be erased in
<> 149:156823d33999 174 * the first Bank (BANK1). This parameter should be between FLASH_BASE
<> 149:156823d33999 175 * and FLASH_BANK1_END.
<> 149:156823d33999 176 * @param Page_Address2: The page address in program memory to be erased in
<> 149:156823d33999 177 * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
<> 149:156823d33999 178 * and FLASH_BANK2_END.
<> 149:156823d33999 179 * @note A Page is erased in the Program memory only if the address to load
<> 149:156823d33999 180 * is the start address of a page (multiple of @ref FLASH_PAGE_SIZE bytes).
<> 149:156823d33999 181 * @retval HAL status
<> 149:156823d33999 182 */
<> 149:156823d33999 183 __RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
<> 149:156823d33999 184 {
<> 149:156823d33999 185 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 186
<> 149:156823d33999 187 /* Wait for last operation to be completed */
<> 149:156823d33999 188 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 189
<> 149:156823d33999 190 if(status == HAL_OK)
<> 149:156823d33999 191 {
<> 149:156823d33999 192 /* Proceed to erase the page */
<> 149:156823d33999 193 SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 149:156823d33999 194 SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
<> 149:156823d33999 195 SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 149:156823d33999 196
<> 149:156823d33999 197 /* Write 00000000h to the first word of the first program page to erase */
<> 149:156823d33999 198 *(__IO uint32_t *)Page_Address1 = 0x00000000;
<> 149:156823d33999 199 /* Write 00000000h to the first word of the second program page to erase */
<> 149:156823d33999 200 *(__IO uint32_t *)Page_Address2 = 0x00000000;
<> 149:156823d33999 201
<> 149:156823d33999 202 /* Wait for last operation to be completed */
<> 149:156823d33999 203 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 204
<> 149:156823d33999 205 /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
<> 149:156823d33999 206 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 149:156823d33999 207 CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
<> 149:156823d33999 208 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 149:156823d33999 209 }
<> 149:156823d33999 210 /* Return the Erase Status */
<> 149:156823d33999 211 return status;
<> 149:156823d33999 212 }
<> 149:156823d33999 213
<> 149:156823d33999 214 /**
<> 149:156823d33999 215 * @brief Program 2 half pages in program memory in parallel (half page size is 32 Words).
<> 149:156823d33999 216 * @note This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5 devices.
<> 149:156823d33999 217 * @param Address1: specifies the first address to be written in the first bank
<> 149:156823d33999 218 * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
<> 149:156823d33999 219 * @param pBuffer1: pointer to the buffer containing the data to be written
<> 149:156823d33999 220 * to the first half page in the first bank.
<> 149:156823d33999 221 * @param Address2: specifies the second address to be written in the second bank
<> 149:156823d33999 222 * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
<> 149:156823d33999 223 * @param pBuffer2: pointer to the buffer containing the data to be written
<> 149:156823d33999 224 * to the second half page in the second bank.
<> 149:156823d33999 225 * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
<> 149:156823d33999 226 * must be called before.
<> 149:156823d33999 227 * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
<> 149:156823d33999 228 * (recommended to protect the FLASH memory against possible unwanted operation).
<> 149:156823d33999 229 * @note Half page write is possible only from SRAM.
<> 149:156823d33999 230 * @note If there are more than 32 words to write, after 32 words another
<> 149:156823d33999 231 * Half Page programming operation starts and has to be finished.
<> 149:156823d33999 232 * @note A half page is written to the program memory only if the first
<> 149:156823d33999 233 * address to load is the start address of a half page (multiple of 128
<> 149:156823d33999 234 * bytes) and the 31 remaining words to load are in the same half page.
<> 149:156823d33999 235 * @note During the Program memory half page write all read operations are
<> 149:156823d33999 236 * forbidden (this includes DMA read operations and debugger read
<> 149:156823d33999 237 * operations such as breakpoints, periodic updates, etc.).
<> 149:156823d33999 238 * @note If a PGAERR is set during a Program memory half page write, the
<> 149:156823d33999 239 * complete write operation is aborted. Software should then reset the
<> 149:156823d33999 240 * FPRG and PROG/DATA bits and restart the write operation from the
<> 149:156823d33999 241 * beginning.
<> 149:156823d33999 242 * @retval HAL status
<> 149:156823d33999 243 */
<> 149:156823d33999 244 __RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
<> 149:156823d33999 245 {
<> 149:156823d33999 246 uint32_t count = 0;
<> 149:156823d33999 247 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 248
<> 149:156823d33999 249 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 149:156823d33999 250 This bit prevents the interruption of multicycle instructions and therefore
<> 149:156823d33999 251 will increase the interrupt latency. of Cortex-M3. */
<> 149:156823d33999 252 SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 253
<> 149:156823d33999 254 /* Wait for last operation to be completed */
<> 149:156823d33999 255 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 256
<> 149:156823d33999 257 if(status == HAL_OK)
<> 149:156823d33999 258 {
<> 149:156823d33999 259 /* Proceed to program the new half page */
<> 149:156823d33999 260 SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 149:156823d33999 261 SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 149:156823d33999 262 SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 149:156823d33999 263
<> 149:156823d33999 264 /* Wait for last operation to be completed */
<> 149:156823d33999 265 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 266 if(status == HAL_OK)
<> 149:156823d33999 267 {
<> 149:156823d33999 268 /* Disable all IRQs */
<> 149:156823d33999 269 __disable_irq();
<> 149:156823d33999 270
<> 149:156823d33999 271 /* Write the first half page directly with 32 different words */
<> 149:156823d33999 272 while(count < 32)
<> 149:156823d33999 273 {
<> 149:156823d33999 274 *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *pBuffer1;
<> 149:156823d33999 275 pBuffer1++;
<> 149:156823d33999 276 count ++;
<> 149:156823d33999 277 }
<> 149:156823d33999 278
<> 149:156823d33999 279 /* Write the second half page directly with 32 different words */
<> 149:156823d33999 280 count = 0;
<> 149:156823d33999 281 while(count < 32)
<> 149:156823d33999 282 {
<> 149:156823d33999 283 *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *pBuffer2;
<> 149:156823d33999 284 pBuffer2++;
<> 149:156823d33999 285 count ++;
<> 149:156823d33999 286 }
<> 149:156823d33999 287
<> 149:156823d33999 288 /* Enable IRQs */
<> 149:156823d33999 289 __enable_irq();
<> 149:156823d33999 290
<> 149:156823d33999 291 /* Wait for last operation to be completed */
<> 149:156823d33999 292 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 293 }
<> 149:156823d33999 294
<> 149:156823d33999 295 /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
<> 149:156823d33999 296 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 149:156823d33999 297 CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 149:156823d33999 298 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK);
<> 149:156823d33999 299 }
<> 149:156823d33999 300
<> 149:156823d33999 301 CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 302
<> 149:156823d33999 303 /* Return the Write Status */
<> 149:156823d33999 304 return status;
<> 149:156823d33999 305 }
<> 149:156823d33999 306 #endif /* FLASH_PECR_PARALLBANK */
<> 149:156823d33999 307
<> 149:156823d33999 308 /**
<> 149:156823d33999 309 * @brief Program a half page in program memory.
<> 149:156823d33999 310 * @param Address: specifies the address to be written.
<> 149:156823d33999 311 * @param pBuffer: pointer to the buffer containing the data to be written to
<> 149:156823d33999 312 * the half page.
<> 149:156823d33999 313 * @note To correctly run this function, the @ref HAL_FLASH_Unlock() function
<> 149:156823d33999 314 * must be called before.
<> 149:156823d33999 315 * Call the @ref HAL_FLASH_Lock() to disable the flash memory access
<> 149:156823d33999 316 * (recommended to protect the FLASH memory against possible unwanted operation)
<> 149:156823d33999 317 * @note Half page write is possible only from SRAM.
<> 149:156823d33999 318 * @note If there are more than 32 words to write, after 32 words another
<> 149:156823d33999 319 * Half Page programming operation starts and has to be finished.
<> 149:156823d33999 320 * @note A half page is written to the program memory only if the first
<> 149:156823d33999 321 * address to load is the start address of a half page (multiple of 128
<> 149:156823d33999 322 * bytes) and the 31 remaining words to load are in the same half page.
<> 149:156823d33999 323 * @note During the Program memory half page write all read operations are
<> 149:156823d33999 324 * forbidden (this includes DMA read operations and debugger read
<> 149:156823d33999 325 * operations such as breakpoints, periodic updates, etc.).
<> 149:156823d33999 326 * @note If a PGAERR is set during a Program memory half page write, the
<> 149:156823d33999 327 * complete write operation is aborted. Software should then reset the
<> 149:156823d33999 328 * FPRG and PROG/DATA bits and restart the write operation from the
<> 149:156823d33999 329 * beginning.
<> 149:156823d33999 330 * @retval HAL status
<> 149:156823d33999 331 */
<> 149:156823d33999 332 __RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
<> 149:156823d33999 333 {
<> 149:156823d33999 334 uint32_t count = 0;
<> 149:156823d33999 335 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 336
<> 149:156823d33999 337 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 149:156823d33999 338 This bit prevents the interruption of multicycle instructions and therefore
<> 149:156823d33999 339 will increase the interrupt latency. of Cortex-M3. */
<> 149:156823d33999 340 SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 341
<> 149:156823d33999 342 /* Wait for last operation to be completed */
<> 149:156823d33999 343 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 344
<> 149:156823d33999 345 if(status == HAL_OK)
<> 149:156823d33999 346 {
<> 149:156823d33999 347 /* Proceed to program the new half page */
<> 149:156823d33999 348 SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 149:156823d33999 349 SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 149:156823d33999 350
<> 149:156823d33999 351 /* Disable all IRQs */
<> 149:156823d33999 352 __disable_irq();
<> 149:156823d33999 353
<> 149:156823d33999 354 /* Write one half page directly with 32 different words */
<> 149:156823d33999 355 while(count < 32)
<> 149:156823d33999 356 {
<> 149:156823d33999 357 *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *pBuffer;
<> 149:156823d33999 358 pBuffer++;
<> 149:156823d33999 359 count ++;
<> 149:156823d33999 360 }
<> 149:156823d33999 361
<> 149:156823d33999 362 /* Enable IRQs */
<> 149:156823d33999 363 __enable_irq();
<> 149:156823d33999 364
<> 149:156823d33999 365 /* Wait for last operation to be completed */
<> 149:156823d33999 366 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 367
<> 149:156823d33999 368 /* If the write operation is completed, disable the PROG and FPRG bits */
<> 149:156823d33999 369 CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
<> 149:156823d33999 370 CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 149:156823d33999 371 }
<> 149:156823d33999 372
<> 149:156823d33999 373 CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 374
<> 149:156823d33999 375 /* Return the Write Status */
<> 149:156823d33999 376 return status;
<> 149:156823d33999 377 }
<> 149:156823d33999 378
<> 149:156823d33999 379 /**
<> 149:156823d33999 380 * @}
<> 149:156823d33999 381 */
<> 149:156823d33999 382
<> 149:156823d33999 383 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group3 Peripheral errors functions
<> 149:156823d33999 384 * @brief Peripheral errors functions
<> 149:156823d33999 385 *
<> 149:156823d33999 386 @verbatim
<> 149:156823d33999 387 ===============================================================================
<> 149:156823d33999 388 ##### Peripheral errors functions #####
<> 149:156823d33999 389 ===============================================================================
<> 149:156823d33999 390 [..]
<> 149:156823d33999 391 This subsection permit to get in run-time errors of the FLASH peripheral.
<> 149:156823d33999 392
<> 149:156823d33999 393 @endverbatim
<> 149:156823d33999 394 * @{
<> 149:156823d33999 395 */
<> 149:156823d33999 396
<> 149:156823d33999 397 /**
<> 149:156823d33999 398 * @brief Get the specific FLASH errors flag.
<> 149:156823d33999 399 * @param Error pointer is the error value. It can be a mixed of:
<> 149:156823d33999 400 @if STM32L100xB
<> 149:156823d33999 401 @elif STM32L100xBA
<> 149:156823d33999 402 * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
<> 149:156823d33999 403 @elif STM32L151xB
<> 149:156823d33999 404 @elif STM32L151xBA
<> 149:156823d33999 405 * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
<> 149:156823d33999 406 @elif STM32L152xB
<> 149:156823d33999 407 @elif STM32L152xBA
<> 149:156823d33999 408 * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
<> 149:156823d33999 409 @elif STM32L100xC
<> 149:156823d33999 410 * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
<> 149:156823d33999 411 * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
<> 149:156823d33999 412 @elif STM32L151xC
<> 149:156823d33999 413 * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
<> 149:156823d33999 414 * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
<> 149:156823d33999 415 @elif STM32L152xC
<> 149:156823d33999 416 * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
<> 149:156823d33999 417 * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
<> 149:156823d33999 418 @elif STM32L162xC
<> 149:156823d33999 419 * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error flag (PCROP)
<> 149:156823d33999 420 * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
<> 149:156823d33999 421 @else
<> 149:156823d33999 422 * @arg @ref HAL_FLASH_ERROR_OPTVUSR FLASH Option User validity error
<> 149:156823d33999 423 @endif
<> 149:156823d33999 424 * @arg @ref HAL_FLASH_ERROR_PGA FLASH Programming Alignment error flag
<> 149:156823d33999 425 * @arg @ref HAL_FLASH_ERROR_WRP FLASH Write protected error flag
<> 149:156823d33999 426 * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option valid error flag
<> 149:156823d33999 427 * @retval HAL Status
<> 149:156823d33999 428 */
<> 149:156823d33999 429 __RAM_FUNC HAL_FLASHEx_GetError(uint32_t * Error)
<> 149:156823d33999 430 {
<> 149:156823d33999 431 *Error = pFlash.ErrorCode;
<> 149:156823d33999 432 return HAL_OK;
<> 149:156823d33999 433 }
<> 149:156823d33999 434
<> 149:156823d33999 435 /**
<> 149:156823d33999 436 * @}
<> 149:156823d33999 437 */
<> 149:156823d33999 438
<> 149:156823d33999 439 /** @defgroup FLASH_RAMFUNC_Exported_Functions_Group4 DATA EEPROM functions
<> 149:156823d33999 440 *
<> 149:156823d33999 441 * @{
<> 149:156823d33999 442 */
<> 149:156823d33999 443
<> 149:156823d33999 444 /**
<> 149:156823d33999 445 * @brief Erase a double word in data memory.
<> 149:156823d33999 446 * @param Address: specifies the address to be erased.
<> 149:156823d33999 447 * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
<> 149:156823d33999 448 * must be called before.
<> 149:156823d33999 449 * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
<> 149:156823d33999 450 * and Flash program erase control register access(recommended to protect
<> 149:156823d33999 451 * the DATA_EEPROM against possible unwanted operation).
<> 149:156823d33999 452 * @note Data memory double word erase is possible only from SRAM.
<> 149:156823d33999 453 * @note A double word is erased to the data memory only if the first address
<> 149:156823d33999 454 * to load is the start address of a double word (multiple of 8 bytes).
<> 149:156823d33999 455 * @note During the Data memory double word erase, all read operations are
<> 149:156823d33999 456 * forbidden (this includes DMA read operations and debugger read
<> 149:156823d33999 457 * operations such as breakpoints, periodic updates, etc.).
<> 149:156823d33999 458 * @retval HAL status
<> 149:156823d33999 459 */
<> 149:156823d33999 460
<> 149:156823d33999 461 __RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
<> 149:156823d33999 462 {
<> 149:156823d33999 463 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 464
<> 149:156823d33999 465 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 149:156823d33999 466 This bit prevents the interruption of multicycle instructions and therefore
<> 149:156823d33999 467 will increase the interrupt latency. of Cortex-M3. */
<> 149:156823d33999 468 SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 469
<> 149:156823d33999 470 /* Wait for last operation to be completed */
<> 149:156823d33999 471 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 472
<> 149:156823d33999 473 if(status == HAL_OK)
<> 149:156823d33999 474 {
<> 149:156823d33999 475 /* If the previous operation is completed, proceed to erase the next double word */
<> 149:156823d33999 476 /* Set the ERASE bit */
<> 149:156823d33999 477 SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
<> 149:156823d33999 478
<> 149:156823d33999 479 /* Set DATA bit */
<> 149:156823d33999 480 SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
<> 149:156823d33999 481
<> 149:156823d33999 482 /* Write 00000000h to the 2 words to erase */
<> 149:156823d33999 483 *(__IO uint32_t *)Address = 0x00000000;
<> 149:156823d33999 484 Address += 4;
<> 149:156823d33999 485 *(__IO uint32_t *)Address = 0x00000000;
<> 149:156823d33999 486
<> 149:156823d33999 487 /* Wait for last operation to be completed */
<> 149:156823d33999 488 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 489
<> 149:156823d33999 490 /* If the erase operation is completed, disable the ERASE and DATA bits */
<> 149:156823d33999 491 CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
<> 149:156823d33999 492 CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
<> 149:156823d33999 493 }
<> 149:156823d33999 494
<> 149:156823d33999 495 CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 496
<> 149:156823d33999 497 /* Return the erase status */
<> 149:156823d33999 498 return status;
<> 149:156823d33999 499 }
<> 149:156823d33999 500
<> 149:156823d33999 501 /**
<> 149:156823d33999 502 * @brief Write a double word in data memory without erase.
<> 149:156823d33999 503 * @param Address: specifies the address to be written.
<> 149:156823d33999 504 * @param Data: specifies the data to be written.
<> 149:156823d33999 505 * @note To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
<> 149:156823d33999 506 * must be called before.
<> 149:156823d33999 507 * Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
<> 149:156823d33999 508 * and Flash program erase control register access(recommended to protect
<> 149:156823d33999 509 * the DATA_EEPROM against possible unwanted operation).
<> 149:156823d33999 510 * @note Data memory double word write is possible only from SRAM.
<> 149:156823d33999 511 * @note A data memory double word is written to the data memory only if the
<> 149:156823d33999 512 * first address to load is the start address of a double word (multiple
<> 149:156823d33999 513 * of double word).
<> 149:156823d33999 514 * @note During the Data memory double word write, all read operations are
<> 149:156823d33999 515 * forbidden (this includes DMA read operations and debugger read
<> 149:156823d33999 516 * operations such as breakpoints, periodic updates, etc.).
<> 149:156823d33999 517 * @retval HAL status
<> 149:156823d33999 518 */
<> 149:156823d33999 519 __RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
<> 149:156823d33999 520 {
<> 149:156823d33999 521 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 522
<> 149:156823d33999 523 /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
<> 149:156823d33999 524 This bit prevents the interruption of multicycle instructions and therefore
<> 149:156823d33999 525 will increase the interrupt latency. of Cortex-M3. */
<> 149:156823d33999 526 SET_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 527
<> 149:156823d33999 528 /* Wait for last operation to be completed */
<> 149:156823d33999 529 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 530
<> 149:156823d33999 531 if(status == HAL_OK)
<> 149:156823d33999 532 {
<> 149:156823d33999 533 /* If the previous operation is completed, proceed to program the new data*/
<> 149:156823d33999 534 SET_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 149:156823d33999 535 SET_BIT(FLASH->PECR, FLASH_PECR_DATA);
<> 149:156823d33999 536
<> 149:156823d33999 537 /* Write the 2 words */
<> 149:156823d33999 538 *(__IO uint32_t *)Address = (uint32_t) Data;
<> 149:156823d33999 539 Address += 4;
<> 149:156823d33999 540 *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
<> 149:156823d33999 541
<> 149:156823d33999 542 /* Wait for last operation to be completed */
<> 149:156823d33999 543 status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
<> 149:156823d33999 544
<> 149:156823d33999 545 /* If the write operation is completed, disable the FPRG and DATA bits */
<> 149:156823d33999 546 CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG);
<> 149:156823d33999 547 CLEAR_BIT(FLASH->PECR, FLASH_PECR_DATA);
<> 149:156823d33999 548 }
<> 149:156823d33999 549
<> 149:156823d33999 550 CLEAR_BIT(SCnSCB->ACTLR, SCnSCB_ACTLR_DISMCYCINT_Msk);
<> 149:156823d33999 551
<> 149:156823d33999 552 /* Return the Write Status */
<> 149:156823d33999 553 return status;
<> 149:156823d33999 554 }
<> 149:156823d33999 555
<> 149:156823d33999 556 /**
<> 149:156823d33999 557 * @}
<> 149:156823d33999 558 */
<> 149:156823d33999 559
<> 149:156823d33999 560 /**
<> 149:156823d33999 561 * @}
<> 149:156823d33999 562 */
<> 149:156823d33999 563
<> 149:156823d33999 564 /** @addtogroup FLASH_RAMFUNC_Private_Functions
<> 149:156823d33999 565 * @{
<> 149:156823d33999 566 */
<> 149:156823d33999 567
<> 149:156823d33999 568 /**
<> 149:156823d33999 569 * @brief Set the specific FLASH error flag.
<> 149:156823d33999 570 * @retval HAL Status
<> 149:156823d33999 571 */
<> 149:156823d33999 572 static __RAM_FUNC FLASHRAM_SetErrorCode(void)
<> 149:156823d33999 573 {
<> 149:156823d33999 574 uint32_t flags = 0;
<> 149:156823d33999 575
<> 149:156823d33999 576 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
<> 149:156823d33999 577 {
<> 149:156823d33999 578 pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
<> 149:156823d33999 579 flags |= FLASH_FLAG_WRPERR;
<> 149:156823d33999 580 }
<> 149:156823d33999 581 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
<> 149:156823d33999 582 {
<> 149:156823d33999 583 pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
<> 149:156823d33999 584 flags |= FLASH_FLAG_PGAERR;
<> 149:156823d33999 585 }
<> 149:156823d33999 586 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
<> 149:156823d33999 587 {
<> 149:156823d33999 588 pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
<> 149:156823d33999 589 flags |= FLASH_FLAG_OPTVERR;
<> 149:156823d33999 590 }
<> 149:156823d33999 591
<> 149:156823d33999 592 #if defined(FLASH_SR_RDERR)
<> 149:156823d33999 593 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
<> 149:156823d33999 594 {
<> 149:156823d33999 595 pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
<> 149:156823d33999 596 flags |= FLASH_FLAG_RDERR;
<> 149:156823d33999 597 }
<> 149:156823d33999 598 #endif /* FLASH_SR_RDERR */
<> 149:156823d33999 599 #if defined(FLASH_SR_OPTVERRUSR)
<> 149:156823d33999 600 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR))
<> 149:156823d33999 601 {
<> 149:156823d33999 602 pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTVUSR;
<> 149:156823d33999 603 flags |= FLASH_FLAG_OPTVERRUSR;
<> 149:156823d33999 604 }
<> 149:156823d33999 605 #endif /* FLASH_SR_OPTVERRUSR */
<> 149:156823d33999 606
<> 149:156823d33999 607 /* Clear FLASH error pending bits */
<> 149:156823d33999 608 __HAL_FLASH_CLEAR_FLAG(flags);
<> 149:156823d33999 609
<> 149:156823d33999 610 return HAL_OK;
<> 149:156823d33999 611 }
<> 149:156823d33999 612
<> 149:156823d33999 613 /**
<> 149:156823d33999 614 * @brief Wait for a FLASH operation to complete.
<> 149:156823d33999 615 * @param Timeout: maximum flash operationtimeout
<> 149:156823d33999 616 * @retval HAL status
<> 149:156823d33999 617 */
<> 149:156823d33999 618 static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout)
<> 149:156823d33999 619 {
<> 149:156823d33999 620 /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
<> 149:156823d33999 621 Even if the FLASH operation fails, the BUSY flag will be reset and an error
<> 149:156823d33999 622 flag will be set */
<> 149:156823d33999 623
<> 149:156823d33999 624 while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00))
<> 149:156823d33999 625 {
<> 149:156823d33999 626 Timeout--;
<> 149:156823d33999 627 }
<> 149:156823d33999 628
<> 149:156823d33999 629 if(Timeout == 0x00 )
<> 149:156823d33999 630 {
<> 149:156823d33999 631 return HAL_TIMEOUT;
<> 149:156823d33999 632 }
<> 149:156823d33999 633
<> 149:156823d33999 634 /* Check FLASH End of Operation flag */
<> 149:156823d33999 635 if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
<> 149:156823d33999 636 {
<> 149:156823d33999 637 /* Clear FLASH End of Operation pending bit */
<> 149:156823d33999 638 __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
<> 149:156823d33999 639 }
<> 149:156823d33999 640
<> 149:156823d33999 641 if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) ||
<> 149:156823d33999 642 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) ||
<> 149:156823d33999 643 #if defined(FLASH_SR_RDERR)
<> 149:156823d33999 644 __HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) ||
<> 149:156823d33999 645 #endif /* FLASH_SR_RDERR */
<> 149:156823d33999 646 #if defined(FLASH_SR_OPTVERRUSR)
<> 149:156823d33999 647 __HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) ||
<> 149:156823d33999 648 #endif /* FLASH_SR_OPTVERRUSR */
<> 149:156823d33999 649 __HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
<> 149:156823d33999 650 {
<> 149:156823d33999 651 /*Save the error code*/
<> 149:156823d33999 652 FLASHRAM_SetErrorCode();
<> 149:156823d33999 653 return HAL_ERROR;
<> 149:156823d33999 654 }
<> 149:156823d33999 655
<> 149:156823d33999 656 /* There is no error flag set */
<> 149:156823d33999 657 return HAL_OK;
<> 149:156823d33999 658 }
<> 149:156823d33999 659
<> 149:156823d33999 660 /**
<> 149:156823d33999 661 * @}
<> 149:156823d33999 662 */
<> 149:156823d33999 663
<> 149:156823d33999 664 /**
<> 149:156823d33999 665 * @}
<> 149:156823d33999 666 */
<> 149:156823d33999 667
<> 149:156823d33999 668 #endif /* HAL_FLASH_MODULE_ENABLED */
<> 149:156823d33999 669 /**
<> 149:156823d33999 670 * @}
<> 149:156823d33999 671 */
<> 149:156823d33999 672
<> 149:156823d33999 673
<> 149:156823d33999 674 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/