mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c@189:f392fc9709a3, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 22:31:08 2019 +0000
Revision:
189:f392fc9709a3
Parent:
188:bcfe06ba3d64 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015-2016 Nuvoton
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #if DEVICE_SERIAL
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 23 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 24 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 25 #include "nu_modutil.h"
<> 144:ef7eb2e8f9f7 26 #include "nu_bitutil.h"
AnnaBridge 165:e614a9f1c9e2 27 #include <string.h>
AnnaBridge 188:bcfe06ba3d64 28 #include <stdbool.h>
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 31 #include "dma_api.h"
<> 144:ef7eb2e8f9f7 32 #include "dma.h"
<> 144:ef7eb2e8f9f7 33 #endif
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 struct nu_uart_var {
<> 151:5eaa88a5bcc7 36 uint32_t ref_cnt; // Reference count of the H/W module
<> 144:ef7eb2e8f9f7 37 serial_t * obj;
<> 144:ef7eb2e8f9f7 38 uint32_t fifo_size_tx;
<> 144:ef7eb2e8f9f7 39 uint32_t fifo_size_rx;
<> 144:ef7eb2e8f9f7 40 void (*vec)(void);
<> 144:ef7eb2e8f9f7 41 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 42 void (*vec_async)(void);
<> 144:ef7eb2e8f9f7 43 uint8_t pdma_perp_tx;
<> 144:ef7eb2e8f9f7 44 uint8_t pdma_perp_rx;
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46 };
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 static void uart0_vec(void);
<> 144:ef7eb2e8f9f7 49 static void uart1_vec(void);
<> 144:ef7eb2e8f9f7 50 static void uart2_vec(void);
<> 144:ef7eb2e8f9f7 51 static void uart3_vec(void);
<> 144:ef7eb2e8f9f7 52 static void uart4_vec(void);
<> 144:ef7eb2e8f9f7 53 static void uart5_vec(void);
<> 144:ef7eb2e8f9f7 54 static void uart_irq(serial_t *obj);
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 57 static void uart0_vec_async(void);
<> 144:ef7eb2e8f9f7 58 static void uart1_vec_async(void);
<> 144:ef7eb2e8f9f7 59 static void uart2_vec_async(void);
<> 144:ef7eb2e8f9f7 60 static void uart3_vec_async(void);
<> 144:ef7eb2e8f9f7 61 static void uart4_vec_async(void);
<> 144:ef7eb2e8f9f7 62 static void uart5_vec_async(void);
<> 144:ef7eb2e8f9f7 63 static void uart_irq_async(serial_t *obj);
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
<> 144:ef7eb2e8f9f7 66 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
<> 144:ef7eb2e8f9f7 69 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
AnnaBridge 165:e614a9f1c9e2 70 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable);
AnnaBridge 165:e614a9f1c9e2 71 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq);
<> 144:ef7eb2e8f9f7 72 static int serial_write_async(serial_t *obj);
<> 144:ef7eb2e8f9f7 73 static int serial_read_async(serial_t *obj);
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 static uint32_t serial_rx_event_check(serial_t *obj);
<> 144:ef7eb2e8f9f7 76 static uint32_t serial_tx_event_check(serial_t *obj);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 static int serial_is_tx_complete(serial_t *obj);
<> 144:ef7eb2e8f9f7 79 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
<> 144:ef7eb2e8f9f7 82 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
<> 144:ef7eb2e8f9f7 83 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
<> 144:ef7eb2e8f9f7 84 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 144:ef7eb2e8f9f7 85 static int serial_is_rx_complete(serial_t *obj);
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
<> 144:ef7eb2e8f9f7 88 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
<> 144:ef7eb2e8f9f7 89 #endif
<> 144:ef7eb2e8f9f7 90
AnnaBridge 188:bcfe06ba3d64 91 bool serial_can_deep_sleep(void);
AnnaBridge 188:bcfe06ba3d64 92
<> 144:ef7eb2e8f9f7 93 static struct nu_uart_var uart0_var = {
<> 151:5eaa88a5bcc7 94 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 95 .obj = NULL,
<> 144:ef7eb2e8f9f7 96 .fifo_size_tx = 64,
<> 144:ef7eb2e8f9f7 97 .fifo_size_rx = 64,
<> 144:ef7eb2e8f9f7 98 .vec = uart0_vec,
<> 144:ef7eb2e8f9f7 99 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 100 .vec_async = uart0_vec_async,
<> 144:ef7eb2e8f9f7 101 .pdma_perp_tx = PDMA_UART0_TX,
<> 144:ef7eb2e8f9f7 102 .pdma_perp_rx = PDMA_UART0_RX
<> 144:ef7eb2e8f9f7 103 #endif
<> 144:ef7eb2e8f9f7 104 };
<> 144:ef7eb2e8f9f7 105 static struct nu_uart_var uart1_var = {
<> 151:5eaa88a5bcc7 106 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 107 .obj = NULL,
<> 144:ef7eb2e8f9f7 108 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 109 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 110 .vec = uart1_vec,
<> 144:ef7eb2e8f9f7 111 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 112 .vec_async = uart1_vec_async,
<> 144:ef7eb2e8f9f7 113 .pdma_perp_tx = PDMA_UART1_TX,
<> 144:ef7eb2e8f9f7 114 .pdma_perp_rx = PDMA_UART1_RX
<> 144:ef7eb2e8f9f7 115 #endif
<> 144:ef7eb2e8f9f7 116 };
<> 144:ef7eb2e8f9f7 117 static struct nu_uart_var uart2_var = {
<> 151:5eaa88a5bcc7 118 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 119 .obj = NULL,
<> 144:ef7eb2e8f9f7 120 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 121 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 122 .vec = uart2_vec,
<> 144:ef7eb2e8f9f7 123 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 124 .vec_async = uart2_vec_async,
<> 144:ef7eb2e8f9f7 125 .pdma_perp_tx = PDMA_UART2_TX,
<> 144:ef7eb2e8f9f7 126 .pdma_perp_rx = PDMA_UART2_RX
<> 144:ef7eb2e8f9f7 127 #endif
<> 144:ef7eb2e8f9f7 128 };
<> 144:ef7eb2e8f9f7 129 static struct nu_uart_var uart3_var = {
<> 151:5eaa88a5bcc7 130 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 131 .obj = NULL,
<> 144:ef7eb2e8f9f7 132 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 133 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 134 .vec = uart3_vec,
<> 144:ef7eb2e8f9f7 135 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 136 .vec_async = uart3_vec_async,
<> 144:ef7eb2e8f9f7 137 .pdma_perp_tx = PDMA_UART3_TX,
<> 144:ef7eb2e8f9f7 138 .pdma_perp_rx = PDMA_UART3_RX
<> 144:ef7eb2e8f9f7 139 #endif
<> 144:ef7eb2e8f9f7 140 };
<> 144:ef7eb2e8f9f7 141 static struct nu_uart_var uart4_var = {
<> 151:5eaa88a5bcc7 142 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 143 .obj = NULL,
<> 144:ef7eb2e8f9f7 144 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 145 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 146 .vec = uart4_vec,
<> 144:ef7eb2e8f9f7 147 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 148 .vec_async = uart4_vec_async,
<> 144:ef7eb2e8f9f7 149 .pdma_perp_tx = PDMA_UART4_TX,
<> 144:ef7eb2e8f9f7 150 .pdma_perp_rx = PDMA_UART4_RX
<> 144:ef7eb2e8f9f7 151 #endif
<> 144:ef7eb2e8f9f7 152 };
<> 144:ef7eb2e8f9f7 153 static struct nu_uart_var uart5_var = {
<> 151:5eaa88a5bcc7 154 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 155 .obj = NULL,
<> 144:ef7eb2e8f9f7 156 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 157 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 158 .vec = uart5_vec,
<> 144:ef7eb2e8f9f7 159 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 160 .vec_async = uart5_vec_async,
<> 144:ef7eb2e8f9f7 161 .pdma_perp_tx = PDMA_UART5_TX,
<> 144:ef7eb2e8f9f7 162 .pdma_perp_rx = PDMA_UART5_RX
<> 144:ef7eb2e8f9f7 163 #endif
<> 144:ef7eb2e8f9f7 164 };
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 int stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 168 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 169 static uint32_t uart_modinit_mask = 0;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 static const struct nu_modinit_s uart_modinit_tab[] = {
<> 144:ef7eb2e8f9f7 172 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
<> 144:ef7eb2e8f9f7 173 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
<> 144:ef7eb2e8f9f7 174 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
<> 144:ef7eb2e8f9f7 175 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
<> 144:ef7eb2e8f9f7 176 {UART_4, UART4_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART4_RST, UART4_IRQn, &uart4_var},
<> 144:ef7eb2e8f9f7 177 {UART_5, UART5_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART5_RST, UART5_IRQn, &uart5_var},
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 144:ef7eb2e8f9f7 180 };
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 extern void mbed_sdk_init(void);
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 185 {
<> 151:5eaa88a5bcc7 186 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
<> 144:ef7eb2e8f9f7 187 mbed_sdk_init();
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 // Determine which UART_x the pins are used for
<> 144:ef7eb2e8f9f7 190 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 191 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 192 // Get the peripheral name (UART_x) from the pins and assign it to the object
<> 144:ef7eb2e8f9f7 193 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
<> 144:ef7eb2e8f9f7 194 MBED_ASSERT((int)obj->serial.uart != NC);
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 197 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 198 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 199
<> 151:5eaa88a5bcc7 200 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 201
<> 151:5eaa88a5bcc7 202 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 203 // Reset this module
<> 151:5eaa88a5bcc7 204 SYS_ResetModule(modinit->rsetidx);
AnnaBridge 189:f392fc9709a3 205
<> 151:5eaa88a5bcc7 206 // Select IP clock source
<> 151:5eaa88a5bcc7 207 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
<> 151:5eaa88a5bcc7 208 // Enable IP clock
<> 151:5eaa88a5bcc7 209 CLK_EnableModuleClock(modinit->clkidx);
<> 144:ef7eb2e8f9f7 210
<> 151:5eaa88a5bcc7 211 pinmap_pinout(tx, PinMap_UART_TX);
<> 151:5eaa88a5bcc7 212 pinmap_pinout(rx, PinMap_UART_RX);
AnnaBridge 189:f392fc9709a3 213
AnnaBridge 189:f392fc9709a3 214 // Configure baudrate
AnnaBridge 189:f392fc9709a3 215 int baudrate = 9600;
AnnaBridge 189:f392fc9709a3 216 if (obj->serial.uart == STDIO_UART) {
AnnaBridge 189:f392fc9709a3 217 #if MBED_CONF_PLATFORM_STDIO_BAUD_RATE
AnnaBridge 189:f392fc9709a3 218 baudrate = MBED_CONF_PLATFORM_STDIO_BAUD_RATE;
AnnaBridge 189:f392fc9709a3 219 #endif
AnnaBridge 189:f392fc9709a3 220 } else {
AnnaBridge 189:f392fc9709a3 221 #if MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE
AnnaBridge 189:f392fc9709a3 222 baudrate = MBED_CONF_PLATFORM_DEFAULT_SERIAL_BAUD_RATE;
AnnaBridge 189:f392fc9709a3 223 #endif
AnnaBridge 189:f392fc9709a3 224 }
AnnaBridge 189:f392fc9709a3 225 serial_baud(obj, baudrate);
AnnaBridge 189:f392fc9709a3 226
AnnaBridge 189:f392fc9709a3 227 // Configure data bits, parity, and stop bits
AnnaBridge 189:f392fc9709a3 228 serial_format(obj, 8, ParityNone, 1);
<> 151:5eaa88a5bcc7 229 }
<> 151:5eaa88a5bcc7 230 var->ref_cnt ++;
AnnaBridge 189:f392fc9709a3 231
<> 151:5eaa88a5bcc7 232 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 233 obj->serial.irq_en = 0;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 236 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 237 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 238 obj->serial.event = 0;
<> 144:ef7eb2e8f9f7 239 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 240 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 241 #endif
<> 144:ef7eb2e8f9f7 242
AnnaBridge 189:f392fc9709a3 243 /* With support for checking H/W UART initialized or not, we allow serial_init(&stdio_uart)
AnnaBridge 189:f392fc9709a3 244 * calls in even though H/W UART 'STDIO_UART' has initialized. When serial_init(&stdio_uart)
AnnaBridge 189:f392fc9709a3 245 * calls in, we only need to set the 'stdio_uart_inited' flag. */
AnnaBridge 189:f392fc9709a3 246 if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) {
AnnaBridge 189:f392fc9709a3 247 MBED_ASSERT(obj->serial.uart == STDIO_UART);
<> 144:ef7eb2e8f9f7 248 stdio_uart_inited = 1;
<> 144:ef7eb2e8f9f7 249 }
AnnaBridge 189:f392fc9709a3 250
<> 151:5eaa88a5bcc7 251 if (var->ref_cnt) {
<> 151:5eaa88a5bcc7 252 // Mark this module to be inited.
<> 151:5eaa88a5bcc7 253 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 254 uart_modinit_mask |= 1 << i;
<> 151:5eaa88a5bcc7 255 }
<> 144:ef7eb2e8f9f7 256 }
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 void serial_free(serial_t *obj)
<> 144:ef7eb2e8f9f7 259 {
<> 144:ef7eb2e8f9f7 260 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 261 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 262 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 263
<> 151:5eaa88a5bcc7 264 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 265
<> 151:5eaa88a5bcc7 266 var->ref_cnt --;
<> 151:5eaa88a5bcc7 267 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 268 #if DEVICE_SERIAL_ASYNCH
<> 151:5eaa88a5bcc7 269 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 270 dma_channel_free(obj->serial.dma_chn_id_tx);
<> 151:5eaa88a5bcc7 271 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 272 }
<> 151:5eaa88a5bcc7 273 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 274 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 151:5eaa88a5bcc7 275 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 276 }
<> 151:5eaa88a5bcc7 277 #endif
<> 151:5eaa88a5bcc7 278
<> 151:5eaa88a5bcc7 279 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
<> 144:ef7eb2e8f9f7 280
<> 151:5eaa88a5bcc7 281 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 151:5eaa88a5bcc7 282 NVIC_DisableIRQ(modinit->irq_n);
<> 144:ef7eb2e8f9f7 283
<> 151:5eaa88a5bcc7 284 // Disable IP clock
<> 151:5eaa88a5bcc7 285 CLK_DisableModuleClock(modinit->clkidx);
<> 151:5eaa88a5bcc7 286 }
<> 151:5eaa88a5bcc7 287
<> 151:5eaa88a5bcc7 288 if (var->obj == obj) {
<> 151:5eaa88a5bcc7 289 var->obj = NULL;
<> 151:5eaa88a5bcc7 290 }
AnnaBridge 189:f392fc9709a3 291
AnnaBridge 189:f392fc9709a3 292 /* Clear the 'stdio_uart_inited' flag when serial_free(&stdio_uart) calls in. */
AnnaBridge 189:f392fc9709a3 293 if (((uintptr_t) obj) == ((uintptr_t) &stdio_uart)) {
AnnaBridge 189:f392fc9709a3 294 MBED_ASSERT(obj->serial.uart == STDIO_UART);
<> 144:ef7eb2e8f9f7 295 stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 296 }
AnnaBridge 189:f392fc9709a3 297
<> 151:5eaa88a5bcc7 298 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 299 // Mark this module to be deinited.
<> 151:5eaa88a5bcc7 300 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 301 uart_modinit_mask &= ~(1 << i);
<> 151:5eaa88a5bcc7 302 }
<> 144:ef7eb2e8f9f7 303 }
<> 144:ef7eb2e8f9f7 304
<> 144:ef7eb2e8f9f7 305 void serial_baud(serial_t *obj, int baudrate) {
<> 144:ef7eb2e8f9f7 306 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 307 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 obj->serial.baudrate = baudrate;
<> 144:ef7eb2e8f9f7 310 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
<> 144:ef7eb2e8f9f7 311 }
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
<> 144:ef7eb2e8f9f7 314 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 315 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 316
AnnaBridge 172:7d866c31b3c5 317 // Sanity check arguments
AnnaBridge 172:7d866c31b3c5 318 MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
AnnaBridge 172:7d866c31b3c5 319 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
AnnaBridge 172:7d866c31b3c5 320 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
AnnaBridge 172:7d866c31b3c5 321
<> 144:ef7eb2e8f9f7 322 obj->serial.databits = data_bits;
<> 144:ef7eb2e8f9f7 323 obj->serial.parity = parity;
<> 144:ef7eb2e8f9f7 324 obj->serial.stopbits = stop_bits;
<> 144:ef7eb2e8f9f7 325
<> 144:ef7eb2e8f9f7 326 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
<> 144:ef7eb2e8f9f7 327 (data_bits == 6) ? UART_WORD_LEN_6 :
<> 144:ef7eb2e8f9f7 328 (data_bits == 7) ? UART_WORD_LEN_7 :
<> 144:ef7eb2e8f9f7 329 UART_WORD_LEN_8;
<> 144:ef7eb2e8f9f7 330 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
<> 144:ef7eb2e8f9f7 331 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
<> 144:ef7eb2e8f9f7 332 UART_PARITY_NONE;
<> 144:ef7eb2e8f9f7 333 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
<> 144:ef7eb2e8f9f7 334 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
<> 144:ef7eb2e8f9f7 335 0, // Don't change baudrate
<> 144:ef7eb2e8f9f7 336 databits_intern,
<> 144:ef7eb2e8f9f7 337 parity_intern,
<> 144:ef7eb2e8f9f7 338 stopbits_intern);
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 #if DEVICE_SERIAL_FC
<> 144:ef7eb2e8f9f7 342
<> 144:ef7eb2e8f9f7 343 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 346
AnnaBridge 189:f392fc9709a3 347 if (rxflow != NC) {
<> 144:ef7eb2e8f9f7 348 // Check if RTS pin matches.
<> 144:ef7eb2e8f9f7 349 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 350 MBED_ASSERT(uart_rts == obj->serial.uart);
<> 144:ef7eb2e8f9f7 351 // Enable the pin for RTS function
<> 144:ef7eb2e8f9f7 352 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 153:fa9ff456f731 353 // nRTS pin output is low level active
<> 153:fa9ff456f731 354 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
AnnaBridge 189:f392fc9709a3 355 // Configure RTS trigger level to 8 bytes
<> 144:ef7eb2e8f9f7 356 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
AnnaBridge 189:f392fc9709a3 357
AnnaBridge 189:f392fc9709a3 358 if (type == FlowControlRTS || type == FlowControlRTSCTS) {
AnnaBridge 189:f392fc9709a3 359 // Enable RTS
AnnaBridge 189:f392fc9709a3 360 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
AnnaBridge 189:f392fc9709a3 361 } else {
AnnaBridge 189:f392fc9709a3 362 // Disable RTS
AnnaBridge 189:f392fc9709a3 363 uart_base->INTEN &= ~UART_INTEN_ATORTSEN_Msk;
AnnaBridge 189:f392fc9709a3 364 /* Drive nRTS pin output to low-active. Allow the peer to be able to send data
AnnaBridge 189:f392fc9709a3 365 * even though its CTS is still enabled. */
AnnaBridge 189:f392fc9709a3 366 uart_base->MODEM &= ~UART_MODEM_RTS_Msk;
AnnaBridge 189:f392fc9709a3 367 }
<> 144:ef7eb2e8f9f7 368 }
AnnaBridge 189:f392fc9709a3 369
AnnaBridge 189:f392fc9709a3 370 /* If CTS is disabled, we don't need to configure CTS. But to be consistent with
AnnaBridge 189:f392fc9709a3 371 * RTS code above, we still configure CTS. */
AnnaBridge 189:f392fc9709a3 372 if (txflow != NC) {
<> 144:ef7eb2e8f9f7 373 // Check if CTS pin matches.
<> 144:ef7eb2e8f9f7 374 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 375 MBED_ASSERT(uart_cts == obj->serial.uart);
<> 144:ef7eb2e8f9f7 376 // Enable the pin for CTS function
<> 144:ef7eb2e8f9f7 377 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 153:fa9ff456f731 378 // nCTS pin input is low level active
<> 153:fa9ff456f731 379 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
AnnaBridge 189:f392fc9709a3 380
AnnaBridge 189:f392fc9709a3 381 if (type == FlowControlCTS || type == FlowControlRTSCTS) {
AnnaBridge 189:f392fc9709a3 382 // Enable CTS
AnnaBridge 189:f392fc9709a3 383 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
AnnaBridge 189:f392fc9709a3 384 } else {
AnnaBridge 189:f392fc9709a3 385 // Disable CTS
AnnaBridge 189:f392fc9709a3 386 uart_base->INTEN &= ~UART_INTEN_ATOCTSEN_Msk;
AnnaBridge 189:f392fc9709a3 387 }
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389 }
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 #endif //DEVICE_SERIAL_FC
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 394 {
<> 144:ef7eb2e8f9f7 395 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 396 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 397
<> 144:ef7eb2e8f9f7 398 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 399 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 400 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 obj->serial.irq_handler = (uint32_t) handler;
<> 144:ef7eb2e8f9f7 403 obj->serial.irq_id = id;
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 // Restore sync-mode vector
<> 144:ef7eb2e8f9f7 406 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
<> 144:ef7eb2e8f9f7 407 }
<> 144:ef7eb2e8f9f7 408
<> 144:ef7eb2e8f9f7 409 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 144:ef7eb2e8f9f7 410 {
AnnaBridge 165:e614a9f1c9e2 411 obj->serial.irq_en = enable;
AnnaBridge 165:e614a9f1c9e2 412 serial_enable_interrupt(obj, irq, enable);
<> 144:ef7eb2e8f9f7 413 }
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 int serial_getc(serial_t *obj)
<> 144:ef7eb2e8f9f7 416 {
AnnaBridge 165:e614a9f1c9e2 417 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 144:ef7eb2e8f9f7 418 while (! serial_readable(obj));
<> 144:ef7eb2e8f9f7 419 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 420
AnnaBridge 165:e614a9f1c9e2 421 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 422 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 144:ef7eb2e8f9f7 423 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 144:ef7eb2e8f9f7 424 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 425 }
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 return c;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429
<> 144:ef7eb2e8f9f7 430 void serial_putc(serial_t *obj, int c)
<> 144:ef7eb2e8f9f7 431 {
AnnaBridge 165:e614a9f1c9e2 432 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 144:ef7eb2e8f9f7 433 while (! serial_writable(obj));
<> 144:ef7eb2e8f9f7 434 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
<> 144:ef7eb2e8f9f7 435
AnnaBridge 165:e614a9f1c9e2 436 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 437 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 144:ef7eb2e8f9f7 438 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 144:ef7eb2e8f9f7 439 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 440 }
<> 144:ef7eb2e8f9f7 441 }
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 int serial_readable(serial_t *obj)
<> 144:ef7eb2e8f9f7 444 {
<> 144:ef7eb2e8f9f7 445 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 446 return ! (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk);
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 int serial_writable(serial_t *obj)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 void serial_pinout_tx(PinName tx)
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 void serial_break_set(serial_t *obj)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 void serial_break_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 static void uart0_vec(void)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 uart_irq(uart0_var.obj);
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 static void uart1_vec(void)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 uart_irq(uart1_var.obj);
<> 144:ef7eb2e8f9f7 477 }
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 static void uart2_vec(void)
<> 144:ef7eb2e8f9f7 480 {
<> 144:ef7eb2e8f9f7 481 uart_irq(uart2_var.obj);
<> 144:ef7eb2e8f9f7 482 }
<> 144:ef7eb2e8f9f7 483
<> 144:ef7eb2e8f9f7 484 static void uart3_vec(void)
<> 144:ef7eb2e8f9f7 485 {
<> 144:ef7eb2e8f9f7 486 uart_irq(uart3_var.obj);
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 static void uart4_vec(void)
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 uart_irq(uart4_var.obj);
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 static void uart5_vec(void)
<> 144:ef7eb2e8f9f7 495 {
<> 144:ef7eb2e8f9f7 496 uart_irq(uart5_var.obj);
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499 static void uart_irq(serial_t *obj)
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 144:ef7eb2e8f9f7 504 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 144:ef7eb2e8f9f7 505 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 506 if (obj->serial.irq_handler) {
<> 144:ef7eb2e8f9f7 507 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
<> 144:ef7eb2e8f9f7 508 }
<> 144:ef7eb2e8f9f7 509 }
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 144:ef7eb2e8f9f7 512 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 144:ef7eb2e8f9f7 513 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 514 if (obj->serial.irq_handler) {
<> 144:ef7eb2e8f9f7 515 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
<> 144:ef7eb2e8f9f7 516 }
<> 144:ef7eb2e8f9f7 517 }
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
<> 144:ef7eb2e8f9f7 520 uart_base->INTSTS = uart_base->INTSTS;
<> 144:ef7eb2e8f9f7 521 uart_base->FIFOSTS = uart_base->FIFOSTS;
<> 144:ef7eb2e8f9f7 522 }
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524
<> 144:ef7eb2e8f9f7 525 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 526 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 144:ef7eb2e8f9f7 527 {
<> 144:ef7eb2e8f9f7 528 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
<> 144:ef7eb2e8f9f7 529
<> 144:ef7eb2e8f9f7 530 obj->serial.dma_usage_tx = hint;
<> 144:ef7eb2e8f9f7 531 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 // UART IRQ is necessary for both interrupt way and DMA way
<> 144:ef7eb2e8f9f7 534 serial_tx_enable_event(obj, event, 1);
<> 144:ef7eb2e8f9f7 535 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
<> 144:ef7eb2e8f9f7 536 //UART_HAL_DisableTransmitter(obj->serial.address);
<> 144:ef7eb2e8f9f7 537 //UART_HAL_FlushTxFifo(obj->serial.address);
<> 144:ef7eb2e8f9f7 538 //UART_HAL_EnableTransmitter(obj->serial.address);
<> 144:ef7eb2e8f9f7 539
<> 144:ef7eb2e8f9f7 540 int n_word = 0;
<> 144:ef7eb2e8f9f7 541 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 542 // Interrupt way
<> 144:ef7eb2e8f9f7 543 n_word = serial_write_async(obj);
<> 144:ef7eb2e8f9f7 544 serial_tx_enable_interrupt(obj, handler, 1);
<> 144:ef7eb2e8f9f7 545 } else {
<> 144:ef7eb2e8f9f7 546 // DMA way
<> 144:ef7eb2e8f9f7 547 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 548 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 549 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 550
<> 161:2cc1468da177 551 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 552
<> 161:2cc1468da177 553 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
<> 144:ef7eb2e8f9f7 554 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 555 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
<> 144:ef7eb2e8f9f7 556 0, // Scatter-gather disabled
<> 144:ef7eb2e8f9f7 557 0); // Scatter-gather descriptor address
<> 144:ef7eb2e8f9f7 558 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 559 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 144:ef7eb2e8f9f7 560 tx_length);
<> 144:ef7eb2e8f9f7 561 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 562 ((uint32_t) tx) + (tx_width / 8) * tx_length, // NOTE: End of source address
<> 144:ef7eb2e8f9f7 563 PDMA_SAR_INC, // Source address incremental
<> 161:2cc1468da177 564 (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
<> 144:ef7eb2e8f9f7 565 PDMA_DAR_FIX); // Destination address fixed
<> 144:ef7eb2e8f9f7 566 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 567 PDMA_REQ_SINGLE, // Single mode
<> 144:ef7eb2e8f9f7 568 0); // Burst size
<> 144:ef7eb2e8f9f7 569 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 570 0); // Interrupt type. No use here
<> 144:ef7eb2e8f9f7 571 // Register DMA event handler
<> 144:ef7eb2e8f9f7 572 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
<> 144:ef7eb2e8f9f7 573 serial_tx_enable_interrupt(obj, handler, 1);
AnnaBridge 184:08ed48f1de7f 574 /* We needn't actually enable UART INT to go UART ISR -> handler.
AnnaBridge 184:08ed48f1de7f 575 * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
AnnaBridge 184:08ed48f1de7f 576 * with serial_tx/rx_enable_interrupt having set up this call path. */
AnnaBridge 184:08ed48f1de7f 577 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 578 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580
<> 144:ef7eb2e8f9f7 581 return n_word;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
<> 144:ef7eb2e8f9f7 585 {
<> 144:ef7eb2e8f9f7 586 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
<> 144:ef7eb2e8f9f7 587
<> 144:ef7eb2e8f9f7 588 obj->serial.dma_usage_rx = hint;
<> 144:ef7eb2e8f9f7 589 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
<> 144:ef7eb2e8f9f7 590 // DMA doesn't support char match, so fall back to IRQ if it is requested.
<> 144:ef7eb2e8f9f7 591 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
<> 144:ef7eb2e8f9f7 592 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 144:ef7eb2e8f9f7 593 char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 144:ef7eb2e8f9f7 594 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 595 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 144:ef7eb2e8f9f7 596 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598
<> 144:ef7eb2e8f9f7 599 // UART IRQ is necessary for both interrupt way and DMA way
<> 144:ef7eb2e8f9f7 600 serial_rx_enable_event(obj, event, 1);
<> 144:ef7eb2e8f9f7 601 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
<> 144:ef7eb2e8f9f7 602 serial_rx_set_char_match(obj, char_match);
<> 144:ef7eb2e8f9f7 603 //UART_HAL_DisableReceiver(obj->serial.address);
<> 144:ef7eb2e8f9f7 604 //UART_HAL_FlushRxFifo(obj->serial.address);
<> 144:ef7eb2e8f9f7 605 //UART_HAL_EnableReceiver(obj->serial.address);
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 608 // Interrupt way
<> 144:ef7eb2e8f9f7 609 serial_rx_enable_interrupt(obj, handler, 1);
<> 144:ef7eb2e8f9f7 610 } else {
<> 144:ef7eb2e8f9f7 611 // DMA way
<> 144:ef7eb2e8f9f7 612 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 613 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 614 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 615
<> 161:2cc1468da177 616 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 617
<> 161:2cc1468da177 618 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
<> 144:ef7eb2e8f9f7 619 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 620 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
<> 144:ef7eb2e8f9f7 621 0, // Scatter-gather disabled
<> 144:ef7eb2e8f9f7 622 0); // Scatter-gather descriptor address
<> 144:ef7eb2e8f9f7 623 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 624 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 144:ef7eb2e8f9f7 625 rx_length);
<> 144:ef7eb2e8f9f7 626 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
<> 161:2cc1468da177 627 (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
<> 144:ef7eb2e8f9f7 628 PDMA_SAR_FIX, // Source address fixed
<> 144:ef7eb2e8f9f7 629 ((uint32_t) rx) + (rx_width / 8) * rx_length, // NOTE: End of destination address
<> 144:ef7eb2e8f9f7 630 PDMA_DAR_INC); // Destination address incremental
<> 144:ef7eb2e8f9f7 631 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 632 PDMA_REQ_SINGLE, // Single mode
<> 144:ef7eb2e8f9f7 633 0); // Burst size
<> 144:ef7eb2e8f9f7 634 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 635 0); // Interrupt type. No use here
<> 144:ef7eb2e8f9f7 636 // Register DMA event handler
<> 144:ef7eb2e8f9f7 637 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
<> 144:ef7eb2e8f9f7 638 serial_rx_enable_interrupt(obj, handler, 1);
AnnaBridge 184:08ed48f1de7f 639 /* We needn't actually enable UART INT to go UART ISR -> handler.
AnnaBridge 184:08ed48f1de7f 640 * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
AnnaBridge 184:08ed48f1de7f 641 * with serial_tx/rx_enable_interrupt having set up this call path. */
AnnaBridge 184:08ed48f1de7f 642 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 643 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
<> 144:ef7eb2e8f9f7 644 }
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 void serial_tx_abort_asynch(serial_t *obj)
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 650 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 651
<> 144:ef7eb2e8f9f7 652 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 653 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 654
<> 144:ef7eb2e8f9f7 655 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 656 PDMA_DisableInt(obj->serial.dma_chn_id_tx, 0);
<> 144:ef7eb2e8f9f7 657 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 144:ef7eb2e8f9f7 658 //PDMA_STOP(obj->serial.dma_chn_id_tx);
<> 161:2cc1468da177 659 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663
<> 144:ef7eb2e8f9f7 664 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 665 serial_enable_interrupt(obj, TxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 666 serial_rollback_interrupt(obj, TxIrq);
<> 144:ef7eb2e8f9f7 667 }
<> 144:ef7eb2e8f9f7 668
<> 144:ef7eb2e8f9f7 669 void serial_rx_abort_asynch(serial_t *obj)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 672 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 673
<> 144:ef7eb2e8f9f7 674 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 675 PDMA_DisableInt(obj->serial.dma_chn_id_rx, 0);
<> 144:ef7eb2e8f9f7 676 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 144:ef7eb2e8f9f7 677 //PDMA_STOP(obj->serial.dma_chn_id_rx);
<> 161:2cc1468da177 678 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
<> 144:ef7eb2e8f9f7 681 }
<> 144:ef7eb2e8f9f7 682
<> 144:ef7eb2e8f9f7 683 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 684 serial_enable_interrupt(obj, RxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 685 serial_rollback_interrupt(obj, RxIrq);
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687
<> 144:ef7eb2e8f9f7 688 uint8_t serial_tx_active(serial_t *obj)
<> 144:ef7eb2e8f9f7 689 {
AnnaBridge 165:e614a9f1c9e2 690 // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 691 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 692 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 693 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 694
AnnaBridge 165:e614a9f1c9e2 695 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 696 return (obj->serial.vec == var->vec_async);
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 uint8_t serial_rx_active(serial_t *obj)
<> 144:ef7eb2e8f9f7 700 {
AnnaBridge 165:e614a9f1c9e2 701 // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 702 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 703 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 704 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 705
AnnaBridge 165:e614a9f1c9e2 706 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 707 return (obj->serial.vec == var->vec_async);
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 int serial_irq_handler_asynch(serial_t *obj)
<> 144:ef7eb2e8f9f7 711 {
<> 144:ef7eb2e8f9f7 712 int event_rx = 0;
<> 144:ef7eb2e8f9f7 713 int event_tx = 0;
<> 144:ef7eb2e8f9f7 714
<> 151:5eaa88a5bcc7 715 // Necessary for both interrupt way and DMA way
<> 144:ef7eb2e8f9f7 716 if (serial_is_irq_en(obj, RxIrq)) {
<> 144:ef7eb2e8f9f7 717 event_rx = serial_rx_event_check(obj);
<> 144:ef7eb2e8f9f7 718 if (event_rx) {
<> 144:ef7eb2e8f9f7 719 serial_rx_abort_asynch(obj);
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 if (serial_is_irq_en(obj, TxIrq)) {
<> 144:ef7eb2e8f9f7 724 event_tx = serial_tx_event_check(obj);
<> 144:ef7eb2e8f9f7 725 if (event_tx) {
<> 144:ef7eb2e8f9f7 726 serial_tx_abort_asynch(obj);
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729
<> 144:ef7eb2e8f9f7 730 return (obj->serial.event & (event_rx | event_tx));
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 static void uart0_vec_async(void)
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 uart_irq_async(uart0_var.obj);
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 static void uart1_vec_async(void)
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 uart_irq_async(uart1_var.obj);
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742
<> 144:ef7eb2e8f9f7 743 static void uart2_vec_async(void)
<> 144:ef7eb2e8f9f7 744 {
<> 144:ef7eb2e8f9f7 745 uart_irq_async(uart2_var.obj);
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 static void uart3_vec_async(void)
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 uart_irq_async(uart3_var.obj);
<> 144:ef7eb2e8f9f7 751 }
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 static void uart4_vec_async(void)
<> 144:ef7eb2e8f9f7 754 {
<> 144:ef7eb2e8f9f7 755 uart_irq_async(uart4_var.obj);
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 static void uart5_vec_async(void)
<> 144:ef7eb2e8f9f7 759 {
<> 144:ef7eb2e8f9f7 760 uart_irq_async(uart5_var.obj);
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 static void uart_irq_async(serial_t *obj)
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 if (serial_is_irq_en(obj, RxIrq)) {
<> 144:ef7eb2e8f9f7 766 (*obj->serial.irq_handler_rx_async)();
<> 144:ef7eb2e8f9f7 767 }
<> 144:ef7eb2e8f9f7 768 if (serial_is_irq_en(obj, TxIrq)) {
<> 144:ef7eb2e8f9f7 769 (*obj->serial.irq_handler_tx_async)();
<> 144:ef7eb2e8f9f7 770 }
<> 144:ef7eb2e8f9f7 771 }
<> 144:ef7eb2e8f9f7 772
<> 144:ef7eb2e8f9f7 773 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
<> 144:ef7eb2e8f9f7 774 {
<> 144:ef7eb2e8f9f7 775 obj->char_match = char_match;
<> 144:ef7eb2e8f9f7 776 obj->char_found = 0;
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 144:ef7eb2e8f9f7 780 {
<> 144:ef7eb2e8f9f7 781 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
<> 144:ef7eb2e8f9f7 782 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
<> 144:ef7eb2e8f9f7 783
<> 144:ef7eb2e8f9f7 784 //if (event & SERIAL_EVENT_TX_COMPLETE) {
<> 144:ef7eb2e8f9f7 785 //}
<> 144:ef7eb2e8f9f7 786 }
<> 144:ef7eb2e8f9f7 787
<> 144:ef7eb2e8f9f7 788 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 144:ef7eb2e8f9f7 789 {
<> 144:ef7eb2e8f9f7 790 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
<> 144:ef7eb2e8f9f7 791 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 //if (event & SERIAL_EVENT_RX_COMPLETE) {
<> 144:ef7eb2e8f9f7 794 //}
<> 144:ef7eb2e8f9f7 795 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
<> 144:ef7eb2e8f9f7 796 //}
<> 144:ef7eb2e8f9f7 797 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
<> 144:ef7eb2e8f9f7 798 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 144:ef7eb2e8f9f7 799 }
<> 144:ef7eb2e8f9f7 800 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
<> 144:ef7eb2e8f9f7 801 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803 if (event & SERIAL_EVENT_RX_OVERFLOW) {
<> 144:ef7eb2e8f9f7 804 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
<> 144:ef7eb2e8f9f7 805 }
<> 144:ef7eb2e8f9f7 806 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
<> 144:ef7eb2e8f9f7 807 //}
<> 144:ef7eb2e8f9f7 808 }
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 static int serial_is_tx_complete(serial_t *obj)
<> 144:ef7eb2e8f9f7 811 {
<> 144:ef7eb2e8f9f7 812 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
<> 144:ef7eb2e8f9f7 813 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 814 // FIXME: Premature abort???
<> 144:ef7eb2e8f9f7 815 return (obj->tx_buff.pos == obj->tx_buff.length);
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 static int serial_is_rx_complete(serial_t *obj)
<> 144:ef7eb2e8f9f7 819 {
<> 144:ef7eb2e8f9f7 820 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 821 return (obj->rx_buff.pos == obj->rx_buff.length);
<> 144:ef7eb2e8f9f7 822 }
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 static uint32_t serial_tx_event_check(serial_t *obj)
<> 144:ef7eb2e8f9f7 825 {
<> 144:ef7eb2e8f9f7 826 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 144:ef7eb2e8f9f7 829 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 144:ef7eb2e8f9f7 830 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 831 }
<> 144:ef7eb2e8f9f7 832
<> 144:ef7eb2e8f9f7 833 uint32_t event = 0;
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 836 serial_write_async(obj);
<> 144:ef7eb2e8f9f7 837 }
<> 144:ef7eb2e8f9f7 838
<> 144:ef7eb2e8f9f7 839 if (serial_is_tx_complete(obj)) {
<> 144:ef7eb2e8f9f7 840 event |= SERIAL_EVENT_TX_COMPLETE;
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842
<> 144:ef7eb2e8f9f7 843 return event;
<> 144:ef7eb2e8f9f7 844 }
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 static uint32_t serial_rx_event_check(serial_t *obj)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 144:ef7eb2e8f9f7 851 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 144:ef7eb2e8f9f7 852 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 853 }
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 uint32_t event = 0;
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
<> 144:ef7eb2e8f9f7 858 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
<> 144:ef7eb2e8f9f7 859 }
<> 144:ef7eb2e8f9f7 860 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
<> 144:ef7eb2e8f9f7 861 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
<> 144:ef7eb2e8f9f7 862 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
<> 144:ef7eb2e8f9f7 865 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
<> 144:ef7eb2e8f9f7 866 event |= SERIAL_EVENT_RX_PARITY_ERROR;
<> 144:ef7eb2e8f9f7 867 }
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
<> 144:ef7eb2e8f9f7 870 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
<> 144:ef7eb2e8f9f7 871 event |= SERIAL_EVENT_RX_OVERFLOW;
<> 144:ef7eb2e8f9f7 872 }
<> 144:ef7eb2e8f9f7 873
<> 144:ef7eb2e8f9f7 874 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 875 serial_read_async(obj);
<> 144:ef7eb2e8f9f7 876 }
<> 144:ef7eb2e8f9f7 877
<> 144:ef7eb2e8f9f7 878 if (serial_is_rx_complete(obj)) {
<> 144:ef7eb2e8f9f7 879 event |= SERIAL_EVENT_RX_COMPLETE;
<> 144:ef7eb2e8f9f7 880 }
<> 144:ef7eb2e8f9f7 881 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
<> 144:ef7eb2e8f9f7 882 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
<> 144:ef7eb2e8f9f7 883 // FIXME: Timing to reset char_found?
<> 144:ef7eb2e8f9f7 884 //obj->char_found = 0;
<> 144:ef7eb2e8f9f7 885 }
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 return event;
<> 144:ef7eb2e8f9f7 888 }
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
<> 144:ef7eb2e8f9f7 891 {
<> 144:ef7eb2e8f9f7 892 serial_t *obj = (serial_t *) id;
<> 144:ef7eb2e8f9f7 893
<> 144:ef7eb2e8f9f7 894 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 895 if (event_dma & DMA_EVENT_ABORT) {
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897 // Expect UART IRQ will catch this transfer done event
<> 144:ef7eb2e8f9f7 898 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 144:ef7eb2e8f9f7 899 obj->tx_buff.pos = obj->tx_buff.length;
<> 144:ef7eb2e8f9f7 900 }
<> 144:ef7eb2e8f9f7 901 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 902 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 144:ef7eb2e8f9f7 903 }
<> 144:ef7eb2e8f9f7 904
<> 144:ef7eb2e8f9f7 905 uart_irq_async(obj);
<> 144:ef7eb2e8f9f7 906 }
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 serial_t *obj = (serial_t *) id;
<> 144:ef7eb2e8f9f7 911
<> 144:ef7eb2e8f9f7 912 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 913 if (event_dma & DMA_EVENT_ABORT) {
<> 144:ef7eb2e8f9f7 914 }
<> 144:ef7eb2e8f9f7 915 // Expect UART IRQ will catch this transfer done event
<> 144:ef7eb2e8f9f7 916 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 144:ef7eb2e8f9f7 917 obj->rx_buff.pos = obj->rx_buff.length;
<> 144:ef7eb2e8f9f7 918 }
<> 144:ef7eb2e8f9f7 919 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 920 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 uart_irq_async(obj);
<> 144:ef7eb2e8f9f7 924 }
<> 144:ef7eb2e8f9f7 925
<> 144:ef7eb2e8f9f7 926 static int serial_write_async(serial_t *obj)
<> 144:ef7eb2e8f9f7 927 {
<> 144:ef7eb2e8f9f7 928 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 929 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 930 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 931
<> 144:ef7eb2e8f9f7 932 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 933
<> 144:ef7eb2e8f9f7 934 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
<> 144:ef7eb2e8f9f7 935 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
<> 144:ef7eb2e8f9f7 936 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
<> 144:ef7eb2e8f9f7 937 tx_fifo_busy = tx_fifo_max;
<> 144:ef7eb2e8f9f7 938 }
<> 144:ef7eb2e8f9f7 939 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
<> 144:ef7eb2e8f9f7 940 if (tx_fifo_free == 0) {
<> 144:ef7eb2e8f9f7 941 // Simulate clear of the interrupt flag
<> 144:ef7eb2e8f9f7 942 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 144:ef7eb2e8f9f7 943 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 944 }
<> 144:ef7eb2e8f9f7 945 return 0;
<> 144:ef7eb2e8f9f7 946 }
<> 144:ef7eb2e8f9f7 947
<> 144:ef7eb2e8f9f7 948 uint32_t bytes_per_word = obj->tx_buff.width / 8;
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
<> 144:ef7eb2e8f9f7 951 int n_words = 0;
<> 144:ef7eb2e8f9f7 952 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
<> 144:ef7eb2e8f9f7 953 switch (bytes_per_word) {
<> 144:ef7eb2e8f9f7 954 case 4:
<> 144:ef7eb2e8f9f7 955 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 956 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 957 case 2:
<> 144:ef7eb2e8f9f7 958 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 959 case 1:
<> 144:ef7eb2e8f9f7 960 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 n_words ++;
<> 144:ef7eb2e8f9f7 964 tx_fifo_free -= bytes_per_word;
<> 144:ef7eb2e8f9f7 965 obj->tx_buff.pos ++;
<> 144:ef7eb2e8f9f7 966 }
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 if (n_words) {
<> 144:ef7eb2e8f9f7 969 // Simulate clear of the interrupt flag
<> 144:ef7eb2e8f9f7 970 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 144:ef7eb2e8f9f7 971 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 972 }
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 return n_words;
<> 144:ef7eb2e8f9f7 976 }
<> 144:ef7eb2e8f9f7 977
<> 144:ef7eb2e8f9f7 978 static int serial_read_async(serial_t *obj)
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 981 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 982 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
<> 144:ef7eb2e8f9f7 985 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
<> 144:ef7eb2e8f9f7 986 //if (rx_fifo_free == 0) {
<> 144:ef7eb2e8f9f7 987 // return 0;
<> 144:ef7eb2e8f9f7 988 //}
<> 144:ef7eb2e8f9f7 989
<> 144:ef7eb2e8f9f7 990 uint32_t bytes_per_word = obj->rx_buff.width / 8;
<> 144:ef7eb2e8f9f7 991
<> 144:ef7eb2e8f9f7 992 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
<> 144:ef7eb2e8f9f7 993 int n_words = 0;
<> 144:ef7eb2e8f9f7 994 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
<> 144:ef7eb2e8f9f7 995 switch (bytes_per_word) {
<> 144:ef7eb2e8f9f7 996 case 4:
<> 144:ef7eb2e8f9f7 997 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 998 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 999 case 2:
<> 144:ef7eb2e8f9f7 1000 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 1001 case 1:
<> 144:ef7eb2e8f9f7 1002 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 1003 }
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 n_words ++;
<> 144:ef7eb2e8f9f7 1006 rx_fifo_busy -= bytes_per_word;
<> 144:ef7eb2e8f9f7 1007 obj->rx_buff.pos ++;
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 144:ef7eb2e8f9f7 1010 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 144:ef7eb2e8f9f7 1011 uint8_t *rx_cmp = rx;
<> 144:ef7eb2e8f9f7 1012 switch (bytes_per_word) {
<> 144:ef7eb2e8f9f7 1013 case 4:
<> 144:ef7eb2e8f9f7 1014 rx_cmp -= 2;
<> 144:ef7eb2e8f9f7 1015 case 2:
<> 144:ef7eb2e8f9f7 1016 rx_cmp --;
<> 144:ef7eb2e8f9f7 1017 case 1:
<> 144:ef7eb2e8f9f7 1018 rx_cmp --;
<> 144:ef7eb2e8f9f7 1019 }
<> 144:ef7eb2e8f9f7 1020 if (*rx_cmp == obj->char_match) {
<> 144:ef7eb2e8f9f7 1021 obj->char_found = 1;
<> 144:ef7eb2e8f9f7 1022 break;
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024 }
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 if (n_words) {
<> 144:ef7eb2e8f9f7 1028 // Simulate clear of the interrupt flag
<> 144:ef7eb2e8f9f7 1029 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 144:ef7eb2e8f9f7 1030 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032 }
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 return n_words;
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
<> 144:ef7eb2e8f9f7 1038 {
<> 144:ef7eb2e8f9f7 1039 obj->tx_buff.buffer = (void *) tx;
<> 144:ef7eb2e8f9f7 1040 obj->tx_buff.length = length;
<> 144:ef7eb2e8f9f7 1041 obj->tx_buff.pos = 0;
<> 144:ef7eb2e8f9f7 1042 obj->tx_buff.width = width;
<> 144:ef7eb2e8f9f7 1043 }
<> 144:ef7eb2e8f9f7 1044
<> 144:ef7eb2e8f9f7 1045 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
<> 144:ef7eb2e8f9f7 1046 {
<> 144:ef7eb2e8f9f7 1047 obj->rx_buff.buffer = rx;
<> 144:ef7eb2e8f9f7 1048 obj->rx_buff.length = length;
<> 144:ef7eb2e8f9f7 1049 obj->rx_buff.pos = 0;
<> 144:ef7eb2e8f9f7 1050 obj->rx_buff.width = width;
<> 144:ef7eb2e8f9f7 1051 }
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 144:ef7eb2e8f9f7 1054 {
<> 144:ef7eb2e8f9f7 1055 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 1056 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1057 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1060 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 1061 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1062 obj->serial.vec = var->vec_async;
<> 144:ef7eb2e8f9f7 1063 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
AnnaBridge 165:e614a9f1c9e2 1064 serial_enable_interrupt(obj, TxIrq, enable);
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 144:ef7eb2e8f9f7 1068 {
<> 144:ef7eb2e8f9f7 1069 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 1070 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1071 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1074 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 1075 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1076 obj->serial.vec = var->vec_async;
<> 144:ef7eb2e8f9f7 1077 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
AnnaBridge 165:e614a9f1c9e2 1078 serial_enable_interrupt(obj, RxIrq, enable);
AnnaBridge 165:e614a9f1c9e2 1079 }
AnnaBridge 165:e614a9f1c9e2 1080
AnnaBridge 165:e614a9f1c9e2 1081 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
AnnaBridge 165:e614a9f1c9e2 1082 {
AnnaBridge 165:e614a9f1c9e2 1083 if (enable) {
AnnaBridge 165:e614a9f1c9e2 1084 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1085 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1086 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1087
AnnaBridge 165:e614a9f1c9e2 1088 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
AnnaBridge 165:e614a9f1c9e2 1089 NVIC_EnableIRQ(modinit->irq_n);
AnnaBridge 165:e614a9f1c9e2 1090
AnnaBridge 165:e614a9f1c9e2 1091 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1092 // Multiple serial S/W objects for single UART H/W module possibly.
AnnaBridge 165:e614a9f1c9e2 1093 // Bind serial S/W object to UART H/W module as interrupt is enabled.
AnnaBridge 165:e614a9f1c9e2 1094 var->obj = obj;
AnnaBridge 165:e614a9f1c9e2 1095
AnnaBridge 165:e614a9f1c9e2 1096 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1097 // NOTE: Setting inten_msk first to avoid race condition
AnnaBridge 165:e614a9f1c9e2 1098 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1099 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1100 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1101 break;
AnnaBridge 165:e614a9f1c9e2 1102 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1103 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1104 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1105 break;
AnnaBridge 165:e614a9f1c9e2 1106 }
AnnaBridge 165:e614a9f1c9e2 1107 }
AnnaBridge 165:e614a9f1c9e2 1108 else { // disable
AnnaBridge 165:e614a9f1c9e2 1109 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1110 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1111 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1112 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1113 break;
AnnaBridge 165:e614a9f1c9e2 1114 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1115 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1116 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1117 break;
AnnaBridge 165:e614a9f1c9e2 1118 }
AnnaBridge 165:e614a9f1c9e2 1119 }
AnnaBridge 165:e614a9f1c9e2 1120 }
AnnaBridge 165:e614a9f1c9e2 1121
AnnaBridge 165:e614a9f1c9e2 1122 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
AnnaBridge 165:e614a9f1c9e2 1123 {
AnnaBridge 165:e614a9f1c9e2 1124 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1125 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1126 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1127
AnnaBridge 165:e614a9f1c9e2 1128 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1129
AnnaBridge 165:e614a9f1c9e2 1130 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 1131 serial_enable_interrupt(obj, irq, obj->serial.irq_en);
<> 144:ef7eb2e8f9f7 1132 }
<> 144:ef7eb2e8f9f7 1133
<> 144:ef7eb2e8f9f7 1134 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
<> 144:ef7eb2e8f9f7 1135 {
<> 144:ef7eb2e8f9f7 1136 if (*dma_usage != DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 1137 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 1138 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 1141 *dma_usage = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 1142 }
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144 else {
<> 144:ef7eb2e8f9f7 1145 dma_channel_free(*dma_ch);
<> 144:ef7eb2e8f9f7 1146 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 1147 }
<> 144:ef7eb2e8f9f7 1148 }
<> 144:ef7eb2e8f9f7 1149
<> 144:ef7eb2e8f9f7 1150 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
<> 144:ef7eb2e8f9f7 1151 {
<> 144:ef7eb2e8f9f7 1152 int inten_msk = 0;
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 switch (irq) {
<> 144:ef7eb2e8f9f7 1155 case RxIrq:
<> 144:ef7eb2e8f9f7 1156 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
<> 144:ef7eb2e8f9f7 1157 break;
<> 144:ef7eb2e8f9f7 1158 case TxIrq:
<> 144:ef7eb2e8f9f7 1159 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
<> 144:ef7eb2e8f9f7 1160 break;
<> 144:ef7eb2e8f9f7 1161 }
<> 144:ef7eb2e8f9f7 1162
<> 144:ef7eb2e8f9f7 1163 return !! inten_msk;
<> 144:ef7eb2e8f9f7 1164 }
<> 144:ef7eb2e8f9f7 1165
<> 144:ef7eb2e8f9f7 1166 #endif // #if DEVICE_SERIAL_ASYNCH
AnnaBridge 188:bcfe06ba3d64 1167
AnnaBridge 188:bcfe06ba3d64 1168 bool serial_can_deep_sleep(void)
AnnaBridge 188:bcfe06ba3d64 1169 {
AnnaBridge 188:bcfe06ba3d64 1170 bool sleep_allowed = 1;
AnnaBridge 188:bcfe06ba3d64 1171 const struct nu_modinit_s *modinit = uart_modinit_tab;
AnnaBridge 188:bcfe06ba3d64 1172 while (modinit->var != NULL) {
AnnaBridge 188:bcfe06ba3d64 1173 struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
AnnaBridge 188:bcfe06ba3d64 1174 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
AnnaBridge 188:bcfe06ba3d64 1175 if (uart_var->ref_cnt > 0) {
AnnaBridge 188:bcfe06ba3d64 1176 if (!UART_IS_TX_EMPTY(uart_base)) {
AnnaBridge 188:bcfe06ba3d64 1177 sleep_allowed = 0;
AnnaBridge 188:bcfe06ba3d64 1178 break;
AnnaBridge 188:bcfe06ba3d64 1179 }
AnnaBridge 188:bcfe06ba3d64 1180 }
AnnaBridge 188:bcfe06ba3d64 1181 modinit++;
AnnaBridge 188:bcfe06ba3d64 1182 }
AnnaBridge 188:bcfe06ba3d64 1183 return sleep_allowed;
AnnaBridge 188:bcfe06ba3d64 1184 }
AnnaBridge 188:bcfe06ba3d64 1185
<> 144:ef7eb2e8f9f7 1186 #endif // #if DEVICE_SERIAL