mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_NUVOTON/TARGET_NUC472/serial_api.c@188:bcfe06ba3d64, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:46:34 2018 +0000
Revision:
188:bcfe06ba3d64
Parent:
184:08ed48f1de7f
Child:
189:f392fc9709a3
mbed-dev library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2015-2016 Nuvoton
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 #include "serial_api.h"
<> 144:ef7eb2e8f9f7 18
<> 144:ef7eb2e8f9f7 19 #if DEVICE_SERIAL
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 22 #include "mbed_error.h"
<> 144:ef7eb2e8f9f7 23 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 24 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 25 #include "nu_modutil.h"
<> 144:ef7eb2e8f9f7 26 #include "nu_bitutil.h"
AnnaBridge 165:e614a9f1c9e2 27 #include <string.h>
AnnaBridge 188:bcfe06ba3d64 28 #include <stdbool.h>
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 31 #include "dma_api.h"
<> 144:ef7eb2e8f9f7 32 #include "dma.h"
<> 144:ef7eb2e8f9f7 33 #endif
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 struct nu_uart_var {
<> 151:5eaa88a5bcc7 36 uint32_t ref_cnt; // Reference count of the H/W module
<> 144:ef7eb2e8f9f7 37 serial_t * obj;
<> 144:ef7eb2e8f9f7 38 uint32_t fifo_size_tx;
<> 144:ef7eb2e8f9f7 39 uint32_t fifo_size_rx;
<> 144:ef7eb2e8f9f7 40 void (*vec)(void);
<> 144:ef7eb2e8f9f7 41 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 42 void (*vec_async)(void);
<> 144:ef7eb2e8f9f7 43 uint8_t pdma_perp_tx;
<> 144:ef7eb2e8f9f7 44 uint8_t pdma_perp_rx;
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46 };
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 static void uart0_vec(void);
<> 144:ef7eb2e8f9f7 49 static void uart1_vec(void);
<> 144:ef7eb2e8f9f7 50 static void uart2_vec(void);
<> 144:ef7eb2e8f9f7 51 static void uart3_vec(void);
<> 144:ef7eb2e8f9f7 52 static void uart4_vec(void);
<> 144:ef7eb2e8f9f7 53 static void uart5_vec(void);
<> 144:ef7eb2e8f9f7 54 static void uart_irq(serial_t *obj);
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 57 static void uart0_vec_async(void);
<> 144:ef7eb2e8f9f7 58 static void uart1_vec_async(void);
<> 144:ef7eb2e8f9f7 59 static void uart2_vec_async(void);
<> 144:ef7eb2e8f9f7 60 static void uart3_vec_async(void);
<> 144:ef7eb2e8f9f7 61 static void uart4_vec_async(void);
<> 144:ef7eb2e8f9f7 62 static void uart5_vec_async(void);
<> 144:ef7eb2e8f9f7 63 static void uart_irq_async(serial_t *obj);
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 static void uart_dma_handler_tx(uint32_t id, uint32_t event);
<> 144:ef7eb2e8f9f7 66 static void uart_dma_handler_rx(uint32_t id, uint32_t event);
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
<> 144:ef7eb2e8f9f7 69 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t address, uint8_t enable);
AnnaBridge 165:e614a9f1c9e2 70 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable);
AnnaBridge 165:e614a9f1c9e2 71 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq);
<> 144:ef7eb2e8f9f7 72 static int serial_write_async(serial_t *obj);
<> 144:ef7eb2e8f9f7 73 static int serial_read_async(serial_t *obj);
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 static uint32_t serial_rx_event_check(serial_t *obj);
<> 144:ef7eb2e8f9f7 76 static uint32_t serial_tx_event_check(serial_t *obj);
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 static int serial_is_tx_complete(serial_t *obj);
<> 144:ef7eb2e8f9f7 79 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width);
<> 144:ef7eb2e8f9f7 82 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width);
<> 144:ef7eb2e8f9f7 83 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match);
<> 144:ef7eb2e8f9f7 84 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable);
<> 144:ef7eb2e8f9f7 85 static int serial_is_rx_complete(serial_t *obj);
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch);
<> 144:ef7eb2e8f9f7 88 static int serial_is_irq_en(serial_t *obj, SerialIrq irq);
<> 144:ef7eb2e8f9f7 89 #endif
<> 144:ef7eb2e8f9f7 90
AnnaBridge 188:bcfe06ba3d64 91 bool serial_can_deep_sleep(void);
AnnaBridge 188:bcfe06ba3d64 92
<> 144:ef7eb2e8f9f7 93 static struct nu_uart_var uart0_var = {
<> 151:5eaa88a5bcc7 94 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 95 .obj = NULL,
<> 144:ef7eb2e8f9f7 96 .fifo_size_tx = 64,
<> 144:ef7eb2e8f9f7 97 .fifo_size_rx = 64,
<> 144:ef7eb2e8f9f7 98 .vec = uart0_vec,
<> 144:ef7eb2e8f9f7 99 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 100 .vec_async = uart0_vec_async,
<> 144:ef7eb2e8f9f7 101 .pdma_perp_tx = PDMA_UART0_TX,
<> 144:ef7eb2e8f9f7 102 .pdma_perp_rx = PDMA_UART0_RX
<> 144:ef7eb2e8f9f7 103 #endif
<> 144:ef7eb2e8f9f7 104 };
<> 144:ef7eb2e8f9f7 105 static struct nu_uart_var uart1_var = {
<> 151:5eaa88a5bcc7 106 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 107 .obj = NULL,
<> 144:ef7eb2e8f9f7 108 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 109 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 110 .vec = uart1_vec,
<> 144:ef7eb2e8f9f7 111 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 112 .vec_async = uart1_vec_async,
<> 144:ef7eb2e8f9f7 113 .pdma_perp_tx = PDMA_UART1_TX,
<> 144:ef7eb2e8f9f7 114 .pdma_perp_rx = PDMA_UART1_RX
<> 144:ef7eb2e8f9f7 115 #endif
<> 144:ef7eb2e8f9f7 116 };
<> 144:ef7eb2e8f9f7 117 static struct nu_uart_var uart2_var = {
<> 151:5eaa88a5bcc7 118 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 119 .obj = NULL,
<> 144:ef7eb2e8f9f7 120 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 121 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 122 .vec = uart2_vec,
<> 144:ef7eb2e8f9f7 123 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 124 .vec_async = uart2_vec_async,
<> 144:ef7eb2e8f9f7 125 .pdma_perp_tx = PDMA_UART2_TX,
<> 144:ef7eb2e8f9f7 126 .pdma_perp_rx = PDMA_UART2_RX
<> 144:ef7eb2e8f9f7 127 #endif
<> 144:ef7eb2e8f9f7 128 };
<> 144:ef7eb2e8f9f7 129 static struct nu_uart_var uart3_var = {
<> 151:5eaa88a5bcc7 130 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 131 .obj = NULL,
<> 144:ef7eb2e8f9f7 132 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 133 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 134 .vec = uart3_vec,
<> 144:ef7eb2e8f9f7 135 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 136 .vec_async = uart3_vec_async,
<> 144:ef7eb2e8f9f7 137 .pdma_perp_tx = PDMA_UART3_TX,
<> 144:ef7eb2e8f9f7 138 .pdma_perp_rx = PDMA_UART3_RX
<> 144:ef7eb2e8f9f7 139 #endif
<> 144:ef7eb2e8f9f7 140 };
<> 144:ef7eb2e8f9f7 141 static struct nu_uart_var uart4_var = {
<> 151:5eaa88a5bcc7 142 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 143 .obj = NULL,
<> 144:ef7eb2e8f9f7 144 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 145 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 146 .vec = uart4_vec,
<> 144:ef7eb2e8f9f7 147 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 148 .vec_async = uart4_vec_async,
<> 144:ef7eb2e8f9f7 149 .pdma_perp_tx = PDMA_UART4_TX,
<> 144:ef7eb2e8f9f7 150 .pdma_perp_rx = PDMA_UART4_RX
<> 144:ef7eb2e8f9f7 151 #endif
<> 144:ef7eb2e8f9f7 152 };
<> 144:ef7eb2e8f9f7 153 static struct nu_uart_var uart5_var = {
<> 151:5eaa88a5bcc7 154 .ref_cnt = 0,
<> 144:ef7eb2e8f9f7 155 .obj = NULL,
<> 144:ef7eb2e8f9f7 156 .fifo_size_tx = 16,
<> 144:ef7eb2e8f9f7 157 .fifo_size_rx = 16,
<> 144:ef7eb2e8f9f7 158 .vec = uart5_vec,
<> 144:ef7eb2e8f9f7 159 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 160 .vec_async = uart5_vec_async,
<> 144:ef7eb2e8f9f7 161 .pdma_perp_tx = PDMA_UART5_TX,
<> 144:ef7eb2e8f9f7 162 .pdma_perp_rx = PDMA_UART5_RX
<> 144:ef7eb2e8f9f7 163 #endif
<> 144:ef7eb2e8f9f7 164 };
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166
<> 144:ef7eb2e8f9f7 167 int stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 168 serial_t stdio_uart;
<> 144:ef7eb2e8f9f7 169 static uint32_t uart_modinit_mask = 0;
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 static const struct nu_modinit_s uart_modinit_tab[] = {
<> 144:ef7eb2e8f9f7 172 {UART_0, UART0_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART0_RST, UART0_IRQn, &uart0_var},
<> 144:ef7eb2e8f9f7 173 {UART_1, UART1_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART1_RST, UART1_IRQn, &uart1_var},
<> 144:ef7eb2e8f9f7 174 {UART_2, UART2_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART2_RST, UART2_IRQn, &uart2_var},
<> 144:ef7eb2e8f9f7 175 {UART_3, UART3_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART3_RST, UART3_IRQn, &uart3_var},
<> 144:ef7eb2e8f9f7 176 {UART_4, UART4_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART4_RST, UART4_IRQn, &uart4_var},
<> 144:ef7eb2e8f9f7 177 {UART_5, UART5_MODULE, CLK_CLKSEL1_UARTSEL_HIRC, CLK_CLKDIV0_UART(1), UART5_RST, UART5_IRQn, &uart5_var},
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 {NC, 0, 0, 0, 0, (IRQn_Type) 0, NULL}
<> 144:ef7eb2e8f9f7 180 };
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 extern void mbed_sdk_init(void);
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 void serial_init(serial_t *obj, PinName tx, PinName rx)
<> 144:ef7eb2e8f9f7 185 {
<> 151:5eaa88a5bcc7 186 // NOTE: With armcc, serial_init() gets called from _sys_open() timing of which is before main()/mbed_sdk_init().
<> 144:ef7eb2e8f9f7 187 mbed_sdk_init();
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 // Determine which UART_x the pins are used for
<> 144:ef7eb2e8f9f7 190 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 191 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
<> 144:ef7eb2e8f9f7 192 // Get the peripheral name (UART_x) from the pins and assign it to the object
<> 144:ef7eb2e8f9f7 193 obj->serial.uart = (UARTName) pinmap_merge(uart_tx, uart_rx);
<> 144:ef7eb2e8f9f7 194 MBED_ASSERT((int)obj->serial.uart != NC);
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 197 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 198 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 199
<> 151:5eaa88a5bcc7 200 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 201
<> 151:5eaa88a5bcc7 202 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 203 // Reset this module
<> 151:5eaa88a5bcc7 204 SYS_ResetModule(modinit->rsetidx);
<> 151:5eaa88a5bcc7 205
<> 151:5eaa88a5bcc7 206 // Select IP clock source
<> 151:5eaa88a5bcc7 207 CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
<> 151:5eaa88a5bcc7 208 // Enable IP clock
<> 151:5eaa88a5bcc7 209 CLK_EnableModuleClock(modinit->clkidx);
<> 144:ef7eb2e8f9f7 210
<> 151:5eaa88a5bcc7 211 pinmap_pinout(tx, PinMap_UART_TX);
<> 151:5eaa88a5bcc7 212 pinmap_pinout(rx, PinMap_UART_RX);
<> 151:5eaa88a5bcc7 213
<> 151:5eaa88a5bcc7 214 obj->serial.pin_tx = tx;
<> 151:5eaa88a5bcc7 215 obj->serial.pin_rx = rx;
<> 151:5eaa88a5bcc7 216 }
<> 151:5eaa88a5bcc7 217 var->ref_cnt ++;
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 // Configure the UART module and set its baudrate
<> 144:ef7eb2e8f9f7 220 serial_baud(obj, 9600);
<> 144:ef7eb2e8f9f7 221 // Configure data bits, parity, and stop bits
<> 144:ef7eb2e8f9f7 222 serial_format(obj, 8, ParityNone, 1);
<> 144:ef7eb2e8f9f7 223
<> 151:5eaa88a5bcc7 224 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 225 obj->serial.irq_en = 0;
<> 144:ef7eb2e8f9f7 226
<> 144:ef7eb2e8f9f7 227 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 228 obj->serial.dma_usage_tx = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 229 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 230 obj->serial.event = 0;
<> 144:ef7eb2e8f9f7 231 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 232 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 233 #endif
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 // For stdio management
<> 151:5eaa88a5bcc7 236 if (obj->serial.uart == STDIO_UART) {
<> 144:ef7eb2e8f9f7 237 stdio_uart_inited = 1;
<> 151:5eaa88a5bcc7 238 memcpy(&stdio_uart, obj, sizeof(serial_t));
<> 144:ef7eb2e8f9f7 239 }
<> 144:ef7eb2e8f9f7 240
<> 151:5eaa88a5bcc7 241 if (var->ref_cnt) {
<> 151:5eaa88a5bcc7 242 // Mark this module to be inited.
<> 151:5eaa88a5bcc7 243 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 244 uart_modinit_mask |= 1 << i;
<> 151:5eaa88a5bcc7 245 }
<> 144:ef7eb2e8f9f7 246 }
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 void serial_free(serial_t *obj)
<> 144:ef7eb2e8f9f7 249 {
<> 144:ef7eb2e8f9f7 250 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 251 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 252 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 253
<> 151:5eaa88a5bcc7 254 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 255
<> 151:5eaa88a5bcc7 256 var->ref_cnt --;
<> 151:5eaa88a5bcc7 257 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 258 #if DEVICE_SERIAL_ASYNCH
<> 151:5eaa88a5bcc7 259 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 260 dma_channel_free(obj->serial.dma_chn_id_tx);
<> 151:5eaa88a5bcc7 261 obj->serial.dma_chn_id_tx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 262 }
<> 151:5eaa88a5bcc7 263 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 151:5eaa88a5bcc7 264 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 151:5eaa88a5bcc7 265 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 151:5eaa88a5bcc7 266 }
<> 151:5eaa88a5bcc7 267 #endif
<> 151:5eaa88a5bcc7 268
<> 151:5eaa88a5bcc7 269 UART_Close((UART_T *) NU_MODBASE(obj->serial.uart));
<> 144:ef7eb2e8f9f7 270
<> 151:5eaa88a5bcc7 271 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_THREIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 151:5eaa88a5bcc7 272 NVIC_DisableIRQ(modinit->irq_n);
<> 144:ef7eb2e8f9f7 273
<> 151:5eaa88a5bcc7 274 // Disable IP clock
<> 151:5eaa88a5bcc7 275 CLK_DisableModuleClock(modinit->clkidx);
<> 151:5eaa88a5bcc7 276 }
<> 151:5eaa88a5bcc7 277
<> 151:5eaa88a5bcc7 278 if (var->obj == obj) {
<> 151:5eaa88a5bcc7 279 var->obj = NULL;
<> 151:5eaa88a5bcc7 280 }
<> 151:5eaa88a5bcc7 281
<> 151:5eaa88a5bcc7 282 if (obj->serial.uart == STDIO_UART) {
<> 144:ef7eb2e8f9f7 283 stdio_uart_inited = 0;
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 151:5eaa88a5bcc7 286 if (! var->ref_cnt) {
<> 151:5eaa88a5bcc7 287 // Mark this module to be deinited.
<> 151:5eaa88a5bcc7 288 int i = modinit - uart_modinit_tab;
<> 151:5eaa88a5bcc7 289 uart_modinit_mask &= ~(1 << i);
<> 151:5eaa88a5bcc7 290 }
<> 144:ef7eb2e8f9f7 291 }
<> 144:ef7eb2e8f9f7 292
<> 144:ef7eb2e8f9f7 293 void serial_baud(serial_t *obj, int baudrate) {
<> 144:ef7eb2e8f9f7 294 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 295 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 296
<> 144:ef7eb2e8f9f7 297 obj->serial.baudrate = baudrate;
<> 144:ef7eb2e8f9f7 298 UART_Open((UART_T *) NU_MODBASE(obj->serial.uart), baudrate);
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300
<> 144:ef7eb2e8f9f7 301 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
<> 144:ef7eb2e8f9f7 302 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 303 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 304
AnnaBridge 172:7d866c31b3c5 305 // Sanity check arguments
AnnaBridge 172:7d866c31b3c5 306 MBED_ASSERT((data_bits == 5) || (data_bits == 6) || (data_bits == 7) || (data_bits == 8));
AnnaBridge 172:7d866c31b3c5 307 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) || (parity == ParityForced1) || (parity == ParityForced0));
AnnaBridge 172:7d866c31b3c5 308 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2));
AnnaBridge 172:7d866c31b3c5 309
<> 144:ef7eb2e8f9f7 310 obj->serial.databits = data_bits;
<> 144:ef7eb2e8f9f7 311 obj->serial.parity = parity;
<> 144:ef7eb2e8f9f7 312 obj->serial.stopbits = stop_bits;
<> 144:ef7eb2e8f9f7 313
<> 144:ef7eb2e8f9f7 314 uint32_t databits_intern = (data_bits == 5) ? UART_WORD_LEN_5 :
<> 144:ef7eb2e8f9f7 315 (data_bits == 6) ? UART_WORD_LEN_6 :
<> 144:ef7eb2e8f9f7 316 (data_bits == 7) ? UART_WORD_LEN_7 :
<> 144:ef7eb2e8f9f7 317 UART_WORD_LEN_8;
<> 144:ef7eb2e8f9f7 318 uint32_t parity_intern = (parity == ParityOdd || parity == ParityForced1) ? UART_PARITY_ODD :
<> 144:ef7eb2e8f9f7 319 (parity == ParityEven || parity == ParityForced0) ? UART_PARITY_EVEN :
<> 144:ef7eb2e8f9f7 320 UART_PARITY_NONE;
<> 144:ef7eb2e8f9f7 321 uint32_t stopbits_intern = (stop_bits == 2) ? UART_STOP_BIT_2 : UART_STOP_BIT_1;
<> 144:ef7eb2e8f9f7 322 UART_SetLine_Config((UART_T *) NU_MODBASE(obj->serial.uart),
<> 144:ef7eb2e8f9f7 323 0, // Don't change baudrate
<> 144:ef7eb2e8f9f7 324 databits_intern,
<> 144:ef7eb2e8f9f7 325 parity_intern,
<> 144:ef7eb2e8f9f7 326 stopbits_intern);
<> 144:ef7eb2e8f9f7 327 }
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 #if DEVICE_SERIAL_FC
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow)
<> 144:ef7eb2e8f9f7 332 {
<> 144:ef7eb2e8f9f7 333 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 // First, disable flow control completely.
<> 144:ef7eb2e8f9f7 336 uart_base->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 if ((type == FlowControlRTS || type == FlowControlRTSCTS) && rxflow != NC) {
<> 144:ef7eb2e8f9f7 339 // Check if RTS pin matches.
<> 144:ef7eb2e8f9f7 340 uint32_t uart_rts = pinmap_peripheral(rxflow, PinMap_UART_RTS);
<> 144:ef7eb2e8f9f7 341 MBED_ASSERT(uart_rts == obj->serial.uart);
<> 144:ef7eb2e8f9f7 342 // Enable the pin for RTS function
<> 144:ef7eb2e8f9f7 343 pinmap_pinout(rxflow, PinMap_UART_RTS);
<> 153:fa9ff456f731 344 // nRTS pin output is low level active
<> 153:fa9ff456f731 345 uart_base->MODEM |= UART_MODEM_RTSACTLV_Msk;
<> 153:fa9ff456f731 346 uart_base->MODEM &= ~UART_MODEM_RTS_Msk;
<> 153:fa9ff456f731 347
<> 144:ef7eb2e8f9f7 348 uart_base->FIFO = (uart_base->FIFO & ~UART_FIFO_RTSTRGLV_Msk) | UART_FIFO_RTSTRGLV_8BYTES;
<> 144:ef7eb2e8f9f7 349 // Enable RTS
<> 144:ef7eb2e8f9f7 350 uart_base->INTEN |= UART_INTEN_ATORTSEN_Msk;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 if ((type == FlowControlCTS || type == FlowControlRTSCTS) && txflow != NC) {
<> 144:ef7eb2e8f9f7 354 // Check if CTS pin matches.
<> 144:ef7eb2e8f9f7 355 uint32_t uart_cts = pinmap_peripheral(txflow, PinMap_UART_CTS);
<> 144:ef7eb2e8f9f7 356 MBED_ASSERT(uart_cts == obj->serial.uart);
<> 144:ef7eb2e8f9f7 357 // Enable the pin for CTS function
<> 144:ef7eb2e8f9f7 358 pinmap_pinout(txflow, PinMap_UART_CTS);
<> 153:fa9ff456f731 359 // nCTS pin input is low level active
<> 153:fa9ff456f731 360 uart_base->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
<> 144:ef7eb2e8f9f7 361 // Enable CTS
<> 144:ef7eb2e8f9f7 362 uart_base->INTEN |= UART_INTEN_ATOCTSEN_Msk;
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366 #endif //DEVICE_SERIAL_FC
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 371 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 374 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 375 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 376
<> 144:ef7eb2e8f9f7 377 obj->serial.irq_handler = (uint32_t) handler;
<> 144:ef7eb2e8f9f7 378 obj->serial.irq_id = id;
<> 144:ef7eb2e8f9f7 379
<> 144:ef7eb2e8f9f7 380 // Restore sync-mode vector
<> 144:ef7eb2e8f9f7 381 obj->serial.vec = ((struct nu_uart_var *) modinit->var)->vec;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
<> 144:ef7eb2e8f9f7 385 {
AnnaBridge 165:e614a9f1c9e2 386 obj->serial.irq_en = enable;
AnnaBridge 165:e614a9f1c9e2 387 serial_enable_interrupt(obj, irq, enable);
<> 144:ef7eb2e8f9f7 388 }
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 int serial_getc(serial_t *obj)
<> 144:ef7eb2e8f9f7 391 {
AnnaBridge 165:e614a9f1c9e2 392 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 144:ef7eb2e8f9f7 393 while (! serial_readable(obj));
<> 144:ef7eb2e8f9f7 394 int c = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 395
AnnaBridge 165:e614a9f1c9e2 396 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 397 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 144:ef7eb2e8f9f7 398 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 144:ef7eb2e8f9f7 399 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 return c;
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 void serial_putc(serial_t *obj, int c)
<> 144:ef7eb2e8f9f7 406 {
AnnaBridge 165:e614a9f1c9e2 407 // NOTE: Every byte access requires accompaniment of one interrupt. This has side effect of performance degradation.
<> 144:ef7eb2e8f9f7 408 while (! serial_writable(obj));
<> 144:ef7eb2e8f9f7 409 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), c);
<> 144:ef7eb2e8f9f7 410
AnnaBridge 165:e614a9f1c9e2 411 // NOTE: On Nuvoton targets, no H/W IRQ to match TxIrq/RxIrq.
AnnaBridge 165:e614a9f1c9e2 412 // Simulation of TxIrq/RxIrq requires the call to Serial::putc()/Serial::getc() respectively.
<> 144:ef7eb2e8f9f7 413 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 144:ef7eb2e8f9f7 414 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 415 }
<> 144:ef7eb2e8f9f7 416 }
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 int serial_readable(serial_t *obj)
<> 144:ef7eb2e8f9f7 419 {
<> 144:ef7eb2e8f9f7 420 //return UART_IS_RX_READY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 421 return ! (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk);
<> 144:ef7eb2e8f9f7 422 }
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 int serial_writable(serial_t *obj)
<> 144:ef7eb2e8f9f7 425 {
<> 144:ef7eb2e8f9f7 426 return ! UART_IS_TX_FULL(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 427 }
<> 144:ef7eb2e8f9f7 428
<> 144:ef7eb2e8f9f7 429 void serial_pinout_tx(PinName tx)
<> 144:ef7eb2e8f9f7 430 {
<> 144:ef7eb2e8f9f7 431 pinmap_pinout(tx, PinMap_UART_TX);
<> 144:ef7eb2e8f9f7 432 }
<> 144:ef7eb2e8f9f7 433
<> 144:ef7eb2e8f9f7 434 void serial_break_set(serial_t *obj)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE |= UART_LINE_BCB_Msk;
<> 144:ef7eb2e8f9f7 437 }
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 void serial_break_clear(serial_t *obj)
<> 144:ef7eb2e8f9f7 440 {
<> 144:ef7eb2e8f9f7 441 ((UART_T *) NU_MODBASE(obj->serial.uart))->LINE &= ~UART_LINE_BCB_Msk;
<> 144:ef7eb2e8f9f7 442 }
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 static void uart0_vec(void)
<> 144:ef7eb2e8f9f7 445 {
<> 144:ef7eb2e8f9f7 446 uart_irq(uart0_var.obj);
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 static void uart1_vec(void)
<> 144:ef7eb2e8f9f7 450 {
<> 144:ef7eb2e8f9f7 451 uart_irq(uart1_var.obj);
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 static void uart2_vec(void)
<> 144:ef7eb2e8f9f7 455 {
<> 144:ef7eb2e8f9f7 456 uart_irq(uart2_var.obj);
<> 144:ef7eb2e8f9f7 457 }
<> 144:ef7eb2e8f9f7 458
<> 144:ef7eb2e8f9f7 459 static void uart3_vec(void)
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 uart_irq(uart3_var.obj);
<> 144:ef7eb2e8f9f7 462 }
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 static void uart4_vec(void)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 uart_irq(uart4_var.obj);
<> 144:ef7eb2e8f9f7 467 }
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 static void uart5_vec(void)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 uart_irq(uart5_var.obj);
<> 144:ef7eb2e8f9f7 472 }
<> 144:ef7eb2e8f9f7 473
<> 144:ef7eb2e8f9f7 474 static void uart_irq(serial_t *obj)
<> 144:ef7eb2e8f9f7 475 {
<> 144:ef7eb2e8f9f7 476 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 477
<> 144:ef7eb2e8f9f7 478 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 144:ef7eb2e8f9f7 479 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 144:ef7eb2e8f9f7 480 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 481 if (obj->serial.irq_handler) {
<> 144:ef7eb2e8f9f7 482 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, RxIrq);
<> 144:ef7eb2e8f9f7 483 }
<> 144:ef7eb2e8f9f7 484 }
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 144:ef7eb2e8f9f7 487 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 144:ef7eb2e8f9f7 488 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 489 if (obj->serial.irq_handler) {
<> 144:ef7eb2e8f9f7 490 ((uart_irq_handler) obj->serial.irq_handler)(obj->serial.irq_id, TxIrq);
<> 144:ef7eb2e8f9f7 491 }
<> 144:ef7eb2e8f9f7 492 }
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 // FIXME: Ignore all other interrupt flags. Clear them. Otherwise, program will get stuck in interrupt.
<> 144:ef7eb2e8f9f7 495 uart_base->INTSTS = uart_base->INTSTS;
<> 144:ef7eb2e8f9f7 496 uart_base->FIFOSTS = uart_base->FIFOSTS;
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 #if DEVICE_SERIAL_ASYNCH
<> 144:ef7eb2e8f9f7 501 int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint)
<> 144:ef7eb2e8f9f7 502 {
<> 144:ef7eb2e8f9f7 503 MBED_ASSERT(tx_width == 8 || tx_width == 16 || tx_width == 32);
<> 144:ef7eb2e8f9f7 504
<> 144:ef7eb2e8f9f7 505 obj->serial.dma_usage_tx = hint;
<> 144:ef7eb2e8f9f7 506 serial_check_dma_usage(&obj->serial.dma_usage_tx, &obj->serial.dma_chn_id_tx);
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 // UART IRQ is necessary for both interrupt way and DMA way
<> 144:ef7eb2e8f9f7 509 serial_tx_enable_event(obj, event, 1);
<> 144:ef7eb2e8f9f7 510 serial_tx_buffer_set(obj, tx, tx_length, tx_width);
<> 144:ef7eb2e8f9f7 511 //UART_HAL_DisableTransmitter(obj->serial.address);
<> 144:ef7eb2e8f9f7 512 //UART_HAL_FlushTxFifo(obj->serial.address);
<> 144:ef7eb2e8f9f7 513 //UART_HAL_EnableTransmitter(obj->serial.address);
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 int n_word = 0;
<> 144:ef7eb2e8f9f7 516 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 517 // Interrupt way
<> 144:ef7eb2e8f9f7 518 n_word = serial_write_async(obj);
<> 144:ef7eb2e8f9f7 519 serial_tx_enable_interrupt(obj, handler, 1);
<> 144:ef7eb2e8f9f7 520 } else {
<> 144:ef7eb2e8f9f7 521 // DMA way
<> 144:ef7eb2e8f9f7 522 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 523 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 524 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 525
<> 161:2cc1468da177 526 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 527
<> 161:2cc1468da177 528 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_tx; // Enable this DMA channel
<> 144:ef7eb2e8f9f7 529 PDMA_SetTransferMode(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 530 ((struct nu_uart_var *) modinit->var)->pdma_perp_tx, // Peripheral connected to this PDMA
<> 144:ef7eb2e8f9f7 531 0, // Scatter-gather disabled
<> 144:ef7eb2e8f9f7 532 0); // Scatter-gather descriptor address
<> 144:ef7eb2e8f9f7 533 PDMA_SetTransferCnt(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 534 (tx_width == 8) ? PDMA_WIDTH_8 : (tx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 144:ef7eb2e8f9f7 535 tx_length);
<> 144:ef7eb2e8f9f7 536 PDMA_SetTransferAddr(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 537 ((uint32_t) tx) + (tx_width / 8) * tx_length, // NOTE: End of source address
<> 144:ef7eb2e8f9f7 538 PDMA_SAR_INC, // Source address incremental
<> 161:2cc1468da177 539 (uint32_t) NU_MODBASE(obj->serial.uart), // Destination address
<> 144:ef7eb2e8f9f7 540 PDMA_DAR_FIX); // Destination address fixed
<> 144:ef7eb2e8f9f7 541 PDMA_SetBurstType(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 542 PDMA_REQ_SINGLE, // Single mode
<> 144:ef7eb2e8f9f7 543 0); // Burst size
<> 144:ef7eb2e8f9f7 544 PDMA_EnableInt(obj->serial.dma_chn_id_tx,
<> 144:ef7eb2e8f9f7 545 0); // Interrupt type. No use here
<> 144:ef7eb2e8f9f7 546 // Register DMA event handler
<> 144:ef7eb2e8f9f7 547 dma_set_handler(obj->serial.dma_chn_id_tx, (uint32_t) uart_dma_handler_tx, (uint32_t) obj, DMA_EVENT_ALL);
<> 144:ef7eb2e8f9f7 548 serial_tx_enable_interrupt(obj, handler, 1);
AnnaBridge 184:08ed48f1de7f 549 /* We needn't actually enable UART INT to go UART ISR -> handler.
AnnaBridge 184:08ed48f1de7f 550 * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
AnnaBridge 184:08ed48f1de7f 551 * with serial_tx/rx_enable_interrupt having set up this call path. */
AnnaBridge 184:08ed48f1de7f 552 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 553 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_TXPDMAEN_Msk; // Start DMA transfer
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 return n_word;
<> 144:ef7eb2e8f9f7 557 }
<> 144:ef7eb2e8f9f7 558
<> 144:ef7eb2e8f9f7 559 void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint)
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 MBED_ASSERT(rx_width == 8 || rx_width == 16 || rx_width == 32);
<> 144:ef7eb2e8f9f7 562
<> 144:ef7eb2e8f9f7 563 obj->serial.dma_usage_rx = hint;
<> 144:ef7eb2e8f9f7 564 serial_check_dma_usage(&obj->serial.dma_usage_rx, &obj->serial.dma_chn_id_rx);
<> 144:ef7eb2e8f9f7 565 // DMA doesn't support char match, so fall back to IRQ if it is requested.
<> 144:ef7eb2e8f9f7 566 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER &&
<> 144:ef7eb2e8f9f7 567 (event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 144:ef7eb2e8f9f7 568 char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 144:ef7eb2e8f9f7 569 obj->serial.dma_usage_rx = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 570 dma_channel_free(obj->serial.dma_chn_id_rx);
<> 144:ef7eb2e8f9f7 571 obj->serial.dma_chn_id_rx = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 // UART IRQ is necessary for both interrupt way and DMA way
<> 144:ef7eb2e8f9f7 575 serial_rx_enable_event(obj, event, 1);
<> 144:ef7eb2e8f9f7 576 serial_rx_buffer_set(obj, rx, rx_length, rx_width);
<> 144:ef7eb2e8f9f7 577 serial_rx_set_char_match(obj, char_match);
<> 144:ef7eb2e8f9f7 578 //UART_HAL_DisableReceiver(obj->serial.address);
<> 144:ef7eb2e8f9f7 579 //UART_HAL_FlushRxFifo(obj->serial.address);
<> 144:ef7eb2e8f9f7 580 //UART_HAL_EnableReceiver(obj->serial.address);
<> 144:ef7eb2e8f9f7 581
<> 144:ef7eb2e8f9f7 582 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 583 // Interrupt way
<> 144:ef7eb2e8f9f7 584 serial_rx_enable_interrupt(obj, handler, 1);
<> 144:ef7eb2e8f9f7 585 } else {
<> 144:ef7eb2e8f9f7 586 // DMA way
<> 144:ef7eb2e8f9f7 587 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 588 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 589 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 590
<> 161:2cc1468da177 591 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 592
<> 161:2cc1468da177 593 pdma_base->CHCTL |= 1 << obj->serial.dma_chn_id_rx; // Enable this DMA channel
<> 144:ef7eb2e8f9f7 594 PDMA_SetTransferMode(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 595 ((struct nu_uart_var *) modinit->var)->pdma_perp_rx, // Peripheral connected to this PDMA
<> 144:ef7eb2e8f9f7 596 0, // Scatter-gather disabled
<> 144:ef7eb2e8f9f7 597 0); // Scatter-gather descriptor address
<> 144:ef7eb2e8f9f7 598 PDMA_SetTransferCnt(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 599 (rx_width == 8) ? PDMA_WIDTH_8 : (rx_width == 16) ? PDMA_WIDTH_16 : PDMA_WIDTH_32,
<> 144:ef7eb2e8f9f7 600 rx_length);
<> 144:ef7eb2e8f9f7 601 PDMA_SetTransferAddr(obj->serial.dma_chn_id_rx,
<> 161:2cc1468da177 602 (uint32_t) NU_MODBASE(obj->serial.uart), // Source address
<> 144:ef7eb2e8f9f7 603 PDMA_SAR_FIX, // Source address fixed
<> 144:ef7eb2e8f9f7 604 ((uint32_t) rx) + (rx_width / 8) * rx_length, // NOTE: End of destination address
<> 144:ef7eb2e8f9f7 605 PDMA_DAR_INC); // Destination address incremental
<> 144:ef7eb2e8f9f7 606 PDMA_SetBurstType(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 607 PDMA_REQ_SINGLE, // Single mode
<> 144:ef7eb2e8f9f7 608 0); // Burst size
<> 144:ef7eb2e8f9f7 609 PDMA_EnableInt(obj->serial.dma_chn_id_rx,
<> 144:ef7eb2e8f9f7 610 0); // Interrupt type. No use here
<> 144:ef7eb2e8f9f7 611 // Register DMA event handler
<> 144:ef7eb2e8f9f7 612 dma_set_handler(obj->serial.dma_chn_id_rx, (uint32_t) uart_dma_handler_rx, (uint32_t) obj, DMA_EVENT_ALL);
<> 144:ef7eb2e8f9f7 613 serial_rx_enable_interrupt(obj, handler, 1);
AnnaBridge 184:08ed48f1de7f 614 /* We needn't actually enable UART INT to go UART ISR -> handler.
AnnaBridge 184:08ed48f1de7f 615 * Instead, as PDMA INT is triggered, we will go PDMA ISR -> UART ISR -> handler
AnnaBridge 184:08ed48f1de7f 616 * with serial_tx/rx_enable_interrupt having set up this call path. */
AnnaBridge 184:08ed48f1de7f 617 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 618 ((UART_T *) NU_MODBASE(obj->serial.uart))->INTEN |= UART_INTEN_RXPDMAEN_Msk; // Start DMA transfer
<> 144:ef7eb2e8f9f7 619 }
<> 144:ef7eb2e8f9f7 620 }
<> 144:ef7eb2e8f9f7 621
<> 144:ef7eb2e8f9f7 622 void serial_tx_abort_asynch(serial_t *obj)
<> 144:ef7eb2e8f9f7 623 {
<> 144:ef7eb2e8f9f7 624 // Flush Tx FIFO. Otherwise, output data may get lost on this change.
<> 161:2cc1468da177 625 while (! UART_IS_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart))));
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 if (obj->serial.dma_usage_tx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 628 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 629
<> 144:ef7eb2e8f9f7 630 if (obj->serial.dma_chn_id_tx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 631 PDMA_DisableInt(obj->serial.dma_chn_id_tx, 0);
<> 144:ef7eb2e8f9f7 632 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 144:ef7eb2e8f9f7 633 //PDMA_STOP(obj->serial.dma_chn_id_tx);
<> 161:2cc1468da177 634 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_tx);
<> 144:ef7eb2e8f9f7 635 }
<> 144:ef7eb2e8f9f7 636 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_TXPDMAEN_Msk);
<> 144:ef7eb2e8f9f7 637 }
<> 144:ef7eb2e8f9f7 638
<> 144:ef7eb2e8f9f7 639 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 640 serial_enable_interrupt(obj, TxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 641 serial_rollback_interrupt(obj, TxIrq);
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 void serial_rx_abort_asynch(serial_t *obj)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 if (obj->serial.dma_usage_rx != DMA_USAGE_NEVER) {
<> 161:2cc1468da177 647 PDMA_T *pdma_base = dma_modbase();
<> 161:2cc1468da177 648
<> 144:ef7eb2e8f9f7 649 if (obj->serial.dma_chn_id_rx != DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 650 PDMA_DisableInt(obj->serial.dma_chn_id_rx, 0);
<> 144:ef7eb2e8f9f7 651 // FIXME: Next PDMA transfer will fail with PDMA_STOP() called. Cause is unknown.
<> 144:ef7eb2e8f9f7 652 //PDMA_STOP(obj->serial.dma_chn_id_rx);
<> 161:2cc1468da177 653 pdma_base->CHCTL &= ~(1 << obj->serial.dma_chn_id_rx);
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RXPDMAEN_Msk);
<> 144:ef7eb2e8f9f7 656 }
<> 144:ef7eb2e8f9f7 657
<> 144:ef7eb2e8f9f7 658 // Necessary for both interrupt way and DMA way
AnnaBridge 165:e614a9f1c9e2 659 serial_enable_interrupt(obj, RxIrq, 0);
AnnaBridge 165:e614a9f1c9e2 660 serial_rollback_interrupt(obj, RxIrq);
<> 144:ef7eb2e8f9f7 661 }
<> 144:ef7eb2e8f9f7 662
<> 144:ef7eb2e8f9f7 663 uint8_t serial_tx_active(serial_t *obj)
<> 144:ef7eb2e8f9f7 664 {
AnnaBridge 165:e614a9f1c9e2 665 // NOTE: Judge by serial_is_irq_en(obj, TxIrq) doesn't work with sync/async modes interleaved. Change with TX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 666 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 667 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 668 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 669
AnnaBridge 165:e614a9f1c9e2 670 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 671 return (obj->serial.vec == var->vec_async);
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 uint8_t serial_rx_active(serial_t *obj)
<> 144:ef7eb2e8f9f7 675 {
AnnaBridge 165:e614a9f1c9e2 676 // NOTE: Judge by serial_is_irq_en(obj, RxIrq) doesn't work with sync/async modes interleaved. Change with RX FIFO empty flag.
AnnaBridge 165:e614a9f1c9e2 677 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 678 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 679 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 680
AnnaBridge 165:e614a9f1c9e2 681 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 682 return (obj->serial.vec == var->vec_async);
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684
<> 144:ef7eb2e8f9f7 685 int serial_irq_handler_asynch(serial_t *obj)
<> 144:ef7eb2e8f9f7 686 {
<> 144:ef7eb2e8f9f7 687 int event_rx = 0;
<> 144:ef7eb2e8f9f7 688 int event_tx = 0;
<> 144:ef7eb2e8f9f7 689
<> 151:5eaa88a5bcc7 690 // Necessary for both interrupt way and DMA way
<> 144:ef7eb2e8f9f7 691 if (serial_is_irq_en(obj, RxIrq)) {
<> 144:ef7eb2e8f9f7 692 event_rx = serial_rx_event_check(obj);
<> 144:ef7eb2e8f9f7 693 if (event_rx) {
<> 144:ef7eb2e8f9f7 694 serial_rx_abort_asynch(obj);
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 if (serial_is_irq_en(obj, TxIrq)) {
<> 144:ef7eb2e8f9f7 699 event_tx = serial_tx_event_check(obj);
<> 144:ef7eb2e8f9f7 700 if (event_tx) {
<> 144:ef7eb2e8f9f7 701 serial_tx_abort_asynch(obj);
<> 144:ef7eb2e8f9f7 702 }
<> 144:ef7eb2e8f9f7 703 }
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 return (obj->serial.event & (event_rx | event_tx));
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707
<> 144:ef7eb2e8f9f7 708 static void uart0_vec_async(void)
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 uart_irq_async(uart0_var.obj);
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 static void uart1_vec_async(void)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 uart_irq_async(uart1_var.obj);
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717
<> 144:ef7eb2e8f9f7 718 static void uart2_vec_async(void)
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 uart_irq_async(uart2_var.obj);
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 static void uart3_vec_async(void)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 uart_irq_async(uart3_var.obj);
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727
<> 144:ef7eb2e8f9f7 728 static void uart4_vec_async(void)
<> 144:ef7eb2e8f9f7 729 {
<> 144:ef7eb2e8f9f7 730 uart_irq_async(uart4_var.obj);
<> 144:ef7eb2e8f9f7 731 }
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 static void uart5_vec_async(void)
<> 144:ef7eb2e8f9f7 734 {
<> 144:ef7eb2e8f9f7 735 uart_irq_async(uart5_var.obj);
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 static void uart_irq_async(serial_t *obj)
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 if (serial_is_irq_en(obj, RxIrq)) {
<> 144:ef7eb2e8f9f7 741 (*obj->serial.irq_handler_rx_async)();
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743 if (serial_is_irq_en(obj, TxIrq)) {
<> 144:ef7eb2e8f9f7 744 (*obj->serial.irq_handler_tx_async)();
<> 144:ef7eb2e8f9f7 745 }
<> 144:ef7eb2e8f9f7 746 }
<> 144:ef7eb2e8f9f7 747
<> 144:ef7eb2e8f9f7 748 static void serial_rx_set_char_match(serial_t *obj, uint8_t char_match)
<> 144:ef7eb2e8f9f7 749 {
<> 144:ef7eb2e8f9f7 750 obj->char_match = char_match;
<> 144:ef7eb2e8f9f7 751 obj->char_found = 0;
<> 144:ef7eb2e8f9f7 752 }
<> 144:ef7eb2e8f9f7 753
<> 144:ef7eb2e8f9f7 754 static void serial_tx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 144:ef7eb2e8f9f7 755 {
<> 144:ef7eb2e8f9f7 756 obj->serial.event &= ~SERIAL_EVENT_TX_MASK;
<> 144:ef7eb2e8f9f7 757 obj->serial.event |= (event & SERIAL_EVENT_TX_MASK);
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 //if (event & SERIAL_EVENT_TX_COMPLETE) {
<> 144:ef7eb2e8f9f7 760 //}
<> 144:ef7eb2e8f9f7 761 }
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 static void serial_rx_enable_event(serial_t *obj, int event, uint8_t enable)
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 obj->serial.event &= ~SERIAL_EVENT_RX_MASK;
<> 144:ef7eb2e8f9f7 766 obj->serial.event |= (event & SERIAL_EVENT_RX_MASK);
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 //if (event & SERIAL_EVENT_RX_COMPLETE) {
<> 144:ef7eb2e8f9f7 769 //}
<> 144:ef7eb2e8f9f7 770 //if (event & SERIAL_EVENT_RX_OVERRUN_ERROR) {
<> 144:ef7eb2e8f9f7 771 //}
<> 144:ef7eb2e8f9f7 772 if (event & SERIAL_EVENT_RX_FRAMING_ERROR) {
<> 144:ef7eb2e8f9f7 773 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 144:ef7eb2e8f9f7 774 }
<> 144:ef7eb2e8f9f7 775 if (event & SERIAL_EVENT_RX_PARITY_ERROR) {
<> 144:ef7eb2e8f9f7 776 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_RLSIEN_Msk);
<> 144:ef7eb2e8f9f7 777 }
<> 144:ef7eb2e8f9f7 778 if (event & SERIAL_EVENT_RX_OVERFLOW) {
<> 144:ef7eb2e8f9f7 779 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_BUFERRIEN_Msk);
<> 144:ef7eb2e8f9f7 780 }
<> 144:ef7eb2e8f9f7 781 //if (event & SERIAL_EVENT_RX_CHARACTER_MATCH) {
<> 144:ef7eb2e8f9f7 782 //}
<> 144:ef7eb2e8f9f7 783 }
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 static int serial_is_tx_complete(serial_t *obj)
<> 144:ef7eb2e8f9f7 786 {
<> 144:ef7eb2e8f9f7 787 // NOTE: Exclude tx fifo empty check due to no such interrupt on DMA way
<> 144:ef7eb2e8f9f7 788 //return (obj->tx_buff.pos == obj->tx_buff.length) && UART_GET_TX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 789 // FIXME: Premature abort???
<> 144:ef7eb2e8f9f7 790 return (obj->tx_buff.pos == obj->tx_buff.length);
<> 144:ef7eb2e8f9f7 791 }
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 static int serial_is_rx_complete(serial_t *obj)
<> 144:ef7eb2e8f9f7 794 {
<> 144:ef7eb2e8f9f7 795 //return (obj->rx_buff.pos == obj->rx_buff.length) && UART_GET_RX_EMPTY(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 796 return (obj->rx_buff.pos == obj->rx_buff.length);
<> 144:ef7eb2e8f9f7 797 }
<> 144:ef7eb2e8f9f7 798
<> 144:ef7eb2e8f9f7 799 static uint32_t serial_tx_event_check(serial_t *obj)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 if (uart_base->INTSTS & UART_INTSTS_THREINT_Msk) {
<> 144:ef7eb2e8f9f7 804 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next write.
<> 144:ef7eb2e8f9f7 805 UART_DISABLE_INT(uart_base, UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 806 }
<> 144:ef7eb2e8f9f7 807
<> 144:ef7eb2e8f9f7 808 uint32_t event = 0;
<> 144:ef7eb2e8f9f7 809
<> 144:ef7eb2e8f9f7 810 if (obj->serial.dma_usage_tx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 811 serial_write_async(obj);
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 if (serial_is_tx_complete(obj)) {
<> 144:ef7eb2e8f9f7 815 event |= SERIAL_EVENT_TX_COMPLETE;
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817
<> 144:ef7eb2e8f9f7 818 return event;
<> 144:ef7eb2e8f9f7 819 }
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 static uint32_t serial_rx_event_check(serial_t *obj)
<> 144:ef7eb2e8f9f7 822 {
<> 144:ef7eb2e8f9f7 823 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 if (uart_base->INTSTS & (UART_INTSTS_RDAINT_Msk | UART_INTSTS_RXTOINT_Msk)) {
<> 144:ef7eb2e8f9f7 826 // Simulate clear of the interrupt flag. Temporarily disable the interrupt here and to be recovered on next read.
<> 144:ef7eb2e8f9f7 827 UART_DISABLE_INT(uart_base, (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 828 }
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 uint32_t event = 0;
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 if (uart_base->FIFOSTS & UART_FIFOSTS_BIF_Msk) {
<> 144:ef7eb2e8f9f7 833 uart_base->FIFOSTS = UART_FIFOSTS_BIF_Msk;
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 if (uart_base->FIFOSTS & UART_FIFOSTS_FEF_Msk) {
<> 144:ef7eb2e8f9f7 836 uart_base->FIFOSTS = UART_FIFOSTS_FEF_Msk;
<> 144:ef7eb2e8f9f7 837 event |= SERIAL_EVENT_RX_FRAMING_ERROR;
<> 144:ef7eb2e8f9f7 838 }
<> 144:ef7eb2e8f9f7 839 if (uart_base->FIFOSTS & UART_FIFOSTS_PEF_Msk) {
<> 144:ef7eb2e8f9f7 840 uart_base->FIFOSTS = UART_FIFOSTS_PEF_Msk;
<> 144:ef7eb2e8f9f7 841 event |= SERIAL_EVENT_RX_PARITY_ERROR;
<> 144:ef7eb2e8f9f7 842 }
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 if (uart_base->FIFOSTS & UART_FIFOSTS_RXOVIF_Msk) {
<> 144:ef7eb2e8f9f7 845 uart_base->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk;
<> 144:ef7eb2e8f9f7 846 event |= SERIAL_EVENT_RX_OVERFLOW;
<> 144:ef7eb2e8f9f7 847 }
<> 144:ef7eb2e8f9f7 848
<> 144:ef7eb2e8f9f7 849 if (obj->serial.dma_usage_rx == DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 850 serial_read_async(obj);
<> 144:ef7eb2e8f9f7 851 }
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 if (serial_is_rx_complete(obj)) {
<> 144:ef7eb2e8f9f7 854 event |= SERIAL_EVENT_RX_COMPLETE;
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856 if ((obj->char_match != SERIAL_RESERVED_CHAR_MATCH) && obj->char_found) {
<> 144:ef7eb2e8f9f7 857 event |= SERIAL_EVENT_RX_CHARACTER_MATCH;
<> 144:ef7eb2e8f9f7 858 // FIXME: Timing to reset char_found?
<> 144:ef7eb2e8f9f7 859 //obj->char_found = 0;
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 return event;
<> 144:ef7eb2e8f9f7 863 }
<> 144:ef7eb2e8f9f7 864
<> 144:ef7eb2e8f9f7 865 static void uart_dma_handler_tx(uint32_t id, uint32_t event_dma)
<> 144:ef7eb2e8f9f7 866 {
<> 144:ef7eb2e8f9f7 867 serial_t *obj = (serial_t *) id;
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 870 if (event_dma & DMA_EVENT_ABORT) {
<> 144:ef7eb2e8f9f7 871 }
<> 144:ef7eb2e8f9f7 872 // Expect UART IRQ will catch this transfer done event
<> 144:ef7eb2e8f9f7 873 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 144:ef7eb2e8f9f7 874 obj->tx_buff.pos = obj->tx_buff.length;
<> 144:ef7eb2e8f9f7 875 }
<> 144:ef7eb2e8f9f7 876 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 877 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 144:ef7eb2e8f9f7 878 }
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 uart_irq_async(obj);
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 static void uart_dma_handler_rx(uint32_t id, uint32_t event_dma)
<> 144:ef7eb2e8f9f7 884 {
<> 144:ef7eb2e8f9f7 885 serial_t *obj = (serial_t *) id;
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 888 if (event_dma & DMA_EVENT_ABORT) {
<> 144:ef7eb2e8f9f7 889 }
<> 144:ef7eb2e8f9f7 890 // Expect UART IRQ will catch this transfer done event
<> 144:ef7eb2e8f9f7 891 if (event_dma & DMA_EVENT_TRANSFER_DONE) {
<> 144:ef7eb2e8f9f7 892 obj->rx_buff.pos = obj->rx_buff.length;
<> 144:ef7eb2e8f9f7 893 }
<> 144:ef7eb2e8f9f7 894 // FIXME: Pass this error to caller
<> 144:ef7eb2e8f9f7 895 if (event_dma & DMA_EVENT_TIMEOUT) {
<> 144:ef7eb2e8f9f7 896 }
<> 144:ef7eb2e8f9f7 897
<> 144:ef7eb2e8f9f7 898 uart_irq_async(obj);
<> 144:ef7eb2e8f9f7 899 }
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 static int serial_write_async(serial_t *obj)
<> 144:ef7eb2e8f9f7 902 {
<> 144:ef7eb2e8f9f7 903 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 904 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 905 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 UART_T *uart_base = (UART_T *) NU_MODBASE(obj->serial.uart);
<> 144:ef7eb2e8f9f7 908
<> 144:ef7eb2e8f9f7 909 uint32_t tx_fifo_max = ((struct nu_uart_var *) modinit->var)->fifo_size_tx;
<> 144:ef7eb2e8f9f7 910 uint32_t tx_fifo_busy = (uart_base->FIFOSTS & UART_FIFOSTS_TXPTR_Msk) >> UART_FIFOSTS_TXPTR_Pos;
<> 144:ef7eb2e8f9f7 911 if (uart_base->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) {
<> 144:ef7eb2e8f9f7 912 tx_fifo_busy = tx_fifo_max;
<> 144:ef7eb2e8f9f7 913 }
<> 144:ef7eb2e8f9f7 914 uint32_t tx_fifo_free = tx_fifo_max - tx_fifo_busy;
<> 144:ef7eb2e8f9f7 915 if (tx_fifo_free == 0) {
<> 144:ef7eb2e8f9f7 916 // Simulate clear of the interrupt flag
<> 144:ef7eb2e8f9f7 917 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 144:ef7eb2e8f9f7 918 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 919 }
<> 144:ef7eb2e8f9f7 920 return 0;
<> 144:ef7eb2e8f9f7 921 }
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 uint32_t bytes_per_word = obj->tx_buff.width / 8;
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 uint8_t *tx = (uint8_t *)(obj->tx_buff.buffer) + bytes_per_word * obj->tx_buff.pos;
<> 144:ef7eb2e8f9f7 926 int n_words = 0;
<> 144:ef7eb2e8f9f7 927 while (obj->tx_buff.pos < obj->tx_buff.length && tx_fifo_free >= bytes_per_word) {
<> 144:ef7eb2e8f9f7 928 switch (bytes_per_word) {
<> 144:ef7eb2e8f9f7 929 case 4:
<> 144:ef7eb2e8f9f7 930 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 931 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 932 case 2:
<> 144:ef7eb2e8f9f7 933 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 934 case 1:
<> 144:ef7eb2e8f9f7 935 UART_WRITE(((UART_T *) NU_MODBASE(obj->serial.uart)), *tx ++);
<> 144:ef7eb2e8f9f7 936 }
<> 144:ef7eb2e8f9f7 937
<> 144:ef7eb2e8f9f7 938 n_words ++;
<> 144:ef7eb2e8f9f7 939 tx_fifo_free -= bytes_per_word;
<> 144:ef7eb2e8f9f7 940 obj->tx_buff.pos ++;
<> 144:ef7eb2e8f9f7 941 }
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 if (n_words) {
<> 144:ef7eb2e8f9f7 944 // Simulate clear of the interrupt flag
<> 144:ef7eb2e8f9f7 945 if (obj->serial.inten_msk & UART_INTEN_THREIEN_Msk) {
<> 144:ef7eb2e8f9f7 946 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
<> 144:ef7eb2e8f9f7 947 }
<> 144:ef7eb2e8f9f7 948 }
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 return n_words;
<> 144:ef7eb2e8f9f7 951 }
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 static int serial_read_async(serial_t *obj)
<> 144:ef7eb2e8f9f7 954 {
<> 144:ef7eb2e8f9f7 955 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 956 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 957 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 uint32_t rx_fifo_busy = (((UART_T *) NU_MODBASE(obj->serial.uart))->FIFOSTS & UART_FIFOSTS_RXPTR_Msk) >> UART_FIFOSTS_RXPTR_Pos;
<> 144:ef7eb2e8f9f7 960 //uint32_t rx_fifo_free = ((struct nu_uart_var *) modinit->var)->fifo_size_rx - rx_fifo_busy;
<> 144:ef7eb2e8f9f7 961 //if (rx_fifo_free == 0) {
<> 144:ef7eb2e8f9f7 962 // return 0;
<> 144:ef7eb2e8f9f7 963 //}
<> 144:ef7eb2e8f9f7 964
<> 144:ef7eb2e8f9f7 965 uint32_t bytes_per_word = obj->rx_buff.width / 8;
<> 144:ef7eb2e8f9f7 966
<> 144:ef7eb2e8f9f7 967 uint8_t *rx = (uint8_t *)(obj->rx_buff.buffer) + bytes_per_word * obj->rx_buff.pos;
<> 144:ef7eb2e8f9f7 968 int n_words = 0;
<> 144:ef7eb2e8f9f7 969 while (obj->rx_buff.pos < obj->rx_buff.length && rx_fifo_busy >= bytes_per_word) {
<> 144:ef7eb2e8f9f7 970 switch (bytes_per_word) {
<> 144:ef7eb2e8f9f7 971 case 4:
<> 144:ef7eb2e8f9f7 972 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 973 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 974 case 2:
<> 144:ef7eb2e8f9f7 975 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 976 case 1:
<> 144:ef7eb2e8f9f7 977 *rx ++ = UART_READ(((UART_T *) NU_MODBASE(obj->serial.uart)));
<> 144:ef7eb2e8f9f7 978 }
<> 144:ef7eb2e8f9f7 979
<> 144:ef7eb2e8f9f7 980 n_words ++;
<> 144:ef7eb2e8f9f7 981 rx_fifo_busy -= bytes_per_word;
<> 144:ef7eb2e8f9f7 982 obj->rx_buff.pos ++;
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 if ((obj->serial.event & SERIAL_EVENT_RX_CHARACTER_MATCH) &&
<> 144:ef7eb2e8f9f7 985 obj->char_match != SERIAL_RESERVED_CHAR_MATCH) {
<> 144:ef7eb2e8f9f7 986 uint8_t *rx_cmp = rx;
<> 144:ef7eb2e8f9f7 987 switch (bytes_per_word) {
<> 144:ef7eb2e8f9f7 988 case 4:
<> 144:ef7eb2e8f9f7 989 rx_cmp -= 2;
<> 144:ef7eb2e8f9f7 990 case 2:
<> 144:ef7eb2e8f9f7 991 rx_cmp --;
<> 144:ef7eb2e8f9f7 992 case 1:
<> 144:ef7eb2e8f9f7 993 rx_cmp --;
<> 144:ef7eb2e8f9f7 994 }
<> 144:ef7eb2e8f9f7 995 if (*rx_cmp == obj->char_match) {
<> 144:ef7eb2e8f9f7 996 obj->char_found = 1;
<> 144:ef7eb2e8f9f7 997 break;
<> 144:ef7eb2e8f9f7 998 }
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000 }
<> 144:ef7eb2e8f9f7 1001
<> 144:ef7eb2e8f9f7 1002 if (n_words) {
<> 144:ef7eb2e8f9f7 1003 // Simulate clear of the interrupt flag
<> 144:ef7eb2e8f9f7 1004 if (obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk)) {
<> 144:ef7eb2e8f9f7 1005 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
<> 144:ef7eb2e8f9f7 1006 }
<> 144:ef7eb2e8f9f7 1007 }
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 return n_words;
<> 144:ef7eb2e8f9f7 1010 }
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 static void serial_tx_buffer_set(serial_t *obj, const void *tx, size_t length, uint8_t width)
<> 144:ef7eb2e8f9f7 1013 {
<> 144:ef7eb2e8f9f7 1014 obj->tx_buff.buffer = (void *) tx;
<> 144:ef7eb2e8f9f7 1015 obj->tx_buff.length = length;
<> 144:ef7eb2e8f9f7 1016 obj->tx_buff.pos = 0;
<> 144:ef7eb2e8f9f7 1017 obj->tx_buff.width = width;
<> 144:ef7eb2e8f9f7 1018 }
<> 144:ef7eb2e8f9f7 1019
<> 144:ef7eb2e8f9f7 1020 static void serial_rx_buffer_set(serial_t *obj, void *rx, size_t length, uint8_t width)
<> 144:ef7eb2e8f9f7 1021 {
<> 144:ef7eb2e8f9f7 1022 obj->rx_buff.buffer = rx;
<> 144:ef7eb2e8f9f7 1023 obj->rx_buff.length = length;
<> 144:ef7eb2e8f9f7 1024 obj->rx_buff.pos = 0;
<> 144:ef7eb2e8f9f7 1025 obj->rx_buff.width = width;
<> 144:ef7eb2e8f9f7 1026 }
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 static void serial_tx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 1031 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1032 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1035 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 1036 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1037 obj->serial.vec = var->vec_async;
<> 144:ef7eb2e8f9f7 1038 obj->serial.irq_handler_tx_async = (void (*)(void)) handler;
AnnaBridge 165:e614a9f1c9e2 1039 serial_enable_interrupt(obj, TxIrq, enable);
<> 144:ef7eb2e8f9f7 1040 }
<> 144:ef7eb2e8f9f7 1041
<> 144:ef7eb2e8f9f7 1042 static void serial_rx_enable_interrupt(serial_t *obj, uint32_t handler, uint8_t enable)
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
<> 144:ef7eb2e8f9f7 1045 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1046 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
<> 144:ef7eb2e8f9f7 1047
<> 144:ef7eb2e8f9f7 1048 // Necessary for both interrupt way and DMA way
<> 151:5eaa88a5bcc7 1049 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
<> 144:ef7eb2e8f9f7 1050 // With our own async vector, tx/rx handlers can be different.
<> 151:5eaa88a5bcc7 1051 obj->serial.vec = var->vec_async;
<> 144:ef7eb2e8f9f7 1052 obj->serial.irq_handler_rx_async = (void (*) (void)) handler;
AnnaBridge 165:e614a9f1c9e2 1053 serial_enable_interrupt(obj, RxIrq, enable);
AnnaBridge 165:e614a9f1c9e2 1054 }
AnnaBridge 165:e614a9f1c9e2 1055
AnnaBridge 165:e614a9f1c9e2 1056 static void serial_enable_interrupt(serial_t *obj, SerialIrq irq, uint32_t enable)
AnnaBridge 165:e614a9f1c9e2 1057 {
AnnaBridge 165:e614a9f1c9e2 1058 if (enable) {
AnnaBridge 165:e614a9f1c9e2 1059 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1060 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1061 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1062
AnnaBridge 165:e614a9f1c9e2 1063 NVIC_SetVector(modinit->irq_n, (uint32_t) obj->serial.vec);
AnnaBridge 165:e614a9f1c9e2 1064 NVIC_EnableIRQ(modinit->irq_n);
AnnaBridge 165:e614a9f1c9e2 1065
AnnaBridge 165:e614a9f1c9e2 1066 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1067 // Multiple serial S/W objects for single UART H/W module possibly.
AnnaBridge 165:e614a9f1c9e2 1068 // Bind serial S/W object to UART H/W module as interrupt is enabled.
AnnaBridge 165:e614a9f1c9e2 1069 var->obj = obj;
AnnaBridge 165:e614a9f1c9e2 1070
AnnaBridge 165:e614a9f1c9e2 1071 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1072 // NOTE: Setting inten_msk first to avoid race condition
AnnaBridge 165:e614a9f1c9e2 1073 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1074 obj->serial.inten_msk = obj->serial.inten_msk | (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1075 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1076 break;
AnnaBridge 165:e614a9f1c9e2 1077 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1078 obj->serial.inten_msk = obj->serial.inten_msk | UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1079 UART_ENABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1080 break;
AnnaBridge 165:e614a9f1c9e2 1081 }
AnnaBridge 165:e614a9f1c9e2 1082 }
AnnaBridge 165:e614a9f1c9e2 1083 else { // disable
AnnaBridge 165:e614a9f1c9e2 1084 switch (irq) {
AnnaBridge 165:e614a9f1c9e2 1085 case RxIrq:
AnnaBridge 165:e614a9f1c9e2 1086 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk));
AnnaBridge 165:e614a9f1c9e2 1087 obj->serial.inten_msk = obj->serial.inten_msk & ~(UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1088 break;
AnnaBridge 165:e614a9f1c9e2 1089 case TxIrq:
AnnaBridge 165:e614a9f1c9e2 1090 UART_DISABLE_INT(((UART_T *) NU_MODBASE(obj->serial.uart)), UART_INTEN_THREIEN_Msk);
AnnaBridge 165:e614a9f1c9e2 1091 obj->serial.inten_msk = obj->serial.inten_msk & ~UART_INTEN_THREIEN_Msk;
AnnaBridge 165:e614a9f1c9e2 1092 break;
AnnaBridge 165:e614a9f1c9e2 1093 }
AnnaBridge 165:e614a9f1c9e2 1094 }
AnnaBridge 165:e614a9f1c9e2 1095 }
AnnaBridge 165:e614a9f1c9e2 1096
AnnaBridge 165:e614a9f1c9e2 1097 static void serial_rollback_interrupt(serial_t *obj, SerialIrq irq)
AnnaBridge 165:e614a9f1c9e2 1098 {
AnnaBridge 165:e614a9f1c9e2 1099 const struct nu_modinit_s *modinit = get_modinit(obj->serial.uart, uart_modinit_tab);
AnnaBridge 165:e614a9f1c9e2 1100 MBED_ASSERT(modinit != NULL);
AnnaBridge 165:e614a9f1c9e2 1101 MBED_ASSERT(modinit->modname == (int) obj->serial.uart);
AnnaBridge 165:e614a9f1c9e2 1102
AnnaBridge 165:e614a9f1c9e2 1103 struct nu_uart_var *var = (struct nu_uart_var *) modinit->var;
AnnaBridge 165:e614a9f1c9e2 1104
AnnaBridge 165:e614a9f1c9e2 1105 obj->serial.vec = var->vec;
AnnaBridge 165:e614a9f1c9e2 1106 serial_enable_interrupt(obj, irq, obj->serial.irq_en);
<> 144:ef7eb2e8f9f7 1107 }
<> 144:ef7eb2e8f9f7 1108
<> 144:ef7eb2e8f9f7 1109 static void serial_check_dma_usage(DMAUsage *dma_usage, int *dma_ch)
<> 144:ef7eb2e8f9f7 1110 {
<> 144:ef7eb2e8f9f7 1111 if (*dma_usage != DMA_USAGE_NEVER) {
<> 144:ef7eb2e8f9f7 1112 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 1113 *dma_ch = dma_channel_allocate(DMA_CAP_NONE);
<> 144:ef7eb2e8f9f7 1114 }
<> 144:ef7eb2e8f9f7 1115 if (*dma_ch == DMA_ERROR_OUT_OF_CHANNELS) {
<> 144:ef7eb2e8f9f7 1116 *dma_usage = DMA_USAGE_NEVER;
<> 144:ef7eb2e8f9f7 1117 }
<> 144:ef7eb2e8f9f7 1118 }
<> 144:ef7eb2e8f9f7 1119 else {
<> 144:ef7eb2e8f9f7 1120 dma_channel_free(*dma_ch);
<> 144:ef7eb2e8f9f7 1121 *dma_ch = DMA_ERROR_OUT_OF_CHANNELS;
<> 144:ef7eb2e8f9f7 1122 }
<> 144:ef7eb2e8f9f7 1123 }
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 static int serial_is_irq_en(serial_t *obj, SerialIrq irq)
<> 144:ef7eb2e8f9f7 1126 {
<> 144:ef7eb2e8f9f7 1127 int inten_msk = 0;
<> 144:ef7eb2e8f9f7 1128
<> 144:ef7eb2e8f9f7 1129 switch (irq) {
<> 144:ef7eb2e8f9f7 1130 case RxIrq:
<> 144:ef7eb2e8f9f7 1131 inten_msk = obj->serial.inten_msk & (UART_INTEN_RDAIEN_Msk | UART_INTEN_RXTOIEN_Msk);
<> 144:ef7eb2e8f9f7 1132 break;
<> 144:ef7eb2e8f9f7 1133 case TxIrq:
<> 144:ef7eb2e8f9f7 1134 inten_msk = obj->serial.inten_msk & UART_INTEN_THREIEN_Msk;
<> 144:ef7eb2e8f9f7 1135 break;
<> 144:ef7eb2e8f9f7 1136 }
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 return !! inten_msk;
<> 144:ef7eb2e8f9f7 1139 }
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 #endif // #if DEVICE_SERIAL_ASYNCH
AnnaBridge 188:bcfe06ba3d64 1142
AnnaBridge 188:bcfe06ba3d64 1143 bool serial_can_deep_sleep(void)
AnnaBridge 188:bcfe06ba3d64 1144 {
AnnaBridge 188:bcfe06ba3d64 1145 bool sleep_allowed = 1;
AnnaBridge 188:bcfe06ba3d64 1146 const struct nu_modinit_s *modinit = uart_modinit_tab;
AnnaBridge 188:bcfe06ba3d64 1147 while (modinit->var != NULL) {
AnnaBridge 188:bcfe06ba3d64 1148 struct nu_uart_var *uart_var = (struct nu_uart_var *) modinit->var;
AnnaBridge 188:bcfe06ba3d64 1149 UART_T *uart_base = (UART_T *) NU_MODBASE(modinit->modname);
AnnaBridge 188:bcfe06ba3d64 1150 if (uart_var->ref_cnt > 0) {
AnnaBridge 188:bcfe06ba3d64 1151 if (!UART_IS_TX_EMPTY(uart_base)) {
AnnaBridge 188:bcfe06ba3d64 1152 sleep_allowed = 0;
AnnaBridge 188:bcfe06ba3d64 1153 break;
AnnaBridge 188:bcfe06ba3d64 1154 }
AnnaBridge 188:bcfe06ba3d64 1155 }
AnnaBridge 188:bcfe06ba3d64 1156 modinit++;
AnnaBridge 188:bcfe06ba3d64 1157 }
AnnaBridge 188:bcfe06ba3d64 1158 return sleep_allowed;
AnnaBridge 188:bcfe06ba3d64 1159 }
AnnaBridge 188:bcfe06ba3d64 1160
<> 144:ef7eb2e8f9f7 1161 #endif // #if DEVICE_SERIAL