mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc.c@167:e84263d55307, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:46:44 2017 +0100
- Revision:
- 167:e84263d55307
- Parent:
- 149:156823d33999
This updates the lib to the mbed lib v 145
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f2xx_hal_rcc.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
AnnaBridge | 167:e84263d55307 | 5 | * @version V1.2.1 |
AnnaBridge | 167:e84263d55307 | 6 | * @date 14-April-2017 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief RCC HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 9 | * functionalities of the Reset and Clock Control (RCC) peripheral: |
<> | 144:ef7eb2e8f9f7 | 10 | * + Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 11 | * + Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 12 | * |
<> | 144:ef7eb2e8f9f7 | 13 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 14 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 15 | ##### RCC specific features ##### |
<> | 144:ef7eb2e8f9f7 | 16 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 17 | [..] |
<> | 144:ef7eb2e8f9f7 | 18 | After reset the device is running from Internal High Speed oscillator |
<> | 144:ef7eb2e8f9f7 | 19 | (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache |
<> | 144:ef7eb2e8f9f7 | 20 | and I-Cache are disabled, and all peripherals are off except internal |
<> | 144:ef7eb2e8f9f7 | 21 | SRAM, Flash and JTAG. |
<> | 144:ef7eb2e8f9f7 | 22 | (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses; |
<> | 144:ef7eb2e8f9f7 | 23 | all peripherals mapped on these busses are running at HSI speed. |
<> | 144:ef7eb2e8f9f7 | 24 | (+) The clock for all peripherals is switched off, except the SRAM and FLASH. |
<> | 144:ef7eb2e8f9f7 | 25 | (+) All GPIOs are in input floating state, except the JTAG pins which |
<> | 144:ef7eb2e8f9f7 | 26 | are assigned to be used for debug purpose. |
<> | 144:ef7eb2e8f9f7 | 27 | |
<> | 144:ef7eb2e8f9f7 | 28 | [..] |
<> | 144:ef7eb2e8f9f7 | 29 | Once the device started from reset, the user application has to: |
<> | 144:ef7eb2e8f9f7 | 30 | (+) Configure the clock source to be used to drive the System clock |
<> | 144:ef7eb2e8f9f7 | 31 | (if the application needs higher frequency/performance) |
<> | 144:ef7eb2e8f9f7 | 32 | (+) Configure the System clock frequency and Flash settings |
<> | 144:ef7eb2e8f9f7 | 33 | (+) Configure the AHB and APB busses prescalers |
<> | 144:ef7eb2e8f9f7 | 34 | (+) Enable the clock for the peripheral(s) to be used |
<> | 144:ef7eb2e8f9f7 | 35 | (+) Configure the clock source(s) for peripherals which clocks are not |
<> | 144:ef7eb2e8f9f7 | 36 | derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | ##### RCC Limitations ##### |
<> | 144:ef7eb2e8f9f7 | 39 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 40 | [..] |
<> | 144:ef7eb2e8f9f7 | 41 | A delay between an RCC peripheral clock enable and the effective peripheral |
<> | 144:ef7eb2e8f9f7 | 42 | enabling should be taken into account in order to manage the peripheral read/write |
<> | 144:ef7eb2e8f9f7 | 43 | from/to registers. |
<> | 144:ef7eb2e8f9f7 | 44 | (+) This delay depends on the peripheral mapping. |
<> | 144:ef7eb2e8f9f7 | 45 | (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle |
<> | 144:ef7eb2e8f9f7 | 46 | after the clock enable bit is set on the hardware register |
<> | 144:ef7eb2e8f9f7 | 47 | (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle |
<> | 144:ef7eb2e8f9f7 | 48 | after the clock enable bit is set on the hardware register |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | [..] |
AnnaBridge | 167:e84263d55307 | 51 | Implemented Workaround: |
AnnaBridge | 167:e84263d55307 | 52 | (+) For AHB & APB peripherals, a dummy read to the peripheral register has been |
AnnaBridge | 167:e84263d55307 | 53 | inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro. |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 56 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 57 | * @attention |
<> | 144:ef7eb2e8f9f7 | 58 | * |
AnnaBridge | 167:e84263d55307 | 59 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 60 | * |
<> | 144:ef7eb2e8f9f7 | 61 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 62 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 63 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 64 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 65 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 66 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 67 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 68 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 69 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 70 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 71 | * |
<> | 144:ef7eb2e8f9f7 | 72 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 73 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 74 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 75 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 76 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 77 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 78 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 79 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 80 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 81 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 82 | * |
<> | 144:ef7eb2e8f9f7 | 83 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 84 | */ |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 87 | #include "stm32f2xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | /** @addtogroup STM32F2xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 90 | * @{ |
<> | 144:ef7eb2e8f9f7 | 91 | */ |
<> | 144:ef7eb2e8f9f7 | 92 | |
<> | 144:ef7eb2e8f9f7 | 93 | /** @defgroup RCC RCC |
<> | 144:ef7eb2e8f9f7 | 94 | * @brief RCC HAL module driver |
<> | 144:ef7eb2e8f9f7 | 95 | * @{ |
<> | 144:ef7eb2e8f9f7 | 96 | */ |
<> | 144:ef7eb2e8f9f7 | 97 | |
<> | 144:ef7eb2e8f9f7 | 98 | #ifdef HAL_RCC_MODULE_ENABLED |
<> | 144:ef7eb2e8f9f7 | 99 | |
<> | 144:ef7eb2e8f9f7 | 100 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 101 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 102 | /** @addtogroup RCC_Private_Constants |
<> | 144:ef7eb2e8f9f7 | 103 | * @{ |
<> | 144:ef7eb2e8f9f7 | 104 | */ |
AnnaBridge | 167:e84263d55307 | 105 | #define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */ |
<> | 144:ef7eb2e8f9f7 | 106 | |
<> | 144:ef7eb2e8f9f7 | 107 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 108 | #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 109 | #define MCO1_GPIO_PORT GPIOA |
<> | 144:ef7eb2e8f9f7 | 110 | #define MCO1_PIN GPIO_PIN_8 |
<> | 144:ef7eb2e8f9f7 | 111 | |
<> | 144:ef7eb2e8f9f7 | 112 | #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 113 | #define MCO2_GPIO_PORT GPIOC |
<> | 144:ef7eb2e8f9f7 | 114 | #define MCO2_PIN GPIO_PIN_9 |
<> | 144:ef7eb2e8f9f7 | 115 | /** |
<> | 144:ef7eb2e8f9f7 | 116 | * @} |
<> | 144:ef7eb2e8f9f7 | 117 | */ |
<> | 144:ef7eb2e8f9f7 | 118 | |
<> | 144:ef7eb2e8f9f7 | 119 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 120 | /** @defgroup RCC_Private_Variables RCC Private Variables |
<> | 144:ef7eb2e8f9f7 | 121 | * @{ |
<> | 144:ef7eb2e8f9f7 | 122 | */ |
<> | 144:ef7eb2e8f9f7 | 123 | /** |
<> | 144:ef7eb2e8f9f7 | 124 | * @} |
<> | 144:ef7eb2e8f9f7 | 125 | */ |
<> | 144:ef7eb2e8f9f7 | 126 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 127 | /* Private functions ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 128 | |
<> | 144:ef7eb2e8f9f7 | 129 | /** @defgroup RCC_Exported_Functions RCC Exported Functions |
<> | 144:ef7eb2e8f9f7 | 130 | * @{ |
<> | 144:ef7eb2e8f9f7 | 131 | */ |
<> | 144:ef7eb2e8f9f7 | 132 | |
<> | 144:ef7eb2e8f9f7 | 133 | /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 134 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 135 | * |
<> | 144:ef7eb2e8f9f7 | 136 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 137 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 138 | ##### Initialization and de-initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 139 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 140 | [..] |
<> | 144:ef7eb2e8f9f7 | 141 | This section provides functions allowing to configure the internal/external oscillators |
<> | 144:ef7eb2e8f9f7 | 142 | (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 |
<> | 144:ef7eb2e8f9f7 | 143 | and APB2). |
<> | 144:ef7eb2e8f9f7 | 144 | |
<> | 144:ef7eb2e8f9f7 | 145 | [..] Internal/external clock and PLL configuration |
<> | 144:ef7eb2e8f9f7 | 146 | (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through |
<> | 144:ef7eb2e8f9f7 | 147 | the PLL as System clock source. |
<> | 144:ef7eb2e8f9f7 | 148 | |
<> | 144:ef7eb2e8f9f7 | 149 | (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC |
<> | 144:ef7eb2e8f9f7 | 150 | clock source. |
<> | 144:ef7eb2e8f9f7 | 151 | |
<> | 144:ef7eb2e8f9f7 | 152 | (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or |
<> | 144:ef7eb2e8f9f7 | 153 | through the PLL as System clock source. Can be used also as RTC clock source. |
<> | 144:ef7eb2e8f9f7 | 154 | |
<> | 144:ef7eb2e8f9f7 | 155 | (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. |
<> | 144:ef7eb2e8f9f7 | 156 | |
<> | 144:ef7eb2e8f9f7 | 157 | (#) PLL (clocked by HSI or HSE), featuring two different output clocks: |
<> | 144:ef7eb2e8f9f7 | 158 | (++) The first output is used to generate the high speed system clock (up to 120 MHz) |
<> | 144:ef7eb2e8f9f7 | 159 | (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), |
<> | 144:ef7eb2e8f9f7 | 160 | the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). |
<> | 144:ef7eb2e8f9f7 | 161 | |
<> | 144:ef7eb2e8f9f7 | 162 | (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 163 | and if a HSE clock failure occurs(HSE used directly or through PLL as System |
<> | 144:ef7eb2e8f9f7 | 164 | clock source), the System clocks automatically switched to HSI and an interrupt |
<> | 144:ef7eb2e8f9f7 | 165 | is generated if enabled. The interrupt is linked to the Cortex-M3 NMI |
<> | 144:ef7eb2e8f9f7 | 166 | (Non-Maskable Interrupt) exception vector. |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL |
<> | 144:ef7eb2e8f9f7 | 169 | clock (through a configurable prescaler) on PA8 pin. |
<> | 144:ef7eb2e8f9f7 | 170 | |
<> | 144:ef7eb2e8f9f7 | 171 | (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S |
<> | 144:ef7eb2e8f9f7 | 172 | clock (through a configurable prescaler) on PC9 pin. |
<> | 144:ef7eb2e8f9f7 | 173 | |
<> | 144:ef7eb2e8f9f7 | 174 | [..] System, AHB and APB busses clocks configuration |
<> | 144:ef7eb2e8f9f7 | 175 | (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI, |
<> | 144:ef7eb2e8f9f7 | 176 | HSE and PLL. |
<> | 144:ef7eb2e8f9f7 | 177 | The AHB clock (HCLK) is derived from System clock through configurable |
<> | 144:ef7eb2e8f9f7 | 178 | prescaler and used to clock the CPU, memory and peripherals mapped |
<> | 144:ef7eb2e8f9f7 | 179 | on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived |
<> | 144:ef7eb2e8f9f7 | 180 | from AHB clock through configurable prescalers and used to clock |
<> | 144:ef7eb2e8f9f7 | 181 | the peripherals mapped on these busses. You can use |
<> | 144:ef7eb2e8f9f7 | 182 | "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. |
<> | 144:ef7eb2e8f9f7 | 183 | |
<> | 144:ef7eb2e8f9f7 | 184 | -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: |
<> | 144:ef7eb2e8f9f7 | 185 | (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or |
<> | 144:ef7eb2e8f9f7 | 186 | from an external clock mapped on the I2S_CKIN pin. |
<> | 144:ef7eb2e8f9f7 | 187 | You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock. |
<> | 144:ef7eb2e8f9f7 | 188 | (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock |
<> | 144:ef7eb2e8f9f7 | 189 | divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE() |
<> | 144:ef7eb2e8f9f7 | 190 | macros to configure this clock. |
<> | 144:ef7eb2e8f9f7 | 191 | (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz |
<> | 144:ef7eb2e8f9f7 | 192 | to work correctly, while the SDIO require a frequency equal or lower than |
<> | 144:ef7eb2e8f9f7 | 193 | to 48. This clock is derived of the main PLL through PLLQ divider. |
<> | 144:ef7eb2e8f9f7 | 194 | (+@) IWDG clock which is always the LSI clock. |
<> | 144:ef7eb2e8f9f7 | 195 | |
<> | 144:ef7eb2e8f9f7 | 196 | (#) For the stm32f2xx devices, the maximum |
<> | 144:ef7eb2e8f9f7 | 197 | frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz. |
<> | 144:ef7eb2e8f9f7 | 198 | Depending on the device voltage range, the maximum frequency should |
<> | 144:ef7eb2e8f9f7 | 199 | be adapted accordingly: |
<> | 144:ef7eb2e8f9f7 | 200 | +-------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 201 | | Latency | HCLK clock frequency (MHz) | |
<> | 144:ef7eb2e8f9f7 | 202 | | |---------------------------------------------------------------------| |
<> | 144:ef7eb2e8f9f7 | 203 | | | voltage range | voltage range | voltage range | voltage range | |
<> | 144:ef7eb2e8f9f7 | 204 | | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V | |
<> | 144:ef7eb2e8f9f7 | 205 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 206 | |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 | |
<> | 144:ef7eb2e8f9f7 | 207 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 208 | |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 | |
<> | 144:ef7eb2e8f9f7 | 209 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 210 | |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 | |
<> | 144:ef7eb2e8f9f7 | 211 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 212 | |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 | |
<> | 144:ef7eb2e8f9f7 | 213 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 214 | |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 | |
<> | 144:ef7eb2e8f9f7 | 215 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 216 | |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 | |
<> | 144:ef7eb2e8f9f7 | 217 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 218 | |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 | |
<> | 144:ef7eb2e8f9f7 | 219 | |---------------|----------------|----------------|-----------------|-----------------| |
<> | 144:ef7eb2e8f9f7 | 220 | |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120| |
<> | 144:ef7eb2e8f9f7 | 221 | +-------------------------------------------------------------------------------------+ |
<> | 144:ef7eb2e8f9f7 | 222 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 223 | * @{ |
<> | 144:ef7eb2e8f9f7 | 224 | */ |
<> | 144:ef7eb2e8f9f7 | 225 | |
<> | 144:ef7eb2e8f9f7 | 226 | /** |
<> | 144:ef7eb2e8f9f7 | 227 | * @brief Resets the RCC clock configuration to the default reset state. |
<> | 144:ef7eb2e8f9f7 | 228 | * @note The default reset state of the clock configuration is given below: |
<> | 144:ef7eb2e8f9f7 | 229 | * - HSI ON and used as system clock source |
<> | 144:ef7eb2e8f9f7 | 230 | * - HSE, PLL and PLLI2S OFF |
<> | 144:ef7eb2e8f9f7 | 231 | * - AHB, APB1 and APB2 prescaler set to 1. |
<> | 144:ef7eb2e8f9f7 | 232 | * - CSS, MCO1 and MCO2 OFF |
<> | 144:ef7eb2e8f9f7 | 233 | * - All interrupts disabled |
<> | 144:ef7eb2e8f9f7 | 234 | * @note This function doesn't modify the configuration of the |
<> | 144:ef7eb2e8f9f7 | 235 | * - Peripheral clocks |
<> | 144:ef7eb2e8f9f7 | 236 | * - LSI, LSE and RTC clocks |
<> | 144:ef7eb2e8f9f7 | 237 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 238 | */ |
<> | 144:ef7eb2e8f9f7 | 239 | void HAL_RCC_DeInit(void) |
<> | 144:ef7eb2e8f9f7 | 240 | { |
<> | 144:ef7eb2e8f9f7 | 241 | /* Set HSION bit */ |
<> | 144:ef7eb2e8f9f7 | 242 | SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4); |
<> | 144:ef7eb2e8f9f7 | 243 | |
<> | 144:ef7eb2e8f9f7 | 244 | /* Reset CFGR register */ |
<> | 144:ef7eb2e8f9f7 | 245 | CLEAR_REG(RCC->CFGR); |
<> | 144:ef7eb2e8f9f7 | 246 | |
<> | 144:ef7eb2e8f9f7 | 247 | /* Reset HSEON, CSSON, PLLON, PLLI2S */ |
<> | 144:ef7eb2e8f9f7 | 248 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON); |
<> | 144:ef7eb2e8f9f7 | 249 | |
<> | 144:ef7eb2e8f9f7 | 250 | /* Reset PLLCFGR register */ |
<> | 144:ef7eb2e8f9f7 | 251 | CLEAR_REG(RCC->PLLCFGR); |
<> | 144:ef7eb2e8f9f7 | 252 | SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2); |
<> | 144:ef7eb2e8f9f7 | 253 | |
<> | 144:ef7eb2e8f9f7 | 254 | /* Reset PLLI2SCFGR register */ |
<> | 144:ef7eb2e8f9f7 | 255 | CLEAR_REG(RCC->PLLI2SCFGR); |
<> | 144:ef7eb2e8f9f7 | 256 | SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1); |
<> | 144:ef7eb2e8f9f7 | 257 | |
<> | 144:ef7eb2e8f9f7 | 258 | /* Reset HSEBYP bit */ |
<> | 144:ef7eb2e8f9f7 | 259 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); |
<> | 144:ef7eb2e8f9f7 | 260 | |
<> | 144:ef7eb2e8f9f7 | 261 | /* Disable all interrupts */ |
<> | 144:ef7eb2e8f9f7 | 262 | CLEAR_REG(RCC->CIR); |
<> | 144:ef7eb2e8f9f7 | 263 | |
<> | 144:ef7eb2e8f9f7 | 264 | /* Update the SystemCoreClock global variable */ |
<> | 144:ef7eb2e8f9f7 | 265 | SystemCoreClock = HSI_VALUE; |
<> | 144:ef7eb2e8f9f7 | 266 | } |
<> | 144:ef7eb2e8f9f7 | 267 | |
<> | 144:ef7eb2e8f9f7 | 268 | /** |
<> | 144:ef7eb2e8f9f7 | 269 | * @brief Initializes the RCC Oscillators according to the specified parameters in the |
<> | 144:ef7eb2e8f9f7 | 270 | * RCC_OscInitTypeDef. |
<> | 144:ef7eb2e8f9f7 | 271 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
<> | 144:ef7eb2e8f9f7 | 272 | * contains the configuration information for the RCC Oscillators. |
<> | 144:ef7eb2e8f9f7 | 273 | * @note The PLL is not disabled when used as system clock. |
<> | 144:ef7eb2e8f9f7 | 274 | * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not |
<> | 144:ef7eb2e8f9f7 | 275 | * supported by this API. User should request a transition to LSE Off |
<> | 144:ef7eb2e8f9f7 | 276 | * first and then LSE On or LSE Bypass. |
<> | 144:ef7eb2e8f9f7 | 277 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not |
<> | 144:ef7eb2e8f9f7 | 278 | * supported by this API. User should request a transition to HSE Off |
<> | 144:ef7eb2e8f9f7 | 279 | * first and then HSE On or HSE Bypass. |
<> | 144:ef7eb2e8f9f7 | 280 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 281 | */ |
<> | 144:ef7eb2e8f9f7 | 282 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
<> | 144:ef7eb2e8f9f7 | 283 | { |
<> | 144:ef7eb2e8f9f7 | 284 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 285 | |
<> | 144:ef7eb2e8f9f7 | 286 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 287 | assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); |
<> | 144:ef7eb2e8f9f7 | 288 | /*------------------------------- HSE Configuration ------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 289 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) |
<> | 144:ef7eb2e8f9f7 | 290 | { |
<> | 144:ef7eb2e8f9f7 | 291 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 292 | assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); |
<> | 144:ef7eb2e8f9f7 | 293 | /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ |
<> | 144:ef7eb2e8f9f7 | 294 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\ |
<> | 144:ef7eb2e8f9f7 | 295 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE))) |
<> | 144:ef7eb2e8f9f7 | 296 | { |
<> | 144:ef7eb2e8f9f7 | 297 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) |
<> | 144:ef7eb2e8f9f7 | 298 | { |
<> | 144:ef7eb2e8f9f7 | 299 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 300 | } |
<> | 144:ef7eb2e8f9f7 | 301 | } |
<> | 144:ef7eb2e8f9f7 | 302 | else |
<> | 144:ef7eb2e8f9f7 | 303 | { |
<> | 144:ef7eb2e8f9f7 | 304 | /* Set the new HSE configuration ---------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 305 | __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); |
<> | 144:ef7eb2e8f9f7 | 306 | |
<> | 144:ef7eb2e8f9f7 | 307 | /* Check the HSE State */ |
<> | 144:ef7eb2e8f9f7 | 308 | if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) |
<> | 144:ef7eb2e8f9f7 | 309 | { |
<> | 144:ef7eb2e8f9f7 | 310 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 311 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 312 | |
<> | 144:ef7eb2e8f9f7 | 313 | /* Wait till HSE is ready */ |
<> | 144:ef7eb2e8f9f7 | 314 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 315 | { |
<> | 144:ef7eb2e8f9f7 | 316 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 317 | { |
<> | 144:ef7eb2e8f9f7 | 318 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 319 | } |
<> | 144:ef7eb2e8f9f7 | 320 | } |
<> | 144:ef7eb2e8f9f7 | 321 | } |
<> | 144:ef7eb2e8f9f7 | 322 | else |
<> | 144:ef7eb2e8f9f7 | 323 | { |
<> | 144:ef7eb2e8f9f7 | 324 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 325 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 326 | |
<> | 144:ef7eb2e8f9f7 | 327 | /* Wait till HSE is bypassed or disabled */ |
<> | 144:ef7eb2e8f9f7 | 328 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) |
<> | 144:ef7eb2e8f9f7 | 329 | { |
<> | 144:ef7eb2e8f9f7 | 330 | if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 331 | { |
<> | 144:ef7eb2e8f9f7 | 332 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 333 | } |
<> | 144:ef7eb2e8f9f7 | 334 | } |
<> | 144:ef7eb2e8f9f7 | 335 | } |
<> | 144:ef7eb2e8f9f7 | 336 | } |
<> | 144:ef7eb2e8f9f7 | 337 | } |
<> | 144:ef7eb2e8f9f7 | 338 | /*----------------------------- HSI Configuration --------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 339 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) |
<> | 144:ef7eb2e8f9f7 | 340 | { |
<> | 144:ef7eb2e8f9f7 | 341 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 342 | assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); |
<> | 144:ef7eb2e8f9f7 | 343 | assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); |
<> | 144:ef7eb2e8f9f7 | 344 | |
<> | 144:ef7eb2e8f9f7 | 345 | /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ |
<> | 144:ef7eb2e8f9f7 | 346 | if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\ |
<> | 144:ef7eb2e8f9f7 | 347 | ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI))) |
<> | 144:ef7eb2e8f9f7 | 348 | { |
<> | 144:ef7eb2e8f9f7 | 349 | /* When HSI is used as system clock it will not disabled */ |
<> | 144:ef7eb2e8f9f7 | 350 | if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) |
<> | 144:ef7eb2e8f9f7 | 351 | { |
<> | 144:ef7eb2e8f9f7 | 352 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 353 | } |
<> | 144:ef7eb2e8f9f7 | 354 | /* Otherwise, just the calibration is allowed */ |
<> | 144:ef7eb2e8f9f7 | 355 | else |
<> | 144:ef7eb2e8f9f7 | 356 | { |
<> | 144:ef7eb2e8f9f7 | 357 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ |
<> | 144:ef7eb2e8f9f7 | 358 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
<> | 144:ef7eb2e8f9f7 | 359 | } |
<> | 144:ef7eb2e8f9f7 | 360 | } |
<> | 144:ef7eb2e8f9f7 | 361 | else |
<> | 144:ef7eb2e8f9f7 | 362 | { |
<> | 144:ef7eb2e8f9f7 | 363 | /* Check the HSI State */ |
<> | 144:ef7eb2e8f9f7 | 364 | if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF) |
<> | 144:ef7eb2e8f9f7 | 365 | { |
<> | 144:ef7eb2e8f9f7 | 366 | /* Enable the Internal High Speed oscillator (HSI). */ |
<> | 144:ef7eb2e8f9f7 | 367 | __HAL_RCC_HSI_ENABLE(); |
<> | 144:ef7eb2e8f9f7 | 368 | |
<> | 144:ef7eb2e8f9f7 | 369 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 370 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 371 | |
<> | 144:ef7eb2e8f9f7 | 372 | /* Wait till HSI is ready */ |
<> | 144:ef7eb2e8f9f7 | 373 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 374 | { |
<> | 144:ef7eb2e8f9f7 | 375 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 376 | { |
<> | 144:ef7eb2e8f9f7 | 377 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 378 | } |
<> | 144:ef7eb2e8f9f7 | 379 | } |
<> | 144:ef7eb2e8f9f7 | 380 | |
<> | 144:ef7eb2e8f9f7 | 381 | /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ |
<> | 144:ef7eb2e8f9f7 | 382 | __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); |
<> | 144:ef7eb2e8f9f7 | 383 | } |
<> | 144:ef7eb2e8f9f7 | 384 | else |
<> | 144:ef7eb2e8f9f7 | 385 | { |
<> | 144:ef7eb2e8f9f7 | 386 | /* Disable the Internal High Speed oscillator (HSI). */ |
<> | 144:ef7eb2e8f9f7 | 387 | __HAL_RCC_HSI_DISABLE(); |
<> | 144:ef7eb2e8f9f7 | 388 | |
<> | 144:ef7eb2e8f9f7 | 389 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 390 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 391 | |
<> | 144:ef7eb2e8f9f7 | 392 | /* Wait till HSI is ready */ |
<> | 144:ef7eb2e8f9f7 | 393 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
<> | 144:ef7eb2e8f9f7 | 394 | { |
<> | 144:ef7eb2e8f9f7 | 395 | if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 396 | { |
<> | 144:ef7eb2e8f9f7 | 397 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 398 | } |
<> | 144:ef7eb2e8f9f7 | 399 | } |
<> | 144:ef7eb2e8f9f7 | 400 | } |
<> | 144:ef7eb2e8f9f7 | 401 | } |
<> | 144:ef7eb2e8f9f7 | 402 | } |
<> | 144:ef7eb2e8f9f7 | 403 | /*------------------------------ LSI Configuration -------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 404 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) |
<> | 144:ef7eb2e8f9f7 | 405 | { |
<> | 144:ef7eb2e8f9f7 | 406 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 407 | assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); |
<> | 144:ef7eb2e8f9f7 | 408 | |
<> | 144:ef7eb2e8f9f7 | 409 | /* Check the LSI State */ |
<> | 144:ef7eb2e8f9f7 | 410 | if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF) |
<> | 144:ef7eb2e8f9f7 | 411 | { |
<> | 144:ef7eb2e8f9f7 | 412 | /* Enable the Internal Low Speed oscillator (LSI). */ |
<> | 144:ef7eb2e8f9f7 | 413 | __HAL_RCC_LSI_ENABLE(); |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 416 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | /* Wait till LSI is ready */ |
<> | 144:ef7eb2e8f9f7 | 419 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 420 | { |
<> | 144:ef7eb2e8f9f7 | 421 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 422 | { |
<> | 144:ef7eb2e8f9f7 | 423 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 424 | } |
<> | 144:ef7eb2e8f9f7 | 425 | } |
<> | 144:ef7eb2e8f9f7 | 426 | } |
<> | 144:ef7eb2e8f9f7 | 427 | else |
<> | 144:ef7eb2e8f9f7 | 428 | { |
<> | 144:ef7eb2e8f9f7 | 429 | /* Disable the Internal Low Speed oscillator (LSI). */ |
<> | 144:ef7eb2e8f9f7 | 430 | __HAL_RCC_LSI_DISABLE(); |
<> | 144:ef7eb2e8f9f7 | 431 | |
<> | 144:ef7eb2e8f9f7 | 432 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 433 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 434 | |
<> | 144:ef7eb2e8f9f7 | 435 | /* Wait till LSI is ready */ |
<> | 144:ef7eb2e8f9f7 | 436 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) |
<> | 144:ef7eb2e8f9f7 | 437 | { |
<> | 144:ef7eb2e8f9f7 | 438 | if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 439 | { |
<> | 144:ef7eb2e8f9f7 | 440 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 441 | } |
<> | 144:ef7eb2e8f9f7 | 442 | } |
<> | 144:ef7eb2e8f9f7 | 443 | } |
<> | 144:ef7eb2e8f9f7 | 444 | } |
<> | 144:ef7eb2e8f9f7 | 445 | /*------------------------------ LSE Configuration -------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 446 | if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) |
<> | 144:ef7eb2e8f9f7 | 447 | { |
<> | 144:ef7eb2e8f9f7 | 448 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 449 | assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); |
<> | 144:ef7eb2e8f9f7 | 450 | |
<> | 144:ef7eb2e8f9f7 | 451 | /* Enable Power Clock*/ |
<> | 144:ef7eb2e8f9f7 | 452 | __HAL_RCC_PWR_CLK_ENABLE(); |
<> | 144:ef7eb2e8f9f7 | 453 | |
<> | 144:ef7eb2e8f9f7 | 454 | /* Enable write access to Backup domain */ |
<> | 144:ef7eb2e8f9f7 | 455 | PWR->CR |= PWR_CR_DBP; |
<> | 144:ef7eb2e8f9f7 | 456 | |
<> | 144:ef7eb2e8f9f7 | 457 | /* Wait for Backup domain Write protection enable */ |
<> | 144:ef7eb2e8f9f7 | 458 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 459 | |
<> | 144:ef7eb2e8f9f7 | 460 | while((PWR->CR & PWR_CR_DBP) == RESET) |
<> | 144:ef7eb2e8f9f7 | 461 | { |
<> | 144:ef7eb2e8f9f7 | 462 | if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 463 | { |
<> | 144:ef7eb2e8f9f7 | 464 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 465 | } |
<> | 144:ef7eb2e8f9f7 | 466 | } |
<> | 144:ef7eb2e8f9f7 | 467 | |
<> | 144:ef7eb2e8f9f7 | 468 | /* Set the new LSE configuration -----------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 469 | __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); |
<> | 144:ef7eb2e8f9f7 | 470 | /* Check the LSE State */ |
<> | 144:ef7eb2e8f9f7 | 471 | if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) |
<> | 144:ef7eb2e8f9f7 | 472 | { |
<> | 144:ef7eb2e8f9f7 | 473 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 474 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 475 | |
<> | 144:ef7eb2e8f9f7 | 476 | /* Wait till LSE is ready */ |
<> | 144:ef7eb2e8f9f7 | 477 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 478 | { |
AnnaBridge | 167:e84263d55307 | 479 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 480 | { |
<> | 144:ef7eb2e8f9f7 | 481 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 482 | } |
<> | 144:ef7eb2e8f9f7 | 483 | } |
<> | 144:ef7eb2e8f9f7 | 484 | } |
<> | 144:ef7eb2e8f9f7 | 485 | else |
<> | 144:ef7eb2e8f9f7 | 486 | { |
<> | 144:ef7eb2e8f9f7 | 487 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 488 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 489 | |
<> | 144:ef7eb2e8f9f7 | 490 | /* Wait till LSE is ready */ |
<> | 144:ef7eb2e8f9f7 | 491 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) |
<> | 144:ef7eb2e8f9f7 | 492 | { |
<> | 144:ef7eb2e8f9f7 | 493 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 494 | { |
<> | 144:ef7eb2e8f9f7 | 495 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 496 | } |
<> | 144:ef7eb2e8f9f7 | 497 | } |
<> | 144:ef7eb2e8f9f7 | 498 | } |
<> | 144:ef7eb2e8f9f7 | 499 | } |
<> | 144:ef7eb2e8f9f7 | 500 | /*-------------------------------- PLL Configuration -----------------------*/ |
<> | 144:ef7eb2e8f9f7 | 501 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 502 | assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); |
<> | 144:ef7eb2e8f9f7 | 503 | if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) |
<> | 144:ef7eb2e8f9f7 | 504 | { |
<> | 144:ef7eb2e8f9f7 | 505 | /* Check if the PLL is used as system clock or not */ |
<> | 144:ef7eb2e8f9f7 | 506 | if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) |
<> | 144:ef7eb2e8f9f7 | 507 | { |
<> | 144:ef7eb2e8f9f7 | 508 | if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) |
<> | 144:ef7eb2e8f9f7 | 509 | { |
<> | 144:ef7eb2e8f9f7 | 510 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 511 | assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource)); |
<> | 144:ef7eb2e8f9f7 | 512 | assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM)); |
<> | 144:ef7eb2e8f9f7 | 513 | assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN)); |
<> | 144:ef7eb2e8f9f7 | 514 | assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); |
<> | 144:ef7eb2e8f9f7 | 515 | assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); |
<> | 144:ef7eb2e8f9f7 | 516 | |
<> | 144:ef7eb2e8f9f7 | 517 | /* Disable the main PLL. */ |
<> | 144:ef7eb2e8f9f7 | 518 | __HAL_RCC_PLL_DISABLE(); |
<> | 144:ef7eb2e8f9f7 | 519 | |
<> | 144:ef7eb2e8f9f7 | 520 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 521 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 522 | |
<> | 144:ef7eb2e8f9f7 | 523 | /* Wait till PLL is ready */ |
<> | 144:ef7eb2e8f9f7 | 524 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
<> | 144:ef7eb2e8f9f7 | 525 | { |
<> | 144:ef7eb2e8f9f7 | 526 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 527 | { |
<> | 144:ef7eb2e8f9f7 | 528 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 529 | } |
<> | 144:ef7eb2e8f9f7 | 530 | } |
<> | 144:ef7eb2e8f9f7 | 531 | |
<> | 144:ef7eb2e8f9f7 | 532 | /* Configure the main PLL clock source, multiplication and division factors. */ |
<> | 144:ef7eb2e8f9f7 | 533 | WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \ |
<> | 144:ef7eb2e8f9f7 | 534 | RCC_OscInitStruct->PLL.PLLM | \ |
<> | 144:ef7eb2e8f9f7 | 535 | (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ |
<> | 144:ef7eb2e8f9f7 | 536 | (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \ |
<> | 144:ef7eb2e8f9f7 | 537 | (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ)))); |
<> | 144:ef7eb2e8f9f7 | 538 | /* Enable the main PLL. */ |
<> | 144:ef7eb2e8f9f7 | 539 | __HAL_RCC_PLL_ENABLE(); |
<> | 144:ef7eb2e8f9f7 | 540 | |
<> | 144:ef7eb2e8f9f7 | 541 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 542 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 543 | |
<> | 144:ef7eb2e8f9f7 | 544 | /* Wait till PLL is ready */ |
<> | 144:ef7eb2e8f9f7 | 545 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 546 | { |
<> | 144:ef7eb2e8f9f7 | 547 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 548 | { |
<> | 144:ef7eb2e8f9f7 | 549 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 550 | } |
<> | 144:ef7eb2e8f9f7 | 551 | } |
<> | 144:ef7eb2e8f9f7 | 552 | } |
<> | 144:ef7eb2e8f9f7 | 553 | else |
<> | 144:ef7eb2e8f9f7 | 554 | { |
<> | 144:ef7eb2e8f9f7 | 555 | /* Disable the main PLL. */ |
<> | 144:ef7eb2e8f9f7 | 556 | __HAL_RCC_PLL_DISABLE(); |
<> | 144:ef7eb2e8f9f7 | 557 | |
<> | 144:ef7eb2e8f9f7 | 558 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 559 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 560 | |
<> | 144:ef7eb2e8f9f7 | 561 | /* Wait till PLL is ready */ |
<> | 144:ef7eb2e8f9f7 | 562 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) |
<> | 144:ef7eb2e8f9f7 | 563 | { |
<> | 144:ef7eb2e8f9f7 | 564 | if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 565 | { |
<> | 144:ef7eb2e8f9f7 | 566 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 567 | } |
<> | 144:ef7eb2e8f9f7 | 568 | } |
<> | 144:ef7eb2e8f9f7 | 569 | } |
<> | 144:ef7eb2e8f9f7 | 570 | } |
<> | 144:ef7eb2e8f9f7 | 571 | else |
<> | 144:ef7eb2e8f9f7 | 572 | { |
<> | 144:ef7eb2e8f9f7 | 573 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 574 | } |
<> | 144:ef7eb2e8f9f7 | 575 | } |
<> | 144:ef7eb2e8f9f7 | 576 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 577 | } |
<> | 144:ef7eb2e8f9f7 | 578 | |
<> | 144:ef7eb2e8f9f7 | 579 | /** |
<> | 144:ef7eb2e8f9f7 | 580 | * @brief Initializes the CPU, AHB and APB busses clocks according to the specified |
<> | 144:ef7eb2e8f9f7 | 581 | * parameters in the RCC_ClkInitStruct. |
<> | 144:ef7eb2e8f9f7 | 582 | * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that |
<> | 144:ef7eb2e8f9f7 | 583 | * contains the configuration information for the RCC peripheral. |
<> | 144:ef7eb2e8f9f7 | 584 | * @param FLatency: FLASH Latency, this parameter depend on device selected |
<> | 144:ef7eb2e8f9f7 | 585 | * |
<> | 144:ef7eb2e8f9f7 | 586 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
<> | 144:ef7eb2e8f9f7 | 587 | * and updated by HAL_RCC_GetHCLKFreq() function called within this function |
<> | 144:ef7eb2e8f9f7 | 588 | * |
<> | 144:ef7eb2e8f9f7 | 589 | * @note The HSI is used (enabled by hardware) as system clock source after |
<> | 144:ef7eb2e8f9f7 | 590 | * startup from Reset, wake-up from STOP and STANDBY mode, or in case |
<> | 144:ef7eb2e8f9f7 | 591 | * of failure of the HSE used directly or indirectly as system clock |
<> | 144:ef7eb2e8f9f7 | 592 | * (if the Clock Security System CSS is enabled). |
<> | 144:ef7eb2e8f9f7 | 593 | * |
<> | 144:ef7eb2e8f9f7 | 594 | * @note A switch from one clock source to another occurs only if the target |
<> | 144:ef7eb2e8f9f7 | 595 | * clock source is ready (clock stable after startup delay or PLL locked). |
<> | 144:ef7eb2e8f9f7 | 596 | * If a clock source which is not yet ready is selected, the switch will |
<> | 144:ef7eb2e8f9f7 | 597 | * occur when the clock source will be ready. |
<> | 144:ef7eb2e8f9f7 | 598 | * |
<> | 144:ef7eb2e8f9f7 | 599 | * @note Depending on the device voltage range, the software has to set correctly |
<> | 144:ef7eb2e8f9f7 | 600 | * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency |
<> | 144:ef7eb2e8f9f7 | 601 | * (for more details refer to section above "Initialization/de-initialization functions") |
<> | 144:ef7eb2e8f9f7 | 602 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 603 | */ |
<> | 144:ef7eb2e8f9f7 | 604 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) |
<> | 144:ef7eb2e8f9f7 | 605 | { |
<> | 144:ef7eb2e8f9f7 | 606 | uint32_t tickstart = 0U; |
<> | 144:ef7eb2e8f9f7 | 607 | |
<> | 144:ef7eb2e8f9f7 | 608 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 609 | assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType)); |
<> | 144:ef7eb2e8f9f7 | 610 | assert_param(IS_FLASH_LATENCY(FLatency)); |
<> | 144:ef7eb2e8f9f7 | 611 | |
<> | 144:ef7eb2e8f9f7 | 612 | /* To correctly read data from FLASH memory, the number of wait states (LATENCY) |
<> | 144:ef7eb2e8f9f7 | 613 | must be correctly programmed according to the frequency of the CPU clock |
<> | 144:ef7eb2e8f9f7 | 614 | (HCLK) and the supply voltage of the device. */ |
<> | 144:ef7eb2e8f9f7 | 615 | |
<> | 144:ef7eb2e8f9f7 | 616 | /* Increasing the number of wait states because of higher CPU frequency */ |
<> | 144:ef7eb2e8f9f7 | 617 | if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) |
<> | 144:ef7eb2e8f9f7 | 618 | { |
<> | 144:ef7eb2e8f9f7 | 619 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
<> | 144:ef7eb2e8f9f7 | 620 | __HAL_FLASH_SET_LATENCY(FLatency); |
<> | 144:ef7eb2e8f9f7 | 621 | |
<> | 144:ef7eb2e8f9f7 | 622 | /* Check that the new number of wait states is taken into account to access the Flash |
<> | 144:ef7eb2e8f9f7 | 623 | memory by reading the FLASH_ACR register */ |
<> | 144:ef7eb2e8f9f7 | 624 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
<> | 144:ef7eb2e8f9f7 | 625 | { |
<> | 144:ef7eb2e8f9f7 | 626 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 627 | } |
<> | 144:ef7eb2e8f9f7 | 628 | } |
<> | 144:ef7eb2e8f9f7 | 629 | |
<> | 144:ef7eb2e8f9f7 | 630 | /*-------------------------- HCLK Configuration --------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 631 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) |
<> | 144:ef7eb2e8f9f7 | 632 | { |
<> | 144:ef7eb2e8f9f7 | 633 | assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); |
<> | 144:ef7eb2e8f9f7 | 634 | MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); |
<> | 144:ef7eb2e8f9f7 | 635 | } |
<> | 144:ef7eb2e8f9f7 | 636 | |
<> | 144:ef7eb2e8f9f7 | 637 | /*------------------------- SYSCLK Configuration ---------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 638 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) |
<> | 144:ef7eb2e8f9f7 | 639 | { |
<> | 144:ef7eb2e8f9f7 | 640 | assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); |
<> | 144:ef7eb2e8f9f7 | 641 | |
<> | 144:ef7eb2e8f9f7 | 642 | /* HSE is selected as System Clock Source */ |
<> | 144:ef7eb2e8f9f7 | 643 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
<> | 144:ef7eb2e8f9f7 | 644 | { |
<> | 144:ef7eb2e8f9f7 | 645 | /* Check the HSE ready flag */ |
<> | 144:ef7eb2e8f9f7 | 646 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 647 | { |
<> | 144:ef7eb2e8f9f7 | 648 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 649 | } |
<> | 144:ef7eb2e8f9f7 | 650 | } |
<> | 144:ef7eb2e8f9f7 | 651 | /* PLL is selected as System Clock Source */ |
<> | 144:ef7eb2e8f9f7 | 652 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
<> | 144:ef7eb2e8f9f7 | 653 | { |
<> | 144:ef7eb2e8f9f7 | 654 | /* Check the PLL ready flag */ |
<> | 144:ef7eb2e8f9f7 | 655 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 656 | { |
<> | 144:ef7eb2e8f9f7 | 657 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 658 | } |
<> | 144:ef7eb2e8f9f7 | 659 | } |
<> | 144:ef7eb2e8f9f7 | 660 | /* HSI is selected as System Clock Source */ |
<> | 144:ef7eb2e8f9f7 | 661 | else |
<> | 144:ef7eb2e8f9f7 | 662 | { |
<> | 144:ef7eb2e8f9f7 | 663 | /* Check the HSI ready flag */ |
<> | 144:ef7eb2e8f9f7 | 664 | if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) |
<> | 144:ef7eb2e8f9f7 | 665 | { |
<> | 144:ef7eb2e8f9f7 | 666 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 667 | } |
<> | 144:ef7eb2e8f9f7 | 668 | } |
<> | 144:ef7eb2e8f9f7 | 669 | |
<> | 144:ef7eb2e8f9f7 | 670 | __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource); |
<> | 144:ef7eb2e8f9f7 | 671 | /* Get Start Tick*/ |
<> | 144:ef7eb2e8f9f7 | 672 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 673 | |
<> | 144:ef7eb2e8f9f7 | 674 | if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) |
<> | 144:ef7eb2e8f9f7 | 675 | { |
<> | 144:ef7eb2e8f9f7 | 676 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) |
<> | 144:ef7eb2e8f9f7 | 677 | { |
<> | 144:ef7eb2e8f9f7 | 678 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 679 | { |
<> | 144:ef7eb2e8f9f7 | 680 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 681 | } |
<> | 144:ef7eb2e8f9f7 | 682 | } |
<> | 144:ef7eb2e8f9f7 | 683 | } |
<> | 144:ef7eb2e8f9f7 | 684 | else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) |
<> | 144:ef7eb2e8f9f7 | 685 | { |
<> | 144:ef7eb2e8f9f7 | 686 | while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) |
<> | 144:ef7eb2e8f9f7 | 687 | { |
<> | 144:ef7eb2e8f9f7 | 688 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 689 | { |
<> | 144:ef7eb2e8f9f7 | 690 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 691 | } |
<> | 144:ef7eb2e8f9f7 | 692 | } |
<> | 144:ef7eb2e8f9f7 | 693 | } |
<> | 144:ef7eb2e8f9f7 | 694 | else |
<> | 144:ef7eb2e8f9f7 | 695 | { |
<> | 144:ef7eb2e8f9f7 | 696 | while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) |
<> | 144:ef7eb2e8f9f7 | 697 | { |
<> | 144:ef7eb2e8f9f7 | 698 | if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) |
<> | 144:ef7eb2e8f9f7 | 699 | { |
<> | 144:ef7eb2e8f9f7 | 700 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 701 | } |
<> | 144:ef7eb2e8f9f7 | 702 | } |
<> | 144:ef7eb2e8f9f7 | 703 | } |
<> | 144:ef7eb2e8f9f7 | 704 | } |
<> | 144:ef7eb2e8f9f7 | 705 | |
<> | 144:ef7eb2e8f9f7 | 706 | /* Decreasing the number of wait states because of lower CPU frequency */ |
<> | 144:ef7eb2e8f9f7 | 707 | if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) |
<> | 144:ef7eb2e8f9f7 | 708 | { |
<> | 144:ef7eb2e8f9f7 | 709 | /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ |
<> | 144:ef7eb2e8f9f7 | 710 | __HAL_FLASH_SET_LATENCY(FLatency); |
<> | 144:ef7eb2e8f9f7 | 711 | |
<> | 144:ef7eb2e8f9f7 | 712 | /* Check that the new number of wait states is taken into account to access the Flash |
<> | 144:ef7eb2e8f9f7 | 713 | memory by reading the FLASH_ACR register */ |
<> | 144:ef7eb2e8f9f7 | 714 | if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) |
<> | 144:ef7eb2e8f9f7 | 715 | { |
<> | 144:ef7eb2e8f9f7 | 716 | return HAL_ERROR; |
<> | 144:ef7eb2e8f9f7 | 717 | } |
<> | 144:ef7eb2e8f9f7 | 718 | } |
<> | 144:ef7eb2e8f9f7 | 719 | |
<> | 144:ef7eb2e8f9f7 | 720 | /*-------------------------- PCLK1 Configuration ---------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 721 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) |
<> | 144:ef7eb2e8f9f7 | 722 | { |
<> | 144:ef7eb2e8f9f7 | 723 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); |
<> | 144:ef7eb2e8f9f7 | 724 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); |
<> | 144:ef7eb2e8f9f7 | 725 | } |
<> | 144:ef7eb2e8f9f7 | 726 | |
<> | 144:ef7eb2e8f9f7 | 727 | /*-------------------------- PCLK2 Configuration ---------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 728 | if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) |
<> | 144:ef7eb2e8f9f7 | 729 | { |
<> | 144:ef7eb2e8f9f7 | 730 | assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); |
<> | 144:ef7eb2e8f9f7 | 731 | MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); |
<> | 144:ef7eb2e8f9f7 | 732 | } |
<> | 144:ef7eb2e8f9f7 | 733 | |
<> | 144:ef7eb2e8f9f7 | 734 | /* Update the SystemCoreClock global variable */ |
AnnaBridge | 167:e84263d55307 | 735 | SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; |
<> | 144:ef7eb2e8f9f7 | 736 | |
<> | 144:ef7eb2e8f9f7 | 737 | /* Configure the source of time base considering new system clocks settings*/ |
<> | 144:ef7eb2e8f9f7 | 738 | HAL_InitTick (TICK_INT_PRIORITY); |
<> | 144:ef7eb2e8f9f7 | 739 | |
<> | 144:ef7eb2e8f9f7 | 740 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 741 | } |
<> | 144:ef7eb2e8f9f7 | 742 | |
<> | 144:ef7eb2e8f9f7 | 743 | /** |
<> | 144:ef7eb2e8f9f7 | 744 | * @} |
<> | 144:ef7eb2e8f9f7 | 745 | */ |
<> | 144:ef7eb2e8f9f7 | 746 | |
<> | 144:ef7eb2e8f9f7 | 747 | /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 748 | * @brief RCC clocks control functions |
<> | 144:ef7eb2e8f9f7 | 749 | * |
<> | 144:ef7eb2e8f9f7 | 750 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 751 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 752 | ##### Peripheral Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 753 | =============================================================================== |
<> | 144:ef7eb2e8f9f7 | 754 | [..] |
<> | 144:ef7eb2e8f9f7 | 755 | This subsection provides a set of functions allowing to control the RCC Clocks |
<> | 144:ef7eb2e8f9f7 | 756 | frequencies. |
<> | 144:ef7eb2e8f9f7 | 757 | |
<> | 144:ef7eb2e8f9f7 | 758 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 759 | * @{ |
<> | 144:ef7eb2e8f9f7 | 760 | */ |
<> | 144:ef7eb2e8f9f7 | 761 | |
<> | 144:ef7eb2e8f9f7 | 762 | /** |
<> | 144:ef7eb2e8f9f7 | 763 | * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9). |
<> | 144:ef7eb2e8f9f7 | 764 | * @note PA8/PC9 should be configured in alternate function mode. |
<> | 144:ef7eb2e8f9f7 | 765 | * @param RCC_MCOx: specifies the output direction for the clock source. |
<> | 144:ef7eb2e8f9f7 | 766 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 767 | * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8). |
<> | 144:ef7eb2e8f9f7 | 768 | * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9). |
<> | 144:ef7eb2e8f9f7 | 769 | * @param RCC_MCOSource: specifies the clock source to output. |
<> | 144:ef7eb2e8f9f7 | 770 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 771 | * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source |
<> | 144:ef7eb2e8f9f7 | 772 | * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source |
<> | 144:ef7eb2e8f9f7 | 773 | * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source |
<> | 144:ef7eb2e8f9f7 | 774 | * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source |
<> | 144:ef7eb2e8f9f7 | 775 | * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source |
<> | 144:ef7eb2e8f9f7 | 776 | * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source |
<> | 144:ef7eb2e8f9f7 | 777 | * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source |
<> | 144:ef7eb2e8f9f7 | 778 | * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source |
<> | 144:ef7eb2e8f9f7 | 779 | * @param RCC_MCODiv: specifies the MCOx prescaler. |
<> | 144:ef7eb2e8f9f7 | 780 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 781 | * @arg RCC_MCODIV_1: no division applied to MCOx clock |
<> | 144:ef7eb2e8f9f7 | 782 | * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock |
<> | 144:ef7eb2e8f9f7 | 783 | * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock |
<> | 144:ef7eb2e8f9f7 | 784 | * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock |
<> | 144:ef7eb2e8f9f7 | 785 | * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock |
<> | 144:ef7eb2e8f9f7 | 786 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 787 | */ |
<> | 144:ef7eb2e8f9f7 | 788 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) |
<> | 144:ef7eb2e8f9f7 | 789 | { |
<> | 144:ef7eb2e8f9f7 | 790 | GPIO_InitTypeDef GPIO_InitStruct; |
<> | 144:ef7eb2e8f9f7 | 791 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 792 | assert_param(IS_RCC_MCO(RCC_MCOx)); |
<> | 144:ef7eb2e8f9f7 | 793 | assert_param(IS_RCC_MCODIV(RCC_MCODiv)); |
<> | 144:ef7eb2e8f9f7 | 794 | /* RCC_MCO1 */ |
<> | 144:ef7eb2e8f9f7 | 795 | if(RCC_MCOx == RCC_MCO1) |
<> | 144:ef7eb2e8f9f7 | 796 | { |
<> | 144:ef7eb2e8f9f7 | 797 | assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); |
<> | 144:ef7eb2e8f9f7 | 798 | |
<> | 144:ef7eb2e8f9f7 | 799 | /* MCO1 Clock Enable */ |
<> | 144:ef7eb2e8f9f7 | 800 | __MCO1_CLK_ENABLE(); |
<> | 144:ef7eb2e8f9f7 | 801 | |
<> | 144:ef7eb2e8f9f7 | 802 | /* Configure the MCO1 pin in alternate function mode */ |
<> | 144:ef7eb2e8f9f7 | 803 | GPIO_InitStruct.Pin = MCO1_PIN; |
<> | 144:ef7eb2e8f9f7 | 804 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
<> | 144:ef7eb2e8f9f7 | 805 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
<> | 144:ef7eb2e8f9f7 | 806 | GPIO_InitStruct.Pull = GPIO_NOPULL; |
<> | 144:ef7eb2e8f9f7 | 807 | GPIO_InitStruct.Alternate = GPIO_AF0_MCO; |
<> | 144:ef7eb2e8f9f7 | 808 | HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); |
<> | 144:ef7eb2e8f9f7 | 809 | |
<> | 144:ef7eb2e8f9f7 | 810 | /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ |
<> | 144:ef7eb2e8f9f7 | 811 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv)); |
<> | 144:ef7eb2e8f9f7 | 812 | } |
<> | 144:ef7eb2e8f9f7 | 813 | else |
<> | 144:ef7eb2e8f9f7 | 814 | { |
<> | 144:ef7eb2e8f9f7 | 815 | assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource)); |
<> | 144:ef7eb2e8f9f7 | 816 | |
<> | 144:ef7eb2e8f9f7 | 817 | /* MCO2 Clock Enable */ |
<> | 144:ef7eb2e8f9f7 | 818 | __MCO2_CLK_ENABLE(); |
<> | 144:ef7eb2e8f9f7 | 819 | |
<> | 144:ef7eb2e8f9f7 | 820 | /* Configure the MCO2 pin in alternate function mode */ |
<> | 144:ef7eb2e8f9f7 | 821 | GPIO_InitStruct.Pin = MCO2_PIN; |
<> | 144:ef7eb2e8f9f7 | 822 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; |
<> | 144:ef7eb2e8f9f7 | 823 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; |
<> | 144:ef7eb2e8f9f7 | 824 | GPIO_InitStruct.Pull = GPIO_NOPULL; |
<> | 144:ef7eb2e8f9f7 | 825 | GPIO_InitStruct.Alternate = GPIO_AF0_MCO; |
<> | 144:ef7eb2e8f9f7 | 826 | HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct); |
<> | 144:ef7eb2e8f9f7 | 827 | |
<> | 144:ef7eb2e8f9f7 | 828 | /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */ |
AnnaBridge | 167:e84263d55307 | 829 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U))); |
<> | 144:ef7eb2e8f9f7 | 830 | } |
<> | 144:ef7eb2e8f9f7 | 831 | } |
<> | 144:ef7eb2e8f9f7 | 832 | |
<> | 144:ef7eb2e8f9f7 | 833 | /** |
<> | 144:ef7eb2e8f9f7 | 834 | * @brief Enables the Clock Security System. |
<> | 144:ef7eb2e8f9f7 | 835 | * @note If a failure is detected on the HSE oscillator clock, this oscillator |
<> | 144:ef7eb2e8f9f7 | 836 | * is automatically disabled and an interrupt is generated to inform the |
<> | 144:ef7eb2e8f9f7 | 837 | * software about the failure (Clock Security System Interrupt, CSSI), |
<> | 144:ef7eb2e8f9f7 | 838 | * allowing the MCU to perform rescue operations. The CSSI is linked to |
<> | 144:ef7eb2e8f9f7 | 839 | * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector. |
<> | 144:ef7eb2e8f9f7 | 840 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 841 | */ |
<> | 144:ef7eb2e8f9f7 | 842 | void HAL_RCC_EnableCSS(void) |
<> | 144:ef7eb2e8f9f7 | 843 | { |
<> | 144:ef7eb2e8f9f7 | 844 | *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE; |
<> | 144:ef7eb2e8f9f7 | 845 | } |
<> | 144:ef7eb2e8f9f7 | 846 | |
<> | 144:ef7eb2e8f9f7 | 847 | /** |
<> | 144:ef7eb2e8f9f7 | 848 | * @brief Disables the Clock Security System. |
<> | 144:ef7eb2e8f9f7 | 849 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 850 | */ |
<> | 144:ef7eb2e8f9f7 | 851 | void HAL_RCC_DisableCSS(void) |
<> | 144:ef7eb2e8f9f7 | 852 | { |
<> | 144:ef7eb2e8f9f7 | 853 | *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE; |
<> | 144:ef7eb2e8f9f7 | 854 | } |
<> | 144:ef7eb2e8f9f7 | 855 | |
<> | 144:ef7eb2e8f9f7 | 856 | /** |
<> | 144:ef7eb2e8f9f7 | 857 | * @brief Returns the SYSCLK frequency |
<> | 144:ef7eb2e8f9f7 | 858 | * |
<> | 144:ef7eb2e8f9f7 | 859 | * @note The system frequency computed by this function is not the real |
<> | 144:ef7eb2e8f9f7 | 860 | * frequency in the chip. It is calculated based on the predefined |
<> | 144:ef7eb2e8f9f7 | 861 | * constant and the selected clock source: |
<> | 144:ef7eb2e8f9f7 | 862 | * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) |
<> | 144:ef7eb2e8f9f7 | 863 | * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) |
<> | 144:ef7eb2e8f9f7 | 864 | * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) |
<> | 144:ef7eb2e8f9f7 | 865 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
<> | 144:ef7eb2e8f9f7 | 866 | * @note (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value |
<> | 144:ef7eb2e8f9f7 | 867 | * 16 MHz) but the real value may vary depending on the variations |
<> | 144:ef7eb2e8f9f7 | 868 | * in voltage and temperature. |
<> | 144:ef7eb2e8f9f7 | 869 | * @note (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value |
<> | 144:ef7eb2e8f9f7 | 870 | * 25 MHz), user has to ensure that HSE_VALUE is same as the real |
<> | 144:ef7eb2e8f9f7 | 871 | * frequency of the crystal used. Otherwise, this function may |
<> | 144:ef7eb2e8f9f7 | 872 | * have wrong result. |
<> | 144:ef7eb2e8f9f7 | 873 | * |
<> | 144:ef7eb2e8f9f7 | 874 | * @note The result of this function could be not correct when using fractional |
<> | 144:ef7eb2e8f9f7 | 875 | * value for HSE crystal. |
<> | 144:ef7eb2e8f9f7 | 876 | * |
<> | 144:ef7eb2e8f9f7 | 877 | * @note This function can be used by the user application to compute the |
<> | 144:ef7eb2e8f9f7 | 878 | * baudrate for the communication peripherals or configure other parameters. |
<> | 144:ef7eb2e8f9f7 | 879 | * |
<> | 144:ef7eb2e8f9f7 | 880 | * @note Each time SYSCLK changes, this function must be called to update the |
<> | 144:ef7eb2e8f9f7 | 881 | * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. |
<> | 144:ef7eb2e8f9f7 | 882 | * |
<> | 144:ef7eb2e8f9f7 | 883 | * |
<> | 144:ef7eb2e8f9f7 | 884 | * @retval SYSCLK frequency |
<> | 144:ef7eb2e8f9f7 | 885 | */ |
<> | 144:ef7eb2e8f9f7 | 886 | uint32_t HAL_RCC_GetSysClockFreq(void) |
<> | 144:ef7eb2e8f9f7 | 887 | { |
<> | 144:ef7eb2e8f9f7 | 888 | uint32_t pllm = 0U, pllvco = 0U, pllp = 0U; |
<> | 144:ef7eb2e8f9f7 | 889 | uint32_t sysclockfreq = 0U; |
<> | 144:ef7eb2e8f9f7 | 890 | |
<> | 144:ef7eb2e8f9f7 | 891 | /* Get SYSCLK source -------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 892 | switch (RCC->CFGR & RCC_CFGR_SWS) |
<> | 144:ef7eb2e8f9f7 | 893 | { |
<> | 144:ef7eb2e8f9f7 | 894 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ |
<> | 144:ef7eb2e8f9f7 | 895 | { |
<> | 144:ef7eb2e8f9f7 | 896 | sysclockfreq = HSI_VALUE; |
<> | 144:ef7eb2e8f9f7 | 897 | break; |
<> | 144:ef7eb2e8f9f7 | 898 | } |
<> | 144:ef7eb2e8f9f7 | 899 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */ |
<> | 144:ef7eb2e8f9f7 | 900 | { |
<> | 144:ef7eb2e8f9f7 | 901 | sysclockfreq = HSE_VALUE; |
<> | 144:ef7eb2e8f9f7 | 902 | break; |
<> | 144:ef7eb2e8f9f7 | 903 | } |
<> | 144:ef7eb2e8f9f7 | 904 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */ |
<> | 144:ef7eb2e8f9f7 | 905 | { |
<> | 144:ef7eb2e8f9f7 | 906 | /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN |
<> | 144:ef7eb2e8f9f7 | 907 | SYSCLK = PLL_VCO / PLLP */ |
<> | 144:ef7eb2e8f9f7 | 908 | pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; |
<> | 144:ef7eb2e8f9f7 | 909 | if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI) |
<> | 144:ef7eb2e8f9f7 | 910 | { |
<> | 144:ef7eb2e8f9f7 | 911 | /* HSE used as PLL clock source */ |
<> | 144:ef7eb2e8f9f7 | 912 | pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); |
<> | 144:ef7eb2e8f9f7 | 913 | } |
<> | 144:ef7eb2e8f9f7 | 914 | else |
<> | 144:ef7eb2e8f9f7 | 915 | { |
<> | 144:ef7eb2e8f9f7 | 916 | /* HSI used as PLL clock source */ |
<> | 144:ef7eb2e8f9f7 | 917 | pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); |
<> | 144:ef7eb2e8f9f7 | 918 | } |
<> | 144:ef7eb2e8f9f7 | 919 | pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U); |
<> | 144:ef7eb2e8f9f7 | 920 | |
<> | 144:ef7eb2e8f9f7 | 921 | sysclockfreq = pllvco/pllp; |
<> | 144:ef7eb2e8f9f7 | 922 | break; |
<> | 144:ef7eb2e8f9f7 | 923 | } |
<> | 144:ef7eb2e8f9f7 | 924 | default: |
<> | 144:ef7eb2e8f9f7 | 925 | { |
<> | 144:ef7eb2e8f9f7 | 926 | sysclockfreq = HSI_VALUE; |
<> | 144:ef7eb2e8f9f7 | 927 | break; |
<> | 144:ef7eb2e8f9f7 | 928 | } |
<> | 144:ef7eb2e8f9f7 | 929 | } |
<> | 144:ef7eb2e8f9f7 | 930 | return sysclockfreq; |
<> | 144:ef7eb2e8f9f7 | 931 | } |
<> | 144:ef7eb2e8f9f7 | 932 | |
<> | 144:ef7eb2e8f9f7 | 933 | /** |
<> | 144:ef7eb2e8f9f7 | 934 | * @brief Returns the HCLK frequency |
<> | 144:ef7eb2e8f9f7 | 935 | * @note Each time HCLK changes, this function must be called to update the |
<> | 144:ef7eb2e8f9f7 | 936 | * right HCLK value. Otherwise, any configuration based on this function will be incorrect. |
<> | 144:ef7eb2e8f9f7 | 937 | * |
<> | 144:ef7eb2e8f9f7 | 938 | * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency |
<> | 144:ef7eb2e8f9f7 | 939 | * and updated within this function |
<> | 144:ef7eb2e8f9f7 | 940 | * @retval HCLK frequency |
<> | 144:ef7eb2e8f9f7 | 941 | */ |
<> | 144:ef7eb2e8f9f7 | 942 | uint32_t HAL_RCC_GetHCLKFreq(void) |
<> | 144:ef7eb2e8f9f7 | 943 | { |
<> | 144:ef7eb2e8f9f7 | 944 | return SystemCoreClock; |
<> | 144:ef7eb2e8f9f7 | 945 | } |
<> | 144:ef7eb2e8f9f7 | 946 | |
<> | 144:ef7eb2e8f9f7 | 947 | /** |
<> | 144:ef7eb2e8f9f7 | 948 | * @brief Returns the PCLK1 frequency |
<> | 144:ef7eb2e8f9f7 | 949 | * @note Each time PCLK1 changes, this function must be called to update the |
<> | 144:ef7eb2e8f9f7 | 950 | * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. |
<> | 144:ef7eb2e8f9f7 | 951 | * @retval PCLK1 frequency |
<> | 144:ef7eb2e8f9f7 | 952 | */ |
<> | 144:ef7eb2e8f9f7 | 953 | uint32_t HAL_RCC_GetPCLK1Freq(void) |
<> | 144:ef7eb2e8f9f7 | 954 | { |
<> | 144:ef7eb2e8f9f7 | 955 | /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ |
AnnaBridge | 167:e84263d55307 | 956 | return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]); |
<> | 144:ef7eb2e8f9f7 | 957 | } |
<> | 144:ef7eb2e8f9f7 | 958 | |
<> | 144:ef7eb2e8f9f7 | 959 | /** |
<> | 144:ef7eb2e8f9f7 | 960 | * @brief Returns the PCLK2 frequency |
<> | 144:ef7eb2e8f9f7 | 961 | * @note Each time PCLK2 changes, this function must be called to update the |
<> | 144:ef7eb2e8f9f7 | 962 | * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. |
<> | 144:ef7eb2e8f9f7 | 963 | * @retval PCLK2 frequency |
<> | 144:ef7eb2e8f9f7 | 964 | */ |
<> | 144:ef7eb2e8f9f7 | 965 | uint32_t HAL_RCC_GetPCLK2Freq(void) |
<> | 144:ef7eb2e8f9f7 | 966 | { |
<> | 144:ef7eb2e8f9f7 | 967 | /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ |
AnnaBridge | 167:e84263d55307 | 968 | return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]); |
<> | 144:ef7eb2e8f9f7 | 969 | } |
<> | 144:ef7eb2e8f9f7 | 970 | |
<> | 144:ef7eb2e8f9f7 | 971 | /** |
<> | 144:ef7eb2e8f9f7 | 972 | * @brief Configures the RCC_OscInitStruct according to the internal |
<> | 144:ef7eb2e8f9f7 | 973 | * RCC configuration registers. |
<> | 144:ef7eb2e8f9f7 | 974 | * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that |
<> | 144:ef7eb2e8f9f7 | 975 | * will be configured. |
<> | 144:ef7eb2e8f9f7 | 976 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 977 | */ |
<> | 144:ef7eb2e8f9f7 | 978 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) |
<> | 144:ef7eb2e8f9f7 | 979 | { |
<> | 144:ef7eb2e8f9f7 | 980 | /* Set all possible values for the Oscillator type parameter ---------------*/ |
<> | 144:ef7eb2e8f9f7 | 981 | RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; |
<> | 144:ef7eb2e8f9f7 | 982 | |
<> | 144:ef7eb2e8f9f7 | 983 | /* Get the HSE configuration -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 984 | if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) |
<> | 144:ef7eb2e8f9f7 | 985 | { |
<> | 144:ef7eb2e8f9f7 | 986 | RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS; |
<> | 144:ef7eb2e8f9f7 | 987 | } |
<> | 144:ef7eb2e8f9f7 | 988 | else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON) |
<> | 144:ef7eb2e8f9f7 | 989 | { |
<> | 144:ef7eb2e8f9f7 | 990 | RCC_OscInitStruct->HSEState = RCC_HSE_ON; |
<> | 144:ef7eb2e8f9f7 | 991 | } |
<> | 144:ef7eb2e8f9f7 | 992 | else |
<> | 144:ef7eb2e8f9f7 | 993 | { |
<> | 144:ef7eb2e8f9f7 | 994 | RCC_OscInitStruct->HSEState = RCC_HSE_OFF; |
<> | 144:ef7eb2e8f9f7 | 995 | } |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | /* Get the HSI configuration -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 998 | if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) |
<> | 144:ef7eb2e8f9f7 | 999 | { |
<> | 144:ef7eb2e8f9f7 | 1000 | RCC_OscInitStruct->HSIState = RCC_HSI_ON; |
<> | 144:ef7eb2e8f9f7 | 1001 | } |
<> | 144:ef7eb2e8f9f7 | 1002 | else |
<> | 144:ef7eb2e8f9f7 | 1003 | { |
<> | 144:ef7eb2e8f9f7 | 1004 | RCC_OscInitStruct->HSIState = RCC_HSI_OFF; |
<> | 144:ef7eb2e8f9f7 | 1005 | } |
<> | 144:ef7eb2e8f9f7 | 1006 | |
<> | 144:ef7eb2e8f9f7 | 1007 | RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM)); |
<> | 144:ef7eb2e8f9f7 | 1008 | |
<> | 144:ef7eb2e8f9f7 | 1009 | /* Get the LSE configuration -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1010 | if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP) |
<> | 144:ef7eb2e8f9f7 | 1011 | { |
<> | 144:ef7eb2e8f9f7 | 1012 | RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS; |
<> | 144:ef7eb2e8f9f7 | 1013 | } |
<> | 144:ef7eb2e8f9f7 | 1014 | else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON) |
<> | 144:ef7eb2e8f9f7 | 1015 | { |
<> | 144:ef7eb2e8f9f7 | 1016 | RCC_OscInitStruct->LSEState = RCC_LSE_ON; |
<> | 144:ef7eb2e8f9f7 | 1017 | } |
<> | 144:ef7eb2e8f9f7 | 1018 | else |
<> | 144:ef7eb2e8f9f7 | 1019 | { |
<> | 144:ef7eb2e8f9f7 | 1020 | RCC_OscInitStruct->LSEState = RCC_LSE_OFF; |
<> | 144:ef7eb2e8f9f7 | 1021 | } |
<> | 144:ef7eb2e8f9f7 | 1022 | |
<> | 144:ef7eb2e8f9f7 | 1023 | /* Get the LSI configuration -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1024 | if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION) |
<> | 144:ef7eb2e8f9f7 | 1025 | { |
<> | 144:ef7eb2e8f9f7 | 1026 | RCC_OscInitStruct->LSIState = RCC_LSI_ON; |
<> | 144:ef7eb2e8f9f7 | 1027 | } |
<> | 144:ef7eb2e8f9f7 | 1028 | else |
<> | 144:ef7eb2e8f9f7 | 1029 | { |
<> | 144:ef7eb2e8f9f7 | 1030 | RCC_OscInitStruct->LSIState = RCC_LSI_OFF; |
<> | 144:ef7eb2e8f9f7 | 1031 | } |
<> | 144:ef7eb2e8f9f7 | 1032 | |
<> | 144:ef7eb2e8f9f7 | 1033 | /* Get the PLL configuration -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1034 | if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON) |
<> | 144:ef7eb2e8f9f7 | 1035 | { |
<> | 144:ef7eb2e8f9f7 | 1036 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; |
<> | 144:ef7eb2e8f9f7 | 1037 | } |
<> | 144:ef7eb2e8f9f7 | 1038 | else |
<> | 144:ef7eb2e8f9f7 | 1039 | { |
<> | 144:ef7eb2e8f9f7 | 1040 | RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; |
<> | 144:ef7eb2e8f9f7 | 1041 | } |
<> | 144:ef7eb2e8f9f7 | 1042 | RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); |
<> | 144:ef7eb2e8f9f7 | 1043 | RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM); |
<> | 144:ef7eb2e8f9f7 | 1044 | RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); |
<> | 144:ef7eb2e8f9f7 | 1045 | RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP)); |
<> | 144:ef7eb2e8f9f7 | 1046 | RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ)); |
<> | 144:ef7eb2e8f9f7 | 1047 | } |
<> | 144:ef7eb2e8f9f7 | 1048 | |
<> | 144:ef7eb2e8f9f7 | 1049 | /** |
<> | 144:ef7eb2e8f9f7 | 1050 | * @brief Configures the RCC_ClkInitStruct according to the internal |
<> | 144:ef7eb2e8f9f7 | 1051 | * RCC configuration registers. |
<> | 144:ef7eb2e8f9f7 | 1052 | * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that |
<> | 144:ef7eb2e8f9f7 | 1053 | * will be configured. |
<> | 144:ef7eb2e8f9f7 | 1054 | * @param pFLatency: Pointer on the Flash Latency. |
<> | 144:ef7eb2e8f9f7 | 1055 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1056 | */ |
<> | 144:ef7eb2e8f9f7 | 1057 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency) |
<> | 144:ef7eb2e8f9f7 | 1058 | { |
<> | 144:ef7eb2e8f9f7 | 1059 | /* Set all possible values for the Clock type parameter --------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1060 | RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
<> | 144:ef7eb2e8f9f7 | 1061 | |
<> | 144:ef7eb2e8f9f7 | 1062 | /* Get the SYSCLK configuration --------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1063 | RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW); |
<> | 144:ef7eb2e8f9f7 | 1064 | |
<> | 144:ef7eb2e8f9f7 | 1065 | /* Get the HCLK configuration ----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1066 | RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); |
<> | 144:ef7eb2e8f9f7 | 1067 | |
<> | 144:ef7eb2e8f9f7 | 1068 | /* Get the APB1 configuration ----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1069 | RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1); |
<> | 144:ef7eb2e8f9f7 | 1070 | |
<> | 144:ef7eb2e8f9f7 | 1071 | /* Get the APB2 configuration ----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1072 | RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U); |
<> | 144:ef7eb2e8f9f7 | 1073 | |
<> | 144:ef7eb2e8f9f7 | 1074 | /* Get the Flash Wait State (Latency) configuration ------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 1075 | *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); |
<> | 144:ef7eb2e8f9f7 | 1076 | } |
<> | 144:ef7eb2e8f9f7 | 1077 | |
<> | 144:ef7eb2e8f9f7 | 1078 | /** |
<> | 144:ef7eb2e8f9f7 | 1079 | * @brief This function handles the RCC CSS interrupt request. |
<> | 144:ef7eb2e8f9f7 | 1080 | * @note This API should be called under the NMI_Handler(). |
<> | 144:ef7eb2e8f9f7 | 1081 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1082 | */ |
<> | 144:ef7eb2e8f9f7 | 1083 | void HAL_RCC_NMI_IRQHandler(void) |
<> | 144:ef7eb2e8f9f7 | 1084 | { |
<> | 144:ef7eb2e8f9f7 | 1085 | /* Check RCC CSSF flag */ |
<> | 144:ef7eb2e8f9f7 | 1086 | if(__HAL_RCC_GET_IT(RCC_IT_CSS)) |
<> | 144:ef7eb2e8f9f7 | 1087 | { |
<> | 144:ef7eb2e8f9f7 | 1088 | /* RCC Clock Security System interrupt user callback */ |
<> | 144:ef7eb2e8f9f7 | 1089 | HAL_RCC_CSSCallback(); |
<> | 144:ef7eb2e8f9f7 | 1090 | |
<> | 144:ef7eb2e8f9f7 | 1091 | /* Clear RCC CSS pending bit */ |
<> | 144:ef7eb2e8f9f7 | 1092 | __HAL_RCC_CLEAR_IT(RCC_IT_CSS); |
<> | 144:ef7eb2e8f9f7 | 1093 | } |
<> | 144:ef7eb2e8f9f7 | 1094 | } |
<> | 144:ef7eb2e8f9f7 | 1095 | |
<> | 144:ef7eb2e8f9f7 | 1096 | /** |
<> | 144:ef7eb2e8f9f7 | 1097 | * @brief RCC Clock Security System interrupt callback |
<> | 144:ef7eb2e8f9f7 | 1098 | * @retval None |
<> | 144:ef7eb2e8f9f7 | 1099 | */ |
<> | 144:ef7eb2e8f9f7 | 1100 | __weak void HAL_RCC_CSSCallback(void) |
<> | 144:ef7eb2e8f9f7 | 1101 | { |
<> | 144:ef7eb2e8f9f7 | 1102 | /* NOTE : This function Should not be modified, when the callback is needed, |
<> | 144:ef7eb2e8f9f7 | 1103 | the HAL_RCC_CSSCallback could be implemented in the user file |
<> | 144:ef7eb2e8f9f7 | 1104 | */ |
<> | 144:ef7eb2e8f9f7 | 1105 | } |
<> | 144:ef7eb2e8f9f7 | 1106 | |
<> | 144:ef7eb2e8f9f7 | 1107 | /** |
<> | 144:ef7eb2e8f9f7 | 1108 | * @} |
<> | 144:ef7eb2e8f9f7 | 1109 | */ |
<> | 144:ef7eb2e8f9f7 | 1110 | |
<> | 144:ef7eb2e8f9f7 | 1111 | /** |
<> | 144:ef7eb2e8f9f7 | 1112 | * @} |
<> | 144:ef7eb2e8f9f7 | 1113 | */ |
<> | 144:ef7eb2e8f9f7 | 1114 | |
<> | 144:ef7eb2e8f9f7 | 1115 | #endif /* HAL_RCC_MODULE_ENABLED */ |
<> | 144:ef7eb2e8f9f7 | 1116 | /** |
<> | 144:ef7eb2e8f9f7 | 1117 | * @} |
<> | 144:ef7eb2e8f9f7 | 1118 | */ |
<> | 144:ef7eb2e8f9f7 | 1119 | |
<> | 144:ef7eb2e8f9f7 | 1120 | /** |
<> | 144:ef7eb2e8f9f7 | 1121 | * @} |
<> | 144:ef7eb2e8f9f7 | 1122 | */ |
<> | 144:ef7eb2e8f9f7 | 1123 | |
<> | 144:ef7eb2e8f9f7 | 1124 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |