mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_rcc.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_rcc.c@144:ef7eb2e8f9f7
Child:
167:e84263d55307
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### RCC specific features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 After reset the device is running from Internal High Speed oscillator
<> 144:ef7eb2e8f9f7 19 (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
<> 144:ef7eb2e8f9f7 20 and I-Cache are disabled, and all peripherals are off except internal
<> 144:ef7eb2e8f9f7 21 SRAM, Flash and JTAG.
<> 144:ef7eb2e8f9f7 22 (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
<> 144:ef7eb2e8f9f7 23 all peripherals mapped on these busses are running at HSI speed.
<> 144:ef7eb2e8f9f7 24 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
<> 144:ef7eb2e8f9f7 25 (+) All GPIOs are in input floating state, except the JTAG pins which
<> 144:ef7eb2e8f9f7 26 are assigned to be used for debug purpose.
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 [..]
<> 144:ef7eb2e8f9f7 29 Once the device started from reset, the user application has to:
<> 144:ef7eb2e8f9f7 30 (+) Configure the clock source to be used to drive the System clock
<> 144:ef7eb2e8f9f7 31 (if the application needs higher frequency/performance)
<> 144:ef7eb2e8f9f7 32 (+) Configure the System clock frequency and Flash settings
<> 144:ef7eb2e8f9f7 33 (+) Configure the AHB and APB busses prescalers
<> 144:ef7eb2e8f9f7 34 (+) Enable the clock for the peripheral(s) to be used
<> 144:ef7eb2e8f9f7 35 (+) Configure the clock source(s) for peripherals which clocks are not
<> 144:ef7eb2e8f9f7 36 derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 ##### RCC Limitations #####
<> 144:ef7eb2e8f9f7 39 ==============================================================================
<> 144:ef7eb2e8f9f7 40 [..]
<> 144:ef7eb2e8f9f7 41 A delay between an RCC peripheral clock enable and the effective peripheral
<> 144:ef7eb2e8f9f7 42 enabling should be taken into account in order to manage the peripheral read/write
<> 144:ef7eb2e8f9f7 43 from/to registers.
<> 144:ef7eb2e8f9f7 44 (+) This delay depends on the peripheral mapping.
<> 144:ef7eb2e8f9f7 45 (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
<> 144:ef7eb2e8f9f7 46 after the clock enable bit is set on the hardware register
<> 144:ef7eb2e8f9f7 47 (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
<> 144:ef7eb2e8f9f7 48 after the clock enable bit is set on the hardware register
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 [..]
<> 144:ef7eb2e8f9f7 51 Possible Workarounds:
<> 144:ef7eb2e8f9f7 52 (#) Enable the peripheral clock sometimes before the peripheral read/write
<> 144:ef7eb2e8f9f7 53 register is required.
<> 144:ef7eb2e8f9f7 54 (#) For AHB peripheral, insert two dummy read to the peripheral register.
<> 144:ef7eb2e8f9f7 55 (#) For APB peripheral, insert a dummy read to the peripheral register.
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 @endverbatim
<> 144:ef7eb2e8f9f7 58 ******************************************************************************
<> 144:ef7eb2e8f9f7 59 * @attention
<> 144:ef7eb2e8f9f7 60 *
<> 144:ef7eb2e8f9f7 61 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 62 *
<> 144:ef7eb2e8f9f7 63 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 64 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 65 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 66 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 67 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 68 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 69 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 70 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 71 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 72 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 75 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 76 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 77 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 78 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 79 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 80 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 81 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 82 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 83 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 ******************************************************************************
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87
<> 144:ef7eb2e8f9f7 88 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 89 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 92 * @{
<> 144:ef7eb2e8f9f7 93 */
<> 144:ef7eb2e8f9f7 94
<> 144:ef7eb2e8f9f7 95 /** @defgroup RCC RCC
<> 144:ef7eb2e8f9f7 96 * @brief RCC HAL module driver
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 103 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 104 /** @addtogroup RCC_Private_Constants
<> 144:ef7eb2e8f9f7 105 * @{
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107 #define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000U) /* 5 s */
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 110 #define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 111 #define MCO1_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 112 #define MCO1_PIN GPIO_PIN_8
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 #define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 115 #define MCO2_GPIO_PORT GPIOC
<> 144:ef7eb2e8f9f7 116 #define MCO2_PIN GPIO_PIN_9
<> 144:ef7eb2e8f9f7 117 /**
<> 144:ef7eb2e8f9f7 118 * @}
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120
<> 144:ef7eb2e8f9f7 121 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 122 /** @defgroup RCC_Private_Variables RCC Private Variables
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125 const uint8_t APBAHBPrescTable[16] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
<> 144:ef7eb2e8f9f7 126 /**
<> 144:ef7eb2e8f9f7 127 * @}
<> 144:ef7eb2e8f9f7 128 */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 131 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 /** @defgroup RCC_Exported_Functions RCC Exported Functions
<> 144:ef7eb2e8f9f7 134 * @{
<> 144:ef7eb2e8f9f7 135 */
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 138 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 139 *
<> 144:ef7eb2e8f9f7 140 @verbatim
<> 144:ef7eb2e8f9f7 141 ===============================================================================
<> 144:ef7eb2e8f9f7 142 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 143 ===============================================================================
<> 144:ef7eb2e8f9f7 144 [..]
<> 144:ef7eb2e8f9f7 145 This section provides functions allowing to configure the internal/external oscillators
<> 144:ef7eb2e8f9f7 146 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
<> 144:ef7eb2e8f9f7 147 and APB2).
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 [..] Internal/external clock and PLL configuration
<> 144:ef7eb2e8f9f7 150 (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
<> 144:ef7eb2e8f9f7 151 the PLL as System clock source.
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 (#) LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
<> 144:ef7eb2e8f9f7 154 clock source.
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 (#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
<> 144:ef7eb2e8f9f7 157 through the PLL as System clock source. Can be used also as RTC clock source.
<> 144:ef7eb2e8f9f7 158
<> 144:ef7eb2e8f9f7 159 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
<> 144:ef7eb2e8f9f7 162 (++) The first output is used to generate the high speed system clock (up to 120 MHz)
<> 144:ef7eb2e8f9f7 163 (++) The second output is used to generate the clock for the USB OTG FS (48 MHz),
<> 144:ef7eb2e8f9f7 164 the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
<> 144:ef7eb2e8f9f7 165
<> 144:ef7eb2e8f9f7 166 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
<> 144:ef7eb2e8f9f7 167 and if a HSE clock failure occurs(HSE used directly or through PLL as System
<> 144:ef7eb2e8f9f7 168 clock source), the System clocks automatically switched to HSI and an interrupt
<> 144:ef7eb2e8f9f7 169 is generated if enabled. The interrupt is linked to the Cortex-M3 NMI
<> 144:ef7eb2e8f9f7 170 (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 (#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
<> 144:ef7eb2e8f9f7 173 clock (through a configurable prescaler) on PA8 pin.
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 (#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
<> 144:ef7eb2e8f9f7 176 clock (through a configurable prescaler) on PC9 pin.
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 [..] System, AHB and APB busses clocks configuration
<> 144:ef7eb2e8f9f7 179 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
<> 144:ef7eb2e8f9f7 180 HSE and PLL.
<> 144:ef7eb2e8f9f7 181 The AHB clock (HCLK) is derived from System clock through configurable
<> 144:ef7eb2e8f9f7 182 prescaler and used to clock the CPU, memory and peripherals mapped
<> 144:ef7eb2e8f9f7 183 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
<> 144:ef7eb2e8f9f7 184 from AHB clock through configurable prescalers and used to clock
<> 144:ef7eb2e8f9f7 185 the peripherals mapped on these busses. You can use
<> 144:ef7eb2e8f9f7 186 "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
<> 144:ef7eb2e8f9f7 189 (+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
<> 144:ef7eb2e8f9f7 190 from an external clock mapped on the I2S_CKIN pin.
<> 144:ef7eb2e8f9f7 191 You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
<> 144:ef7eb2e8f9f7 192 (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
<> 144:ef7eb2e8f9f7 193 divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
<> 144:ef7eb2e8f9f7 194 macros to configure this clock.
<> 144:ef7eb2e8f9f7 195 (+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
<> 144:ef7eb2e8f9f7 196 to work correctly, while the SDIO require a frequency equal or lower than
<> 144:ef7eb2e8f9f7 197 to 48. This clock is derived of the main PLL through PLLQ divider.
<> 144:ef7eb2e8f9f7 198 (+@) IWDG clock which is always the LSI clock.
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 (#) For the stm32f2xx devices, the maximum
<> 144:ef7eb2e8f9f7 201 frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
<> 144:ef7eb2e8f9f7 202 Depending on the device voltage range, the maximum frequency should
<> 144:ef7eb2e8f9f7 203 be adapted accordingly:
<> 144:ef7eb2e8f9f7 204 +-------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 205 | Latency | HCLK clock frequency (MHz) |
<> 144:ef7eb2e8f9f7 206 | |---------------------------------------------------------------------|
<> 144:ef7eb2e8f9f7 207 | | voltage range | voltage range | voltage range | voltage range |
<> 144:ef7eb2e8f9f7 208 | | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
<> 144:ef7eb2e8f9f7 209 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 210 |0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
<> 144:ef7eb2e8f9f7 211 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 212 |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
<> 144:ef7eb2e8f9f7 213 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 214 |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
<> 144:ef7eb2e8f9f7 215 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 216 |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
<> 144:ef7eb2e8f9f7 217 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 218 |4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
<> 144:ef7eb2e8f9f7 219 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 220 |5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
<> 144:ef7eb2e8f9f7 221 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 222 |6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
<> 144:ef7eb2e8f9f7 223 |---------------|----------------|----------------|-----------------|-----------------|
<> 144:ef7eb2e8f9f7 224 |7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
<> 144:ef7eb2e8f9f7 225 +-------------------------------------------------------------------------------------+
<> 144:ef7eb2e8f9f7 226 @endverbatim
<> 144:ef7eb2e8f9f7 227 * @{
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /**
<> 144:ef7eb2e8f9f7 231 * @brief Resets the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 232 * @note The default reset state of the clock configuration is given below:
<> 144:ef7eb2e8f9f7 233 * - HSI ON and used as system clock source
<> 144:ef7eb2e8f9f7 234 * - HSE, PLL and PLLI2S OFF
<> 144:ef7eb2e8f9f7 235 * - AHB, APB1 and APB2 prescaler set to 1.
<> 144:ef7eb2e8f9f7 236 * - CSS, MCO1 and MCO2 OFF
<> 144:ef7eb2e8f9f7 237 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 238 * @note This function doesn't modify the configuration of the
<> 144:ef7eb2e8f9f7 239 * - Peripheral clocks
<> 144:ef7eb2e8f9f7 240 * - LSI, LSE and RTC clocks
<> 144:ef7eb2e8f9f7 241 * @retval None
<> 144:ef7eb2e8f9f7 242 */
<> 144:ef7eb2e8f9f7 243 void HAL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 244 {
<> 144:ef7eb2e8f9f7 245 /* Set HSION bit */
<> 144:ef7eb2e8f9f7 246 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 249 CLEAR_REG(RCC->CFGR);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Reset HSEON, CSSON, PLLON, PLLI2S */
<> 144:ef7eb2e8f9f7 252 CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Reset PLLCFGR register */
<> 144:ef7eb2e8f9f7 255 CLEAR_REG(RCC->PLLCFGR);
<> 144:ef7eb2e8f9f7 256 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* Reset PLLI2SCFGR register */
<> 144:ef7eb2e8f9f7 259 CLEAR_REG(RCC->PLLI2SCFGR);
<> 144:ef7eb2e8f9f7 260 SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 263 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 266 CLEAR_REG(RCC->CIR);
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 269 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 270 }
<> 144:ef7eb2e8f9f7 271
<> 144:ef7eb2e8f9f7 272 /**
<> 144:ef7eb2e8f9f7 273 * @brief Initializes the RCC Oscillators according to the specified parameters in the
<> 144:ef7eb2e8f9f7 274 * RCC_OscInitTypeDef.
<> 144:ef7eb2e8f9f7 275 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 276 * contains the configuration information for the RCC Oscillators.
<> 144:ef7eb2e8f9f7 277 * @note The PLL is not disabled when used as system clock.
<> 144:ef7eb2e8f9f7 278 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<> 144:ef7eb2e8f9f7 279 * supported by this API. User should request a transition to LSE Off
<> 144:ef7eb2e8f9f7 280 * first and then LSE On or LSE Bypass.
<> 144:ef7eb2e8f9f7 281 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 282 * supported by this API. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 283 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 284 * @retval HAL status
<> 144:ef7eb2e8f9f7 285 */
<> 144:ef7eb2e8f9f7 286 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 287 {
<> 144:ef7eb2e8f9f7 288 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /* Check the parameters */
<> 144:ef7eb2e8f9f7 291 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<> 144:ef7eb2e8f9f7 292 /*------------------------------- HSE Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 293 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 /* Check the parameters */
<> 144:ef7eb2e8f9f7 296 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<> 144:ef7eb2e8f9f7 297 /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */
<> 144:ef7eb2e8f9f7 298 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) ||\
<> 144:ef7eb2e8f9f7 299 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305 }
<> 144:ef7eb2e8f9f7 306 else
<> 144:ef7eb2e8f9f7 307 {
<> 144:ef7eb2e8f9f7 308 /* Set the new HSE configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 309 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Check the HSE State */
<> 144:ef7eb2e8f9f7 312 if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 315 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Wait till HSE is ready */
<> 144:ef7eb2e8f9f7 318 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326 else
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 329 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Wait till HSE is bypassed or disabled */
<> 144:ef7eb2e8f9f7 332 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342 /*----------------------------- HSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 343 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 346 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<> 144:ef7eb2e8f9f7 347 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<> 144:ef7eb2e8f9f7 350 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
<> 144:ef7eb2e8f9f7 351 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 /* When HSI is used as system clock it will not disabled */
<> 144:ef7eb2e8f9f7 354 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 /* Otherwise, just the calibration is allowed */
<> 144:ef7eb2e8f9f7 359 else
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 362 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365 else
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 /* Check the HSI State */
<> 144:ef7eb2e8f9f7 368 if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 /* Enable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 371 __HAL_RCC_HSI_ENABLE();
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 374 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 377 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 380 {
<> 144:ef7eb2e8f9f7 381 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 386 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388 else
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 /* Disable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 391 __HAL_RCC_HSI_DISABLE();
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 394 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 397 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 /*------------------------------ LSI Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 408 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 /* Check the parameters */
<> 144:ef7eb2e8f9f7 411 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Check the LSI State */
<> 144:ef7eb2e8f9f7 414 if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 /* Enable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 417 __HAL_RCC_LSI_ENABLE();
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 420 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 423 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431 else
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 /* Disable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 434 __HAL_RCC_LSI_DISABLE();
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 437 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 440 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449 /*------------------------------ LSE Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 450 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 /* Check the parameters */
<> 144:ef7eb2e8f9f7 453 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<> 144:ef7eb2e8f9f7 454
<> 144:ef7eb2e8f9f7 455 /* Enable Power Clock*/
<> 144:ef7eb2e8f9f7 456 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 459 PWR->CR |= PWR_CR_DBP;
<> 144:ef7eb2e8f9f7 460
<> 144:ef7eb2e8f9f7 461 /* Wait for Backup domain Write protection enable */
<> 144:ef7eb2e8f9f7 462 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 463
<> 144:ef7eb2e8f9f7 464 while((PWR->CR & PWR_CR_DBP) == RESET)
<> 144:ef7eb2e8f9f7 465 {
<> 144:ef7eb2e8f9f7 466 if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 467 {
<> 144:ef7eb2e8f9f7 468 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 469 }
<> 144:ef7eb2e8f9f7 470 }
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 /* Set the new LSE configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 473 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<> 144:ef7eb2e8f9f7 474 /* Check the LSE State */
<> 144:ef7eb2e8f9f7 475 if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 478 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 481 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 482 {
<> 144:ef7eb2e8f9f7 483 if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 484 {
<> 144:ef7eb2e8f9f7 485 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 486 }
<> 144:ef7eb2e8f9f7 487 }
<> 144:ef7eb2e8f9f7 488 }
<> 144:ef7eb2e8f9f7 489 else
<> 144:ef7eb2e8f9f7 490 {
<> 144:ef7eb2e8f9f7 491 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 492 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 493
<> 144:ef7eb2e8f9f7 494 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 495 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<> 144:ef7eb2e8f9f7 496 {
<> 144:ef7eb2e8f9f7 497 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 498 {
<> 144:ef7eb2e8f9f7 499 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 500 }
<> 144:ef7eb2e8f9f7 501 }
<> 144:ef7eb2e8f9f7 502 }
<> 144:ef7eb2e8f9f7 503 }
<> 144:ef7eb2e8f9f7 504 /*-------------------------------- PLL Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 505 /* Check the parameters */
<> 144:ef7eb2e8f9f7 506 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<> 144:ef7eb2e8f9f7 507 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 510 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
<> 144:ef7eb2e8f9f7 511 {
<> 144:ef7eb2e8f9f7 512 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<> 144:ef7eb2e8f9f7 513 {
<> 144:ef7eb2e8f9f7 514 /* Check the parameters */
<> 144:ef7eb2e8f9f7 515 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<> 144:ef7eb2e8f9f7 516 assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
<> 144:ef7eb2e8f9f7 517 assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
<> 144:ef7eb2e8f9f7 518 assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
<> 144:ef7eb2e8f9f7 519 assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 522 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 523
<> 144:ef7eb2e8f9f7 524 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 525 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 528 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 529 {
<> 144:ef7eb2e8f9f7 530 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 531 {
<> 144:ef7eb2e8f9f7 532 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 533 }
<> 144:ef7eb2e8f9f7 534 }
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536 /* Configure the main PLL clock source, multiplication and division factors. */
<> 144:ef7eb2e8f9f7 537 WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
<> 144:ef7eb2e8f9f7 538 RCC_OscInitStruct->PLL.PLLM | \
<> 144:ef7eb2e8f9f7 539 (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
<> 144:ef7eb2e8f9f7 540 (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
<> 144:ef7eb2e8f9f7 541 (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
<> 144:ef7eb2e8f9f7 542 /* Enable the main PLL. */
<> 144:ef7eb2e8f9f7 543 __HAL_RCC_PLL_ENABLE();
<> 144:ef7eb2e8f9f7 544
<> 144:ef7eb2e8f9f7 545 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 546 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 549 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 550 {
<> 144:ef7eb2e8f9f7 551 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 552 {
<> 144:ef7eb2e8f9f7 553 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 554 }
<> 144:ef7eb2e8f9f7 555 }
<> 144:ef7eb2e8f9f7 556 }
<> 144:ef7eb2e8f9f7 557 else
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 560 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 563 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 566 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 569 {
<> 144:ef7eb2e8f9f7 570 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572 }
<> 144:ef7eb2e8f9f7 573 }
<> 144:ef7eb2e8f9f7 574 }
<> 144:ef7eb2e8f9f7 575 else
<> 144:ef7eb2e8f9f7 576 {
<> 144:ef7eb2e8f9f7 577 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 578 }
<> 144:ef7eb2e8f9f7 579 }
<> 144:ef7eb2e8f9f7 580 return HAL_OK;
<> 144:ef7eb2e8f9f7 581 }
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /**
<> 144:ef7eb2e8f9f7 584 * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
<> 144:ef7eb2e8f9f7 585 * parameters in the RCC_ClkInitStruct.
<> 144:ef7eb2e8f9f7 586 * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 587 * contains the configuration information for the RCC peripheral.
<> 144:ef7eb2e8f9f7 588 * @param FLatency: FLASH Latency, this parameter depend on device selected
<> 144:ef7eb2e8f9f7 589 *
<> 144:ef7eb2e8f9f7 590 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 591 * and updated by HAL_RCC_GetHCLKFreq() function called within this function
<> 144:ef7eb2e8f9f7 592 *
<> 144:ef7eb2e8f9f7 593 * @note The HSI is used (enabled by hardware) as system clock source after
<> 144:ef7eb2e8f9f7 594 * startup from Reset, wake-up from STOP and STANDBY mode, or in case
<> 144:ef7eb2e8f9f7 595 * of failure of the HSE used directly or indirectly as system clock
<> 144:ef7eb2e8f9f7 596 * (if the Clock Security System CSS is enabled).
<> 144:ef7eb2e8f9f7 597 *
<> 144:ef7eb2e8f9f7 598 * @note A switch from one clock source to another occurs only if the target
<> 144:ef7eb2e8f9f7 599 * clock source is ready (clock stable after startup delay or PLL locked).
<> 144:ef7eb2e8f9f7 600 * If a clock source which is not yet ready is selected, the switch will
<> 144:ef7eb2e8f9f7 601 * occur when the clock source will be ready.
<> 144:ef7eb2e8f9f7 602 *
<> 144:ef7eb2e8f9f7 603 * @note Depending on the device voltage range, the software has to set correctly
<> 144:ef7eb2e8f9f7 604 * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
<> 144:ef7eb2e8f9f7 605 * (for more details refer to section above "Initialization/de-initialization functions")
<> 144:ef7eb2e8f9f7 606 * @retval None
<> 144:ef7eb2e8f9f7 607 */
<> 144:ef7eb2e8f9f7 608 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<> 144:ef7eb2e8f9f7 609 {
<> 144:ef7eb2e8f9f7 610 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 611
<> 144:ef7eb2e8f9f7 612 /* Check the parameters */
<> 144:ef7eb2e8f9f7 613 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<> 144:ef7eb2e8f9f7 614 assert_param(IS_FLASH_LATENCY(FLatency));
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
<> 144:ef7eb2e8f9f7 617 must be correctly programmed according to the frequency of the CPU clock
<> 144:ef7eb2e8f9f7 618 (HCLK) and the supply voltage of the device. */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620 /* Increasing the number of wait states because of higher CPU frequency */
<> 144:ef7eb2e8f9f7 621 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 622 {
<> 144:ef7eb2e8f9f7 623 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 624 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 625
<> 144:ef7eb2e8f9f7 626 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 627 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 628 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 }
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 /*-------------------------- HCLK Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 635 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<> 144:ef7eb2e8f9f7 636 {
<> 144:ef7eb2e8f9f7 637 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 638 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 639 }
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /*------------------------- SYSCLK Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 642 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
<> 144:ef7eb2e8f9f7 645
<> 144:ef7eb2e8f9f7 646 /* HSE is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 647 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 648 {
<> 144:ef7eb2e8f9f7 649 /* Check the HSE ready flag */
<> 144:ef7eb2e8f9f7 650 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655 /* PLL is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 656 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 /* Check the PLL ready flag */
<> 144:ef7eb2e8f9f7 659 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 660 {
<> 144:ef7eb2e8f9f7 661 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 662 }
<> 144:ef7eb2e8f9f7 663 }
<> 144:ef7eb2e8f9f7 664 /* HSI is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 665 else
<> 144:ef7eb2e8f9f7 666 {
<> 144:ef7eb2e8f9f7 667 /* Check the HSI ready flag */
<> 144:ef7eb2e8f9f7 668 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 671 }
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
<> 144:ef7eb2e8f9f7 675 /* Get Start Tick*/
<> 144:ef7eb2e8f9f7 676 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 679 {
<> 144:ef7eb2e8f9f7 680 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 681 {
<> 144:ef7eb2e8f9f7 682 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 683 {
<> 144:ef7eb2e8f9f7 684 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 685 }
<> 144:ef7eb2e8f9f7 686 }
<> 144:ef7eb2e8f9f7 687 }
<> 144:ef7eb2e8f9f7 688 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 691 {
<> 144:ef7eb2e8f9f7 692 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 693 {
<> 144:ef7eb2e8f9f7 694 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 695 }
<> 144:ef7eb2e8f9f7 696 }
<> 144:ef7eb2e8f9f7 697 }
<> 144:ef7eb2e8f9f7 698 else
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 701 {
<> 144:ef7eb2e8f9f7 702 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 705 }
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /* Decreasing the number of wait states because of lower CPU frequency */
<> 144:ef7eb2e8f9f7 711 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 714 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 715
<> 144:ef7eb2e8f9f7 716 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 717 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 718 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 721 }
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 /*-------------------------- PCLK1 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 725 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<> 144:ef7eb2e8f9f7 726 {
<> 144:ef7eb2e8f9f7 727 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 728 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /*-------------------------- PCLK2 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 732 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
<> 144:ef7eb2e8f9f7 733 {
<> 144:ef7eb2e8f9f7 734 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
<> 144:ef7eb2e8f9f7 735 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
<> 144:ef7eb2e8f9f7 736 }
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 739 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 742 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 return HAL_OK;
<> 144:ef7eb2e8f9f7 745 }
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 /**
<> 144:ef7eb2e8f9f7 748 * @}
<> 144:ef7eb2e8f9f7 749 */
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 752 * @brief RCC clocks control functions
<> 144:ef7eb2e8f9f7 753 *
<> 144:ef7eb2e8f9f7 754 @verbatim
<> 144:ef7eb2e8f9f7 755 ===============================================================================
<> 144:ef7eb2e8f9f7 756 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 757 ===============================================================================
<> 144:ef7eb2e8f9f7 758 [..]
<> 144:ef7eb2e8f9f7 759 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 760 frequencies.
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 @endverbatim
<> 144:ef7eb2e8f9f7 763 * @{
<> 144:ef7eb2e8f9f7 764 */
<> 144:ef7eb2e8f9f7 765
<> 144:ef7eb2e8f9f7 766 /**
<> 144:ef7eb2e8f9f7 767 * @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
<> 144:ef7eb2e8f9f7 768 * @note PA8/PC9 should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 769 * @param RCC_MCOx: specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 770 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 771 * @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 772 * @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
<> 144:ef7eb2e8f9f7 773 * @param RCC_MCOSource: specifies the clock source to output.
<> 144:ef7eb2e8f9f7 774 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 775 * @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 776 * @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 777 * @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 778 * @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
<> 144:ef7eb2e8f9f7 779 * @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
<> 144:ef7eb2e8f9f7 780 * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
<> 144:ef7eb2e8f9f7 781 * @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
<> 144:ef7eb2e8f9f7 782 * @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
<> 144:ef7eb2e8f9f7 783 * @param RCC_MCODiv: specifies the MCOx prescaler.
<> 144:ef7eb2e8f9f7 784 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 785 * @arg RCC_MCODIV_1: no division applied to MCOx clock
<> 144:ef7eb2e8f9f7 786 * @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
<> 144:ef7eb2e8f9f7 787 * @arg RCC_MCODIV_3: division by 3 applied to MCOx clock
<> 144:ef7eb2e8f9f7 788 * @arg RCC_MCODIV_4: division by 4 applied to MCOx clock
<> 144:ef7eb2e8f9f7 789 * @arg RCC_MCODIV_5: division by 5 applied to MCOx clock
<> 144:ef7eb2e8f9f7 790 * @retval None
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<> 144:ef7eb2e8f9f7 793 {
<> 144:ef7eb2e8f9f7 794 GPIO_InitTypeDef GPIO_InitStruct;
<> 144:ef7eb2e8f9f7 795 /* Check the parameters */
<> 144:ef7eb2e8f9f7 796 assert_param(IS_RCC_MCO(RCC_MCOx));
<> 144:ef7eb2e8f9f7 797 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<> 144:ef7eb2e8f9f7 798 /* RCC_MCO1 */
<> 144:ef7eb2e8f9f7 799 if(RCC_MCOx == RCC_MCO1)
<> 144:ef7eb2e8f9f7 800 {
<> 144:ef7eb2e8f9f7 801 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 /* MCO1 Clock Enable */
<> 144:ef7eb2e8f9f7 804 __MCO1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /* Configure the MCO1 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 807 GPIO_InitStruct.Pin = MCO1_PIN;
<> 144:ef7eb2e8f9f7 808 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 809 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
<> 144:ef7eb2e8f9f7 810 GPIO_InitStruct.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 811 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
<> 144:ef7eb2e8f9f7 812 HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
<> 144:ef7eb2e8f9f7 815 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
<> 144:ef7eb2e8f9f7 816 }
<> 144:ef7eb2e8f9f7 817 else
<> 144:ef7eb2e8f9f7 818 {
<> 144:ef7eb2e8f9f7 819 assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* MCO2 Clock Enable */
<> 144:ef7eb2e8f9f7 822 __MCO2_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 823
<> 144:ef7eb2e8f9f7 824 /* Configure the MCO2 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 825 GPIO_InitStruct.Pin = MCO2_PIN;
<> 144:ef7eb2e8f9f7 826 GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 827 GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
<> 144:ef7eb2e8f9f7 828 GPIO_InitStruct.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 829 GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
<> 144:ef7eb2e8f9f7 830 HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
<> 144:ef7eb2e8f9f7 831
<> 144:ef7eb2e8f9f7 832 /* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
<> 144:ef7eb2e8f9f7 833 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 }
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 /**
<> 144:ef7eb2e8f9f7 838 * @brief Enables the Clock Security System.
<> 144:ef7eb2e8f9f7 839 * @note If a failure is detected on the HSE oscillator clock, this oscillator
<> 144:ef7eb2e8f9f7 840 * is automatically disabled and an interrupt is generated to inform the
<> 144:ef7eb2e8f9f7 841 * software about the failure (Clock Security System Interrupt, CSSI),
<> 144:ef7eb2e8f9f7 842 * allowing the MCU to perform rescue operations. The CSSI is linked to
<> 144:ef7eb2e8f9f7 843 * the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 844 * @retval None
<> 144:ef7eb2e8f9f7 845 */
<> 144:ef7eb2e8f9f7 846 void HAL_RCC_EnableCSS(void)
<> 144:ef7eb2e8f9f7 847 {
<> 144:ef7eb2e8f9f7 848 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
<> 144:ef7eb2e8f9f7 849 }
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /**
<> 144:ef7eb2e8f9f7 852 * @brief Disables the Clock Security System.
<> 144:ef7eb2e8f9f7 853 * @retval None
<> 144:ef7eb2e8f9f7 854 */
<> 144:ef7eb2e8f9f7 855 void HAL_RCC_DisableCSS(void)
<> 144:ef7eb2e8f9f7 856 {
<> 144:ef7eb2e8f9f7 857 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
<> 144:ef7eb2e8f9f7 858 }
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /**
<> 144:ef7eb2e8f9f7 861 * @brief Returns the SYSCLK frequency
<> 144:ef7eb2e8f9f7 862 *
<> 144:ef7eb2e8f9f7 863 * @note The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 864 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 865 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 866 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 867 * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 868 * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
<> 144:ef7eb2e8f9f7 869 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
<> 144:ef7eb2e8f9f7 870 * @note (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 871 * 16 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 872 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 873 * @note (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 874 * 25 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 875 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 876 * have wrong result.
<> 144:ef7eb2e8f9f7 877 *
<> 144:ef7eb2e8f9f7 878 * @note The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 879 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 880 *
<> 144:ef7eb2e8f9f7 881 * @note This function can be used by the user application to compute the
<> 144:ef7eb2e8f9f7 882 * baudrate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 883 *
<> 144:ef7eb2e8f9f7 884 * @note Each time SYSCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 885 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 886 *
<> 144:ef7eb2e8f9f7 887 *
<> 144:ef7eb2e8f9f7 888 * @retval SYSCLK frequency
<> 144:ef7eb2e8f9f7 889 */
<> 144:ef7eb2e8f9f7 890 uint32_t HAL_RCC_GetSysClockFreq(void)
<> 144:ef7eb2e8f9f7 891 {
<> 144:ef7eb2e8f9f7 892 uint32_t pllm = 0U, pllvco = 0U, pllp = 0U;
<> 144:ef7eb2e8f9f7 893 uint32_t sysclockfreq = 0U;
<> 144:ef7eb2e8f9f7 894
<> 144:ef7eb2e8f9f7 895 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 896 switch (RCC->CFGR & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 897 {
<> 144:ef7eb2e8f9f7 898 case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 899 {
<> 144:ef7eb2e8f9f7 900 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 901 break;
<> 144:ef7eb2e8f9f7 902 }
<> 144:ef7eb2e8f9f7 903 case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
<> 144:ef7eb2e8f9f7 904 {
<> 144:ef7eb2e8f9f7 905 sysclockfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 906 break;
<> 144:ef7eb2e8f9f7 907 }
<> 144:ef7eb2e8f9f7 908 case RCC_CFGR_SWS_PLL: /* PLL used as system clock source */
<> 144:ef7eb2e8f9f7 909 {
<> 144:ef7eb2e8f9f7 910 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
<> 144:ef7eb2e8f9f7 911 SYSCLK = PLL_VCO / PLLP */
<> 144:ef7eb2e8f9f7 912 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
<> 144:ef7eb2e8f9f7 913 if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
<> 144:ef7eb2e8f9f7 914 {
<> 144:ef7eb2e8f9f7 915 /* HSE used as PLL clock source */
<> 144:ef7eb2e8f9f7 916 pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
<> 144:ef7eb2e8f9f7 917 }
<> 144:ef7eb2e8f9f7 918 else
<> 144:ef7eb2e8f9f7 919 {
<> 144:ef7eb2e8f9f7 920 /* HSI used as PLL clock source */
<> 144:ef7eb2e8f9f7 921 pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
<> 144:ef7eb2e8f9f7 922 }
<> 144:ef7eb2e8f9f7 923 pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
<> 144:ef7eb2e8f9f7 924
<> 144:ef7eb2e8f9f7 925 sysclockfreq = pllvco/pllp;
<> 144:ef7eb2e8f9f7 926 break;
<> 144:ef7eb2e8f9f7 927 }
<> 144:ef7eb2e8f9f7 928 default:
<> 144:ef7eb2e8f9f7 929 {
<> 144:ef7eb2e8f9f7 930 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 931 break;
<> 144:ef7eb2e8f9f7 932 }
<> 144:ef7eb2e8f9f7 933 }
<> 144:ef7eb2e8f9f7 934 return sysclockfreq;
<> 144:ef7eb2e8f9f7 935 }
<> 144:ef7eb2e8f9f7 936
<> 144:ef7eb2e8f9f7 937 /**
<> 144:ef7eb2e8f9f7 938 * @brief Returns the HCLK frequency
<> 144:ef7eb2e8f9f7 939 * @note Each time HCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 940 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 941 *
<> 144:ef7eb2e8f9f7 942 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 943 * and updated within this function
<> 144:ef7eb2e8f9f7 944 * @retval HCLK frequency
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 uint32_t HAL_RCC_GetHCLKFreq(void)
<> 144:ef7eb2e8f9f7 947 {
<> 144:ef7eb2e8f9f7 948 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950
<> 144:ef7eb2e8f9f7 951 /**
<> 144:ef7eb2e8f9f7 952 * @brief Returns the PCLK1 frequency
<> 144:ef7eb2e8f9f7 953 * @note Each time PCLK1 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 954 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 955 * @retval PCLK1 frequency
<> 144:ef7eb2e8f9f7 956 */
<> 144:ef7eb2e8f9f7 957 uint32_t HAL_RCC_GetPCLK1Freq(void)
<> 144:ef7eb2e8f9f7 958 {
<> 144:ef7eb2e8f9f7 959 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 960 return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
<> 144:ef7eb2e8f9f7 961 }
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963 /**
<> 144:ef7eb2e8f9f7 964 * @brief Returns the PCLK2 frequency
<> 144:ef7eb2e8f9f7 965 * @note Each time PCLK2 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 966 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 967 * @retval PCLK2 frequency
<> 144:ef7eb2e8f9f7 968 */
<> 144:ef7eb2e8f9f7 969 uint32_t HAL_RCC_GetPCLK2Freq(void)
<> 144:ef7eb2e8f9f7 970 {
<> 144:ef7eb2e8f9f7 971 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 972 return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
<> 144:ef7eb2e8f9f7 973 }
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /**
<> 144:ef7eb2e8f9f7 976 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 977 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 978 * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 979 * will be configured.
<> 144:ef7eb2e8f9f7 980 * @retval None
<> 144:ef7eb2e8f9f7 981 */
<> 144:ef7eb2e8f9f7 982 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 983 {
<> 144:ef7eb2e8f9f7 984 /* Set all possible values for the Oscillator type parameter ---------------*/
<> 144:ef7eb2e8f9f7 985 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
<> 144:ef7eb2e8f9f7 986
<> 144:ef7eb2e8f9f7 987 /* Get the HSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 988 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<> 144:ef7eb2e8f9f7 989 {
<> 144:ef7eb2e8f9f7 990 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<> 144:ef7eb2e8f9f7 991 }
<> 144:ef7eb2e8f9f7 992 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<> 144:ef7eb2e8f9f7 993 {
<> 144:ef7eb2e8f9f7 994 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 else
<> 144:ef7eb2e8f9f7 997 {
<> 144:ef7eb2e8f9f7 998 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 999 }
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /* Get the HSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1002 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 1003 {
<> 144:ef7eb2e8f9f7 1004 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006 else
<> 144:ef7eb2e8f9f7 1007 {
<> 144:ef7eb2e8f9f7 1008 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 1009 }
<> 144:ef7eb2e8f9f7 1010
<> 144:ef7eb2e8f9f7 1011 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /* Get the LSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1014 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<> 144:ef7eb2e8f9f7 1017 }
<> 144:ef7eb2e8f9f7 1018 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
<> 144:ef7eb2e8f9f7 1019 {
<> 144:ef7eb2e8f9f7 1020 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<> 144:ef7eb2e8f9f7 1021 }
<> 144:ef7eb2e8f9f7 1022 else
<> 144:ef7eb2e8f9f7 1023 {
<> 144:ef7eb2e8f9f7 1024 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 1025 }
<> 144:ef7eb2e8f9f7 1026
<> 144:ef7eb2e8f9f7 1027 /* Get the LSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1028 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1029 {
<> 144:ef7eb2e8f9f7 1030 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<> 144:ef7eb2e8f9f7 1031 }
<> 144:ef7eb2e8f9f7 1032 else
<> 144:ef7eb2e8f9f7 1033 {
<> 144:ef7eb2e8f9f7 1034 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 1035 }
<> 144:ef7eb2e8f9f7 1036
<> 144:ef7eb2e8f9f7 1037 /* Get the PLL configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1038 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1039 {
<> 144:ef7eb2e8f9f7 1040 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 1041 }
<> 144:ef7eb2e8f9f7 1042 else
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
<> 144:ef7eb2e8f9f7 1047 RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
<> 144:ef7eb2e8f9f7 1048 RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
<> 144:ef7eb2e8f9f7 1049 RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
<> 144:ef7eb2e8f9f7 1050 RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
<> 144:ef7eb2e8f9f7 1051 }
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 /**
<> 144:ef7eb2e8f9f7 1054 * @brief Configures the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1055 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1056 * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1057 * will be configured.
<> 144:ef7eb2e8f9f7 1058 * @param pFLatency: Pointer on the Flash Latency.
<> 144:ef7eb2e8f9f7 1059 * @retval None
<> 144:ef7eb2e8f9f7 1060 */
<> 144:ef7eb2e8f9f7 1061 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
<> 144:ef7eb2e8f9f7 1062 {
<> 144:ef7eb2e8f9f7 1063 /* Set all possible values for the Clock type parameter --------------------*/
<> 144:ef7eb2e8f9f7 1064 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /* Get the SYSCLK configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1067 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 1068
<> 144:ef7eb2e8f9f7 1069 /* Get the HCLK configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1070 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<> 144:ef7eb2e8f9f7 1071
<> 144:ef7eb2e8f9f7 1072 /* Get the APB1 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1073 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
<> 144:ef7eb2e8f9f7 1074
<> 144:ef7eb2e8f9f7 1075 /* Get the APB2 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1076 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Get the Flash Wait State (Latency) configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1079 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<> 144:ef7eb2e8f9f7 1080 }
<> 144:ef7eb2e8f9f7 1081
<> 144:ef7eb2e8f9f7 1082 /**
<> 144:ef7eb2e8f9f7 1083 * @brief This function handles the RCC CSS interrupt request.
<> 144:ef7eb2e8f9f7 1084 * @note This API should be called under the NMI_Handler().
<> 144:ef7eb2e8f9f7 1085 * @retval None
<> 144:ef7eb2e8f9f7 1086 */
<> 144:ef7eb2e8f9f7 1087 void HAL_RCC_NMI_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1088 {
<> 144:ef7eb2e8f9f7 1089 /* Check RCC CSSF flag */
<> 144:ef7eb2e8f9f7 1090 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<> 144:ef7eb2e8f9f7 1091 {
<> 144:ef7eb2e8f9f7 1092 /* RCC Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 1093 HAL_RCC_CSSCallback();
<> 144:ef7eb2e8f9f7 1094
<> 144:ef7eb2e8f9f7 1095 /* Clear RCC CSS pending bit */
<> 144:ef7eb2e8f9f7 1096 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<> 144:ef7eb2e8f9f7 1097 }
<> 144:ef7eb2e8f9f7 1098 }
<> 144:ef7eb2e8f9f7 1099
<> 144:ef7eb2e8f9f7 1100 /**
<> 144:ef7eb2e8f9f7 1101 * @brief RCC Clock Security System interrupt callback
<> 144:ef7eb2e8f9f7 1102 * @retval None
<> 144:ef7eb2e8f9f7 1103 */
<> 144:ef7eb2e8f9f7 1104 __weak void HAL_RCC_CSSCallback(void)
<> 144:ef7eb2e8f9f7 1105 {
<> 144:ef7eb2e8f9f7 1106 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1107 the HAL_RCC_CSSCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1108 */
<> 144:ef7eb2e8f9f7 1109 }
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /**
<> 144:ef7eb2e8f9f7 1112 * @}
<> 144:ef7eb2e8f9f7 1113 */
<> 144:ef7eb2e8f9f7 1114
<> 144:ef7eb2e8f9f7 1115 /**
<> 144:ef7eb2e8f9f7 1116 * @}
<> 144:ef7eb2e8f9f7 1117 */
<> 144:ef7eb2e8f9f7 1118
<> 144:ef7eb2e8f9f7 1119 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1120 /**
<> 144:ef7eb2e8f9f7 1121 * @}
<> 144:ef7eb2e8f9f7 1122 */
<> 144:ef7eb2e8f9f7 1123
<> 144:ef7eb2e8f9f7 1124 /**
<> 144:ef7eb2e8f9f7 1125 * @}
<> 144:ef7eb2e8f9f7 1126 */
<> 144:ef7eb2e8f9f7 1127
<> 144:ef7eb2e8f9f7 1128 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/