mbed-dev - mbed library sources. Supersedes mbed-src.

Users » mbed_official » Code » mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:39:01 2017 +0100
Revision:: 165:e614a9f1c9e2
Child:: 187:0387e8f68319

This updates the lib to the mbed lib v 143

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:e614a9f1c9e2	1	/**
AnnaBridge	165:e614a9f1c9e2	2	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	3	* @file stm32f1xx_ll_i2c.h
AnnaBridge	165:e614a9f1c9e2	4	* @author MCD Application Team
AnnaBridge	165:e614a9f1c9e2	5	* @version V1.1.0
AnnaBridge	165:e614a9f1c9e2	6	* @date 14-April-2017
AnnaBridge	165:e614a9f1c9e2	7	* @brief Header file of I2C LL module.
AnnaBridge	165:e614a9f1c9e2	8	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	9	* @attention
AnnaBridge	165:e614a9f1c9e2	10	*
AnnaBridge	165:e614a9f1c9e2	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	165:e614a9f1c9e2	12	*
AnnaBridge	165:e614a9f1c9e2	13	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:e614a9f1c9e2	14	* are permitted provided that the following conditions are met:
AnnaBridge	165:e614a9f1c9e2	15	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	16	* this list of conditions and the following disclaimer.
AnnaBridge	165:e614a9f1c9e2	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:e614a9f1c9e2	18	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:e614a9f1c9e2	19	* and/or other materials provided with the distribution.
AnnaBridge	165:e614a9f1c9e2	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:e614a9f1c9e2	21	* may be used to endorse or promote products derived from this software
AnnaBridge	165:e614a9f1c9e2	22	* without specific prior written permission.
AnnaBridge	165:e614a9f1c9e2	23	*
AnnaBridge	165:e614a9f1c9e2	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:e614a9f1c9e2	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:e614a9f1c9e2	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:e614a9f1c9e2	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:e614a9f1c9e2	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:e614a9f1c9e2	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:e614a9f1c9e2	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:e614a9f1c9e2	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:e614a9f1c9e2	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:e614a9f1c9e2	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:e614a9f1c9e2	34	*
AnnaBridge	165:e614a9f1c9e2	35	******************************************************************************
AnnaBridge	165:e614a9f1c9e2	36	*/
AnnaBridge	165:e614a9f1c9e2	37
AnnaBridge	165:e614a9f1c9e2	38	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	39	#ifndef __STM32F1xx_LL_I2C_H
AnnaBridge	165:e614a9f1c9e2	40	#define __STM32F1xx_LL_I2C_H
AnnaBridge	165:e614a9f1c9e2	41
AnnaBridge	165:e614a9f1c9e2	42	#ifdef __cplusplus
AnnaBridge	165:e614a9f1c9e2	43	extern "C" {
AnnaBridge	165:e614a9f1c9e2	44	#endif
AnnaBridge	165:e614a9f1c9e2	45
AnnaBridge	165:e614a9f1c9e2	46	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	47	#include "stm32f1xx.h"
AnnaBridge	165:e614a9f1c9e2	48
AnnaBridge	165:e614a9f1c9e2	49	/** @addtogroup STM32F1xx_LL_Driver
AnnaBridge	165:e614a9f1c9e2	50	* @{
AnnaBridge	165:e614a9f1c9e2	51	*/
AnnaBridge	165:e614a9f1c9e2	52
AnnaBridge	165:e614a9f1c9e2	53	#if defined (I2C1) \|\| defined (I2C2)
AnnaBridge	165:e614a9f1c9e2	54
AnnaBridge	165:e614a9f1c9e2	55	/** @defgroup I2C_LL I2C
AnnaBridge	165:e614a9f1c9e2	56	* @{
AnnaBridge	165:e614a9f1c9e2	57	*/
AnnaBridge	165:e614a9f1c9e2	58
AnnaBridge	165:e614a9f1c9e2	59	/* Private types -------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	60	/* Private variables ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	61
AnnaBridge	165:e614a9f1c9e2	62	/* Private constants ---------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	63	/** @defgroup I2C_LL_Private_Constants I2C Private Constants
AnnaBridge	165:e614a9f1c9e2	64	* @{
AnnaBridge	165:e614a9f1c9e2	65	*/
AnnaBridge	165:e614a9f1c9e2	66
AnnaBridge	165:e614a9f1c9e2	67	/* Defines used to perform compute and check in the macros */
AnnaBridge	165:e614a9f1c9e2	68	#define LL_I2C_MAX_SPEED_STANDARD 100000U
AnnaBridge	165:e614a9f1c9e2	69	#define LL_I2C_MAX_SPEED_FAST 400000U
AnnaBridge	165:e614a9f1c9e2	70	/**
AnnaBridge	165:e614a9f1c9e2	71	* @}
AnnaBridge	165:e614a9f1c9e2	72	*/
AnnaBridge	165:e614a9f1c9e2	73
AnnaBridge	165:e614a9f1c9e2	74	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	75	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	76	/** @defgroup I2C_LL_Private_Macros I2C Private Macros
AnnaBridge	165:e614a9f1c9e2	77	* @{
AnnaBridge	165:e614a9f1c9e2	78	*/
AnnaBridge	165:e614a9f1c9e2	79	/**
AnnaBridge	165:e614a9f1c9e2	80	* @}
AnnaBridge	165:e614a9f1c9e2	81	*/
AnnaBridge	165:e614a9f1c9e2	82	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	165:e614a9f1c9e2	83
AnnaBridge	165:e614a9f1c9e2	84	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	85	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	86	/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
AnnaBridge	165:e614a9f1c9e2	87	* @{
AnnaBridge	165:e614a9f1c9e2	88	*/
AnnaBridge	165:e614a9f1c9e2	89	typedef struct
AnnaBridge	165:e614a9f1c9e2	90	{
AnnaBridge	165:e614a9f1c9e2	91	uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
AnnaBridge	165:e614a9f1c9e2	92	This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
AnnaBridge	165:e614a9f1c9e2	93
AnnaBridge	165:e614a9f1c9e2	94	This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
AnnaBridge	165:e614a9f1c9e2	95
AnnaBridge	165:e614a9f1c9e2	96	uint32_t ClockSpeed; /*!< Specifies the clock frequency.
AnnaBridge	165:e614a9f1c9e2	97	This parameter must be set to a value lower than 400kHz (in Hz)
AnnaBridge	165:e614a9f1c9e2	98
AnnaBridge	165:e614a9f1c9e2	99	This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
AnnaBridge	165:e614a9f1c9e2	100	or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
AnnaBridge	165:e614a9f1c9e2	101
AnnaBridge	165:e614a9f1c9e2	102	uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
AnnaBridge	165:e614a9f1c9e2	103	This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
AnnaBridge	165:e614a9f1c9e2	104
AnnaBridge	165:e614a9f1c9e2	105	This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
AnnaBridge	165:e614a9f1c9e2	106
AnnaBridge	165:e614a9f1c9e2	107	uint32_t OwnAddress1; /*!< Specifies the device own address 1.
AnnaBridge	165:e614a9f1c9e2	108	This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
AnnaBridge	165:e614a9f1c9e2	109
AnnaBridge	165:e614a9f1c9e2	110	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge	165:e614a9f1c9e2	111
AnnaBridge	165:e614a9f1c9e2	112	uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge	165:e614a9f1c9e2	113	This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
AnnaBridge	165:e614a9f1c9e2	114
AnnaBridge	165:e614a9f1c9e2	115	This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
AnnaBridge	165:e614a9f1c9e2	116
AnnaBridge	165:e614a9f1c9e2	117	uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
AnnaBridge	165:e614a9f1c9e2	118	This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
AnnaBridge	165:e614a9f1c9e2	119
AnnaBridge	165:e614a9f1c9e2	120	This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge	165:e614a9f1c9e2	121	} LL_I2C_InitTypeDef;
AnnaBridge	165:e614a9f1c9e2	122	/**
AnnaBridge	165:e614a9f1c9e2	123	* @}
AnnaBridge	165:e614a9f1c9e2	124	*/
AnnaBridge	165:e614a9f1c9e2	125	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	165:e614a9f1c9e2	126
AnnaBridge	165:e614a9f1c9e2	127	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	128	/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
AnnaBridge	165:e614a9f1c9e2	129	* @{
AnnaBridge	165:e614a9f1c9e2	130	*/
AnnaBridge	165:e614a9f1c9e2	131
AnnaBridge	165:e614a9f1c9e2	132	/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	165:e614a9f1c9e2	133	* @brief Flags defines which can be used with LL_I2C_ReadReg function
AnnaBridge	165:e614a9f1c9e2	134	* @{
AnnaBridge	165:e614a9f1c9e2	135	*/
AnnaBridge	165:e614a9f1c9e2	136	#define LL_I2C_SR1_SB I2C_SR1_SB /!< Start Bit (master mode) /
AnnaBridge	165:e614a9f1c9e2	137	#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
AnnaBridge	165:e614a9f1c9e2	138	Address matched flag (slave mode) */
AnnaBridge	165:e614a9f1c9e2	139	#define LL_I2C_SR1_BTF I2C_SR1_BTF /!< Byte Transfer Finished flag /
AnnaBridge	165:e614a9f1c9e2	140	#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /!< 10-bit header sent (master mode) /
AnnaBridge	165:e614a9f1c9e2	141	#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /!< Stop detection flag (slave mode) /
AnnaBridge	165:e614a9f1c9e2	142	#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /!< Data register not empty (receivers) /
AnnaBridge	165:e614a9f1c9e2	143	#define LL_I2C_SR1_TXE I2C_SR1_TXE /!< Data register empty (transmitters) /
AnnaBridge	165:e614a9f1c9e2	144	#define LL_I2C_SR1_BERR I2C_SR1_BERR /!< Bus error /
AnnaBridge	165:e614a9f1c9e2	145	#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /!< Arbitration lost /
AnnaBridge	165:e614a9f1c9e2	146	#define LL_I2C_SR1_AF I2C_SR1_AF /!< Acknowledge failure flag /
AnnaBridge	165:e614a9f1c9e2	147	#define LL_I2C_SR1_OVR I2C_SR1_OVR /!< Overrun/Underrun /
AnnaBridge	165:e614a9f1c9e2	148	#define LL_I2C_SR1_PECERR I2C_ISR_PECERR /!< PEC Error in reception (SMBus mode) /
AnnaBridge	165:e614a9f1c9e2	149	#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /!< Timeout detection flag (SMBus mode) /
AnnaBridge	165:e614a9f1c9e2	150	#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /!< SMBus alert (SMBus mode) /
AnnaBridge	165:e614a9f1c9e2	151	#define LL_I2C_SR2_MSL I2C_SR2_MSL /!< Master/Slave flag /
AnnaBridge	165:e614a9f1c9e2	152	#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /!< Bus busy flag /
AnnaBridge	165:e614a9f1c9e2	153	#define LL_I2C_SR2_TRA I2C_SR2_TRA /!< Transmitter/receiver direction /
AnnaBridge	165:e614a9f1c9e2	154	#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /!< General call address (Slave mode) /
AnnaBridge	165:e614a9f1c9e2	155	#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /!< SMBus Device default address (Slave mode) /
AnnaBridge	165:e614a9f1c9e2	156	#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /!< SMBus Host address (Slave mode) /
AnnaBridge	165:e614a9f1c9e2	157	#define LL_I2C_SR2_DUALF I2C_SR2_DUALF /!< Dual flag (Slave mode) /
AnnaBridge	165:e614a9f1c9e2	158	/**
AnnaBridge	165:e614a9f1c9e2	159	* @}
AnnaBridge	165:e614a9f1c9e2	160	*/
AnnaBridge	165:e614a9f1c9e2	161
AnnaBridge	165:e614a9f1c9e2	162	/** @defgroup I2C_LL_EC_IT IT Defines
AnnaBridge	165:e614a9f1c9e2	163	* @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
AnnaBridge	165:e614a9f1c9e2	164	* @{
AnnaBridge	165:e614a9f1c9e2	165	*/
AnnaBridge	165:e614a9f1c9e2	166	#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /!< Events interrupts enable /
AnnaBridge	165:e614a9f1c9e2	167	#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /!< Buffer interrupts enable /
AnnaBridge	165:e614a9f1c9e2	168	#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /!< Error interrupts enable /
AnnaBridge	165:e614a9f1c9e2	169	/**
AnnaBridge	165:e614a9f1c9e2	170	* @}
AnnaBridge	165:e614a9f1c9e2	171	*/
AnnaBridge	165:e614a9f1c9e2	172
AnnaBridge	165:e614a9f1c9e2	173	/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
AnnaBridge	165:e614a9f1c9e2	174	* @{
AnnaBridge	165:e614a9f1c9e2	175	*/
AnnaBridge	165:e614a9f1c9e2	176	#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /!< Own address 1 is a 7-bit address. /
AnnaBridge	165:e614a9f1c9e2	177	#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE \| 0x00004000U) /!< Own address 1 is a 10-bit address. /
AnnaBridge	165:e614a9f1c9e2	178	/**
AnnaBridge	165:e614a9f1c9e2	179	* @}
AnnaBridge	165:e614a9f1c9e2	180	*/
AnnaBridge	165:e614a9f1c9e2	181
AnnaBridge	165:e614a9f1c9e2	182	/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
AnnaBridge	165:e614a9f1c9e2	183	* @{
AnnaBridge	165:e614a9f1c9e2	184	*/
AnnaBridge	165:e614a9f1c9e2	185	#define LL_I2C_DUTYCYCLE_2 0x00000000U /!< I2C fast mode Tlow/Thigh = 2 /
AnnaBridge	165:e614a9f1c9e2	186	#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /!< I2C fast mode Tlow/Thigh = 16/9 /
AnnaBridge	165:e614a9f1c9e2	187	/**
AnnaBridge	165:e614a9f1c9e2	188	* @}
AnnaBridge	165:e614a9f1c9e2	189	*/
AnnaBridge	165:e614a9f1c9e2	190
AnnaBridge	165:e614a9f1c9e2	191	/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
AnnaBridge	165:e614a9f1c9e2	192	* @{
AnnaBridge	165:e614a9f1c9e2	193	*/
AnnaBridge	165:e614a9f1c9e2	194	#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /!< Master clock speed range is standard mode /
AnnaBridge	165:e614a9f1c9e2	195	#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /!< Master clock speed range is fast mode /
AnnaBridge	165:e614a9f1c9e2	196	/**
AnnaBridge	165:e614a9f1c9e2	197	* @}
AnnaBridge	165:e614a9f1c9e2	198	*/
AnnaBridge	165:e614a9f1c9e2	199
AnnaBridge	165:e614a9f1c9e2	200	/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
AnnaBridge	165:e614a9f1c9e2	201	* @{
AnnaBridge	165:e614a9f1c9e2	202	*/
AnnaBridge	165:e614a9f1c9e2	203	#define LL_I2C_MODE_I2C 0x00000000U /!< I2C Master or Slave mode /
AnnaBridge	165:e614a9f1c9e2	204	#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP) /!< SMBus Host address acknowledge /
AnnaBridge	165:e614a9f1c9e2	205	#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /!< SMBus Device default mode (Default address not acknowledge) /
AnnaBridge	165:e614a9f1c9e2	206	#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS \| I2C_CR1_ENARP) /!< SMBus Device Default address acknowledge /
AnnaBridge	165:e614a9f1c9e2	207	/**
AnnaBridge	165:e614a9f1c9e2	208	* @}
AnnaBridge	165:e614a9f1c9e2	209	*/
AnnaBridge	165:e614a9f1c9e2	210
AnnaBridge	165:e614a9f1c9e2	211	/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
AnnaBridge	165:e614a9f1c9e2	212	* @{
AnnaBridge	165:e614a9f1c9e2	213	*/
AnnaBridge	165:e614a9f1c9e2	214	#define LL_I2C_ACK I2C_CR1_ACK /!< ACK is sent after current received byte. /
AnnaBridge	165:e614a9f1c9e2	215	#define LL_I2C_NACK 0x00000000U /!< NACK is sent after current received byte./
AnnaBridge	165:e614a9f1c9e2	216	/**
AnnaBridge	165:e614a9f1c9e2	217	* @}
AnnaBridge	165:e614a9f1c9e2	218	*/
AnnaBridge	165:e614a9f1c9e2	219
AnnaBridge	165:e614a9f1c9e2	220	/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
AnnaBridge	165:e614a9f1c9e2	221	* @{
AnnaBridge	165:e614a9f1c9e2	222	*/
AnnaBridge	165:e614a9f1c9e2	223	#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /!< Bus is in write transfer /
AnnaBridge	165:e614a9f1c9e2	224	#define LL_I2C_DIRECTION_READ 0x00000000U /!< Bus is in read transfer /
AnnaBridge	165:e614a9f1c9e2	225	/**
AnnaBridge	165:e614a9f1c9e2	226	* @}
AnnaBridge	165:e614a9f1c9e2	227	*/
AnnaBridge	165:e614a9f1c9e2	228
AnnaBridge	165:e614a9f1c9e2	229	/**
AnnaBridge	165:e614a9f1c9e2	230	* @}
AnnaBridge	165:e614a9f1c9e2	231	*/
AnnaBridge	165:e614a9f1c9e2	232
AnnaBridge	165:e614a9f1c9e2	233	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	234	/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
AnnaBridge	165:e614a9f1c9e2	235	* @{
AnnaBridge	165:e614a9f1c9e2	236	*/
AnnaBridge	165:e614a9f1c9e2	237
AnnaBridge	165:e614a9f1c9e2	238	/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	165:e614a9f1c9e2	239	* @{
AnnaBridge	165:e614a9f1c9e2	240	*/
AnnaBridge	165:e614a9f1c9e2	241
AnnaBridge	165:e614a9f1c9e2	242	/**
AnnaBridge	165:e614a9f1c9e2	243	* @brief Write a value in I2C register
AnnaBridge	165:e614a9f1c9e2	244	* @param __INSTANCE__ I2C Instance
AnnaBridge	165:e614a9f1c9e2	245	* @param __REG__ Register to be written
AnnaBridge	165:e614a9f1c9e2	246	* @param __VALUE__ Value to be written in the register
AnnaBridge	165:e614a9f1c9e2	247	* @retval None
AnnaBridge	165:e614a9f1c9e2	248	*/
AnnaBridge	165:e614a9f1c9e2	249	#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge	165:e614a9f1c9e2	250
AnnaBridge	165:e614a9f1c9e2	251	/**
AnnaBridge	165:e614a9f1c9e2	252	* @brief Read a value in I2C register
AnnaBridge	165:e614a9f1c9e2	253	* @param __INSTANCE__ I2C Instance
AnnaBridge	165:e614a9f1c9e2	254	* @param __REG__ Register to be read
AnnaBridge	165:e614a9f1c9e2	255	* @retval Register value
AnnaBridge	165:e614a9f1c9e2	256	*/
AnnaBridge	165:e614a9f1c9e2	257	#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge	165:e614a9f1c9e2	258	/**
AnnaBridge	165:e614a9f1c9e2	259	* @}
AnnaBridge	165:e614a9f1c9e2	260	*/
AnnaBridge	165:e614a9f1c9e2	261
AnnaBridge	165:e614a9f1c9e2	262	/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
AnnaBridge	165:e614a9f1c9e2	263	* @{
AnnaBridge	165:e614a9f1c9e2	264	*/
AnnaBridge	165:e614a9f1c9e2	265
AnnaBridge	165:e614a9f1c9e2	266	/**
AnnaBridge	165:e614a9f1c9e2	267	* @brief Convert Peripheral Clock Frequency in Mhz.
AnnaBridge	165:e614a9f1c9e2	268	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	165:e614a9f1c9e2	269	* @retval Value of peripheral clock (in Mhz)
AnnaBridge	165:e614a9f1c9e2	270	*/
AnnaBridge	165:e614a9f1c9e2	271	#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
AnnaBridge	165:e614a9f1c9e2	272
AnnaBridge	165:e614a9f1c9e2	273	/**
AnnaBridge	165:e614a9f1c9e2	274	* @brief Convert Peripheral Clock Frequency in Hz.
AnnaBridge	165:e614a9f1c9e2	275	* @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge	165:e614a9f1c9e2	276	* @retval Value of peripheral clock (in Hz)
AnnaBridge	165:e614a9f1c9e2	277	*/
AnnaBridge	165:e614a9f1c9e2	278	#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
AnnaBridge	165:e614a9f1c9e2	279
AnnaBridge	165:e614a9f1c9e2	280	/**
AnnaBridge	165:e614a9f1c9e2	281	* @brief Compute I2C Clock rising time.
AnnaBridge	165:e614a9f1c9e2	282	* @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge	165:e614a9f1c9e2	283	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	165:e614a9f1c9e2	284	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge	165:e614a9f1c9e2	285	*/
AnnaBridge	165:e614a9f1c9e2	286	#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
AnnaBridge	165:e614a9f1c9e2	287
AnnaBridge	165:e614a9f1c9e2	288	/**
AnnaBridge	165:e614a9f1c9e2	289	* @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	165:e614a9f1c9e2	290	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	165:e614a9f1c9e2	291	* @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	165:e614a9f1c9e2	292	* @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	293	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	165:e614a9f1c9e2	294	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	165:e614a9f1c9e2	295	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	165:e614a9f1c9e2	296	*/
AnnaBridge	165:e614a9f1c9e2	297	#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
AnnaBridge	165:e614a9f1c9e2	298	(__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
AnnaBridge	165:e614a9f1c9e2	299	(__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
AnnaBridge	165:e614a9f1c9e2	300
AnnaBridge	165:e614a9f1c9e2	301	/**
AnnaBridge	165:e614a9f1c9e2	302	* @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	165:e614a9f1c9e2	303	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	165:e614a9f1c9e2	304	* @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
AnnaBridge	165:e614a9f1c9e2	305	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
AnnaBridge	165:e614a9f1c9e2	306	*/
AnnaBridge	165:e614a9f1c9e2	307	#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
AnnaBridge	165:e614a9f1c9e2	308
AnnaBridge	165:e614a9f1c9e2	309	/**
AnnaBridge	165:e614a9f1c9e2	310	* @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge	165:e614a9f1c9e2	311	* @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge	165:e614a9f1c9e2	312	* @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
AnnaBridge	165:e614a9f1c9e2	313	* @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	314	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	165:e614a9f1c9e2	315	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	165:e614a9f1c9e2	316	* @retval Value between Min_Data=0x001 and Max_Data=0xFFF
AnnaBridge	165:e614a9f1c9e2	317	*/
AnnaBridge	165:e614a9f1c9e2	318	#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
AnnaBridge	165:e614a9f1c9e2	319	(((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
AnnaBridge	165:e614a9f1c9e2	320	(((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
AnnaBridge	165:e614a9f1c9e2	321
AnnaBridge	165:e614a9f1c9e2	322	/**
AnnaBridge	165:e614a9f1c9e2	323	* @brief Get the Least significant bits of a 10-Bits address.
AnnaBridge	165:e614a9f1c9e2	324	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	165:e614a9f1c9e2	325	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	326	*/
AnnaBridge	165:e614a9f1c9e2	327	#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
AnnaBridge	165:e614a9f1c9e2	328
AnnaBridge	165:e614a9f1c9e2	329	/**
AnnaBridge	165:e614a9f1c9e2	330	* @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
AnnaBridge	165:e614a9f1c9e2	331	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	165:e614a9f1c9e2	332	* @retval Value between Min_Data=0xF0 and Max_Data=0xF6
AnnaBridge	165:e614a9f1c9e2	333	*/
AnnaBridge	165:e614a9f1c9e2	334	#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF0))))
AnnaBridge	165:e614a9f1c9e2	335
AnnaBridge	165:e614a9f1c9e2	336	/**
AnnaBridge	165:e614a9f1c9e2	337	* @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
AnnaBridge	165:e614a9f1c9e2	338	* @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge	165:e614a9f1c9e2	339	* @retval Value between Min_Data=0xF1 and Max_Data=0xF7
AnnaBridge	165:e614a9f1c9e2	340	*/
AnnaBridge	165:e614a9f1c9e2	341	#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) \| (uint16_t)(0xF1))))
AnnaBridge	165:e614a9f1c9e2	342
AnnaBridge	165:e614a9f1c9e2	343	/**
AnnaBridge	165:e614a9f1c9e2	344	* @}
AnnaBridge	165:e614a9f1c9e2	345	*/
AnnaBridge	165:e614a9f1c9e2	346
AnnaBridge	165:e614a9f1c9e2	347	/**
AnnaBridge	165:e614a9f1c9e2	348	* @}
AnnaBridge	165:e614a9f1c9e2	349	*/
AnnaBridge	165:e614a9f1c9e2	350
AnnaBridge	165:e614a9f1c9e2	351	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:e614a9f1c9e2	352
AnnaBridge	165:e614a9f1c9e2	353	/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
AnnaBridge	165:e614a9f1c9e2	354	* @{
AnnaBridge	165:e614a9f1c9e2	355	*/
AnnaBridge	165:e614a9f1c9e2	356
AnnaBridge	165:e614a9f1c9e2	357	/** @defgroup I2C_LL_EF_Configuration Configuration
AnnaBridge	165:e614a9f1c9e2	358	* @{
AnnaBridge	165:e614a9f1c9e2	359	*/
AnnaBridge	165:e614a9f1c9e2	360
AnnaBridge	165:e614a9f1c9e2	361	/**
AnnaBridge	165:e614a9f1c9e2	362	* @brief Enable I2C peripheral (PE = 1).
AnnaBridge	165:e614a9f1c9e2	363	* @rmtoll CR1 PE LL_I2C_Enable
AnnaBridge	165:e614a9f1c9e2	364	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	365	* @retval None
AnnaBridge	165:e614a9f1c9e2	366	*/
AnnaBridge	165:e614a9f1c9e2	367	__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	368	{
AnnaBridge	165:e614a9f1c9e2	369	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	165:e614a9f1c9e2	370	}
AnnaBridge	165:e614a9f1c9e2	371
AnnaBridge	165:e614a9f1c9e2	372	/**
AnnaBridge	165:e614a9f1c9e2	373	* @brief Disable I2C peripheral (PE = 0).
AnnaBridge	165:e614a9f1c9e2	374	* @rmtoll CR1 PE LL_I2C_Disable
AnnaBridge	165:e614a9f1c9e2	375	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	376	* @retval None
AnnaBridge	165:e614a9f1c9e2	377	*/
AnnaBridge	165:e614a9f1c9e2	378	__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	379	{
AnnaBridge	165:e614a9f1c9e2	380	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	165:e614a9f1c9e2	381	}
AnnaBridge	165:e614a9f1c9e2	382
AnnaBridge	165:e614a9f1c9e2	383	/**
AnnaBridge	165:e614a9f1c9e2	384	* @brief Check if the I2C peripheral is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	385	* @rmtoll CR1 PE LL_I2C_IsEnabled
AnnaBridge	165:e614a9f1c9e2	386	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	387	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	388	*/
AnnaBridge	165:e614a9f1c9e2	389	__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	390	{
AnnaBridge	165:e614a9f1c9e2	391	return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
AnnaBridge	165:e614a9f1c9e2	392	}
AnnaBridge	165:e614a9f1c9e2	393
AnnaBridge	165:e614a9f1c9e2	394
AnnaBridge	165:e614a9f1c9e2	395	/**
AnnaBridge	165:e614a9f1c9e2	396	* @brief Enable DMA transmission requests.
AnnaBridge	165:e614a9f1c9e2	397	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	398	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	399	* @retval None
AnnaBridge	165:e614a9f1c9e2	400	*/
AnnaBridge	165:e614a9f1c9e2	401	__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	402	{
AnnaBridge	165:e614a9f1c9e2	403	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	165:e614a9f1c9e2	404	}
AnnaBridge	165:e614a9f1c9e2	405
AnnaBridge	165:e614a9f1c9e2	406	/**
AnnaBridge	165:e614a9f1c9e2	407	* @brief Disable DMA transmission requests.
AnnaBridge	165:e614a9f1c9e2	408	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	409	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	410	* @retval None
AnnaBridge	165:e614a9f1c9e2	411	*/
AnnaBridge	165:e614a9f1c9e2	412	__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	413	{
AnnaBridge	165:e614a9f1c9e2	414	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	165:e614a9f1c9e2	415	}
AnnaBridge	165:e614a9f1c9e2	416
AnnaBridge	165:e614a9f1c9e2	417	/**
AnnaBridge	165:e614a9f1c9e2	418	* @brief Check if DMA transmission requests are enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	419	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
AnnaBridge	165:e614a9f1c9e2	420	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	421	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	422	*/
AnnaBridge	165:e614a9f1c9e2	423	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	424	{
AnnaBridge	165:e614a9f1c9e2	425	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge	165:e614a9f1c9e2	426	}
AnnaBridge	165:e614a9f1c9e2	427
AnnaBridge	165:e614a9f1c9e2	428	/**
AnnaBridge	165:e614a9f1c9e2	429	* @brief Enable DMA reception requests.
AnnaBridge	165:e614a9f1c9e2	430	* @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	431	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	432	* @retval None
AnnaBridge	165:e614a9f1c9e2	433	*/
AnnaBridge	165:e614a9f1c9e2	434	__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	435	{
AnnaBridge	165:e614a9f1c9e2	436	SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	165:e614a9f1c9e2	437	}
AnnaBridge	165:e614a9f1c9e2	438
AnnaBridge	165:e614a9f1c9e2	439	/**
AnnaBridge	165:e614a9f1c9e2	440	* @brief Disable DMA reception requests.
AnnaBridge	165:e614a9f1c9e2	441	* @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	442	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	443	* @retval None
AnnaBridge	165:e614a9f1c9e2	444	*/
AnnaBridge	165:e614a9f1c9e2	445	__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	446	{
AnnaBridge	165:e614a9f1c9e2	447	CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge	165:e614a9f1c9e2	448	}
AnnaBridge	165:e614a9f1c9e2	449
AnnaBridge	165:e614a9f1c9e2	450	/**
AnnaBridge	165:e614a9f1c9e2	451	* @brief Check if DMA reception requests are enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	452	* @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
AnnaBridge	165:e614a9f1c9e2	453	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	454	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	455	*/
AnnaBridge	165:e614a9f1c9e2	456	__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	457	{
AnnaBridge	165:e614a9f1c9e2	458	return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge	165:e614a9f1c9e2	459	}
AnnaBridge	165:e614a9f1c9e2	460
AnnaBridge	165:e614a9f1c9e2	461	/**
AnnaBridge	165:e614a9f1c9e2	462	* @brief Get the data register address used for DMA transfer.
AnnaBridge	165:e614a9f1c9e2	463	* @rmtoll DR DR LL_I2C_DMA_GetRegAddr
AnnaBridge	165:e614a9f1c9e2	464	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	465	* @retval Address of data register
AnnaBridge	165:e614a9f1c9e2	466	*/
AnnaBridge	165:e614a9f1c9e2	467	__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	468	{
AnnaBridge	165:e614a9f1c9e2	469	return (uint32_t) & (I2Cx->DR);
AnnaBridge	165:e614a9f1c9e2	470	}
AnnaBridge	165:e614a9f1c9e2	471
AnnaBridge	165:e614a9f1c9e2	472	/**
AnnaBridge	165:e614a9f1c9e2	473	* @brief Enable Clock stretching.
AnnaBridge	165:e614a9f1c9e2	474	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	165:e614a9f1c9e2	475	* @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
AnnaBridge	165:e614a9f1c9e2	476	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	477	* @retval None
AnnaBridge	165:e614a9f1c9e2	478	*/
AnnaBridge	165:e614a9f1c9e2	479	__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	480	{
AnnaBridge	165:e614a9f1c9e2	481	CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge	165:e614a9f1c9e2	482	}
AnnaBridge	165:e614a9f1c9e2	483
AnnaBridge	165:e614a9f1c9e2	484	/**
AnnaBridge	165:e614a9f1c9e2	485	* @brief Disable Clock stretching.
AnnaBridge	165:e614a9f1c9e2	486	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	165:e614a9f1c9e2	487	* @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
AnnaBridge	165:e614a9f1c9e2	488	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	489	* @retval None
AnnaBridge	165:e614a9f1c9e2	490	*/
AnnaBridge	165:e614a9f1c9e2	491	__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	492	{
AnnaBridge	165:e614a9f1c9e2	493	SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge	165:e614a9f1c9e2	494	}
AnnaBridge	165:e614a9f1c9e2	495
AnnaBridge	165:e614a9f1c9e2	496	/**
AnnaBridge	165:e614a9f1c9e2	497	* @brief Check if Clock stretching is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	498	* @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
AnnaBridge	165:e614a9f1c9e2	499	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	500	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	501	*/
AnnaBridge	165:e614a9f1c9e2	502	__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	503	{
AnnaBridge	165:e614a9f1c9e2	504	return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
AnnaBridge	165:e614a9f1c9e2	505	}
AnnaBridge	165:e614a9f1c9e2	506
AnnaBridge	165:e614a9f1c9e2	507	/**
AnnaBridge	165:e614a9f1c9e2	508	* @brief Enable General Call.
AnnaBridge	165:e614a9f1c9e2	509	* @note When enabled the Address 0x00 is ACKed.
AnnaBridge	165:e614a9f1c9e2	510	* @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
AnnaBridge	165:e614a9f1c9e2	511	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	512	* @retval None
AnnaBridge	165:e614a9f1c9e2	513	*/
AnnaBridge	165:e614a9f1c9e2	514	__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	515	{
AnnaBridge	165:e614a9f1c9e2	516	SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge	165:e614a9f1c9e2	517	}
AnnaBridge	165:e614a9f1c9e2	518
AnnaBridge	165:e614a9f1c9e2	519	/**
AnnaBridge	165:e614a9f1c9e2	520	* @brief Disable General Call.
AnnaBridge	165:e614a9f1c9e2	521	* @note When disabled the Address 0x00 is NACKed.
AnnaBridge	165:e614a9f1c9e2	522	* @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
AnnaBridge	165:e614a9f1c9e2	523	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	524	* @retval None
AnnaBridge	165:e614a9f1c9e2	525	*/
AnnaBridge	165:e614a9f1c9e2	526	__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	527	{
AnnaBridge	165:e614a9f1c9e2	528	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge	165:e614a9f1c9e2	529	}
AnnaBridge	165:e614a9f1c9e2	530
AnnaBridge	165:e614a9f1c9e2	531	/**
AnnaBridge	165:e614a9f1c9e2	532	* @brief Check if General Call is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	533	* @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
AnnaBridge	165:e614a9f1c9e2	534	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	535	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	536	*/
AnnaBridge	165:e614a9f1c9e2	537	__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	538	{
AnnaBridge	165:e614a9f1c9e2	539	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
AnnaBridge	165:e614a9f1c9e2	540	}
AnnaBridge	165:e614a9f1c9e2	541
AnnaBridge	165:e614a9f1c9e2	542	/**
AnnaBridge	165:e614a9f1c9e2	543	* @brief Set the Own Address1.
AnnaBridge	165:e614a9f1c9e2	544	* @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
AnnaBridge	165:e614a9f1c9e2	545	* OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
AnnaBridge	165:e614a9f1c9e2	546	* OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
AnnaBridge	165:e614a9f1c9e2	547	* OAR1 ADDMODE LL_I2C_SetOwnAddress1
AnnaBridge	165:e614a9f1c9e2	548	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	549	* @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
AnnaBridge	165:e614a9f1c9e2	550	* @param OwnAddrSize This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	551	* @arg @ref LL_I2C_OWNADDRESS1_7BIT
AnnaBridge	165:e614a9f1c9e2	552	* @arg @ref LL_I2C_OWNADDRESS1_10BIT
AnnaBridge	165:e614a9f1c9e2	553	* @retval None
AnnaBridge	165:e614a9f1c9e2	554	*/
AnnaBridge	165:e614a9f1c9e2	555	__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
AnnaBridge	165:e614a9f1c9e2	556	{
AnnaBridge	165:e614a9f1c9e2	557	MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 \| I2C_OAR1_ADD1_7 \| I2C_OAR1_ADD8_9 \| I2C_OAR1_ADDMODE, OwnAddress1 \| OwnAddrSize);
AnnaBridge	165:e614a9f1c9e2	558	}
AnnaBridge	165:e614a9f1c9e2	559
AnnaBridge	165:e614a9f1c9e2	560	/**
AnnaBridge	165:e614a9f1c9e2	561	* @brief Set the 7bits Own Address2.
AnnaBridge	165:e614a9f1c9e2	562	* @note This action has no effect if own address2 is enabled.
AnnaBridge	165:e614a9f1c9e2	563	* @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
AnnaBridge	165:e614a9f1c9e2	564	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	565	* @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
AnnaBridge	165:e614a9f1c9e2	566	* @retval None
AnnaBridge	165:e614a9f1c9e2	567	*/
AnnaBridge	165:e614a9f1c9e2	568	__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
AnnaBridge	165:e614a9f1c9e2	569	{
AnnaBridge	165:e614a9f1c9e2	570	MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
AnnaBridge	165:e614a9f1c9e2	571	}
AnnaBridge	165:e614a9f1c9e2	572
AnnaBridge	165:e614a9f1c9e2	573	/**
AnnaBridge	165:e614a9f1c9e2	574	* @brief Enable acknowledge on Own Address2 match address.
AnnaBridge	165:e614a9f1c9e2	575	* @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
AnnaBridge	165:e614a9f1c9e2	576	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	577	* @retval None
AnnaBridge	165:e614a9f1c9e2	578	*/
AnnaBridge	165:e614a9f1c9e2	579	__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	580	{
AnnaBridge	165:e614a9f1c9e2	581	SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge	165:e614a9f1c9e2	582	}
AnnaBridge	165:e614a9f1c9e2	583
AnnaBridge	165:e614a9f1c9e2	584	/**
AnnaBridge	165:e614a9f1c9e2	585	* @brief Disable acknowledge on Own Address2 match address.
AnnaBridge	165:e614a9f1c9e2	586	* @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
AnnaBridge	165:e614a9f1c9e2	587	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	588	* @retval None
AnnaBridge	165:e614a9f1c9e2	589	*/
AnnaBridge	165:e614a9f1c9e2	590	__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	591	{
AnnaBridge	165:e614a9f1c9e2	592	CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge	165:e614a9f1c9e2	593	}
AnnaBridge	165:e614a9f1c9e2	594
AnnaBridge	165:e614a9f1c9e2	595	/**
AnnaBridge	165:e614a9f1c9e2	596	* @brief Check if Own Address1 acknowledge is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	597	* @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
AnnaBridge	165:e614a9f1c9e2	598	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	599	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	600	*/
AnnaBridge	165:e614a9f1c9e2	601	__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	602	{
AnnaBridge	165:e614a9f1c9e2	603	return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
AnnaBridge	165:e614a9f1c9e2	604	}
AnnaBridge	165:e614a9f1c9e2	605
AnnaBridge	165:e614a9f1c9e2	606	/**
AnnaBridge	165:e614a9f1c9e2	607	* @brief Configure the Peripheral clock frequency.
AnnaBridge	165:e614a9f1c9e2	608	* @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
AnnaBridge	165:e614a9f1c9e2	609	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	610	* @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge	165:e614a9f1c9e2	611	* @retval None
AnnaBridge	165:e614a9f1c9e2	612	*/
AnnaBridge	165:e614a9f1c9e2	613	__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
AnnaBridge	165:e614a9f1c9e2	614	{
AnnaBridge	165:e614a9f1c9e2	615	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
AnnaBridge	165:e614a9f1c9e2	616	}
AnnaBridge	165:e614a9f1c9e2	617
AnnaBridge	165:e614a9f1c9e2	618	/**
AnnaBridge	165:e614a9f1c9e2	619	* @brief Get the Peripheral clock frequency.
AnnaBridge	165:e614a9f1c9e2	620	* @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
AnnaBridge	165:e614a9f1c9e2	621	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	622	* @retval Value of Peripheral Clock (in Hz)
AnnaBridge	165:e614a9f1c9e2	623	*/
AnnaBridge	165:e614a9f1c9e2	624	__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	625	{
AnnaBridge	165:e614a9f1c9e2	626	return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
AnnaBridge	165:e614a9f1c9e2	627	}
AnnaBridge	165:e614a9f1c9e2	628
AnnaBridge	165:e614a9f1c9e2	629	/**
AnnaBridge	165:e614a9f1c9e2	630	* @brief Configure the Duty cycle (Fast mode only).
AnnaBridge	165:e614a9f1c9e2	631	* @rmtoll CCR DUTY LL_I2C_SetDutyCycle
AnnaBridge	165:e614a9f1c9e2	632	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	633	* @param DutyCycle This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	634	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	165:e614a9f1c9e2	635	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	165:e614a9f1c9e2	636	* @retval None
AnnaBridge	165:e614a9f1c9e2	637	*/
AnnaBridge	165:e614a9f1c9e2	638	__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
AnnaBridge	165:e614a9f1c9e2	639	{
AnnaBridge	165:e614a9f1c9e2	640	MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
AnnaBridge	165:e614a9f1c9e2	641	}
AnnaBridge	165:e614a9f1c9e2	642
AnnaBridge	165:e614a9f1c9e2	643	/**
AnnaBridge	165:e614a9f1c9e2	644	* @brief Get the Duty cycle (Fast mode only).
AnnaBridge	165:e614a9f1c9e2	645	* @rmtoll CCR DUTY LL_I2C_GetDutyCycle
AnnaBridge	165:e614a9f1c9e2	646	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	647	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	648	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	165:e614a9f1c9e2	649	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	165:e614a9f1c9e2	650	*/
AnnaBridge	165:e614a9f1c9e2	651	__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	652	{
AnnaBridge	165:e614a9f1c9e2	653	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
AnnaBridge	165:e614a9f1c9e2	654	}
AnnaBridge	165:e614a9f1c9e2	655
AnnaBridge	165:e614a9f1c9e2	656	/**
AnnaBridge	165:e614a9f1c9e2	657	* @brief Configure the I2C master clock speed mode.
AnnaBridge	165:e614a9f1c9e2	658	* @rmtoll CCR FS LL_I2C_SetClockSpeedMode
AnnaBridge	165:e614a9f1c9e2	659	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	660	* @param ClockSpeedMode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	661	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge	165:e614a9f1c9e2	662	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge	165:e614a9f1c9e2	663	* @retval None
AnnaBridge	165:e614a9f1c9e2	664	*/
AnnaBridge	165:e614a9f1c9e2	665	__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
AnnaBridge	165:e614a9f1c9e2	666	{
AnnaBridge	165:e614a9f1c9e2	667	MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
AnnaBridge	165:e614a9f1c9e2	668	}
AnnaBridge	165:e614a9f1c9e2	669
AnnaBridge	165:e614a9f1c9e2	670	/**
AnnaBridge	165:e614a9f1c9e2	671	* @brief Get the the I2C master speed mode.
AnnaBridge	165:e614a9f1c9e2	672	* @rmtoll CCR FS LL_I2C_GetClockSpeedMode
AnnaBridge	165:e614a9f1c9e2	673	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	674	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	675	* @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge	165:e614a9f1c9e2	676	* @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge	165:e614a9f1c9e2	677	*/
AnnaBridge	165:e614a9f1c9e2	678	__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	679	{
AnnaBridge	165:e614a9f1c9e2	680	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
AnnaBridge	165:e614a9f1c9e2	681	}
AnnaBridge	165:e614a9f1c9e2	682
AnnaBridge	165:e614a9f1c9e2	683	/**
AnnaBridge	165:e614a9f1c9e2	684	* @brief Configure the SCL, SDA rising time.
AnnaBridge	165:e614a9f1c9e2	685	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	165:e614a9f1c9e2	686	* @rmtoll TRISE TRISE LL_I2C_SetRiseTime
AnnaBridge	165:e614a9f1c9e2	687	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	688	* @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
AnnaBridge	165:e614a9f1c9e2	689	* @retval None
AnnaBridge	165:e614a9f1c9e2	690	*/
AnnaBridge	165:e614a9f1c9e2	691	__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
AnnaBridge	165:e614a9f1c9e2	692	{
AnnaBridge	165:e614a9f1c9e2	693	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
AnnaBridge	165:e614a9f1c9e2	694	}
AnnaBridge	165:e614a9f1c9e2	695
AnnaBridge	165:e614a9f1c9e2	696	/**
AnnaBridge	165:e614a9f1c9e2	697	* @brief Get the SCL, SDA rising time.
AnnaBridge	165:e614a9f1c9e2	698	* @rmtoll TRISE TRISE LL_I2C_GetRiseTime
AnnaBridge	165:e614a9f1c9e2	699	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	700	* @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge	165:e614a9f1c9e2	701	*/
AnnaBridge	165:e614a9f1c9e2	702	__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	703	{
AnnaBridge	165:e614a9f1c9e2	704	return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
AnnaBridge	165:e614a9f1c9e2	705	}
AnnaBridge	165:e614a9f1c9e2	706
AnnaBridge	165:e614a9f1c9e2	707	/**
AnnaBridge	165:e614a9f1c9e2	708	* @brief Configure the SCL high and low period.
AnnaBridge	165:e614a9f1c9e2	709	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	165:e614a9f1c9e2	710	* @rmtoll CCR CCR LL_I2C_SetClockPeriod
AnnaBridge	165:e614a9f1c9e2	711	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	712	* @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	165:e614a9f1c9e2	713	* @retval None
AnnaBridge	165:e614a9f1c9e2	714	*/
AnnaBridge	165:e614a9f1c9e2	715	__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
AnnaBridge	165:e614a9f1c9e2	716	{
AnnaBridge	165:e614a9f1c9e2	717	MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
AnnaBridge	165:e614a9f1c9e2	718	}
AnnaBridge	165:e614a9f1c9e2	719
AnnaBridge	165:e614a9f1c9e2	720	/**
AnnaBridge	165:e614a9f1c9e2	721	* @brief Get the SCL high and low period.
AnnaBridge	165:e614a9f1c9e2	722	* @rmtoll CCR CCR LL_I2C_GetClockPeriod
AnnaBridge	165:e614a9f1c9e2	723	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	724	* @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge	165:e614a9f1c9e2	725	*/
AnnaBridge	165:e614a9f1c9e2	726	__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	727	{
AnnaBridge	165:e614a9f1c9e2	728	return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
AnnaBridge	165:e614a9f1c9e2	729	}
AnnaBridge	165:e614a9f1c9e2	730
AnnaBridge	165:e614a9f1c9e2	731	/**
AnnaBridge	165:e614a9f1c9e2	732	* @brief Configure the SCL speed.
AnnaBridge	165:e614a9f1c9e2	733	* @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge	165:e614a9f1c9e2	734	* @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
AnnaBridge	165:e614a9f1c9e2	735	* TRISE TRISE LL_I2C_ConfigSpeed\n
AnnaBridge	165:e614a9f1c9e2	736	* CCR FS LL_I2C_ConfigSpeed\n
AnnaBridge	165:e614a9f1c9e2	737	* CCR DUTY LL_I2C_ConfigSpeed\n
AnnaBridge	165:e614a9f1c9e2	738	* CCR CCR LL_I2C_ConfigSpeed
AnnaBridge	165:e614a9f1c9e2	739	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	740	* @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge	165:e614a9f1c9e2	741	* @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge	165:e614a9f1c9e2	742	* @param DutyCycle This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	743	* @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge	165:e614a9f1c9e2	744	* @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge	165:e614a9f1c9e2	745	* @retval None
AnnaBridge	165:e614a9f1c9e2	746	*/
AnnaBridge	165:e614a9f1c9e2	747	__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
AnnaBridge	165:e614a9f1c9e2	748	uint32_t DutyCycle)
AnnaBridge	165:e614a9f1c9e2	749	{
AnnaBridge	165:e614a9f1c9e2	750	register uint32_t freqrange = 0x0U;
AnnaBridge	165:e614a9f1c9e2	751	register uint32_t clockconfig = 0x0U;
AnnaBridge	165:e614a9f1c9e2	752
AnnaBridge	165:e614a9f1c9e2	753	/* Compute frequency range */
AnnaBridge	165:e614a9f1c9e2	754	freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
AnnaBridge	165:e614a9f1c9e2	755
AnnaBridge	165:e614a9f1c9e2	756	/* Configure I2Cx: Frequency range register */
AnnaBridge	165:e614a9f1c9e2	757	MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
AnnaBridge	165:e614a9f1c9e2	758
AnnaBridge	165:e614a9f1c9e2	759	/* Configure I2Cx: Rise Time register */
AnnaBridge	165:e614a9f1c9e2	760	MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
AnnaBridge	165:e614a9f1c9e2	761
AnnaBridge	165:e614a9f1c9e2	762	/* Configure Speed mode, Duty Cycle and Clock control register value */
AnnaBridge	165:e614a9f1c9e2	763	if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
AnnaBridge	165:e614a9f1c9e2	764	{
AnnaBridge	165:e614a9f1c9e2	765	/* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
AnnaBridge	165:e614a9f1c9e2	766	clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE \| \
AnnaBridge	165:e614a9f1c9e2	767	__LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) \| \
AnnaBridge	165:e614a9f1c9e2	768	DutyCycle;
AnnaBridge	165:e614a9f1c9e2	769	}
AnnaBridge	165:e614a9f1c9e2	770	else
AnnaBridge	165:e614a9f1c9e2	771	{
AnnaBridge	165:e614a9f1c9e2	772	/* Set Speed mode at standard for Clock Speed request in standard clock range */
AnnaBridge	165:e614a9f1c9e2	773	clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE \| \
AnnaBridge	165:e614a9f1c9e2	774	__LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
AnnaBridge	165:e614a9f1c9e2	775	}
AnnaBridge	165:e614a9f1c9e2	776
AnnaBridge	165:e614a9f1c9e2	777	/* Configure I2Cx: Clock control register */
AnnaBridge	165:e614a9f1c9e2	778	MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS \| I2C_CCR_DUTY \| I2C_CCR_CCR), clockconfig);
AnnaBridge	165:e614a9f1c9e2	779	}
AnnaBridge	165:e614a9f1c9e2	780
AnnaBridge	165:e614a9f1c9e2	781	/**
AnnaBridge	165:e614a9f1c9e2	782	* @brief Configure peripheral mode.
AnnaBridge	165:e614a9f1c9e2	783	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	784	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	785	* @rmtoll CR1 SMBUS LL_I2C_SetMode\n
AnnaBridge	165:e614a9f1c9e2	786	* CR1 SMBTYPE LL_I2C_SetMode\n
AnnaBridge	165:e614a9f1c9e2	787	* CR1 ENARP LL_I2C_SetMode
AnnaBridge	165:e614a9f1c9e2	788	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	789	* @param PeripheralMode This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	790	* @arg @ref LL_I2C_MODE_I2C
AnnaBridge	165:e614a9f1c9e2	791	* @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge	165:e614a9f1c9e2	792	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge	165:e614a9f1c9e2	793	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge	165:e614a9f1c9e2	794	* @retval None
AnnaBridge	165:e614a9f1c9e2	795	*/
AnnaBridge	165:e614a9f1c9e2	796	__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
AnnaBridge	165:e614a9f1c9e2	797	{
AnnaBridge	165:e614a9f1c9e2	798	MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP, PeripheralMode);
AnnaBridge	165:e614a9f1c9e2	799	}
AnnaBridge	165:e614a9f1c9e2	800
AnnaBridge	165:e614a9f1c9e2	801	/**
AnnaBridge	165:e614a9f1c9e2	802	* @brief Get peripheral mode.
AnnaBridge	165:e614a9f1c9e2	803	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	804	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	805	* @rmtoll CR1 SMBUS LL_I2C_GetMode\n
AnnaBridge	165:e614a9f1c9e2	806	* CR1 SMBTYPE LL_I2C_GetMode\n
AnnaBridge	165:e614a9f1c9e2	807	* CR1 ENARP LL_I2C_GetMode
AnnaBridge	165:e614a9f1c9e2	808	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	809	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	810	* @arg @ref LL_I2C_MODE_I2C
AnnaBridge	165:e614a9f1c9e2	811	* @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge	165:e614a9f1c9e2	812	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge	165:e614a9f1c9e2	813	* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge	165:e614a9f1c9e2	814	*/
AnnaBridge	165:e614a9f1c9e2	815	__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	816	{
AnnaBridge	165:e614a9f1c9e2	817	return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS \| I2C_CR1_SMBTYPE \| I2C_CR1_ENARP));
AnnaBridge	165:e614a9f1c9e2	818	}
AnnaBridge	165:e614a9f1c9e2	819
AnnaBridge	165:e614a9f1c9e2	820	/**
AnnaBridge	165:e614a9f1c9e2	821	* @brief Enable SMBus alert (Host or Device mode)
AnnaBridge	165:e614a9f1c9e2	822	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	823	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	824	* @note SMBus Device mode:
AnnaBridge	165:e614a9f1c9e2	825	* - SMBus Alert pin is drived low and
AnnaBridge	165:e614a9f1c9e2	826	* Alert Response Address Header acknowledge is enabled.
AnnaBridge	165:e614a9f1c9e2	827	* SMBus Host mode:
AnnaBridge	165:e614a9f1c9e2	828	* - SMBus Alert pin management is supported.
AnnaBridge	165:e614a9f1c9e2	829	* @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
AnnaBridge	165:e614a9f1c9e2	830	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	831	* @retval None
AnnaBridge	165:e614a9f1c9e2	832	*/
AnnaBridge	165:e614a9f1c9e2	833	__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	834	{
AnnaBridge	165:e614a9f1c9e2	835	SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge	165:e614a9f1c9e2	836	}
AnnaBridge	165:e614a9f1c9e2	837
AnnaBridge	165:e614a9f1c9e2	838	/**
AnnaBridge	165:e614a9f1c9e2	839	* @brief Disable SMBus alert (Host or Device mode)
AnnaBridge	165:e614a9f1c9e2	840	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	841	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	842	* @note SMBus Device mode:
AnnaBridge	165:e614a9f1c9e2	843	* - SMBus Alert pin is not drived (can be used as a standard GPIO) and
AnnaBridge	165:e614a9f1c9e2	844	* Alert Response Address Header acknowledge is disabled.
AnnaBridge	165:e614a9f1c9e2	845	* SMBus Host mode:
AnnaBridge	165:e614a9f1c9e2	846	* - SMBus Alert pin management is not supported.
AnnaBridge	165:e614a9f1c9e2	847	* @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
AnnaBridge	165:e614a9f1c9e2	848	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	849	* @retval None
AnnaBridge	165:e614a9f1c9e2	850	*/
AnnaBridge	165:e614a9f1c9e2	851	__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	852	{
AnnaBridge	165:e614a9f1c9e2	853	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge	165:e614a9f1c9e2	854	}
AnnaBridge	165:e614a9f1c9e2	855
AnnaBridge	165:e614a9f1c9e2	856	/**
AnnaBridge	165:e614a9f1c9e2	857	* @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	858	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	859	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	860	* @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
AnnaBridge	165:e614a9f1c9e2	861	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	862	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	863	*/
AnnaBridge	165:e614a9f1c9e2	864	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	865	{
AnnaBridge	165:e614a9f1c9e2	866	return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
AnnaBridge	165:e614a9f1c9e2	867	}
AnnaBridge	165:e614a9f1c9e2	868
AnnaBridge	165:e614a9f1c9e2	869	/**
AnnaBridge	165:e614a9f1c9e2	870	* @brief Enable SMBus Packet Error Calculation (PEC).
AnnaBridge	165:e614a9f1c9e2	871	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	872	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	873	* @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
AnnaBridge	165:e614a9f1c9e2	874	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	875	* @retval None
AnnaBridge	165:e614a9f1c9e2	876	*/
AnnaBridge	165:e614a9f1c9e2	877	__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	878	{
AnnaBridge	165:e614a9f1c9e2	879	SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge	165:e614a9f1c9e2	880	}
AnnaBridge	165:e614a9f1c9e2	881
AnnaBridge	165:e614a9f1c9e2	882	/**
AnnaBridge	165:e614a9f1c9e2	883	* @brief Disable SMBus Packet Error Calculation (PEC).
AnnaBridge	165:e614a9f1c9e2	884	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	885	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	886	* @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
AnnaBridge	165:e614a9f1c9e2	887	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	888	* @retval None
AnnaBridge	165:e614a9f1c9e2	889	*/
AnnaBridge	165:e614a9f1c9e2	890	__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	891	{
AnnaBridge	165:e614a9f1c9e2	892	CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge	165:e614a9f1c9e2	893	}
AnnaBridge	165:e614a9f1c9e2	894
AnnaBridge	165:e614a9f1c9e2	895	/**
AnnaBridge	165:e614a9f1c9e2	896	* @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	897	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	898	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	899	* @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
AnnaBridge	165:e614a9f1c9e2	900	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	901	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	902	*/
AnnaBridge	165:e614a9f1c9e2	903	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	904	{
AnnaBridge	165:e614a9f1c9e2	905	return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
AnnaBridge	165:e614a9f1c9e2	906	}
AnnaBridge	165:e614a9f1c9e2	907
AnnaBridge	165:e614a9f1c9e2	908	/**
AnnaBridge	165:e614a9f1c9e2	909	* @}
AnnaBridge	165:e614a9f1c9e2	910	*/
AnnaBridge	165:e614a9f1c9e2	911
AnnaBridge	165:e614a9f1c9e2	912	/** @defgroup I2C_LL_EF_IT_Management IT_Management
AnnaBridge	165:e614a9f1c9e2	913	* @{
AnnaBridge	165:e614a9f1c9e2	914	*/
AnnaBridge	165:e614a9f1c9e2	915
AnnaBridge	165:e614a9f1c9e2	916	/**
AnnaBridge	165:e614a9f1c9e2	917	* @brief Enable TXE interrupt.
AnnaBridge	165:e614a9f1c9e2	918	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
AnnaBridge	165:e614a9f1c9e2	919	* CR2 ITBUFEN LL_I2C_EnableIT_TX
AnnaBridge	165:e614a9f1c9e2	920	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	921	* @retval None
AnnaBridge	165:e614a9f1c9e2	922	*/
AnnaBridge	165:e614a9f1c9e2	923	__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	924	{
AnnaBridge	165:e614a9f1c9e2	925	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	165:e614a9f1c9e2	926	}
AnnaBridge	165:e614a9f1c9e2	927
AnnaBridge	165:e614a9f1c9e2	928	/**
AnnaBridge	165:e614a9f1c9e2	929	* @brief Disable TXE interrupt.
AnnaBridge	165:e614a9f1c9e2	930	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
AnnaBridge	165:e614a9f1c9e2	931	* CR2 ITBUFEN LL_I2C_DisableIT_TX
AnnaBridge	165:e614a9f1c9e2	932	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	933	* @retval None
AnnaBridge	165:e614a9f1c9e2	934	*/
AnnaBridge	165:e614a9f1c9e2	935	__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	936	{
AnnaBridge	165:e614a9f1c9e2	937	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	165:e614a9f1c9e2	938	}
AnnaBridge	165:e614a9f1c9e2	939
AnnaBridge	165:e614a9f1c9e2	940	/**
AnnaBridge	165:e614a9f1c9e2	941	* @brief Check if the TXE Interrupt is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	942	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
AnnaBridge	165:e614a9f1c9e2	943	* CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
AnnaBridge	165:e614a9f1c9e2	944	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	945	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	946	*/
AnnaBridge	165:e614a9f1c9e2	947	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	948	{
AnnaBridge	165:e614a9f1c9e2	949	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
AnnaBridge	165:e614a9f1c9e2	950	}
AnnaBridge	165:e614a9f1c9e2	951
AnnaBridge	165:e614a9f1c9e2	952	/**
AnnaBridge	165:e614a9f1c9e2	953	* @brief Enable RXNE interrupt.
AnnaBridge	165:e614a9f1c9e2	954	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
AnnaBridge	165:e614a9f1c9e2	955	* CR2 ITBUFEN LL_I2C_EnableIT_RX
AnnaBridge	165:e614a9f1c9e2	956	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	957	* @retval None
AnnaBridge	165:e614a9f1c9e2	958	*/
AnnaBridge	165:e614a9f1c9e2	959	__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	960	{
AnnaBridge	165:e614a9f1c9e2	961	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	165:e614a9f1c9e2	962	}
AnnaBridge	165:e614a9f1c9e2	963
AnnaBridge	165:e614a9f1c9e2	964	/**
AnnaBridge	165:e614a9f1c9e2	965	* @brief Disable RXNE interrupt.
AnnaBridge	165:e614a9f1c9e2	966	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
AnnaBridge	165:e614a9f1c9e2	967	* CR2 ITBUFEN LL_I2C_DisableIT_RX
AnnaBridge	165:e614a9f1c9e2	968	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	969	* @retval None
AnnaBridge	165:e614a9f1c9e2	970	*/
AnnaBridge	165:e614a9f1c9e2	971	__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	972	{
AnnaBridge	165:e614a9f1c9e2	973	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN);
AnnaBridge	165:e614a9f1c9e2	974	}
AnnaBridge	165:e614a9f1c9e2	975
AnnaBridge	165:e614a9f1c9e2	976	/**
AnnaBridge	165:e614a9f1c9e2	977	* @brief Check if the RXNE Interrupt is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	978	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
AnnaBridge	165:e614a9f1c9e2	979	* CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
AnnaBridge	165:e614a9f1c9e2	980	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	981	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	982	*/
AnnaBridge	165:e614a9f1c9e2	983	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	984	{
AnnaBridge	165:e614a9f1c9e2	985	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN \| I2C_CR2_ITBUFEN));
AnnaBridge	165:e614a9f1c9e2	986	}
AnnaBridge	165:e614a9f1c9e2	987
AnnaBridge	165:e614a9f1c9e2	988	/**
AnnaBridge	165:e614a9f1c9e2	989	* @brief Enable Events interrupts.
AnnaBridge	165:e614a9f1c9e2	990	* @note Any of these events will generate interrupt :
AnnaBridge	165:e614a9f1c9e2	991	* Start Bit (SB)
AnnaBridge	165:e614a9f1c9e2	992	* Address sent, Address matched (ADDR)
AnnaBridge	165:e614a9f1c9e2	993	* 10-bit header sent (ADD10)
AnnaBridge	165:e614a9f1c9e2	994	* Stop detection (STOPF)
AnnaBridge	165:e614a9f1c9e2	995	* Byte transfer finished (BTF)
AnnaBridge	165:e614a9f1c9e2	996	*
AnnaBridge	165:e614a9f1c9e2	997	* @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
AnnaBridge	165:e614a9f1c9e2	998	* Receive buffer not empty (RXNE)
AnnaBridge	165:e614a9f1c9e2	999	* Transmit buffer empty (TXE)
AnnaBridge	165:e614a9f1c9e2	1000	* @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
AnnaBridge	165:e614a9f1c9e2	1001	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1002	* @retval None
AnnaBridge	165:e614a9f1c9e2	1003	*/
AnnaBridge	165:e614a9f1c9e2	1004	__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1005	{
AnnaBridge	165:e614a9f1c9e2	1006	SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge	165:e614a9f1c9e2	1007	}
AnnaBridge	165:e614a9f1c9e2	1008
AnnaBridge	165:e614a9f1c9e2	1009	/**
AnnaBridge	165:e614a9f1c9e2	1010	* @brief Disable Events interrupts.
AnnaBridge	165:e614a9f1c9e2	1011	* @note Any of these events will generate interrupt :
AnnaBridge	165:e614a9f1c9e2	1012	* Start Bit (SB)
AnnaBridge	165:e614a9f1c9e2	1013	* Address sent, Address matched (ADDR)
AnnaBridge	165:e614a9f1c9e2	1014	* 10-bit header sent (ADD10)
AnnaBridge	165:e614a9f1c9e2	1015	* Stop detection (STOPF)
AnnaBridge	165:e614a9f1c9e2	1016	* Byte transfer finished (BTF)
AnnaBridge	165:e614a9f1c9e2	1017	* Receive buffer not empty (RXNE)
AnnaBridge	165:e614a9f1c9e2	1018	* Transmit buffer empty (TXE)
AnnaBridge	165:e614a9f1c9e2	1019	* @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
AnnaBridge	165:e614a9f1c9e2	1020	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1021	* @retval None
AnnaBridge	165:e614a9f1c9e2	1022	*/
AnnaBridge	165:e614a9f1c9e2	1023	__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1024	{
AnnaBridge	165:e614a9f1c9e2	1025	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge	165:e614a9f1c9e2	1026	}
AnnaBridge	165:e614a9f1c9e2	1027
AnnaBridge	165:e614a9f1c9e2	1028	/**
AnnaBridge	165:e614a9f1c9e2	1029	* @brief Check if Events interrupts are enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	1030	* @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
AnnaBridge	165:e614a9f1c9e2	1031	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1032	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1033	*/
AnnaBridge	165:e614a9f1c9e2	1034	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1035	{
AnnaBridge	165:e614a9f1c9e2	1036	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
AnnaBridge	165:e614a9f1c9e2	1037	}
AnnaBridge	165:e614a9f1c9e2	1038
AnnaBridge	165:e614a9f1c9e2	1039	/**
AnnaBridge	165:e614a9f1c9e2	1040	* @brief Enable Buffer interrupts.
AnnaBridge	165:e614a9f1c9e2	1041	* @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
AnnaBridge	165:e614a9f1c9e2	1042	* Receive buffer not empty (RXNE)
AnnaBridge	165:e614a9f1c9e2	1043	* Transmit buffer empty (TXE)
AnnaBridge	165:e614a9f1c9e2	1044	* @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
AnnaBridge	165:e614a9f1c9e2	1045	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1046	* @retval None
AnnaBridge	165:e614a9f1c9e2	1047	*/
AnnaBridge	165:e614a9f1c9e2	1048	__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1049	{
AnnaBridge	165:e614a9f1c9e2	1050	SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge	165:e614a9f1c9e2	1051	}
AnnaBridge	165:e614a9f1c9e2	1052
AnnaBridge	165:e614a9f1c9e2	1053	/**
AnnaBridge	165:e614a9f1c9e2	1054	* @brief Disable Buffer interrupts.
AnnaBridge	165:e614a9f1c9e2	1055	* @note Any of these Buffer events will generate interrupt :
AnnaBridge	165:e614a9f1c9e2	1056	* Receive buffer not empty (RXNE)
AnnaBridge	165:e614a9f1c9e2	1057	* Transmit buffer empty (TXE)
AnnaBridge	165:e614a9f1c9e2	1058	* @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
AnnaBridge	165:e614a9f1c9e2	1059	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1060	* @retval None
AnnaBridge	165:e614a9f1c9e2	1061	*/
AnnaBridge	165:e614a9f1c9e2	1062	__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1063	{
AnnaBridge	165:e614a9f1c9e2	1064	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge	165:e614a9f1c9e2	1065	}
AnnaBridge	165:e614a9f1c9e2	1066
AnnaBridge	165:e614a9f1c9e2	1067	/**
AnnaBridge	165:e614a9f1c9e2	1068	* @brief Check if Buffer interrupts are enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	1069	* @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
AnnaBridge	165:e614a9f1c9e2	1070	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1071	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1072	*/
AnnaBridge	165:e614a9f1c9e2	1073	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1074	{
AnnaBridge	165:e614a9f1c9e2	1075	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
AnnaBridge	165:e614a9f1c9e2	1076	}
AnnaBridge	165:e614a9f1c9e2	1077
AnnaBridge	165:e614a9f1c9e2	1078	/**
AnnaBridge	165:e614a9f1c9e2	1079	* @brief Enable Error interrupts.
AnnaBridge	165:e614a9f1c9e2	1080	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1081	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1082	* @note Any of these errors will generate interrupt :
AnnaBridge	165:e614a9f1c9e2	1083	* Bus Error detection (BERR)
AnnaBridge	165:e614a9f1c9e2	1084	* Arbitration Loss (ARLO)
AnnaBridge	165:e614a9f1c9e2	1085	* Acknowledge Failure(AF)
AnnaBridge	165:e614a9f1c9e2	1086	* Overrun/Underrun (OVR)
AnnaBridge	165:e614a9f1c9e2	1087	* SMBus Timeout detection (TIMEOUT)
AnnaBridge	165:e614a9f1c9e2	1088	* SMBus PEC error detection (PECERR)
AnnaBridge	165:e614a9f1c9e2	1089	* SMBus Alert pin event detection (SMBALERT)
AnnaBridge	165:e614a9f1c9e2	1090	* @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
AnnaBridge	165:e614a9f1c9e2	1091	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1092	* @retval None
AnnaBridge	165:e614a9f1c9e2	1093	*/
AnnaBridge	165:e614a9f1c9e2	1094	__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1095	{
AnnaBridge	165:e614a9f1c9e2	1096	SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge	165:e614a9f1c9e2	1097	}
AnnaBridge	165:e614a9f1c9e2	1098
AnnaBridge	165:e614a9f1c9e2	1099	/**
AnnaBridge	165:e614a9f1c9e2	1100	* @brief Disable Error interrupts.
AnnaBridge	165:e614a9f1c9e2	1101	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1102	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1103	* @note Any of these errors will generate interrupt :
AnnaBridge	165:e614a9f1c9e2	1104	* Bus Error detection (BERR)
AnnaBridge	165:e614a9f1c9e2	1105	* Arbitration Loss (ARLO)
AnnaBridge	165:e614a9f1c9e2	1106	* Acknowledge Failure(AF)
AnnaBridge	165:e614a9f1c9e2	1107	* Overrun/Underrun (OVR)
AnnaBridge	165:e614a9f1c9e2	1108	* SMBus Timeout detection (TIMEOUT)
AnnaBridge	165:e614a9f1c9e2	1109	* SMBus PEC error detection (PECERR)
AnnaBridge	165:e614a9f1c9e2	1110	* SMBus Alert pin event detection (SMBALERT)
AnnaBridge	165:e614a9f1c9e2	1111	* @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
AnnaBridge	165:e614a9f1c9e2	1112	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1113	* @retval None
AnnaBridge	165:e614a9f1c9e2	1114	*/
AnnaBridge	165:e614a9f1c9e2	1115	__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1116	{
AnnaBridge	165:e614a9f1c9e2	1117	CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge	165:e614a9f1c9e2	1118	}
AnnaBridge	165:e614a9f1c9e2	1119
AnnaBridge	165:e614a9f1c9e2	1120	/**
AnnaBridge	165:e614a9f1c9e2	1121	* @brief Check if Error interrupts are enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	1122	* @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
AnnaBridge	165:e614a9f1c9e2	1123	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1124	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1125	*/
AnnaBridge	165:e614a9f1c9e2	1126	__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1127	{
AnnaBridge	165:e614a9f1c9e2	1128	return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
AnnaBridge	165:e614a9f1c9e2	1129	}
AnnaBridge	165:e614a9f1c9e2	1130
AnnaBridge	165:e614a9f1c9e2	1131	/**
AnnaBridge	165:e614a9f1c9e2	1132	* @}
AnnaBridge	165:e614a9f1c9e2	1133	*/
AnnaBridge	165:e614a9f1c9e2	1134
AnnaBridge	165:e614a9f1c9e2	1135	/** @defgroup I2C_LL_EF_FLAG_management FLAG_management
AnnaBridge	165:e614a9f1c9e2	1136	* @{
AnnaBridge	165:e614a9f1c9e2	1137	*/
AnnaBridge	165:e614a9f1c9e2	1138
AnnaBridge	165:e614a9f1c9e2	1139	/**
AnnaBridge	165:e614a9f1c9e2	1140	* @brief Indicate the status of Transmit data register empty flag.
AnnaBridge	165:e614a9f1c9e2	1141	* @note RESET: When next data is written in Transmit data register.
AnnaBridge	165:e614a9f1c9e2	1142	* SET: When Transmit data register is empty.
AnnaBridge	165:e614a9f1c9e2	1143	* @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
AnnaBridge	165:e614a9f1c9e2	1144	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1145	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1146	*/
AnnaBridge	165:e614a9f1c9e2	1147	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1148	{
AnnaBridge	165:e614a9f1c9e2	1149	return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
AnnaBridge	165:e614a9f1c9e2	1150	}
AnnaBridge	165:e614a9f1c9e2	1151
AnnaBridge	165:e614a9f1c9e2	1152	/**
AnnaBridge	165:e614a9f1c9e2	1153	* @brief Indicate the status of Byte Transfer Finished flag.
AnnaBridge	165:e614a9f1c9e2	1154	* RESET: When Data byte transfer not done.
AnnaBridge	165:e614a9f1c9e2	1155	* SET: When Data byte transfer succeeded.
AnnaBridge	165:e614a9f1c9e2	1156	* @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
AnnaBridge	165:e614a9f1c9e2	1157	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1158	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1159	*/
AnnaBridge	165:e614a9f1c9e2	1160	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1161	{
AnnaBridge	165:e614a9f1c9e2	1162	return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
AnnaBridge	165:e614a9f1c9e2	1163	}
AnnaBridge	165:e614a9f1c9e2	1164
AnnaBridge	165:e614a9f1c9e2	1165	/**
AnnaBridge	165:e614a9f1c9e2	1166	* @brief Indicate the status of Receive data register not empty flag.
AnnaBridge	165:e614a9f1c9e2	1167	* @note RESET: When Receive data register is read.
AnnaBridge	165:e614a9f1c9e2	1168	* SET: When the received data is copied in Receive data register.
AnnaBridge	165:e614a9f1c9e2	1169	* @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
AnnaBridge	165:e614a9f1c9e2	1170	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1171	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1172	*/
AnnaBridge	165:e614a9f1c9e2	1173	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1174	{
AnnaBridge	165:e614a9f1c9e2	1175	return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
AnnaBridge	165:e614a9f1c9e2	1176	}
AnnaBridge	165:e614a9f1c9e2	1177
AnnaBridge	165:e614a9f1c9e2	1178	/**
AnnaBridge	165:e614a9f1c9e2	1179	* @brief Indicate the status of Start Bit (master mode).
AnnaBridge	165:e614a9f1c9e2	1180	* @note RESET: When No Start condition.
AnnaBridge	165:e614a9f1c9e2	1181	* SET: When Start condition is generated.
AnnaBridge	165:e614a9f1c9e2	1182	* @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
AnnaBridge	165:e614a9f1c9e2	1183	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1184	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1185	*/
AnnaBridge	165:e614a9f1c9e2	1186	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1187	{
AnnaBridge	165:e614a9f1c9e2	1188	return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
AnnaBridge	165:e614a9f1c9e2	1189	}
AnnaBridge	165:e614a9f1c9e2	1190
AnnaBridge	165:e614a9f1c9e2	1191	/**
AnnaBridge	165:e614a9f1c9e2	1192	* @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
AnnaBridge	165:e614a9f1c9e2	1193	* @note RESET: Clear default value.
AnnaBridge	165:e614a9f1c9e2	1194	* SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
AnnaBridge	165:e614a9f1c9e2	1195	* @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
AnnaBridge	165:e614a9f1c9e2	1196	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1197	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1198	*/
AnnaBridge	165:e614a9f1c9e2	1199	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1200	{
AnnaBridge	165:e614a9f1c9e2	1201	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
AnnaBridge	165:e614a9f1c9e2	1202	}
AnnaBridge	165:e614a9f1c9e2	1203
AnnaBridge	165:e614a9f1c9e2	1204	/**
AnnaBridge	165:e614a9f1c9e2	1205	* @brief Indicate the status of 10-bit header sent (master mode).
AnnaBridge	165:e614a9f1c9e2	1206	* @note RESET: When no ADD10 event occured.
AnnaBridge	165:e614a9f1c9e2	1207	* SET: When the master has sent the first address byte (header).
AnnaBridge	165:e614a9f1c9e2	1208	* @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
AnnaBridge	165:e614a9f1c9e2	1209	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1210	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1211	*/
AnnaBridge	165:e614a9f1c9e2	1212	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1213	{
AnnaBridge	165:e614a9f1c9e2	1214	return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
AnnaBridge	165:e614a9f1c9e2	1215	}
AnnaBridge	165:e614a9f1c9e2	1216
AnnaBridge	165:e614a9f1c9e2	1217	/**
AnnaBridge	165:e614a9f1c9e2	1218	* @brief Indicate the status of Acknowledge failure flag.
AnnaBridge	165:e614a9f1c9e2	1219	* @note RESET: No acknowledge failure.
AnnaBridge	165:e614a9f1c9e2	1220	* SET: When an acknowledge failure is received after a byte transmission.
AnnaBridge	165:e614a9f1c9e2	1221	* @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
AnnaBridge	165:e614a9f1c9e2	1222	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1223	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1224	*/
AnnaBridge	165:e614a9f1c9e2	1225	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1226	{
AnnaBridge	165:e614a9f1c9e2	1227	return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
AnnaBridge	165:e614a9f1c9e2	1228	}
AnnaBridge	165:e614a9f1c9e2	1229
AnnaBridge	165:e614a9f1c9e2	1230	/**
AnnaBridge	165:e614a9f1c9e2	1231	* @brief Indicate the status of Stop detection flag (slave mode).
AnnaBridge	165:e614a9f1c9e2	1232	* @note RESET: Clear default value.
AnnaBridge	165:e614a9f1c9e2	1233	* SET: When a Stop condition is detected.
AnnaBridge	165:e614a9f1c9e2	1234	* @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
AnnaBridge	165:e614a9f1c9e2	1235	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1236	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1237	*/
AnnaBridge	165:e614a9f1c9e2	1238	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1239	{
AnnaBridge	165:e614a9f1c9e2	1240	return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
AnnaBridge	165:e614a9f1c9e2	1241	}
AnnaBridge	165:e614a9f1c9e2	1242
AnnaBridge	165:e614a9f1c9e2	1243	/**
AnnaBridge	165:e614a9f1c9e2	1244	* @brief Indicate the status of Bus error flag.
AnnaBridge	165:e614a9f1c9e2	1245	* @note RESET: Clear default value.
AnnaBridge	165:e614a9f1c9e2	1246	* SET: When a misplaced Start or Stop condition is detected.
AnnaBridge	165:e614a9f1c9e2	1247	* @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
AnnaBridge	165:e614a9f1c9e2	1248	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1249	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1250	*/
AnnaBridge	165:e614a9f1c9e2	1251	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1252	{
AnnaBridge	165:e614a9f1c9e2	1253	return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
AnnaBridge	165:e614a9f1c9e2	1254	}
AnnaBridge	165:e614a9f1c9e2	1255
AnnaBridge	165:e614a9f1c9e2	1256	/**
AnnaBridge	165:e614a9f1c9e2	1257	* @brief Indicate the status of Arbitration lost flag.
AnnaBridge	165:e614a9f1c9e2	1258	* @note RESET: Clear default value.
AnnaBridge	165:e614a9f1c9e2	1259	* SET: When arbitration lost.
AnnaBridge	165:e614a9f1c9e2	1260	* @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
AnnaBridge	165:e614a9f1c9e2	1261	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1262	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1263	*/
AnnaBridge	165:e614a9f1c9e2	1264	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1265	{
AnnaBridge	165:e614a9f1c9e2	1266	return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
AnnaBridge	165:e614a9f1c9e2	1267	}
AnnaBridge	165:e614a9f1c9e2	1268
AnnaBridge	165:e614a9f1c9e2	1269	/**
AnnaBridge	165:e614a9f1c9e2	1270	* @brief Indicate the status of Overrun/Underrun flag.
AnnaBridge	165:e614a9f1c9e2	1271	* @note RESET: Clear default value.
AnnaBridge	165:e614a9f1c9e2	1272	* SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
AnnaBridge	165:e614a9f1c9e2	1273	* @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
AnnaBridge	165:e614a9f1c9e2	1274	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1275	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1276	*/
AnnaBridge	165:e614a9f1c9e2	1277	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1278	{
AnnaBridge	165:e614a9f1c9e2	1279	return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
AnnaBridge	165:e614a9f1c9e2	1280	}
AnnaBridge	165:e614a9f1c9e2	1281
AnnaBridge	165:e614a9f1c9e2	1282	/**
AnnaBridge	165:e614a9f1c9e2	1283	* @brief Indicate the status of SMBus PEC error flag in reception.
AnnaBridge	165:e614a9f1c9e2	1284	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1285	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1286	* @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
AnnaBridge	165:e614a9f1c9e2	1287	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1288	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1289	*/
AnnaBridge	165:e614a9f1c9e2	1290	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1291	{
AnnaBridge	165:e614a9f1c9e2	1292	return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
AnnaBridge	165:e614a9f1c9e2	1293	}
AnnaBridge	165:e614a9f1c9e2	1294
AnnaBridge	165:e614a9f1c9e2	1295	/**
AnnaBridge	165:e614a9f1c9e2	1296	* @brief Indicate the status of SMBus Timeout detection flag.
AnnaBridge	165:e614a9f1c9e2	1297	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1298	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1299	* @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
AnnaBridge	165:e614a9f1c9e2	1300	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1301	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1302	*/
AnnaBridge	165:e614a9f1c9e2	1303	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1304	{
AnnaBridge	165:e614a9f1c9e2	1305	return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
AnnaBridge	165:e614a9f1c9e2	1306	}
AnnaBridge	165:e614a9f1c9e2	1307
AnnaBridge	165:e614a9f1c9e2	1308	/**
AnnaBridge	165:e614a9f1c9e2	1309	* @brief Indicate the status of SMBus alert flag.
AnnaBridge	165:e614a9f1c9e2	1310	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1311	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1312	* @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
AnnaBridge	165:e614a9f1c9e2	1313	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1314	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1315	*/
AnnaBridge	165:e614a9f1c9e2	1316	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1317	{
AnnaBridge	165:e614a9f1c9e2	1318	return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
AnnaBridge	165:e614a9f1c9e2	1319	}
AnnaBridge	165:e614a9f1c9e2	1320
AnnaBridge	165:e614a9f1c9e2	1321	/**
AnnaBridge	165:e614a9f1c9e2	1322	* @brief Indicate the status of Bus Busy flag.
AnnaBridge	165:e614a9f1c9e2	1323	* @note RESET: Clear default value.
AnnaBridge	165:e614a9f1c9e2	1324	* SET: When a Start condition is detected.
AnnaBridge	165:e614a9f1c9e2	1325	* @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
AnnaBridge	165:e614a9f1c9e2	1326	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1327	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1328	*/
AnnaBridge	165:e614a9f1c9e2	1329	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1330	{
AnnaBridge	165:e614a9f1c9e2	1331	return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
AnnaBridge	165:e614a9f1c9e2	1332	}
AnnaBridge	165:e614a9f1c9e2	1333
AnnaBridge	165:e614a9f1c9e2	1334	/**
AnnaBridge	165:e614a9f1c9e2	1335	* @brief Indicate the status of Dual flag.
AnnaBridge	165:e614a9f1c9e2	1336	* @note RESET: Received address matched with OAR1.
AnnaBridge	165:e614a9f1c9e2	1337	* SET: Received address matched with OAR2.
AnnaBridge	165:e614a9f1c9e2	1338	* @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
AnnaBridge	165:e614a9f1c9e2	1339	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1340	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1341	*/
AnnaBridge	165:e614a9f1c9e2	1342	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1343	{
AnnaBridge	165:e614a9f1c9e2	1344	return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
AnnaBridge	165:e614a9f1c9e2	1345	}
AnnaBridge	165:e614a9f1c9e2	1346
AnnaBridge	165:e614a9f1c9e2	1347	/**
AnnaBridge	165:e614a9f1c9e2	1348	* @brief Indicate the status of SMBus Host address reception (Slave mode).
AnnaBridge	165:e614a9f1c9e2	1349	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1350	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1351	* @note RESET: No SMBus Host address
AnnaBridge	165:e614a9f1c9e2	1352	* SET: SMBus Host address received.
AnnaBridge	165:e614a9f1c9e2	1353	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	165:e614a9f1c9e2	1354	* @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
AnnaBridge	165:e614a9f1c9e2	1355	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1356	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1357	*/
AnnaBridge	165:e614a9f1c9e2	1358	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1359	{
AnnaBridge	165:e614a9f1c9e2	1360	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
AnnaBridge	165:e614a9f1c9e2	1361	}
AnnaBridge	165:e614a9f1c9e2	1362
AnnaBridge	165:e614a9f1c9e2	1363	/**
AnnaBridge	165:e614a9f1c9e2	1364	* @brief Indicate the status of SMBus Device default address reception (Slave mode).
AnnaBridge	165:e614a9f1c9e2	1365	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1366	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1367	* @note RESET: No SMBus Device default address
AnnaBridge	165:e614a9f1c9e2	1368	* SET: SMBus Device default address received.
AnnaBridge	165:e614a9f1c9e2	1369	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	165:e614a9f1c9e2	1370	* @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
AnnaBridge	165:e614a9f1c9e2	1371	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1372	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1373	*/
AnnaBridge	165:e614a9f1c9e2	1374	__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1375	{
AnnaBridge	165:e614a9f1c9e2	1376	return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
AnnaBridge	165:e614a9f1c9e2	1377	}
AnnaBridge	165:e614a9f1c9e2	1378
AnnaBridge	165:e614a9f1c9e2	1379	/**
AnnaBridge	165:e614a9f1c9e2	1380	* @brief Indicate the status of General call address reception (Slave mode).
AnnaBridge	165:e614a9f1c9e2	1381	* @note RESET: No Generall call address
AnnaBridge	165:e614a9f1c9e2	1382	* SET: General call address received.
AnnaBridge	165:e614a9f1c9e2	1383	* @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge	165:e614a9f1c9e2	1384	* @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
AnnaBridge	165:e614a9f1c9e2	1385	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1386	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1387	*/
AnnaBridge	165:e614a9f1c9e2	1388	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1389	{
AnnaBridge	165:e614a9f1c9e2	1390	return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
AnnaBridge	165:e614a9f1c9e2	1391	}
AnnaBridge	165:e614a9f1c9e2	1392
AnnaBridge	165:e614a9f1c9e2	1393	/**
AnnaBridge	165:e614a9f1c9e2	1394	* @brief Indicate the status of Master/Slave flag.
AnnaBridge	165:e614a9f1c9e2	1395	* @note RESET: Slave Mode.
AnnaBridge	165:e614a9f1c9e2	1396	* SET: Master Mode.
AnnaBridge	165:e614a9f1c9e2	1397	* @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
AnnaBridge	165:e614a9f1c9e2	1398	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1399	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1400	*/
AnnaBridge	165:e614a9f1c9e2	1401	__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1402	{
AnnaBridge	165:e614a9f1c9e2	1403	return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
AnnaBridge	165:e614a9f1c9e2	1404	}
AnnaBridge	165:e614a9f1c9e2	1405
AnnaBridge	165:e614a9f1c9e2	1406	/**
AnnaBridge	165:e614a9f1c9e2	1407	* @brief Clear Address Matched flag.
AnnaBridge	165:e614a9f1c9e2	1408	* @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge	165:e614a9f1c9e2	1409	* register followed by a read access to the I2Cx_SR2 register.
AnnaBridge	165:e614a9f1c9e2	1410	* @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
AnnaBridge	165:e614a9f1c9e2	1411	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1412	* @retval None
AnnaBridge	165:e614a9f1c9e2	1413	*/
AnnaBridge	165:e614a9f1c9e2	1414	__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1415	{
AnnaBridge	165:e614a9f1c9e2	1416	__IO uint32_t tmpreg;
AnnaBridge	165:e614a9f1c9e2	1417	tmpreg = I2Cx->SR1;
AnnaBridge	165:e614a9f1c9e2	1418	(void) tmpreg;
AnnaBridge	165:e614a9f1c9e2	1419	tmpreg = I2Cx->SR2;
AnnaBridge	165:e614a9f1c9e2	1420	(void) tmpreg;
AnnaBridge	165:e614a9f1c9e2	1421	}
AnnaBridge	165:e614a9f1c9e2	1422
AnnaBridge	165:e614a9f1c9e2	1423	/**
AnnaBridge	165:e614a9f1c9e2	1424	* @brief Clear Acknowledge failure flag.
AnnaBridge	165:e614a9f1c9e2	1425	* @rmtoll SR1 AF LL_I2C_ClearFlag_AF
AnnaBridge	165:e614a9f1c9e2	1426	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1427	* @retval None
AnnaBridge	165:e614a9f1c9e2	1428	*/
AnnaBridge	165:e614a9f1c9e2	1429	__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1430	{
AnnaBridge	165:e614a9f1c9e2	1431	CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
AnnaBridge	165:e614a9f1c9e2	1432	}
AnnaBridge	165:e614a9f1c9e2	1433
AnnaBridge	165:e614a9f1c9e2	1434	/**
AnnaBridge	165:e614a9f1c9e2	1435	* @brief Clear Stop detection flag.
AnnaBridge	165:e614a9f1c9e2	1436	* @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge	165:e614a9f1c9e2	1437	* register followed by a write access to I2Cx_CR1 register.
AnnaBridge	165:e614a9f1c9e2	1438	* @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
AnnaBridge	165:e614a9f1c9e2	1439	* CR1 PE LL_I2C_ClearFlag_STOP
AnnaBridge	165:e614a9f1c9e2	1440	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1441	* @retval None
AnnaBridge	165:e614a9f1c9e2	1442	*/
AnnaBridge	165:e614a9f1c9e2	1443	__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1444	{
AnnaBridge	165:e614a9f1c9e2	1445	__IO uint32_t tmpreg;
AnnaBridge	165:e614a9f1c9e2	1446	tmpreg = I2Cx->SR1;
AnnaBridge	165:e614a9f1c9e2	1447	(void) tmpreg;
AnnaBridge	165:e614a9f1c9e2	1448	SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge	165:e614a9f1c9e2	1449	}
AnnaBridge	165:e614a9f1c9e2	1450
AnnaBridge	165:e614a9f1c9e2	1451	/**
AnnaBridge	165:e614a9f1c9e2	1452	* @brief Clear Bus error flag.
AnnaBridge	165:e614a9f1c9e2	1453	* @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
AnnaBridge	165:e614a9f1c9e2	1454	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1455	* @retval None
AnnaBridge	165:e614a9f1c9e2	1456	*/
AnnaBridge	165:e614a9f1c9e2	1457	__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1458	{
AnnaBridge	165:e614a9f1c9e2	1459	CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
AnnaBridge	165:e614a9f1c9e2	1460	}
AnnaBridge	165:e614a9f1c9e2	1461
AnnaBridge	165:e614a9f1c9e2	1462	/**
AnnaBridge	165:e614a9f1c9e2	1463	* @brief Clear Arbitration lost flag.
AnnaBridge	165:e614a9f1c9e2	1464	* @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
AnnaBridge	165:e614a9f1c9e2	1465	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1466	* @retval None
AnnaBridge	165:e614a9f1c9e2	1467	*/
AnnaBridge	165:e614a9f1c9e2	1468	__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1469	{
AnnaBridge	165:e614a9f1c9e2	1470	CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
AnnaBridge	165:e614a9f1c9e2	1471	}
AnnaBridge	165:e614a9f1c9e2	1472
AnnaBridge	165:e614a9f1c9e2	1473	/**
AnnaBridge	165:e614a9f1c9e2	1474	* @brief Clear Overrun/Underrun flag.
AnnaBridge	165:e614a9f1c9e2	1475	* @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
AnnaBridge	165:e614a9f1c9e2	1476	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1477	* @retval None
AnnaBridge	165:e614a9f1c9e2	1478	*/
AnnaBridge	165:e614a9f1c9e2	1479	__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1480	{
AnnaBridge	165:e614a9f1c9e2	1481	CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
AnnaBridge	165:e614a9f1c9e2	1482	}
AnnaBridge	165:e614a9f1c9e2	1483
AnnaBridge	165:e614a9f1c9e2	1484	/**
AnnaBridge	165:e614a9f1c9e2	1485	* @brief Clear SMBus PEC error flag.
AnnaBridge	165:e614a9f1c9e2	1486	* @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
AnnaBridge	165:e614a9f1c9e2	1487	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1488	* @retval None
AnnaBridge	165:e614a9f1c9e2	1489	*/
AnnaBridge	165:e614a9f1c9e2	1490	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1491	{
AnnaBridge	165:e614a9f1c9e2	1492	CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
AnnaBridge	165:e614a9f1c9e2	1493	}
AnnaBridge	165:e614a9f1c9e2	1494
AnnaBridge	165:e614a9f1c9e2	1495	/**
AnnaBridge	165:e614a9f1c9e2	1496	* @brief Clear SMBus Timeout detection flag.
AnnaBridge	165:e614a9f1c9e2	1497	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1498	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1499	* @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
AnnaBridge	165:e614a9f1c9e2	1500	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1501	* @retval None
AnnaBridge	165:e614a9f1c9e2	1502	*/
AnnaBridge	165:e614a9f1c9e2	1503	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1504	{
AnnaBridge	165:e614a9f1c9e2	1505	CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
AnnaBridge	165:e614a9f1c9e2	1506	}
AnnaBridge	165:e614a9f1c9e2	1507
AnnaBridge	165:e614a9f1c9e2	1508	/**
AnnaBridge	165:e614a9f1c9e2	1509	* @brief Clear SMBus Alert flag.
AnnaBridge	165:e614a9f1c9e2	1510	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1511	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1512	* @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
AnnaBridge	165:e614a9f1c9e2	1513	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1514	* @retval None
AnnaBridge	165:e614a9f1c9e2	1515	*/
AnnaBridge	165:e614a9f1c9e2	1516	__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1517	{
AnnaBridge	165:e614a9f1c9e2	1518	CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
AnnaBridge	165:e614a9f1c9e2	1519	}
AnnaBridge	165:e614a9f1c9e2	1520
AnnaBridge	165:e614a9f1c9e2	1521	/**
AnnaBridge	165:e614a9f1c9e2	1522	* @}
AnnaBridge	165:e614a9f1c9e2	1523	*/
AnnaBridge	165:e614a9f1c9e2	1524
AnnaBridge	165:e614a9f1c9e2	1525	/** @defgroup I2C_LL_EF_Data_Management Data_Management
AnnaBridge	165:e614a9f1c9e2	1526	* @{
AnnaBridge	165:e614a9f1c9e2	1527	*/
AnnaBridge	165:e614a9f1c9e2	1528
AnnaBridge	165:e614a9f1c9e2	1529	/**
AnnaBridge	165:e614a9f1c9e2	1530	* @brief Enable Reset of I2C peripheral.
AnnaBridge	165:e614a9f1c9e2	1531	* @rmtoll CR1 SWRST LL_I2C_EnableReset
AnnaBridge	165:e614a9f1c9e2	1532	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1533	* @retval None
AnnaBridge	165:e614a9f1c9e2	1534	*/
AnnaBridge	165:e614a9f1c9e2	1535	__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1536	{
AnnaBridge	165:e614a9f1c9e2	1537	SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge	165:e614a9f1c9e2	1538	}
AnnaBridge	165:e614a9f1c9e2	1539
AnnaBridge	165:e614a9f1c9e2	1540	/**
AnnaBridge	165:e614a9f1c9e2	1541	* @brief Disable Reset of I2C peripheral.
AnnaBridge	165:e614a9f1c9e2	1542	* @rmtoll CR1 SWRST LL_I2C_DisableReset
AnnaBridge	165:e614a9f1c9e2	1543	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1544	* @retval None
AnnaBridge	165:e614a9f1c9e2	1545	*/
AnnaBridge	165:e614a9f1c9e2	1546	__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1547	{
AnnaBridge	165:e614a9f1c9e2	1548	CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge	165:e614a9f1c9e2	1549	}
AnnaBridge	165:e614a9f1c9e2	1550
AnnaBridge	165:e614a9f1c9e2	1551	/**
AnnaBridge	165:e614a9f1c9e2	1552	* @brief Check if the I2C peripheral is under reset state or not.
AnnaBridge	165:e614a9f1c9e2	1553	* @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
AnnaBridge	165:e614a9f1c9e2	1554	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1555	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1556	*/
AnnaBridge	165:e614a9f1c9e2	1557	__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1558	{
AnnaBridge	165:e614a9f1c9e2	1559	return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
AnnaBridge	165:e614a9f1c9e2	1560	}
AnnaBridge	165:e614a9f1c9e2	1561
AnnaBridge	165:e614a9f1c9e2	1562	/**
AnnaBridge	165:e614a9f1c9e2	1563	* @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge	165:e614a9f1c9e2	1564	* @note Usage in Slave or Master mode.
AnnaBridge	165:e614a9f1c9e2	1565	* @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
AnnaBridge	165:e614a9f1c9e2	1566	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1567	* @param TypeAcknowledge This parameter can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1568	* @arg @ref LL_I2C_ACK
AnnaBridge	165:e614a9f1c9e2	1569	* @arg @ref LL_I2C_NACK
AnnaBridge	165:e614a9f1c9e2	1570	* @retval None
AnnaBridge	165:e614a9f1c9e2	1571	*/
AnnaBridge	165:e614a9f1c9e2	1572	__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
AnnaBridge	165:e614a9f1c9e2	1573	{
AnnaBridge	165:e614a9f1c9e2	1574	MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
AnnaBridge	165:e614a9f1c9e2	1575	}
AnnaBridge	165:e614a9f1c9e2	1576
AnnaBridge	165:e614a9f1c9e2	1577	/**
AnnaBridge	165:e614a9f1c9e2	1578	* @brief Generate a START or RESTART condition
AnnaBridge	165:e614a9f1c9e2	1579	* @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
AnnaBridge	165:e614a9f1c9e2	1580	* This action has no effect when RELOAD is set.
AnnaBridge	165:e614a9f1c9e2	1581	* @rmtoll CR1 START LL_I2C_GenerateStartCondition
AnnaBridge	165:e614a9f1c9e2	1582	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1583	* @retval None
AnnaBridge	165:e614a9f1c9e2	1584	*/
AnnaBridge	165:e614a9f1c9e2	1585	__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1586	{
AnnaBridge	165:e614a9f1c9e2	1587	SET_BIT(I2Cx->CR1, I2C_CR1_START);
AnnaBridge	165:e614a9f1c9e2	1588	}
AnnaBridge	165:e614a9f1c9e2	1589
AnnaBridge	165:e614a9f1c9e2	1590	/**
AnnaBridge	165:e614a9f1c9e2	1591	* @brief Generate a STOP condition after the current byte transfer (master mode).
AnnaBridge	165:e614a9f1c9e2	1592	* @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
AnnaBridge	165:e614a9f1c9e2	1593	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1594	* @retval None
AnnaBridge	165:e614a9f1c9e2	1595	*/
AnnaBridge	165:e614a9f1c9e2	1596	__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1597	{
AnnaBridge	165:e614a9f1c9e2	1598	SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
AnnaBridge	165:e614a9f1c9e2	1599	}
AnnaBridge	165:e614a9f1c9e2	1600
AnnaBridge	165:e614a9f1c9e2	1601	/**
AnnaBridge	165:e614a9f1c9e2	1602	* @brief Enable bit POS (master/host mode).
AnnaBridge	165:e614a9f1c9e2	1603	* @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
AnnaBridge	165:e614a9f1c9e2	1604	* @rmtoll CR1 POS LL_I2C_EnableBitPOS
AnnaBridge	165:e614a9f1c9e2	1605	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1606	* @retval None
AnnaBridge	165:e614a9f1c9e2	1607	*/
AnnaBridge	165:e614a9f1c9e2	1608	__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1609	{
AnnaBridge	165:e614a9f1c9e2	1610	SET_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge	165:e614a9f1c9e2	1611	}
AnnaBridge	165:e614a9f1c9e2	1612
AnnaBridge	165:e614a9f1c9e2	1613	/**
AnnaBridge	165:e614a9f1c9e2	1614	* @brief Disable bit POS (master/host mode).
AnnaBridge	165:e614a9f1c9e2	1615	* @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
AnnaBridge	165:e614a9f1c9e2	1616	* @rmtoll CR1 POS LL_I2C_DisableBitPOS
AnnaBridge	165:e614a9f1c9e2	1617	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1618	* @retval None
AnnaBridge	165:e614a9f1c9e2	1619	*/
AnnaBridge	165:e614a9f1c9e2	1620	__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1621	{
AnnaBridge	165:e614a9f1c9e2	1622	CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge	165:e614a9f1c9e2	1623	}
AnnaBridge	165:e614a9f1c9e2	1624
AnnaBridge	165:e614a9f1c9e2	1625	/**
AnnaBridge	165:e614a9f1c9e2	1626	* @brief Check if bit POS is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	1627	* @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
AnnaBridge	165:e614a9f1c9e2	1628	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1629	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1630	*/
AnnaBridge	165:e614a9f1c9e2	1631	__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1632	{
AnnaBridge	165:e614a9f1c9e2	1633	return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
AnnaBridge	165:e614a9f1c9e2	1634	}
AnnaBridge	165:e614a9f1c9e2	1635
AnnaBridge	165:e614a9f1c9e2	1636	/**
AnnaBridge	165:e614a9f1c9e2	1637	* @brief Indicate the value of transfer direction.
AnnaBridge	165:e614a9f1c9e2	1638	* @note RESET: Bus is in read transfer (peripheral point of view).
AnnaBridge	165:e614a9f1c9e2	1639	* SET: Bus is in write transfer (peripheral point of view).
AnnaBridge	165:e614a9f1c9e2	1640	* @rmtoll SR2 TRA LL_I2C_GetTransferDirection
AnnaBridge	165:e614a9f1c9e2	1641	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1642	* @retval Returned value can be one of the following values:
AnnaBridge	165:e614a9f1c9e2	1643	* @arg @ref LL_I2C_DIRECTION_WRITE
AnnaBridge	165:e614a9f1c9e2	1644	* @arg @ref LL_I2C_DIRECTION_READ
AnnaBridge	165:e614a9f1c9e2	1645	*/
AnnaBridge	165:e614a9f1c9e2	1646	__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1647	{
AnnaBridge	165:e614a9f1c9e2	1648	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
AnnaBridge	165:e614a9f1c9e2	1649	}
AnnaBridge	165:e614a9f1c9e2	1650
AnnaBridge	165:e614a9f1c9e2	1651	/**
AnnaBridge	165:e614a9f1c9e2	1652	* @brief Enable DMA last transfer.
AnnaBridge	165:e614a9f1c9e2	1653	* @note This action mean that next DMA EOT is the last transfer.
AnnaBridge	165:e614a9f1c9e2	1654	* @rmtoll CR2 LAST LL_I2C_EnableLastDMA
AnnaBridge	165:e614a9f1c9e2	1655	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1656	* @retval None
AnnaBridge	165:e614a9f1c9e2	1657	*/
AnnaBridge	165:e614a9f1c9e2	1658	__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1659	{
AnnaBridge	165:e614a9f1c9e2	1660	SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge	165:e614a9f1c9e2	1661	}
AnnaBridge	165:e614a9f1c9e2	1662
AnnaBridge	165:e614a9f1c9e2	1663	/**
AnnaBridge	165:e614a9f1c9e2	1664	* @brief Disable DMA last transfer.
AnnaBridge	165:e614a9f1c9e2	1665	* @note This action mean that next DMA EOT is not the last transfer.
AnnaBridge	165:e614a9f1c9e2	1666	* @rmtoll CR2 LAST LL_I2C_DisableLastDMA
AnnaBridge	165:e614a9f1c9e2	1667	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1668	* @retval None
AnnaBridge	165:e614a9f1c9e2	1669	*/
AnnaBridge	165:e614a9f1c9e2	1670	__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1671	{
AnnaBridge	165:e614a9f1c9e2	1672	CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge	165:e614a9f1c9e2	1673	}
AnnaBridge	165:e614a9f1c9e2	1674
AnnaBridge	165:e614a9f1c9e2	1675	/**
AnnaBridge	165:e614a9f1c9e2	1676	* @brief Check if DMA last transfer is enabled or disabled.
AnnaBridge	165:e614a9f1c9e2	1677	* @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
AnnaBridge	165:e614a9f1c9e2	1678	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1679	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1680	*/
AnnaBridge	165:e614a9f1c9e2	1681	__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1682	{
AnnaBridge	165:e614a9f1c9e2	1683	return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
AnnaBridge	165:e614a9f1c9e2	1684	}
AnnaBridge	165:e614a9f1c9e2	1685
AnnaBridge	165:e614a9f1c9e2	1686	/**
AnnaBridge	165:e614a9f1c9e2	1687	* @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge	165:e614a9f1c9e2	1688	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1689	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1690	* @note This feature is cleared by hardware when the PEC byte is transferred or compared,
AnnaBridge	165:e614a9f1c9e2	1691	* or by a START or STOP condition, it is also cleared by software.
AnnaBridge	165:e614a9f1c9e2	1692	* @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
AnnaBridge	165:e614a9f1c9e2	1693	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1694	* @retval None
AnnaBridge	165:e614a9f1c9e2	1695	*/
AnnaBridge	165:e614a9f1c9e2	1696	__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1697	{
AnnaBridge	165:e614a9f1c9e2	1698	SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge	165:e614a9f1c9e2	1699	}
AnnaBridge	165:e614a9f1c9e2	1700
AnnaBridge	165:e614a9f1c9e2	1701	/**
AnnaBridge	165:e614a9f1c9e2	1702	* @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge	165:e614a9f1c9e2	1703	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1704	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1705	* @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
AnnaBridge	165:e614a9f1c9e2	1706	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1707	* @retval None
AnnaBridge	165:e614a9f1c9e2	1708	*/
AnnaBridge	165:e614a9f1c9e2	1709	__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1710	{
AnnaBridge	165:e614a9f1c9e2	1711	CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge	165:e614a9f1c9e2	1712	}
AnnaBridge	165:e614a9f1c9e2	1713
AnnaBridge	165:e614a9f1c9e2	1714	/**
AnnaBridge	165:e614a9f1c9e2	1715	* @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
AnnaBridge	165:e614a9f1c9e2	1716	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1717	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1718	* @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
AnnaBridge	165:e614a9f1c9e2	1719	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1720	* @retval State of bit (1 or 0).
AnnaBridge	165:e614a9f1c9e2	1721	*/
AnnaBridge	165:e614a9f1c9e2	1722	__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1723	{
AnnaBridge	165:e614a9f1c9e2	1724	return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
AnnaBridge	165:e614a9f1c9e2	1725	}
AnnaBridge	165:e614a9f1c9e2	1726
AnnaBridge	165:e614a9f1c9e2	1727	/**
AnnaBridge	165:e614a9f1c9e2	1728	* @brief Get the SMBus Packet Error byte calculated.
AnnaBridge	165:e614a9f1c9e2	1729	* @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge	165:e614a9f1c9e2	1730	* SMBus feature is supported by the I2Cx Instance.
AnnaBridge	165:e614a9f1c9e2	1731	* @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
AnnaBridge	165:e614a9f1c9e2	1732	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1733	* @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	1734	*/
AnnaBridge	165:e614a9f1c9e2	1735	__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1736	{
AnnaBridge	165:e614a9f1c9e2	1737	return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
AnnaBridge	165:e614a9f1c9e2	1738	}
AnnaBridge	165:e614a9f1c9e2	1739
AnnaBridge	165:e614a9f1c9e2	1740	/**
AnnaBridge	165:e614a9f1c9e2	1741	* @brief Read Receive Data register.
AnnaBridge	165:e614a9f1c9e2	1742	* @rmtoll DR DR LL_I2C_ReceiveData8
AnnaBridge	165:e614a9f1c9e2	1743	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1744	* @retval Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	1745	*/
AnnaBridge	165:e614a9f1c9e2	1746	__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
AnnaBridge	165:e614a9f1c9e2	1747	{
AnnaBridge	165:e614a9f1c9e2	1748	return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
AnnaBridge	165:e614a9f1c9e2	1749	}
AnnaBridge	165:e614a9f1c9e2	1750
AnnaBridge	165:e614a9f1c9e2	1751	/**
AnnaBridge	165:e614a9f1c9e2	1752	* @brief Write in Transmit Data Register .
AnnaBridge	165:e614a9f1c9e2	1753	* @rmtoll DR DR LL_I2C_TransmitData8
AnnaBridge	165:e614a9f1c9e2	1754	* @param I2Cx I2C Instance.
AnnaBridge	165:e614a9f1c9e2	1755	* @param Data Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge	165:e614a9f1c9e2	1756	* @retval None
AnnaBridge	165:e614a9f1c9e2	1757	*/
AnnaBridge	165:e614a9f1c9e2	1758	__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
AnnaBridge	165:e614a9f1c9e2	1759	{
AnnaBridge	165:e614a9f1c9e2	1760	MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
AnnaBridge	165:e614a9f1c9e2	1761	}
AnnaBridge	165:e614a9f1c9e2	1762
AnnaBridge	165:e614a9f1c9e2	1763	/**
AnnaBridge	165:e614a9f1c9e2	1764	* @}
AnnaBridge	165:e614a9f1c9e2	1765	*/
AnnaBridge	165:e614a9f1c9e2	1766
AnnaBridge	165:e614a9f1c9e2	1767	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:e614a9f1c9e2	1768	/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
AnnaBridge	165:e614a9f1c9e2	1769	* @{
AnnaBridge	165:e614a9f1c9e2	1770	*/
AnnaBridge	165:e614a9f1c9e2	1771
AnnaBridge	165:e614a9f1c9e2	1772	uint32_t LL_I2C_Init(I2C_TypeDef I2Cx, LL_I2C_InitTypeDef I2C_InitStruct);
AnnaBridge	165:e614a9f1c9e2	1773	uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
AnnaBridge	165:e614a9f1c9e2	1774	void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge	165:e614a9f1c9e2	1775
AnnaBridge	165:e614a9f1c9e2	1776
AnnaBridge	165:e614a9f1c9e2	1777	/**
AnnaBridge	165:e614a9f1c9e2	1778	* @}
AnnaBridge	165:e614a9f1c9e2	1779	*/
AnnaBridge	165:e614a9f1c9e2	1780	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:e614a9f1c9e2	1781
AnnaBridge	165:e614a9f1c9e2	1782	/**
AnnaBridge	165:e614a9f1c9e2	1783	* @}
AnnaBridge	165:e614a9f1c9e2	1784	*/
AnnaBridge	165:e614a9f1c9e2	1785
AnnaBridge	165:e614a9f1c9e2	1786	/**
AnnaBridge	165:e614a9f1c9e2	1787	* @}
AnnaBridge	165:e614a9f1c9e2	1788	*/
AnnaBridge	165:e614a9f1c9e2	1789
AnnaBridge	165:e614a9f1c9e2	1790	#endif /* I2C1 \|\| I2C2 */
AnnaBridge	165:e614a9f1c9e2	1791
AnnaBridge	165:e614a9f1c9e2	1792	/**
AnnaBridge	165:e614a9f1c9e2	1793	* @}
AnnaBridge	165:e614a9f1c9e2	1794	*/
AnnaBridge	165:e614a9f1c9e2	1795
AnnaBridge	165:e614a9f1c9e2	1796	#ifdef __cplusplus
AnnaBridge	165:e614a9f1c9e2	1797	}
AnnaBridge	165:e614a9f1c9e2	1798	#endif
AnnaBridge	165:e614a9f1c9e2	1799
AnnaBridge	165:e614a9f1c9e2	1800	#endif /* __STM32F1xx_LL_I2C_H */
AnnaBridge	165:e614a9f1c9e2	1801
AnnaBridge	165:e614a9f1c9e2	1802	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/