mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_i2c.h@187:0387e8f68319, 2018-09-06 (annotated)

Committer:
AnnaBridge
Date:
Thu Sep 06 13:40:20 2018 +0100
Revision:
187:0387e8f68319
Parent:
165:e614a9f1c9e2 
mbed-dev library. Release version 163

Who changed what in which revision?

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AnnaBridge 165:e614a9f1c9e2 1 /**
AnnaBridge 165:e614a9f1c9e2 2 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 3 * @file stm32f1xx_ll_i2c.h
AnnaBridge 165:e614a9f1c9e2 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @brief Header file of I2C LL module.
AnnaBridge 165:e614a9f1c9e2 6 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 7 * @attention
AnnaBridge 165:e614a9f1c9e2 8 *
AnnaBridge 165:e614a9f1c9e2 9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 165:e614a9f1c9e2 10 *
AnnaBridge 165:e614a9f1c9e2 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 165:e614a9f1c9e2 12 * are permitted provided that the following conditions are met:
AnnaBridge 165:e614a9f1c9e2 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 165:e614a9f1c9e2 14 * this list of conditions and the following disclaimer.
AnnaBridge 165:e614a9f1c9e2 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 165:e614a9f1c9e2 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 165:e614a9f1c9e2 17 * and/or other materials provided with the distribution.
AnnaBridge 165:e614a9f1c9e2 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 165:e614a9f1c9e2 19 * may be used to endorse or promote products derived from this software
AnnaBridge 165:e614a9f1c9e2 20 * without specific prior written permission.
AnnaBridge 165:e614a9f1c9e2 21 *
AnnaBridge 165:e614a9f1c9e2 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 165:e614a9f1c9e2 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 165:e614a9f1c9e2 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 165:e614a9f1c9e2 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 165:e614a9f1c9e2 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 165:e614a9f1c9e2 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 165:e614a9f1c9e2 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 165:e614a9f1c9e2 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 165:e614a9f1c9e2 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 165:e614a9f1c9e2 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 165:e614a9f1c9e2 32 *
AnnaBridge 165:e614a9f1c9e2 33 ******************************************************************************
AnnaBridge 165:e614a9f1c9e2 34 */
AnnaBridge 165:e614a9f1c9e2 35
AnnaBridge 165:e614a9f1c9e2 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 37 #ifndef __STM32F1xx_LL_I2C_H
AnnaBridge 165:e614a9f1c9e2 38 #define __STM32F1xx_LL_I2C_H
AnnaBridge 165:e614a9f1c9e2 39
AnnaBridge 165:e614a9f1c9e2 40 #ifdef __cplusplus
AnnaBridge 165:e614a9f1c9e2 41 extern "C" {
AnnaBridge 165:e614a9f1c9e2 42 #endif
AnnaBridge 165:e614a9f1c9e2 43
AnnaBridge 165:e614a9f1c9e2 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 45 #include "stm32f1xx.h"
AnnaBridge 165:e614a9f1c9e2 46
AnnaBridge 165:e614a9f1c9e2 47 /** @addtogroup STM32F1xx_LL_Driver
AnnaBridge 165:e614a9f1c9e2 48 * @{
AnnaBridge 165:e614a9f1c9e2 49 */
AnnaBridge 165:e614a9f1c9e2 50
AnnaBridge 165:e614a9f1c9e2 51 #if defined (I2C1) || defined (I2C2)
AnnaBridge 165:e614a9f1c9e2 52
AnnaBridge 165:e614a9f1c9e2 53 /** @defgroup I2C_LL I2C
AnnaBridge 165:e614a9f1c9e2 54 * @{
AnnaBridge 165:e614a9f1c9e2 55 */
AnnaBridge 165:e614a9f1c9e2 56
AnnaBridge 165:e614a9f1c9e2 57 /* Private types -------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 58 /* Private variables ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 59
AnnaBridge 165:e614a9f1c9e2 60 /* Private constants ---------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 61 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
AnnaBridge 165:e614a9f1c9e2 62 * @{
AnnaBridge 165:e614a9f1c9e2 63 */
AnnaBridge 165:e614a9f1c9e2 64
AnnaBridge 165:e614a9f1c9e2 65 /* Defines used to perform compute and check in the macros */
AnnaBridge 165:e614a9f1c9e2 66 #define LL_I2C_MAX_SPEED_STANDARD 100000U
AnnaBridge 165:e614a9f1c9e2 67 #define LL_I2C_MAX_SPEED_FAST 400000U
AnnaBridge 165:e614a9f1c9e2 68 /**
AnnaBridge 165:e614a9f1c9e2 69 * @}
AnnaBridge 165:e614a9f1c9e2 70 */
AnnaBridge 165:e614a9f1c9e2 71
AnnaBridge 165:e614a9f1c9e2 72 /* Private macros ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 73 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 165:e614a9f1c9e2 74 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
AnnaBridge 165:e614a9f1c9e2 75 * @{
AnnaBridge 165:e614a9f1c9e2 76 */
AnnaBridge 165:e614a9f1c9e2 77 /**
AnnaBridge 165:e614a9f1c9e2 78 * @}
AnnaBridge 165:e614a9f1c9e2 79 */
AnnaBridge 165:e614a9f1c9e2 80 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 165:e614a9f1c9e2 81
AnnaBridge 165:e614a9f1c9e2 82 /* Exported types ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 83 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 165:e614a9f1c9e2 84 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
AnnaBridge 165:e614a9f1c9e2 85 * @{
AnnaBridge 165:e614a9f1c9e2 86 */
AnnaBridge 165:e614a9f1c9e2 87 typedef struct
AnnaBridge 165:e614a9f1c9e2 88 {
AnnaBridge 165:e614a9f1c9e2 89 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
AnnaBridge 165:e614a9f1c9e2 90 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
AnnaBridge 165:e614a9f1c9e2 91
AnnaBridge 165:e614a9f1c9e2 92 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
AnnaBridge 165:e614a9f1c9e2 93
AnnaBridge 165:e614a9f1c9e2 94 uint32_t ClockSpeed; /*!< Specifies the clock frequency.
AnnaBridge 165:e614a9f1c9e2 95 This parameter must be set to a value lower than 400kHz (in Hz)
AnnaBridge 165:e614a9f1c9e2 96
AnnaBridge 165:e614a9f1c9e2 97 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod()
AnnaBridge 165:e614a9f1c9e2 98 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */
AnnaBridge 165:e614a9f1c9e2 99
AnnaBridge 165:e614a9f1c9e2 100 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
AnnaBridge 165:e614a9f1c9e2 101 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE
AnnaBridge 165:e614a9f1c9e2 102
AnnaBridge 165:e614a9f1c9e2 103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */
AnnaBridge 165:e614a9f1c9e2 104
AnnaBridge 165:e614a9f1c9e2 105 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
AnnaBridge 165:e614a9f1c9e2 106 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
AnnaBridge 165:e614a9f1c9e2 107
AnnaBridge 165:e614a9f1c9e2 108 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge 165:e614a9f1c9e2 109
AnnaBridge 165:e614a9f1c9e2 110 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge 165:e614a9f1c9e2 111 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
AnnaBridge 165:e614a9f1c9e2 112
AnnaBridge 165:e614a9f1c9e2 113 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
AnnaBridge 165:e614a9f1c9e2 114
AnnaBridge 165:e614a9f1c9e2 115 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
AnnaBridge 165:e614a9f1c9e2 116 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
AnnaBridge 165:e614a9f1c9e2 117
AnnaBridge 165:e614a9f1c9e2 118 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
AnnaBridge 165:e614a9f1c9e2 119 } LL_I2C_InitTypeDef;
AnnaBridge 165:e614a9f1c9e2 120 /**
AnnaBridge 165:e614a9f1c9e2 121 * @}
AnnaBridge 165:e614a9f1c9e2 122 */
AnnaBridge 165:e614a9f1c9e2 123 #endif /*USE_FULL_LL_DRIVER*/
AnnaBridge 165:e614a9f1c9e2 124
AnnaBridge 165:e614a9f1c9e2 125 /* Exported constants --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 126 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
AnnaBridge 165:e614a9f1c9e2 127 * @{
AnnaBridge 165:e614a9f1c9e2 128 */
AnnaBridge 165:e614a9f1c9e2 129
AnnaBridge 165:e614a9f1c9e2 130 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge 165:e614a9f1c9e2 131 * @brief Flags defines which can be used with LL_I2C_ReadReg function
AnnaBridge 165:e614a9f1c9e2 132 * @{
AnnaBridge 165:e614a9f1c9e2 133 */
AnnaBridge 165:e614a9f1c9e2 134 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */
AnnaBridge 165:e614a9f1c9e2 135 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or
AnnaBridge 165:e614a9f1c9e2 136 Address matched flag (slave mode) */
AnnaBridge 165:e614a9f1c9e2 137 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */
AnnaBridge 165:e614a9f1c9e2 138 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */
AnnaBridge 165:e614a9f1c9e2 139 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */
AnnaBridge 165:e614a9f1c9e2 140 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */
AnnaBridge 165:e614a9f1c9e2 141 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */
AnnaBridge 165:e614a9f1c9e2 142 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */
AnnaBridge 165:e614a9f1c9e2 143 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */
AnnaBridge 165:e614a9f1c9e2 144 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */
AnnaBridge 165:e614a9f1c9e2 145 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */
AnnaBridge 165:e614a9f1c9e2 146 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
AnnaBridge 165:e614a9f1c9e2 147 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
AnnaBridge 165:e614a9f1c9e2 148 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */
AnnaBridge 165:e614a9f1c9e2 149 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */
AnnaBridge 165:e614a9f1c9e2 150 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */
AnnaBridge 165:e614a9f1c9e2 151 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */
AnnaBridge 165:e614a9f1c9e2 152 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */
AnnaBridge 165:e614a9f1c9e2 153 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */
AnnaBridge 165:e614a9f1c9e2 154 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */
AnnaBridge 165:e614a9f1c9e2 155 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */
AnnaBridge 165:e614a9f1c9e2 156 /**
AnnaBridge 165:e614a9f1c9e2 157 * @}
AnnaBridge 165:e614a9f1c9e2 158 */
AnnaBridge 165:e614a9f1c9e2 159
AnnaBridge 165:e614a9f1c9e2 160 /** @defgroup I2C_LL_EC_IT IT Defines
AnnaBridge 165:e614a9f1c9e2 161 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
AnnaBridge 165:e614a9f1c9e2 162 * @{
AnnaBridge 165:e614a9f1c9e2 163 */
AnnaBridge 165:e614a9f1c9e2 164 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */
AnnaBridge 165:e614a9f1c9e2 165 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */
AnnaBridge 165:e614a9f1c9e2 166 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */
AnnaBridge 165:e614a9f1c9e2 167 /**
AnnaBridge 165:e614a9f1c9e2 168 * @}
AnnaBridge 165:e614a9f1c9e2 169 */
AnnaBridge 165:e614a9f1c9e2 170
AnnaBridge 165:e614a9f1c9e2 171 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
AnnaBridge 165:e614a9f1c9e2 172 * @{
AnnaBridge 165:e614a9f1c9e2 173 */
AnnaBridge 165:e614a9f1c9e2 174 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */
AnnaBridge 165:e614a9f1c9e2 175 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */
AnnaBridge 165:e614a9f1c9e2 176 /**
AnnaBridge 165:e614a9f1c9e2 177 * @}
AnnaBridge 165:e614a9f1c9e2 178 */
AnnaBridge 165:e614a9f1c9e2 179
AnnaBridge 165:e614a9f1c9e2 180 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle
AnnaBridge 165:e614a9f1c9e2 181 * @{
AnnaBridge 165:e614a9f1c9e2 182 */
AnnaBridge 165:e614a9f1c9e2 183 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */
AnnaBridge 165:e614a9f1c9e2 184 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */
AnnaBridge 165:e614a9f1c9e2 185 /**
AnnaBridge 165:e614a9f1c9e2 186 * @}
AnnaBridge 165:e614a9f1c9e2 187 */
AnnaBridge 165:e614a9f1c9e2 188
AnnaBridge 165:e614a9f1c9e2 189 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode
AnnaBridge 165:e614a9f1c9e2 190 * @{
AnnaBridge 165:e614a9f1c9e2 191 */
AnnaBridge 165:e614a9f1c9e2 192 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */
AnnaBridge 165:e614a9f1c9e2 193 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */
AnnaBridge 165:e614a9f1c9e2 194 /**
AnnaBridge 165:e614a9f1c9e2 195 * @}
AnnaBridge 165:e614a9f1c9e2 196 */
AnnaBridge 165:e614a9f1c9e2 197
AnnaBridge 165:e614a9f1c9e2 198 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
AnnaBridge 165:e614a9f1c9e2 199 * @{
AnnaBridge 165:e614a9f1c9e2 200 */
AnnaBridge 165:e614a9f1c9e2 201 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
AnnaBridge 165:e614a9f1c9e2 202 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */
AnnaBridge 165:e614a9f1c9e2 203 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */
AnnaBridge 165:e614a9f1c9e2 204 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */
AnnaBridge 165:e614a9f1c9e2 205 /**
AnnaBridge 165:e614a9f1c9e2 206 * @}
AnnaBridge 165:e614a9f1c9e2 207 */
AnnaBridge 165:e614a9f1c9e2 208
AnnaBridge 165:e614a9f1c9e2 209 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
AnnaBridge 165:e614a9f1c9e2 210 * @{
AnnaBridge 165:e614a9f1c9e2 211 */
AnnaBridge 165:e614a9f1c9e2 212 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */
AnnaBridge 165:e614a9f1c9e2 213 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/
AnnaBridge 165:e614a9f1c9e2 214 /**
AnnaBridge 165:e614a9f1c9e2 215 * @}
AnnaBridge 165:e614a9f1c9e2 216 */
AnnaBridge 165:e614a9f1c9e2 217
AnnaBridge 165:e614a9f1c9e2 218 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
AnnaBridge 165:e614a9f1c9e2 219 * @{
AnnaBridge 165:e614a9f1c9e2 220 */
AnnaBridge 165:e614a9f1c9e2 221 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */
AnnaBridge 165:e614a9f1c9e2 222 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */
AnnaBridge 165:e614a9f1c9e2 223 /**
AnnaBridge 165:e614a9f1c9e2 224 * @}
AnnaBridge 165:e614a9f1c9e2 225 */
AnnaBridge 165:e614a9f1c9e2 226
AnnaBridge 165:e614a9f1c9e2 227 /**
AnnaBridge 165:e614a9f1c9e2 228 * @}
AnnaBridge 165:e614a9f1c9e2 229 */
AnnaBridge 165:e614a9f1c9e2 230
AnnaBridge 165:e614a9f1c9e2 231 /* Exported macro ------------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 232 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
AnnaBridge 165:e614a9f1c9e2 233 * @{
AnnaBridge 165:e614a9f1c9e2 234 */
AnnaBridge 165:e614a9f1c9e2 235
AnnaBridge 165:e614a9f1c9e2 236 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge 165:e614a9f1c9e2 237 * @{
AnnaBridge 165:e614a9f1c9e2 238 */
AnnaBridge 165:e614a9f1c9e2 239
AnnaBridge 165:e614a9f1c9e2 240 /**
AnnaBridge 165:e614a9f1c9e2 241 * @brief Write a value in I2C register
AnnaBridge 165:e614a9f1c9e2 242 * @param __INSTANCE__ I2C Instance
AnnaBridge 165:e614a9f1c9e2 243 * @param __REG__ Register to be written
AnnaBridge 165:e614a9f1c9e2 244 * @param __VALUE__ Value to be written in the register
AnnaBridge 165:e614a9f1c9e2 245 * @retval None
AnnaBridge 165:e614a9f1c9e2 246 */
AnnaBridge 165:e614a9f1c9e2 247 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
AnnaBridge 165:e614a9f1c9e2 248
AnnaBridge 165:e614a9f1c9e2 249 /**
AnnaBridge 165:e614a9f1c9e2 250 * @brief Read a value in I2C register
AnnaBridge 165:e614a9f1c9e2 251 * @param __INSTANCE__ I2C Instance
AnnaBridge 165:e614a9f1c9e2 252 * @param __REG__ Register to be read
AnnaBridge 165:e614a9f1c9e2 253 * @retval Register value
AnnaBridge 165:e614a9f1c9e2 254 */
AnnaBridge 165:e614a9f1c9e2 255 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
AnnaBridge 165:e614a9f1c9e2 256 /**
AnnaBridge 165:e614a9f1c9e2 257 * @}
AnnaBridge 165:e614a9f1c9e2 258 */
AnnaBridge 165:e614a9f1c9e2 259
AnnaBridge 165:e614a9f1c9e2 260 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
AnnaBridge 165:e614a9f1c9e2 261 * @{
AnnaBridge 165:e614a9f1c9e2 262 */
AnnaBridge 165:e614a9f1c9e2 263
AnnaBridge 165:e614a9f1c9e2 264 /**
AnnaBridge 165:e614a9f1c9e2 265 * @brief Convert Peripheral Clock Frequency in Mhz.
AnnaBridge 165:e614a9f1c9e2 266 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 165:e614a9f1c9e2 267 * @retval Value of peripheral clock (in Mhz)
AnnaBridge 165:e614a9f1c9e2 268 */
AnnaBridge 165:e614a9f1c9e2 269 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
AnnaBridge 165:e614a9f1c9e2 270
AnnaBridge 165:e614a9f1c9e2 271 /**
AnnaBridge 165:e614a9f1c9e2 272 * @brief Convert Peripheral Clock Frequency in Hz.
AnnaBridge 165:e614a9f1c9e2 273 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge 165:e614a9f1c9e2 274 * @retval Value of peripheral clock (in Hz)
AnnaBridge 165:e614a9f1c9e2 275 */
AnnaBridge 165:e614a9f1c9e2 276 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
AnnaBridge 165:e614a9f1c9e2 277
AnnaBridge 165:e614a9f1c9e2 278 /**
AnnaBridge 165:e614a9f1c9e2 279 * @brief Compute I2C Clock rising time.
AnnaBridge 165:e614a9f1c9e2 280 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz).
AnnaBridge 165:e614a9f1c9e2 281 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 165:e614a9f1c9e2 282 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge 165:e614a9f1c9e2 283 */
AnnaBridge 165:e614a9f1c9e2 284 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
AnnaBridge 165:e614a9f1c9e2 285
AnnaBridge 165:e614a9f1c9e2 286 /**
AnnaBridge 165:e614a9f1c9e2 287 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 165:e614a9f1c9e2 288 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 165:e614a9f1c9e2 289 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 165:e614a9f1c9e2 290 * @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 291 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 165:e614a9f1c9e2 292 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 165:e614a9f1c9e2 293 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 165:e614a9f1c9e2 294 */
AnnaBridge 165:e614a9f1c9e2 295 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
AnnaBridge 165:e614a9f1c9e2 296 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
AnnaBridge 165:e614a9f1c9e2 297 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
AnnaBridge 165:e614a9f1c9e2 298
AnnaBridge 165:e614a9f1c9e2 299 /**
AnnaBridge 165:e614a9f1c9e2 300 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 165:e614a9f1c9e2 301 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 165:e614a9f1c9e2 302 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz).
AnnaBridge 165:e614a9f1c9e2 303 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF.
AnnaBridge 165:e614a9f1c9e2 304 */
AnnaBridge 165:e614a9f1c9e2 305 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
AnnaBridge 165:e614a9f1c9e2 306
AnnaBridge 165:e614a9f1c9e2 307 /**
AnnaBridge 165:e614a9f1c9e2 308 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value.
AnnaBridge 165:e614a9f1c9e2 309 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz).
AnnaBridge 165:e614a9f1c9e2 310 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz).
AnnaBridge 165:e614a9f1c9e2 311 * @param __DUTYCYCLE__ This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 312 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 165:e614a9f1c9e2 313 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 165:e614a9f1c9e2 314 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF
AnnaBridge 165:e614a9f1c9e2 315 */
AnnaBridge 165:e614a9f1c9e2 316 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
AnnaBridge 165:e614a9f1c9e2 317 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
AnnaBridge 165:e614a9f1c9e2 318 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
AnnaBridge 165:e614a9f1c9e2 319
AnnaBridge 165:e614a9f1c9e2 320 /**
AnnaBridge 165:e614a9f1c9e2 321 * @brief Get the Least significant bits of a 10-Bits address.
AnnaBridge 165:e614a9f1c9e2 322 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 165:e614a9f1c9e2 323 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 165:e614a9f1c9e2 324 */
AnnaBridge 165:e614a9f1c9e2 325 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
AnnaBridge 165:e614a9f1c9e2 326
AnnaBridge 165:e614a9f1c9e2 327 /**
AnnaBridge 165:e614a9f1c9e2 328 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction.
AnnaBridge 165:e614a9f1c9e2 329 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 165:e614a9f1c9e2 330 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6
AnnaBridge 165:e614a9f1c9e2 331 */
AnnaBridge 165:e614a9f1c9e2 332 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
AnnaBridge 165:e614a9f1c9e2 333
AnnaBridge 165:e614a9f1c9e2 334 /**
AnnaBridge 165:e614a9f1c9e2 335 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction.
AnnaBridge 165:e614a9f1c9e2 336 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address.
AnnaBridge 165:e614a9f1c9e2 337 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7
AnnaBridge 165:e614a9f1c9e2 338 */
AnnaBridge 165:e614a9f1c9e2 339 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
AnnaBridge 165:e614a9f1c9e2 340
AnnaBridge 165:e614a9f1c9e2 341 /**
AnnaBridge 165:e614a9f1c9e2 342 * @}
AnnaBridge 165:e614a9f1c9e2 343 */
AnnaBridge 165:e614a9f1c9e2 344
AnnaBridge 165:e614a9f1c9e2 345 /**
AnnaBridge 165:e614a9f1c9e2 346 * @}
AnnaBridge 165:e614a9f1c9e2 347 */
AnnaBridge 165:e614a9f1c9e2 348
AnnaBridge 165:e614a9f1c9e2 349 /* Exported functions --------------------------------------------------------*/
AnnaBridge 165:e614a9f1c9e2 350
AnnaBridge 165:e614a9f1c9e2 351 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
AnnaBridge 165:e614a9f1c9e2 352 * @{
AnnaBridge 165:e614a9f1c9e2 353 */
AnnaBridge 165:e614a9f1c9e2 354
AnnaBridge 165:e614a9f1c9e2 355 /** @defgroup I2C_LL_EF_Configuration Configuration
AnnaBridge 165:e614a9f1c9e2 356 * @{
AnnaBridge 165:e614a9f1c9e2 357 */
AnnaBridge 165:e614a9f1c9e2 358
AnnaBridge 165:e614a9f1c9e2 359 /**
AnnaBridge 165:e614a9f1c9e2 360 * @brief Enable I2C peripheral (PE = 1).
AnnaBridge 165:e614a9f1c9e2 361 * @rmtoll CR1 PE LL_I2C_Enable
AnnaBridge 165:e614a9f1c9e2 362 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 363 * @retval None
AnnaBridge 165:e614a9f1c9e2 364 */
AnnaBridge 165:e614a9f1c9e2 365 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 366 {
AnnaBridge 165:e614a9f1c9e2 367 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 165:e614a9f1c9e2 368 }
AnnaBridge 165:e614a9f1c9e2 369
AnnaBridge 165:e614a9f1c9e2 370 /**
AnnaBridge 165:e614a9f1c9e2 371 * @brief Disable I2C peripheral (PE = 0).
AnnaBridge 165:e614a9f1c9e2 372 * @rmtoll CR1 PE LL_I2C_Disable
AnnaBridge 165:e614a9f1c9e2 373 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 374 * @retval None
AnnaBridge 165:e614a9f1c9e2 375 */
AnnaBridge 165:e614a9f1c9e2 376 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 377 {
AnnaBridge 165:e614a9f1c9e2 378 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 165:e614a9f1c9e2 379 }
AnnaBridge 165:e614a9f1c9e2 380
AnnaBridge 165:e614a9f1c9e2 381 /**
AnnaBridge 165:e614a9f1c9e2 382 * @brief Check if the I2C peripheral is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 383 * @rmtoll CR1 PE LL_I2C_IsEnabled
AnnaBridge 165:e614a9f1c9e2 384 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 385 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 386 */
AnnaBridge 165:e614a9f1c9e2 387 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 388 {
AnnaBridge 165:e614a9f1c9e2 389 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
AnnaBridge 165:e614a9f1c9e2 390 }
AnnaBridge 165:e614a9f1c9e2 391
AnnaBridge 165:e614a9f1c9e2 392
AnnaBridge 165:e614a9f1c9e2 393 /**
AnnaBridge 165:e614a9f1c9e2 394 * @brief Enable DMA transmission requests.
AnnaBridge 165:e614a9f1c9e2 395 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX
AnnaBridge 165:e614a9f1c9e2 396 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 397 * @retval None
AnnaBridge 165:e614a9f1c9e2 398 */
AnnaBridge 165:e614a9f1c9e2 399 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 400 {
AnnaBridge 165:e614a9f1c9e2 401 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 165:e614a9f1c9e2 402 }
AnnaBridge 165:e614a9f1c9e2 403
AnnaBridge 165:e614a9f1c9e2 404 /**
AnnaBridge 165:e614a9f1c9e2 405 * @brief Disable DMA transmission requests.
AnnaBridge 165:e614a9f1c9e2 406 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX
AnnaBridge 165:e614a9f1c9e2 407 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 408 * @retval None
AnnaBridge 165:e614a9f1c9e2 409 */
AnnaBridge 165:e614a9f1c9e2 410 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 411 {
AnnaBridge 165:e614a9f1c9e2 412 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 165:e614a9f1c9e2 413 }
AnnaBridge 165:e614a9f1c9e2 414
AnnaBridge 165:e614a9f1c9e2 415 /**
AnnaBridge 165:e614a9f1c9e2 416 * @brief Check if DMA transmission requests are enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 417 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX
AnnaBridge 165:e614a9f1c9e2 418 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 419 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 420 */
AnnaBridge 165:e614a9f1c9e2 421 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 422 {
AnnaBridge 165:e614a9f1c9e2 423 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge 165:e614a9f1c9e2 424 }
AnnaBridge 165:e614a9f1c9e2 425
AnnaBridge 165:e614a9f1c9e2 426 /**
AnnaBridge 165:e614a9f1c9e2 427 * @brief Enable DMA reception requests.
AnnaBridge 165:e614a9f1c9e2 428 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX
AnnaBridge 165:e614a9f1c9e2 429 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 430 * @retval None
AnnaBridge 165:e614a9f1c9e2 431 */
AnnaBridge 165:e614a9f1c9e2 432 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 433 {
AnnaBridge 165:e614a9f1c9e2 434 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 165:e614a9f1c9e2 435 }
AnnaBridge 165:e614a9f1c9e2 436
AnnaBridge 165:e614a9f1c9e2 437 /**
AnnaBridge 165:e614a9f1c9e2 438 * @brief Disable DMA reception requests.
AnnaBridge 165:e614a9f1c9e2 439 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX
AnnaBridge 165:e614a9f1c9e2 440 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 441 * @retval None
AnnaBridge 165:e614a9f1c9e2 442 */
AnnaBridge 165:e614a9f1c9e2 443 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 444 {
AnnaBridge 165:e614a9f1c9e2 445 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
AnnaBridge 165:e614a9f1c9e2 446 }
AnnaBridge 165:e614a9f1c9e2 447
AnnaBridge 165:e614a9f1c9e2 448 /**
AnnaBridge 165:e614a9f1c9e2 449 * @brief Check if DMA reception requests are enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 450 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX
AnnaBridge 165:e614a9f1c9e2 451 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 452 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 453 */
AnnaBridge 165:e614a9f1c9e2 454 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 455 {
AnnaBridge 165:e614a9f1c9e2 456 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
AnnaBridge 165:e614a9f1c9e2 457 }
AnnaBridge 165:e614a9f1c9e2 458
AnnaBridge 165:e614a9f1c9e2 459 /**
AnnaBridge 165:e614a9f1c9e2 460 * @brief Get the data register address used for DMA transfer.
AnnaBridge 165:e614a9f1c9e2 461 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr
AnnaBridge 165:e614a9f1c9e2 462 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 463 * @retval Address of data register
AnnaBridge 165:e614a9f1c9e2 464 */
AnnaBridge 165:e614a9f1c9e2 465 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 466 {
AnnaBridge 165:e614a9f1c9e2 467 return (uint32_t) & (I2Cx->DR);
AnnaBridge 165:e614a9f1c9e2 468 }
AnnaBridge 165:e614a9f1c9e2 469
AnnaBridge 165:e614a9f1c9e2 470 /**
AnnaBridge 165:e614a9f1c9e2 471 * @brief Enable Clock stretching.
AnnaBridge 165:e614a9f1c9e2 472 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 165:e614a9f1c9e2 473 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
AnnaBridge 165:e614a9f1c9e2 474 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 475 * @retval None
AnnaBridge 165:e614a9f1c9e2 476 */
AnnaBridge 165:e614a9f1c9e2 477 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 478 {
AnnaBridge 165:e614a9f1c9e2 479 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge 165:e614a9f1c9e2 480 }
AnnaBridge 165:e614a9f1c9e2 481
AnnaBridge 165:e614a9f1c9e2 482 /**
AnnaBridge 165:e614a9f1c9e2 483 * @brief Disable Clock stretching.
AnnaBridge 165:e614a9f1c9e2 484 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 165:e614a9f1c9e2 485 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
AnnaBridge 165:e614a9f1c9e2 486 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 487 * @retval None
AnnaBridge 165:e614a9f1c9e2 488 */
AnnaBridge 165:e614a9f1c9e2 489 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 490 {
AnnaBridge 165:e614a9f1c9e2 491 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
AnnaBridge 165:e614a9f1c9e2 492 }
AnnaBridge 165:e614a9f1c9e2 493
AnnaBridge 165:e614a9f1c9e2 494 /**
AnnaBridge 165:e614a9f1c9e2 495 * @brief Check if Clock stretching is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 496 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
AnnaBridge 165:e614a9f1c9e2 497 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 498 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 499 */
AnnaBridge 165:e614a9f1c9e2 500 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 501 {
AnnaBridge 165:e614a9f1c9e2 502 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
AnnaBridge 165:e614a9f1c9e2 503 }
AnnaBridge 165:e614a9f1c9e2 504
AnnaBridge 165:e614a9f1c9e2 505 /**
AnnaBridge 165:e614a9f1c9e2 506 * @brief Enable General Call.
AnnaBridge 165:e614a9f1c9e2 507 * @note When enabled the Address 0x00 is ACKed.
AnnaBridge 165:e614a9f1c9e2 508 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall
AnnaBridge 165:e614a9f1c9e2 509 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 510 * @retval None
AnnaBridge 165:e614a9f1c9e2 511 */
AnnaBridge 165:e614a9f1c9e2 512 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 513 {
AnnaBridge 165:e614a9f1c9e2 514 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge 165:e614a9f1c9e2 515 }
AnnaBridge 165:e614a9f1c9e2 516
AnnaBridge 165:e614a9f1c9e2 517 /**
AnnaBridge 165:e614a9f1c9e2 518 * @brief Disable General Call.
AnnaBridge 165:e614a9f1c9e2 519 * @note When disabled the Address 0x00 is NACKed.
AnnaBridge 165:e614a9f1c9e2 520 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall
AnnaBridge 165:e614a9f1c9e2 521 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 522 * @retval None
AnnaBridge 165:e614a9f1c9e2 523 */
AnnaBridge 165:e614a9f1c9e2 524 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 525 {
AnnaBridge 165:e614a9f1c9e2 526 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
AnnaBridge 165:e614a9f1c9e2 527 }
AnnaBridge 165:e614a9f1c9e2 528
AnnaBridge 165:e614a9f1c9e2 529 /**
AnnaBridge 165:e614a9f1c9e2 530 * @brief Check if General Call is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 531 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall
AnnaBridge 165:e614a9f1c9e2 532 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 533 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 534 */
AnnaBridge 165:e614a9f1c9e2 535 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 536 {
AnnaBridge 165:e614a9f1c9e2 537 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
AnnaBridge 165:e614a9f1c9e2 538 }
AnnaBridge 165:e614a9f1c9e2 539
AnnaBridge 165:e614a9f1c9e2 540 /**
AnnaBridge 165:e614a9f1c9e2 541 * @brief Set the Own Address1.
AnnaBridge 165:e614a9f1c9e2 542 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n
AnnaBridge 165:e614a9f1c9e2 543 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n
AnnaBridge 165:e614a9f1c9e2 544 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n
AnnaBridge 165:e614a9f1c9e2 545 * OAR1 ADDMODE LL_I2C_SetOwnAddress1
AnnaBridge 165:e614a9f1c9e2 546 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 547 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
AnnaBridge 165:e614a9f1c9e2 548 * @param OwnAddrSize This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 549 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
AnnaBridge 165:e614a9f1c9e2 550 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
AnnaBridge 165:e614a9f1c9e2 551 * @retval None
AnnaBridge 165:e614a9f1c9e2 552 */
AnnaBridge 165:e614a9f1c9e2 553 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
AnnaBridge 165:e614a9f1c9e2 554 {
AnnaBridge 165:e614a9f1c9e2 555 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
AnnaBridge 165:e614a9f1c9e2 556 }
AnnaBridge 165:e614a9f1c9e2 557
AnnaBridge 165:e614a9f1c9e2 558 /**
AnnaBridge 165:e614a9f1c9e2 559 * @brief Set the 7bits Own Address2.
AnnaBridge 165:e614a9f1c9e2 560 * @note This action has no effect if own address2 is enabled.
AnnaBridge 165:e614a9f1c9e2 561 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2
AnnaBridge 165:e614a9f1c9e2 562 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 563 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F.
AnnaBridge 165:e614a9f1c9e2 564 * @retval None
AnnaBridge 165:e614a9f1c9e2 565 */
AnnaBridge 165:e614a9f1c9e2 566 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
AnnaBridge 165:e614a9f1c9e2 567 {
AnnaBridge 165:e614a9f1c9e2 568 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
AnnaBridge 165:e614a9f1c9e2 569 }
AnnaBridge 165:e614a9f1c9e2 570
AnnaBridge 165:e614a9f1c9e2 571 /**
AnnaBridge 165:e614a9f1c9e2 572 * @brief Enable acknowledge on Own Address2 match address.
AnnaBridge 165:e614a9f1c9e2 573 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2
AnnaBridge 165:e614a9f1c9e2 574 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 575 * @retval None
AnnaBridge 165:e614a9f1c9e2 576 */
AnnaBridge 165:e614a9f1c9e2 577 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 578 {
AnnaBridge 165:e614a9f1c9e2 579 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge 165:e614a9f1c9e2 580 }
AnnaBridge 165:e614a9f1c9e2 581
AnnaBridge 165:e614a9f1c9e2 582 /**
AnnaBridge 165:e614a9f1c9e2 583 * @brief Disable acknowledge on Own Address2 match address.
AnnaBridge 165:e614a9f1c9e2 584 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2
AnnaBridge 165:e614a9f1c9e2 585 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 586 * @retval None
AnnaBridge 165:e614a9f1c9e2 587 */
AnnaBridge 165:e614a9f1c9e2 588 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 589 {
AnnaBridge 165:e614a9f1c9e2 590 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
AnnaBridge 165:e614a9f1c9e2 591 }
AnnaBridge 165:e614a9f1c9e2 592
AnnaBridge 165:e614a9f1c9e2 593 /**
AnnaBridge 165:e614a9f1c9e2 594 * @brief Check if Own Address1 acknowledge is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 595 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2
AnnaBridge 165:e614a9f1c9e2 596 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 597 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 598 */
AnnaBridge 165:e614a9f1c9e2 599 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 600 {
AnnaBridge 165:e614a9f1c9e2 601 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
AnnaBridge 165:e614a9f1c9e2 602 }
AnnaBridge 165:e614a9f1c9e2 603
AnnaBridge 165:e614a9f1c9e2 604 /**
AnnaBridge 165:e614a9f1c9e2 605 * @brief Configure the Peripheral clock frequency.
AnnaBridge 165:e614a9f1c9e2 606 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock
AnnaBridge 165:e614a9f1c9e2 607 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 608 * @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge 165:e614a9f1c9e2 609 * @retval None
AnnaBridge 165:e614a9f1c9e2 610 */
AnnaBridge 165:e614a9f1c9e2 611 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
AnnaBridge 165:e614a9f1c9e2 612 {
AnnaBridge 165:e614a9f1c9e2 613 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
AnnaBridge 165:e614a9f1c9e2 614 }
AnnaBridge 165:e614a9f1c9e2 615
AnnaBridge 165:e614a9f1c9e2 616 /**
AnnaBridge 165:e614a9f1c9e2 617 * @brief Get the Peripheral clock frequency.
AnnaBridge 165:e614a9f1c9e2 618 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock
AnnaBridge 165:e614a9f1c9e2 619 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 620 * @retval Value of Peripheral Clock (in Hz)
AnnaBridge 165:e614a9f1c9e2 621 */
AnnaBridge 165:e614a9f1c9e2 622 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 623 {
AnnaBridge 165:e614a9f1c9e2 624 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
AnnaBridge 165:e614a9f1c9e2 625 }
AnnaBridge 165:e614a9f1c9e2 626
AnnaBridge 165:e614a9f1c9e2 627 /**
AnnaBridge 165:e614a9f1c9e2 628 * @brief Configure the Duty cycle (Fast mode only).
AnnaBridge 165:e614a9f1c9e2 629 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle
AnnaBridge 165:e614a9f1c9e2 630 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 631 * @param DutyCycle This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 632 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 165:e614a9f1c9e2 633 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 165:e614a9f1c9e2 634 * @retval None
AnnaBridge 165:e614a9f1c9e2 635 */
AnnaBridge 165:e614a9f1c9e2 636 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
AnnaBridge 165:e614a9f1c9e2 637 {
AnnaBridge 165:e614a9f1c9e2 638 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
AnnaBridge 165:e614a9f1c9e2 639 }
AnnaBridge 165:e614a9f1c9e2 640
AnnaBridge 165:e614a9f1c9e2 641 /**
AnnaBridge 165:e614a9f1c9e2 642 * @brief Get the Duty cycle (Fast mode only).
AnnaBridge 165:e614a9f1c9e2 643 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle
AnnaBridge 165:e614a9f1c9e2 644 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 645 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 646 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 165:e614a9f1c9e2 647 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 165:e614a9f1c9e2 648 */
AnnaBridge 165:e614a9f1c9e2 649 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 650 {
AnnaBridge 165:e614a9f1c9e2 651 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
AnnaBridge 165:e614a9f1c9e2 652 }
AnnaBridge 165:e614a9f1c9e2 653
AnnaBridge 165:e614a9f1c9e2 654 /**
AnnaBridge 165:e614a9f1c9e2 655 * @brief Configure the I2C master clock speed mode.
AnnaBridge 165:e614a9f1c9e2 656 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode
AnnaBridge 165:e614a9f1c9e2 657 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 658 * @param ClockSpeedMode This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 659 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge 165:e614a9f1c9e2 660 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge 165:e614a9f1c9e2 661 * @retval None
AnnaBridge 165:e614a9f1c9e2 662 */
AnnaBridge 165:e614a9f1c9e2 663 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
AnnaBridge 165:e614a9f1c9e2 664 {
AnnaBridge 165:e614a9f1c9e2 665 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
AnnaBridge 165:e614a9f1c9e2 666 }
AnnaBridge 165:e614a9f1c9e2 667
AnnaBridge 165:e614a9f1c9e2 668 /**
AnnaBridge 165:e614a9f1c9e2 669 * @brief Get the the I2C master speed mode.
AnnaBridge 165:e614a9f1c9e2 670 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode
AnnaBridge 165:e614a9f1c9e2 671 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 672 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 673 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE
AnnaBridge 165:e614a9f1c9e2 674 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE
AnnaBridge 165:e614a9f1c9e2 675 */
AnnaBridge 165:e614a9f1c9e2 676 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 677 {
AnnaBridge 165:e614a9f1c9e2 678 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
AnnaBridge 165:e614a9f1c9e2 679 }
AnnaBridge 165:e614a9f1c9e2 680
AnnaBridge 165:e614a9f1c9e2 681 /**
AnnaBridge 165:e614a9f1c9e2 682 * @brief Configure the SCL, SDA rising time.
AnnaBridge 165:e614a9f1c9e2 683 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 165:e614a9f1c9e2 684 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime
AnnaBridge 165:e614a9f1c9e2 685 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 686 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F.
AnnaBridge 165:e614a9f1c9e2 687 * @retval None
AnnaBridge 165:e614a9f1c9e2 688 */
AnnaBridge 165:e614a9f1c9e2 689 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
AnnaBridge 165:e614a9f1c9e2 690 {
AnnaBridge 165:e614a9f1c9e2 691 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
AnnaBridge 165:e614a9f1c9e2 692 }
AnnaBridge 165:e614a9f1c9e2 693
AnnaBridge 165:e614a9f1c9e2 694 /**
AnnaBridge 165:e614a9f1c9e2 695 * @brief Get the SCL, SDA rising time.
AnnaBridge 165:e614a9f1c9e2 696 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime
AnnaBridge 165:e614a9f1c9e2 697 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 698 * @retval Value between Min_Data=0x02 and Max_Data=0x3F
AnnaBridge 165:e614a9f1c9e2 699 */
AnnaBridge 165:e614a9f1c9e2 700 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 701 {
AnnaBridge 165:e614a9f1c9e2 702 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
AnnaBridge 165:e614a9f1c9e2 703 }
AnnaBridge 165:e614a9f1c9e2 704
AnnaBridge 165:e614a9f1c9e2 705 /**
AnnaBridge 165:e614a9f1c9e2 706 * @brief Configure the SCL high and low period.
AnnaBridge 165:e614a9f1c9e2 707 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 165:e614a9f1c9e2 708 * @rmtoll CCR CCR LL_I2C_SetClockPeriod
AnnaBridge 165:e614a9f1c9e2 709 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 710 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 165:e614a9f1c9e2 711 * @retval None
AnnaBridge 165:e614a9f1c9e2 712 */
AnnaBridge 165:e614a9f1c9e2 713 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
AnnaBridge 165:e614a9f1c9e2 714 {
AnnaBridge 165:e614a9f1c9e2 715 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
AnnaBridge 165:e614a9f1c9e2 716 }
AnnaBridge 165:e614a9f1c9e2 717
AnnaBridge 165:e614a9f1c9e2 718 /**
AnnaBridge 165:e614a9f1c9e2 719 * @brief Get the SCL high and low period.
AnnaBridge 165:e614a9f1c9e2 720 * @rmtoll CCR CCR LL_I2C_GetClockPeriod
AnnaBridge 165:e614a9f1c9e2 721 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 722 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001.
AnnaBridge 165:e614a9f1c9e2 723 */
AnnaBridge 165:e614a9f1c9e2 724 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 725 {
AnnaBridge 165:e614a9f1c9e2 726 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
AnnaBridge 165:e614a9f1c9e2 727 }
AnnaBridge 165:e614a9f1c9e2 728
AnnaBridge 165:e614a9f1c9e2 729 /**
AnnaBridge 165:e614a9f1c9e2 730 * @brief Configure the SCL speed.
AnnaBridge 165:e614a9f1c9e2 731 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
AnnaBridge 165:e614a9f1c9e2 732 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n
AnnaBridge 165:e614a9f1c9e2 733 * TRISE TRISE LL_I2C_ConfigSpeed\n
AnnaBridge 165:e614a9f1c9e2 734 * CCR FS LL_I2C_ConfigSpeed\n
AnnaBridge 165:e614a9f1c9e2 735 * CCR DUTY LL_I2C_ConfigSpeed\n
AnnaBridge 165:e614a9f1c9e2 736 * CCR CCR LL_I2C_ConfigSpeed
AnnaBridge 165:e614a9f1c9e2 737 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 738 * @param PeriphClock Peripheral Clock (in Hz)
AnnaBridge 165:e614a9f1c9e2 739 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz).
AnnaBridge 165:e614a9f1c9e2 740 * @param DutyCycle This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 741 * @arg @ref LL_I2C_DUTYCYCLE_2
AnnaBridge 165:e614a9f1c9e2 742 * @arg @ref LL_I2C_DUTYCYCLE_16_9
AnnaBridge 165:e614a9f1c9e2 743 * @retval None
AnnaBridge 165:e614a9f1c9e2 744 */
AnnaBridge 165:e614a9f1c9e2 745 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
AnnaBridge 165:e614a9f1c9e2 746 uint32_t DutyCycle)
AnnaBridge 165:e614a9f1c9e2 747 {
AnnaBridge 165:e614a9f1c9e2 748 register uint32_t freqrange = 0x0U;
AnnaBridge 165:e614a9f1c9e2 749 register uint32_t clockconfig = 0x0U;
AnnaBridge 165:e614a9f1c9e2 750
AnnaBridge 165:e614a9f1c9e2 751 /* Compute frequency range */
AnnaBridge 165:e614a9f1c9e2 752 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
AnnaBridge 165:e614a9f1c9e2 753
AnnaBridge 165:e614a9f1c9e2 754 /* Configure I2Cx: Frequency range register */
AnnaBridge 165:e614a9f1c9e2 755 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
AnnaBridge 165:e614a9f1c9e2 756
AnnaBridge 165:e614a9f1c9e2 757 /* Configure I2Cx: Rise Time register */
AnnaBridge 165:e614a9f1c9e2 758 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
AnnaBridge 165:e614a9f1c9e2 759
AnnaBridge 165:e614a9f1c9e2 760 /* Configure Speed mode, Duty Cycle and Clock control register value */
AnnaBridge 165:e614a9f1c9e2 761 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
AnnaBridge 165:e614a9f1c9e2 762 {
AnnaBridge 165:e614a9f1c9e2 763 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
AnnaBridge 165:e614a9f1c9e2 764 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
AnnaBridge 165:e614a9f1c9e2 765 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
AnnaBridge 165:e614a9f1c9e2 766 DutyCycle;
AnnaBridge 165:e614a9f1c9e2 767 }
AnnaBridge 165:e614a9f1c9e2 768 else
AnnaBridge 165:e614a9f1c9e2 769 {
AnnaBridge 165:e614a9f1c9e2 770 /* Set Speed mode at standard for Clock Speed request in standard clock range */
AnnaBridge 165:e614a9f1c9e2 771 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
AnnaBridge 165:e614a9f1c9e2 772 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
AnnaBridge 165:e614a9f1c9e2 773 }
AnnaBridge 165:e614a9f1c9e2 774
AnnaBridge 165:e614a9f1c9e2 775 /* Configure I2Cx: Clock control register */
AnnaBridge 165:e614a9f1c9e2 776 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
AnnaBridge 165:e614a9f1c9e2 777 }
AnnaBridge 165:e614a9f1c9e2 778
AnnaBridge 165:e614a9f1c9e2 779 /**
AnnaBridge 165:e614a9f1c9e2 780 * @brief Configure peripheral mode.
AnnaBridge 165:e614a9f1c9e2 781 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 782 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 783 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n
AnnaBridge 165:e614a9f1c9e2 784 * CR1 SMBTYPE LL_I2C_SetMode\n
AnnaBridge 165:e614a9f1c9e2 785 * CR1 ENARP LL_I2C_SetMode
AnnaBridge 165:e614a9f1c9e2 786 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 787 * @param PeripheralMode This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 788 * @arg @ref LL_I2C_MODE_I2C
AnnaBridge 165:e614a9f1c9e2 789 * @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge 165:e614a9f1c9e2 790 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge 165:e614a9f1c9e2 791 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge 165:e614a9f1c9e2 792 * @retval None
AnnaBridge 165:e614a9f1c9e2 793 */
AnnaBridge 165:e614a9f1c9e2 794 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
AnnaBridge 165:e614a9f1c9e2 795 {
AnnaBridge 165:e614a9f1c9e2 796 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
AnnaBridge 165:e614a9f1c9e2 797 }
AnnaBridge 165:e614a9f1c9e2 798
AnnaBridge 165:e614a9f1c9e2 799 /**
AnnaBridge 165:e614a9f1c9e2 800 * @brief Get peripheral mode.
AnnaBridge 165:e614a9f1c9e2 801 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 802 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 803 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n
AnnaBridge 165:e614a9f1c9e2 804 * CR1 SMBTYPE LL_I2C_GetMode\n
AnnaBridge 165:e614a9f1c9e2 805 * CR1 ENARP LL_I2C_GetMode
AnnaBridge 165:e614a9f1c9e2 806 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 807 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 808 * @arg @ref LL_I2C_MODE_I2C
AnnaBridge 165:e614a9f1c9e2 809 * @arg @ref LL_I2C_MODE_SMBUS_HOST
AnnaBridge 165:e614a9f1c9e2 810 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
AnnaBridge 165:e614a9f1c9e2 811 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
AnnaBridge 165:e614a9f1c9e2 812 */
AnnaBridge 165:e614a9f1c9e2 813 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 814 {
AnnaBridge 165:e614a9f1c9e2 815 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
AnnaBridge 165:e614a9f1c9e2 816 }
AnnaBridge 165:e614a9f1c9e2 817
AnnaBridge 165:e614a9f1c9e2 818 /**
AnnaBridge 165:e614a9f1c9e2 819 * @brief Enable SMBus alert (Host or Device mode)
AnnaBridge 165:e614a9f1c9e2 820 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 821 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 822 * @note SMBus Device mode:
AnnaBridge 165:e614a9f1c9e2 823 * - SMBus Alert pin is drived low and
AnnaBridge 165:e614a9f1c9e2 824 * Alert Response Address Header acknowledge is enabled.
AnnaBridge 165:e614a9f1c9e2 825 * SMBus Host mode:
AnnaBridge 165:e614a9f1c9e2 826 * - SMBus Alert pin management is supported.
AnnaBridge 165:e614a9f1c9e2 827 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert
AnnaBridge 165:e614a9f1c9e2 828 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 829 * @retval None
AnnaBridge 165:e614a9f1c9e2 830 */
AnnaBridge 165:e614a9f1c9e2 831 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 832 {
AnnaBridge 165:e614a9f1c9e2 833 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge 165:e614a9f1c9e2 834 }
AnnaBridge 165:e614a9f1c9e2 835
AnnaBridge 165:e614a9f1c9e2 836 /**
AnnaBridge 165:e614a9f1c9e2 837 * @brief Disable SMBus alert (Host or Device mode)
AnnaBridge 165:e614a9f1c9e2 838 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 839 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 840 * @note SMBus Device mode:
AnnaBridge 165:e614a9f1c9e2 841 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
AnnaBridge 165:e614a9f1c9e2 842 * Alert Response Address Header acknowledge is disabled.
AnnaBridge 165:e614a9f1c9e2 843 * SMBus Host mode:
AnnaBridge 165:e614a9f1c9e2 844 * - SMBus Alert pin management is not supported.
AnnaBridge 165:e614a9f1c9e2 845 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert
AnnaBridge 165:e614a9f1c9e2 846 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 847 * @retval None
AnnaBridge 165:e614a9f1c9e2 848 */
AnnaBridge 165:e614a9f1c9e2 849 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 850 {
AnnaBridge 165:e614a9f1c9e2 851 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
AnnaBridge 165:e614a9f1c9e2 852 }
AnnaBridge 165:e614a9f1c9e2 853
AnnaBridge 165:e614a9f1c9e2 854 /**
AnnaBridge 165:e614a9f1c9e2 855 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 856 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 857 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 858 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert
AnnaBridge 165:e614a9f1c9e2 859 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 860 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 861 */
AnnaBridge 165:e614a9f1c9e2 862 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 863 {
AnnaBridge 165:e614a9f1c9e2 864 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
AnnaBridge 165:e614a9f1c9e2 865 }
AnnaBridge 165:e614a9f1c9e2 866
AnnaBridge 165:e614a9f1c9e2 867 /**
AnnaBridge 165:e614a9f1c9e2 868 * @brief Enable SMBus Packet Error Calculation (PEC).
AnnaBridge 165:e614a9f1c9e2 869 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 870 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 871 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC
AnnaBridge 165:e614a9f1c9e2 872 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 873 * @retval None
AnnaBridge 165:e614a9f1c9e2 874 */
AnnaBridge 165:e614a9f1c9e2 875 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 876 {
AnnaBridge 165:e614a9f1c9e2 877 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge 165:e614a9f1c9e2 878 }
AnnaBridge 165:e614a9f1c9e2 879
AnnaBridge 165:e614a9f1c9e2 880 /**
AnnaBridge 165:e614a9f1c9e2 881 * @brief Disable SMBus Packet Error Calculation (PEC).
AnnaBridge 165:e614a9f1c9e2 882 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 883 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 884 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC
AnnaBridge 165:e614a9f1c9e2 885 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 886 * @retval None
AnnaBridge 165:e614a9f1c9e2 887 */
AnnaBridge 165:e614a9f1c9e2 888 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 889 {
AnnaBridge 165:e614a9f1c9e2 890 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
AnnaBridge 165:e614a9f1c9e2 891 }
AnnaBridge 165:e614a9f1c9e2 892
AnnaBridge 165:e614a9f1c9e2 893 /**
AnnaBridge 165:e614a9f1c9e2 894 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 895 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 896 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 897 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC
AnnaBridge 165:e614a9f1c9e2 898 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 899 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 900 */
AnnaBridge 165:e614a9f1c9e2 901 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 902 {
AnnaBridge 165:e614a9f1c9e2 903 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
AnnaBridge 165:e614a9f1c9e2 904 }
AnnaBridge 165:e614a9f1c9e2 905
AnnaBridge 165:e614a9f1c9e2 906 /**
AnnaBridge 165:e614a9f1c9e2 907 * @}
AnnaBridge 165:e614a9f1c9e2 908 */
AnnaBridge 165:e614a9f1c9e2 909
AnnaBridge 165:e614a9f1c9e2 910 /** @defgroup I2C_LL_EF_IT_Management IT_Management
AnnaBridge 165:e614a9f1c9e2 911 * @{
AnnaBridge 165:e614a9f1c9e2 912 */
AnnaBridge 165:e614a9f1c9e2 913
AnnaBridge 165:e614a9f1c9e2 914 /**
AnnaBridge 165:e614a9f1c9e2 915 * @brief Enable TXE interrupt.
AnnaBridge 165:e614a9f1c9e2 916 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n
AnnaBridge 165:e614a9f1c9e2 917 * CR2 ITBUFEN LL_I2C_EnableIT_TX
AnnaBridge 165:e614a9f1c9e2 918 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 919 * @retval None
AnnaBridge 165:e614a9f1c9e2 920 */
AnnaBridge 165:e614a9f1c9e2 921 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 922 {
AnnaBridge 165:e614a9f1c9e2 923 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 165:e614a9f1c9e2 924 }
AnnaBridge 165:e614a9f1c9e2 925
AnnaBridge 165:e614a9f1c9e2 926 /**
AnnaBridge 165:e614a9f1c9e2 927 * @brief Disable TXE interrupt.
AnnaBridge 165:e614a9f1c9e2 928 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n
AnnaBridge 165:e614a9f1c9e2 929 * CR2 ITBUFEN LL_I2C_DisableIT_TX
AnnaBridge 165:e614a9f1c9e2 930 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 931 * @retval None
AnnaBridge 165:e614a9f1c9e2 932 */
AnnaBridge 165:e614a9f1c9e2 933 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 934 {
AnnaBridge 165:e614a9f1c9e2 935 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 165:e614a9f1c9e2 936 }
AnnaBridge 165:e614a9f1c9e2 937
AnnaBridge 165:e614a9f1c9e2 938 /**
AnnaBridge 165:e614a9f1c9e2 939 * @brief Check if the TXE Interrupt is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 940 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n
AnnaBridge 165:e614a9f1c9e2 941 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX
AnnaBridge 165:e614a9f1c9e2 942 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 943 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 944 */
AnnaBridge 165:e614a9f1c9e2 945 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 946 {
AnnaBridge 165:e614a9f1c9e2 947 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
AnnaBridge 165:e614a9f1c9e2 948 }
AnnaBridge 165:e614a9f1c9e2 949
AnnaBridge 165:e614a9f1c9e2 950 /**
AnnaBridge 165:e614a9f1c9e2 951 * @brief Enable RXNE interrupt.
AnnaBridge 165:e614a9f1c9e2 952 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n
AnnaBridge 165:e614a9f1c9e2 953 * CR2 ITBUFEN LL_I2C_EnableIT_RX
AnnaBridge 165:e614a9f1c9e2 954 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 955 * @retval None
AnnaBridge 165:e614a9f1c9e2 956 */
AnnaBridge 165:e614a9f1c9e2 957 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 958 {
AnnaBridge 165:e614a9f1c9e2 959 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 165:e614a9f1c9e2 960 }
AnnaBridge 165:e614a9f1c9e2 961
AnnaBridge 165:e614a9f1c9e2 962 /**
AnnaBridge 165:e614a9f1c9e2 963 * @brief Disable RXNE interrupt.
AnnaBridge 165:e614a9f1c9e2 964 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n
AnnaBridge 165:e614a9f1c9e2 965 * CR2 ITBUFEN LL_I2C_DisableIT_RX
AnnaBridge 165:e614a9f1c9e2 966 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 967 * @retval None
AnnaBridge 165:e614a9f1c9e2 968 */
AnnaBridge 165:e614a9f1c9e2 969 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 970 {
AnnaBridge 165:e614a9f1c9e2 971 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
AnnaBridge 165:e614a9f1c9e2 972 }
AnnaBridge 165:e614a9f1c9e2 973
AnnaBridge 165:e614a9f1c9e2 974 /**
AnnaBridge 165:e614a9f1c9e2 975 * @brief Check if the RXNE Interrupt is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 976 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n
AnnaBridge 165:e614a9f1c9e2 977 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX
AnnaBridge 165:e614a9f1c9e2 978 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 979 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 980 */
AnnaBridge 165:e614a9f1c9e2 981 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 982 {
AnnaBridge 165:e614a9f1c9e2 983 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
AnnaBridge 165:e614a9f1c9e2 984 }
AnnaBridge 165:e614a9f1c9e2 985
AnnaBridge 165:e614a9f1c9e2 986 /**
AnnaBridge 165:e614a9f1c9e2 987 * @brief Enable Events interrupts.
AnnaBridge 165:e614a9f1c9e2 988 * @note Any of these events will generate interrupt :
AnnaBridge 165:e614a9f1c9e2 989 * Start Bit (SB)
AnnaBridge 165:e614a9f1c9e2 990 * Address sent, Address matched (ADDR)
AnnaBridge 165:e614a9f1c9e2 991 * 10-bit header sent (ADD10)
AnnaBridge 165:e614a9f1c9e2 992 * Stop detection (STOPF)
AnnaBridge 165:e614a9f1c9e2 993 * Byte transfer finished (BTF)
AnnaBridge 165:e614a9f1c9e2 994 *
AnnaBridge 165:e614a9f1c9e2 995 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) :
AnnaBridge 165:e614a9f1c9e2 996 * Receive buffer not empty (RXNE)
AnnaBridge 165:e614a9f1c9e2 997 * Transmit buffer empty (TXE)
AnnaBridge 165:e614a9f1c9e2 998 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT
AnnaBridge 165:e614a9f1c9e2 999 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1000 * @retval None
AnnaBridge 165:e614a9f1c9e2 1001 */
AnnaBridge 165:e614a9f1c9e2 1002 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1003 {
AnnaBridge 165:e614a9f1c9e2 1004 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge 165:e614a9f1c9e2 1005 }
AnnaBridge 165:e614a9f1c9e2 1006
AnnaBridge 165:e614a9f1c9e2 1007 /**
AnnaBridge 165:e614a9f1c9e2 1008 * @brief Disable Events interrupts.
AnnaBridge 165:e614a9f1c9e2 1009 * @note Any of these events will generate interrupt :
AnnaBridge 165:e614a9f1c9e2 1010 * Start Bit (SB)
AnnaBridge 165:e614a9f1c9e2 1011 * Address sent, Address matched (ADDR)
AnnaBridge 165:e614a9f1c9e2 1012 * 10-bit header sent (ADD10)
AnnaBridge 165:e614a9f1c9e2 1013 * Stop detection (STOPF)
AnnaBridge 165:e614a9f1c9e2 1014 * Byte transfer finished (BTF)
AnnaBridge 165:e614a9f1c9e2 1015 * Receive buffer not empty (RXNE)
AnnaBridge 165:e614a9f1c9e2 1016 * Transmit buffer empty (TXE)
AnnaBridge 165:e614a9f1c9e2 1017 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT
AnnaBridge 165:e614a9f1c9e2 1018 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1019 * @retval None
AnnaBridge 165:e614a9f1c9e2 1020 */
AnnaBridge 165:e614a9f1c9e2 1021 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1022 {
AnnaBridge 165:e614a9f1c9e2 1023 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
AnnaBridge 165:e614a9f1c9e2 1024 }
AnnaBridge 165:e614a9f1c9e2 1025
AnnaBridge 165:e614a9f1c9e2 1026 /**
AnnaBridge 165:e614a9f1c9e2 1027 * @brief Check if Events interrupts are enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 1028 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT
AnnaBridge 165:e614a9f1c9e2 1029 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1030 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1031 */
AnnaBridge 165:e614a9f1c9e2 1032 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1033 {
AnnaBridge 165:e614a9f1c9e2 1034 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
AnnaBridge 165:e614a9f1c9e2 1035 }
AnnaBridge 165:e614a9f1c9e2 1036
AnnaBridge 165:e614a9f1c9e2 1037 /**
AnnaBridge 165:e614a9f1c9e2 1038 * @brief Enable Buffer interrupts.
AnnaBridge 165:e614a9f1c9e2 1039 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) :
AnnaBridge 165:e614a9f1c9e2 1040 * Receive buffer not empty (RXNE)
AnnaBridge 165:e614a9f1c9e2 1041 * Transmit buffer empty (TXE)
AnnaBridge 165:e614a9f1c9e2 1042 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF
AnnaBridge 165:e614a9f1c9e2 1043 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1044 * @retval None
AnnaBridge 165:e614a9f1c9e2 1045 */
AnnaBridge 165:e614a9f1c9e2 1046 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1047 {
AnnaBridge 165:e614a9f1c9e2 1048 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge 165:e614a9f1c9e2 1049 }
AnnaBridge 165:e614a9f1c9e2 1050
AnnaBridge 165:e614a9f1c9e2 1051 /**
AnnaBridge 165:e614a9f1c9e2 1052 * @brief Disable Buffer interrupts.
AnnaBridge 165:e614a9f1c9e2 1053 * @note Any of these Buffer events will generate interrupt :
AnnaBridge 165:e614a9f1c9e2 1054 * Receive buffer not empty (RXNE)
AnnaBridge 165:e614a9f1c9e2 1055 * Transmit buffer empty (TXE)
AnnaBridge 165:e614a9f1c9e2 1056 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF
AnnaBridge 165:e614a9f1c9e2 1057 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1058 * @retval None
AnnaBridge 165:e614a9f1c9e2 1059 */
AnnaBridge 165:e614a9f1c9e2 1060 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1061 {
AnnaBridge 165:e614a9f1c9e2 1062 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
AnnaBridge 165:e614a9f1c9e2 1063 }
AnnaBridge 165:e614a9f1c9e2 1064
AnnaBridge 165:e614a9f1c9e2 1065 /**
AnnaBridge 165:e614a9f1c9e2 1066 * @brief Check if Buffer interrupts are enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 1067 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF
AnnaBridge 165:e614a9f1c9e2 1068 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1069 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1070 */
AnnaBridge 165:e614a9f1c9e2 1071 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1072 {
AnnaBridge 165:e614a9f1c9e2 1073 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
AnnaBridge 165:e614a9f1c9e2 1074 }
AnnaBridge 165:e614a9f1c9e2 1075
AnnaBridge 165:e614a9f1c9e2 1076 /**
AnnaBridge 165:e614a9f1c9e2 1077 * @brief Enable Error interrupts.
AnnaBridge 165:e614a9f1c9e2 1078 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1079 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1080 * @note Any of these errors will generate interrupt :
AnnaBridge 165:e614a9f1c9e2 1081 * Bus Error detection (BERR)
AnnaBridge 165:e614a9f1c9e2 1082 * Arbitration Loss (ARLO)
AnnaBridge 165:e614a9f1c9e2 1083 * Acknowledge Failure(AF)
AnnaBridge 165:e614a9f1c9e2 1084 * Overrun/Underrun (OVR)
AnnaBridge 165:e614a9f1c9e2 1085 * SMBus Timeout detection (TIMEOUT)
AnnaBridge 165:e614a9f1c9e2 1086 * SMBus PEC error detection (PECERR)
AnnaBridge 165:e614a9f1c9e2 1087 * SMBus Alert pin event detection (SMBALERT)
AnnaBridge 165:e614a9f1c9e2 1088 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR
AnnaBridge 165:e614a9f1c9e2 1089 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1090 * @retval None
AnnaBridge 165:e614a9f1c9e2 1091 */
AnnaBridge 165:e614a9f1c9e2 1092 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1093 {
AnnaBridge 165:e614a9f1c9e2 1094 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge 165:e614a9f1c9e2 1095 }
AnnaBridge 165:e614a9f1c9e2 1096
AnnaBridge 165:e614a9f1c9e2 1097 /**
AnnaBridge 165:e614a9f1c9e2 1098 * @brief Disable Error interrupts.
AnnaBridge 165:e614a9f1c9e2 1099 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1100 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1101 * @note Any of these errors will generate interrupt :
AnnaBridge 165:e614a9f1c9e2 1102 * Bus Error detection (BERR)
AnnaBridge 165:e614a9f1c9e2 1103 * Arbitration Loss (ARLO)
AnnaBridge 165:e614a9f1c9e2 1104 * Acknowledge Failure(AF)
AnnaBridge 165:e614a9f1c9e2 1105 * Overrun/Underrun (OVR)
AnnaBridge 165:e614a9f1c9e2 1106 * SMBus Timeout detection (TIMEOUT)
AnnaBridge 165:e614a9f1c9e2 1107 * SMBus PEC error detection (PECERR)
AnnaBridge 165:e614a9f1c9e2 1108 * SMBus Alert pin event detection (SMBALERT)
AnnaBridge 165:e614a9f1c9e2 1109 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR
AnnaBridge 165:e614a9f1c9e2 1110 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1111 * @retval None
AnnaBridge 165:e614a9f1c9e2 1112 */
AnnaBridge 165:e614a9f1c9e2 1113 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1114 {
AnnaBridge 165:e614a9f1c9e2 1115 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
AnnaBridge 165:e614a9f1c9e2 1116 }
AnnaBridge 165:e614a9f1c9e2 1117
AnnaBridge 165:e614a9f1c9e2 1118 /**
AnnaBridge 165:e614a9f1c9e2 1119 * @brief Check if Error interrupts are enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 1120 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR
AnnaBridge 165:e614a9f1c9e2 1121 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1122 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1123 */
AnnaBridge 165:e614a9f1c9e2 1124 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1125 {
AnnaBridge 165:e614a9f1c9e2 1126 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
AnnaBridge 165:e614a9f1c9e2 1127 }
AnnaBridge 165:e614a9f1c9e2 1128
AnnaBridge 165:e614a9f1c9e2 1129 /**
AnnaBridge 165:e614a9f1c9e2 1130 * @}
AnnaBridge 165:e614a9f1c9e2 1131 */
AnnaBridge 165:e614a9f1c9e2 1132
AnnaBridge 165:e614a9f1c9e2 1133 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
AnnaBridge 165:e614a9f1c9e2 1134 * @{
AnnaBridge 165:e614a9f1c9e2 1135 */
AnnaBridge 165:e614a9f1c9e2 1136
AnnaBridge 165:e614a9f1c9e2 1137 /**
AnnaBridge 165:e614a9f1c9e2 1138 * @brief Indicate the status of Transmit data register empty flag.
AnnaBridge 165:e614a9f1c9e2 1139 * @note RESET: When next data is written in Transmit data register.
AnnaBridge 165:e614a9f1c9e2 1140 * SET: When Transmit data register is empty.
AnnaBridge 165:e614a9f1c9e2 1141 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE
AnnaBridge 165:e614a9f1c9e2 1142 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1143 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1144 */
AnnaBridge 165:e614a9f1c9e2 1145 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1146 {
AnnaBridge 165:e614a9f1c9e2 1147 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
AnnaBridge 165:e614a9f1c9e2 1148 }
AnnaBridge 165:e614a9f1c9e2 1149
AnnaBridge 165:e614a9f1c9e2 1150 /**
AnnaBridge 165:e614a9f1c9e2 1151 * @brief Indicate the status of Byte Transfer Finished flag.
AnnaBridge 165:e614a9f1c9e2 1152 * RESET: When Data byte transfer not done.
AnnaBridge 165:e614a9f1c9e2 1153 * SET: When Data byte transfer succeeded.
AnnaBridge 165:e614a9f1c9e2 1154 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF
AnnaBridge 165:e614a9f1c9e2 1155 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1156 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1157 */
AnnaBridge 165:e614a9f1c9e2 1158 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1159 {
AnnaBridge 165:e614a9f1c9e2 1160 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
AnnaBridge 165:e614a9f1c9e2 1161 }
AnnaBridge 165:e614a9f1c9e2 1162
AnnaBridge 165:e614a9f1c9e2 1163 /**
AnnaBridge 165:e614a9f1c9e2 1164 * @brief Indicate the status of Receive data register not empty flag.
AnnaBridge 165:e614a9f1c9e2 1165 * @note RESET: When Receive data register is read.
AnnaBridge 165:e614a9f1c9e2 1166 * SET: When the received data is copied in Receive data register.
AnnaBridge 165:e614a9f1c9e2 1167 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE
AnnaBridge 165:e614a9f1c9e2 1168 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1169 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1170 */
AnnaBridge 165:e614a9f1c9e2 1171 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1172 {
AnnaBridge 165:e614a9f1c9e2 1173 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
AnnaBridge 165:e614a9f1c9e2 1174 }
AnnaBridge 165:e614a9f1c9e2 1175
AnnaBridge 165:e614a9f1c9e2 1176 /**
AnnaBridge 165:e614a9f1c9e2 1177 * @brief Indicate the status of Start Bit (master mode).
AnnaBridge 165:e614a9f1c9e2 1178 * @note RESET: When No Start condition.
AnnaBridge 165:e614a9f1c9e2 1179 * SET: When Start condition is generated.
AnnaBridge 165:e614a9f1c9e2 1180 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB
AnnaBridge 165:e614a9f1c9e2 1181 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1182 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1183 */
AnnaBridge 165:e614a9f1c9e2 1184 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1185 {
AnnaBridge 165:e614a9f1c9e2 1186 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
AnnaBridge 165:e614a9f1c9e2 1187 }
AnnaBridge 165:e614a9f1c9e2 1188
AnnaBridge 165:e614a9f1c9e2 1189 /**
AnnaBridge 165:e614a9f1c9e2 1190 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode).
AnnaBridge 165:e614a9f1c9e2 1191 * @note RESET: Clear default value.
AnnaBridge 165:e614a9f1c9e2 1192 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode).
AnnaBridge 165:e614a9f1c9e2 1193 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR
AnnaBridge 165:e614a9f1c9e2 1194 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1195 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1196 */
AnnaBridge 165:e614a9f1c9e2 1197 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1198 {
AnnaBridge 165:e614a9f1c9e2 1199 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
AnnaBridge 165:e614a9f1c9e2 1200 }
AnnaBridge 165:e614a9f1c9e2 1201
AnnaBridge 165:e614a9f1c9e2 1202 /**
AnnaBridge 165:e614a9f1c9e2 1203 * @brief Indicate the status of 10-bit header sent (master mode).
AnnaBridge 165:e614a9f1c9e2 1204 * @note RESET: When no ADD10 event occured.
AnnaBridge 165:e614a9f1c9e2 1205 * SET: When the master has sent the first address byte (header).
AnnaBridge 165:e614a9f1c9e2 1206 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10
AnnaBridge 165:e614a9f1c9e2 1207 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1208 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1209 */
AnnaBridge 165:e614a9f1c9e2 1210 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1211 {
AnnaBridge 165:e614a9f1c9e2 1212 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
AnnaBridge 165:e614a9f1c9e2 1213 }
AnnaBridge 165:e614a9f1c9e2 1214
AnnaBridge 165:e614a9f1c9e2 1215 /**
AnnaBridge 165:e614a9f1c9e2 1216 * @brief Indicate the status of Acknowledge failure flag.
AnnaBridge 165:e614a9f1c9e2 1217 * @note RESET: No acknowledge failure.
AnnaBridge 165:e614a9f1c9e2 1218 * SET: When an acknowledge failure is received after a byte transmission.
AnnaBridge 165:e614a9f1c9e2 1219 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF
AnnaBridge 165:e614a9f1c9e2 1220 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1221 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1222 */
AnnaBridge 165:e614a9f1c9e2 1223 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1224 {
AnnaBridge 165:e614a9f1c9e2 1225 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
AnnaBridge 165:e614a9f1c9e2 1226 }
AnnaBridge 165:e614a9f1c9e2 1227
AnnaBridge 165:e614a9f1c9e2 1228 /**
AnnaBridge 165:e614a9f1c9e2 1229 * @brief Indicate the status of Stop detection flag (slave mode).
AnnaBridge 165:e614a9f1c9e2 1230 * @note RESET: Clear default value.
AnnaBridge 165:e614a9f1c9e2 1231 * SET: When a Stop condition is detected.
AnnaBridge 165:e614a9f1c9e2 1232 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP
AnnaBridge 165:e614a9f1c9e2 1233 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1234 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1235 */
AnnaBridge 165:e614a9f1c9e2 1236 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1237 {
AnnaBridge 165:e614a9f1c9e2 1238 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
AnnaBridge 165:e614a9f1c9e2 1239 }
AnnaBridge 165:e614a9f1c9e2 1240
AnnaBridge 165:e614a9f1c9e2 1241 /**
AnnaBridge 165:e614a9f1c9e2 1242 * @brief Indicate the status of Bus error flag.
AnnaBridge 165:e614a9f1c9e2 1243 * @note RESET: Clear default value.
AnnaBridge 165:e614a9f1c9e2 1244 * SET: When a misplaced Start or Stop condition is detected.
AnnaBridge 165:e614a9f1c9e2 1245 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR
AnnaBridge 165:e614a9f1c9e2 1246 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1247 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1248 */
AnnaBridge 165:e614a9f1c9e2 1249 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1250 {
AnnaBridge 165:e614a9f1c9e2 1251 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
AnnaBridge 165:e614a9f1c9e2 1252 }
AnnaBridge 165:e614a9f1c9e2 1253
AnnaBridge 165:e614a9f1c9e2 1254 /**
AnnaBridge 165:e614a9f1c9e2 1255 * @brief Indicate the status of Arbitration lost flag.
AnnaBridge 165:e614a9f1c9e2 1256 * @note RESET: Clear default value.
AnnaBridge 165:e614a9f1c9e2 1257 * SET: When arbitration lost.
AnnaBridge 165:e614a9f1c9e2 1258 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO
AnnaBridge 165:e614a9f1c9e2 1259 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1260 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1261 */
AnnaBridge 165:e614a9f1c9e2 1262 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1263 {
AnnaBridge 165:e614a9f1c9e2 1264 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
AnnaBridge 165:e614a9f1c9e2 1265 }
AnnaBridge 165:e614a9f1c9e2 1266
AnnaBridge 165:e614a9f1c9e2 1267 /**
AnnaBridge 165:e614a9f1c9e2 1268 * @brief Indicate the status of Overrun/Underrun flag.
AnnaBridge 165:e614a9f1c9e2 1269 * @note RESET: Clear default value.
AnnaBridge 165:e614a9f1c9e2 1270 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
AnnaBridge 165:e614a9f1c9e2 1271 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR
AnnaBridge 165:e614a9f1c9e2 1272 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1273 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1274 */
AnnaBridge 165:e614a9f1c9e2 1275 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1276 {
AnnaBridge 165:e614a9f1c9e2 1277 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
AnnaBridge 165:e614a9f1c9e2 1278 }
AnnaBridge 165:e614a9f1c9e2 1279
AnnaBridge 165:e614a9f1c9e2 1280 /**
AnnaBridge 165:e614a9f1c9e2 1281 * @brief Indicate the status of SMBus PEC error flag in reception.
AnnaBridge 165:e614a9f1c9e2 1282 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1283 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1284 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR
AnnaBridge 165:e614a9f1c9e2 1285 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1286 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1287 */
AnnaBridge 165:e614a9f1c9e2 1288 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1289 {
AnnaBridge 165:e614a9f1c9e2 1290 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
AnnaBridge 165:e614a9f1c9e2 1291 }
AnnaBridge 165:e614a9f1c9e2 1292
AnnaBridge 165:e614a9f1c9e2 1293 /**
AnnaBridge 165:e614a9f1c9e2 1294 * @brief Indicate the status of SMBus Timeout detection flag.
AnnaBridge 165:e614a9f1c9e2 1295 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1296 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1297 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
AnnaBridge 165:e614a9f1c9e2 1298 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1299 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1300 */
AnnaBridge 165:e614a9f1c9e2 1301 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1302 {
AnnaBridge 165:e614a9f1c9e2 1303 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
AnnaBridge 165:e614a9f1c9e2 1304 }
AnnaBridge 165:e614a9f1c9e2 1305
AnnaBridge 165:e614a9f1c9e2 1306 /**
AnnaBridge 165:e614a9f1c9e2 1307 * @brief Indicate the status of SMBus alert flag.
AnnaBridge 165:e614a9f1c9e2 1308 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1309 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1310 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT
AnnaBridge 165:e614a9f1c9e2 1311 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1312 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1313 */
AnnaBridge 165:e614a9f1c9e2 1314 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1315 {
AnnaBridge 165:e614a9f1c9e2 1316 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
AnnaBridge 165:e614a9f1c9e2 1317 }
AnnaBridge 165:e614a9f1c9e2 1318
AnnaBridge 165:e614a9f1c9e2 1319 /**
AnnaBridge 165:e614a9f1c9e2 1320 * @brief Indicate the status of Bus Busy flag.
AnnaBridge 165:e614a9f1c9e2 1321 * @note RESET: Clear default value.
AnnaBridge 165:e614a9f1c9e2 1322 * SET: When a Start condition is detected.
AnnaBridge 165:e614a9f1c9e2 1323 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY
AnnaBridge 165:e614a9f1c9e2 1324 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1325 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1326 */
AnnaBridge 165:e614a9f1c9e2 1327 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1328 {
AnnaBridge 165:e614a9f1c9e2 1329 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
AnnaBridge 165:e614a9f1c9e2 1330 }
AnnaBridge 165:e614a9f1c9e2 1331
AnnaBridge 165:e614a9f1c9e2 1332 /**
AnnaBridge 165:e614a9f1c9e2 1333 * @brief Indicate the status of Dual flag.
AnnaBridge 165:e614a9f1c9e2 1334 * @note RESET: Received address matched with OAR1.
AnnaBridge 165:e614a9f1c9e2 1335 * SET: Received address matched with OAR2.
AnnaBridge 165:e614a9f1c9e2 1336 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL
AnnaBridge 165:e614a9f1c9e2 1337 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1338 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1339 */
AnnaBridge 165:e614a9f1c9e2 1340 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1341 {
AnnaBridge 165:e614a9f1c9e2 1342 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
AnnaBridge 165:e614a9f1c9e2 1343 }
AnnaBridge 165:e614a9f1c9e2 1344
AnnaBridge 165:e614a9f1c9e2 1345 /**
AnnaBridge 165:e614a9f1c9e2 1346 * @brief Indicate the status of SMBus Host address reception (Slave mode).
AnnaBridge 165:e614a9f1c9e2 1347 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1348 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1349 * @note RESET: No SMBus Host address
AnnaBridge 165:e614a9f1c9e2 1350 * SET: SMBus Host address received.
AnnaBridge 165:e614a9f1c9e2 1351 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 165:e614a9f1c9e2 1352 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST
AnnaBridge 165:e614a9f1c9e2 1353 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1354 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1355 */
AnnaBridge 165:e614a9f1c9e2 1356 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1357 {
AnnaBridge 165:e614a9f1c9e2 1358 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
AnnaBridge 165:e614a9f1c9e2 1359 }
AnnaBridge 165:e614a9f1c9e2 1360
AnnaBridge 165:e614a9f1c9e2 1361 /**
AnnaBridge 165:e614a9f1c9e2 1362 * @brief Indicate the status of SMBus Device default address reception (Slave mode).
AnnaBridge 165:e614a9f1c9e2 1363 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1364 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1365 * @note RESET: No SMBus Device default address
AnnaBridge 165:e614a9f1c9e2 1366 * SET: SMBus Device default address received.
AnnaBridge 165:e614a9f1c9e2 1367 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 165:e614a9f1c9e2 1368 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT
AnnaBridge 165:e614a9f1c9e2 1369 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1370 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1371 */
AnnaBridge 165:e614a9f1c9e2 1372 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1373 {
AnnaBridge 165:e614a9f1c9e2 1374 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
AnnaBridge 165:e614a9f1c9e2 1375 }
AnnaBridge 165:e614a9f1c9e2 1376
AnnaBridge 165:e614a9f1c9e2 1377 /**
AnnaBridge 165:e614a9f1c9e2 1378 * @brief Indicate the status of General call address reception (Slave mode).
AnnaBridge 165:e614a9f1c9e2 1379 * @note RESET: No Generall call address
AnnaBridge 165:e614a9f1c9e2 1380 * SET: General call address received.
AnnaBridge 165:e614a9f1c9e2 1381 * @note This status is cleared by hardware after a STOP condition or repeated START condition.
AnnaBridge 165:e614a9f1c9e2 1382 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL
AnnaBridge 165:e614a9f1c9e2 1383 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1384 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1385 */
AnnaBridge 165:e614a9f1c9e2 1386 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1387 {
AnnaBridge 165:e614a9f1c9e2 1388 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
AnnaBridge 165:e614a9f1c9e2 1389 }
AnnaBridge 165:e614a9f1c9e2 1390
AnnaBridge 165:e614a9f1c9e2 1391 /**
AnnaBridge 165:e614a9f1c9e2 1392 * @brief Indicate the status of Master/Slave flag.
AnnaBridge 165:e614a9f1c9e2 1393 * @note RESET: Slave Mode.
AnnaBridge 165:e614a9f1c9e2 1394 * SET: Master Mode.
AnnaBridge 165:e614a9f1c9e2 1395 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL
AnnaBridge 165:e614a9f1c9e2 1396 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1397 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1398 */
AnnaBridge 165:e614a9f1c9e2 1399 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1400 {
AnnaBridge 165:e614a9f1c9e2 1401 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
AnnaBridge 165:e614a9f1c9e2 1402 }
AnnaBridge 165:e614a9f1c9e2 1403
AnnaBridge 165:e614a9f1c9e2 1404 /**
AnnaBridge 165:e614a9f1c9e2 1405 * @brief Clear Address Matched flag.
AnnaBridge 165:e614a9f1c9e2 1406 * @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge 165:e614a9f1c9e2 1407 * register followed by a read access to the I2Cx_SR2 register.
AnnaBridge 165:e614a9f1c9e2 1408 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR
AnnaBridge 165:e614a9f1c9e2 1409 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1410 * @retval None
AnnaBridge 165:e614a9f1c9e2 1411 */
AnnaBridge 165:e614a9f1c9e2 1412 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1413 {
AnnaBridge 165:e614a9f1c9e2 1414 __IO uint32_t tmpreg;
AnnaBridge 165:e614a9f1c9e2 1415 tmpreg = I2Cx->SR1;
AnnaBridge 165:e614a9f1c9e2 1416 (void) tmpreg;
AnnaBridge 165:e614a9f1c9e2 1417 tmpreg = I2Cx->SR2;
AnnaBridge 165:e614a9f1c9e2 1418 (void) tmpreg;
AnnaBridge 165:e614a9f1c9e2 1419 }
AnnaBridge 165:e614a9f1c9e2 1420
AnnaBridge 165:e614a9f1c9e2 1421 /**
AnnaBridge 165:e614a9f1c9e2 1422 * @brief Clear Acknowledge failure flag.
AnnaBridge 165:e614a9f1c9e2 1423 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF
AnnaBridge 165:e614a9f1c9e2 1424 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1425 * @retval None
AnnaBridge 165:e614a9f1c9e2 1426 */
AnnaBridge 165:e614a9f1c9e2 1427 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1428 {
AnnaBridge 165:e614a9f1c9e2 1429 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
AnnaBridge 165:e614a9f1c9e2 1430 }
AnnaBridge 165:e614a9f1c9e2 1431
AnnaBridge 165:e614a9f1c9e2 1432 /**
AnnaBridge 165:e614a9f1c9e2 1433 * @brief Clear Stop detection flag.
AnnaBridge 165:e614a9f1c9e2 1434 * @note Clearing this flag is done by a read access to the I2Cx_SR1
AnnaBridge 165:e614a9f1c9e2 1435 * register followed by a write access to I2Cx_CR1 register.
AnnaBridge 165:e614a9f1c9e2 1436 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n
AnnaBridge 165:e614a9f1c9e2 1437 * CR1 PE LL_I2C_ClearFlag_STOP
AnnaBridge 165:e614a9f1c9e2 1438 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1439 * @retval None
AnnaBridge 165:e614a9f1c9e2 1440 */
AnnaBridge 165:e614a9f1c9e2 1441 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1442 {
AnnaBridge 165:e614a9f1c9e2 1443 __IO uint32_t tmpreg;
AnnaBridge 165:e614a9f1c9e2 1444 tmpreg = I2Cx->SR1;
AnnaBridge 165:e614a9f1c9e2 1445 (void) tmpreg;
AnnaBridge 165:e614a9f1c9e2 1446 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
AnnaBridge 165:e614a9f1c9e2 1447 }
AnnaBridge 165:e614a9f1c9e2 1448
AnnaBridge 165:e614a9f1c9e2 1449 /**
AnnaBridge 165:e614a9f1c9e2 1450 * @brief Clear Bus error flag.
AnnaBridge 165:e614a9f1c9e2 1451 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR
AnnaBridge 165:e614a9f1c9e2 1452 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1453 * @retval None
AnnaBridge 165:e614a9f1c9e2 1454 */
AnnaBridge 165:e614a9f1c9e2 1455 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1456 {
AnnaBridge 165:e614a9f1c9e2 1457 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
AnnaBridge 165:e614a9f1c9e2 1458 }
AnnaBridge 165:e614a9f1c9e2 1459
AnnaBridge 165:e614a9f1c9e2 1460 /**
AnnaBridge 165:e614a9f1c9e2 1461 * @brief Clear Arbitration lost flag.
AnnaBridge 165:e614a9f1c9e2 1462 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO
AnnaBridge 165:e614a9f1c9e2 1463 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1464 * @retval None
AnnaBridge 165:e614a9f1c9e2 1465 */
AnnaBridge 165:e614a9f1c9e2 1466 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1467 {
AnnaBridge 165:e614a9f1c9e2 1468 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
AnnaBridge 165:e614a9f1c9e2 1469 }
AnnaBridge 165:e614a9f1c9e2 1470
AnnaBridge 165:e614a9f1c9e2 1471 /**
AnnaBridge 165:e614a9f1c9e2 1472 * @brief Clear Overrun/Underrun flag.
AnnaBridge 165:e614a9f1c9e2 1473 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR
AnnaBridge 165:e614a9f1c9e2 1474 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1475 * @retval None
AnnaBridge 165:e614a9f1c9e2 1476 */
AnnaBridge 165:e614a9f1c9e2 1477 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1478 {
AnnaBridge 165:e614a9f1c9e2 1479 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
AnnaBridge 165:e614a9f1c9e2 1480 }
AnnaBridge 165:e614a9f1c9e2 1481
AnnaBridge 165:e614a9f1c9e2 1482 /**
AnnaBridge 165:e614a9f1c9e2 1483 * @brief Clear SMBus PEC error flag.
AnnaBridge 165:e614a9f1c9e2 1484 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR
AnnaBridge 165:e614a9f1c9e2 1485 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1486 * @retval None
AnnaBridge 165:e614a9f1c9e2 1487 */
AnnaBridge 165:e614a9f1c9e2 1488 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1489 {
AnnaBridge 165:e614a9f1c9e2 1490 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
AnnaBridge 165:e614a9f1c9e2 1491 }
AnnaBridge 165:e614a9f1c9e2 1492
AnnaBridge 165:e614a9f1c9e2 1493 /**
AnnaBridge 165:e614a9f1c9e2 1494 * @brief Clear SMBus Timeout detection flag.
AnnaBridge 165:e614a9f1c9e2 1495 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1496 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1497 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT
AnnaBridge 165:e614a9f1c9e2 1498 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1499 * @retval None
AnnaBridge 165:e614a9f1c9e2 1500 */
AnnaBridge 165:e614a9f1c9e2 1501 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1502 {
AnnaBridge 165:e614a9f1c9e2 1503 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
AnnaBridge 165:e614a9f1c9e2 1504 }
AnnaBridge 165:e614a9f1c9e2 1505
AnnaBridge 165:e614a9f1c9e2 1506 /**
AnnaBridge 165:e614a9f1c9e2 1507 * @brief Clear SMBus Alert flag.
AnnaBridge 165:e614a9f1c9e2 1508 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1509 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1510 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT
AnnaBridge 165:e614a9f1c9e2 1511 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1512 * @retval None
AnnaBridge 165:e614a9f1c9e2 1513 */
AnnaBridge 165:e614a9f1c9e2 1514 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1515 {
AnnaBridge 165:e614a9f1c9e2 1516 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
AnnaBridge 165:e614a9f1c9e2 1517 }
AnnaBridge 165:e614a9f1c9e2 1518
AnnaBridge 165:e614a9f1c9e2 1519 /**
AnnaBridge 165:e614a9f1c9e2 1520 * @}
AnnaBridge 165:e614a9f1c9e2 1521 */
AnnaBridge 165:e614a9f1c9e2 1522
AnnaBridge 165:e614a9f1c9e2 1523 /** @defgroup I2C_LL_EF_Data_Management Data_Management
AnnaBridge 165:e614a9f1c9e2 1524 * @{
AnnaBridge 165:e614a9f1c9e2 1525 */
AnnaBridge 165:e614a9f1c9e2 1526
AnnaBridge 165:e614a9f1c9e2 1527 /**
AnnaBridge 165:e614a9f1c9e2 1528 * @brief Enable Reset of I2C peripheral.
AnnaBridge 165:e614a9f1c9e2 1529 * @rmtoll CR1 SWRST LL_I2C_EnableReset
AnnaBridge 165:e614a9f1c9e2 1530 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1531 * @retval None
AnnaBridge 165:e614a9f1c9e2 1532 */
AnnaBridge 165:e614a9f1c9e2 1533 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1534 {
AnnaBridge 165:e614a9f1c9e2 1535 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge 165:e614a9f1c9e2 1536 }
AnnaBridge 165:e614a9f1c9e2 1537
AnnaBridge 165:e614a9f1c9e2 1538 /**
AnnaBridge 165:e614a9f1c9e2 1539 * @brief Disable Reset of I2C peripheral.
AnnaBridge 165:e614a9f1c9e2 1540 * @rmtoll CR1 SWRST LL_I2C_DisableReset
AnnaBridge 165:e614a9f1c9e2 1541 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1542 * @retval None
AnnaBridge 165:e614a9f1c9e2 1543 */
AnnaBridge 165:e614a9f1c9e2 1544 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1545 {
AnnaBridge 165:e614a9f1c9e2 1546 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
AnnaBridge 165:e614a9f1c9e2 1547 }
AnnaBridge 165:e614a9f1c9e2 1548
AnnaBridge 165:e614a9f1c9e2 1549 /**
AnnaBridge 165:e614a9f1c9e2 1550 * @brief Check if the I2C peripheral is under reset state or not.
AnnaBridge 165:e614a9f1c9e2 1551 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled
AnnaBridge 165:e614a9f1c9e2 1552 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1553 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1554 */
AnnaBridge 165:e614a9f1c9e2 1555 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1556 {
AnnaBridge 165:e614a9f1c9e2 1557 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
AnnaBridge 165:e614a9f1c9e2 1558 }
AnnaBridge 165:e614a9f1c9e2 1559
AnnaBridge 165:e614a9f1c9e2 1560 /**
AnnaBridge 165:e614a9f1c9e2 1561 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
AnnaBridge 165:e614a9f1c9e2 1562 * @note Usage in Slave or Master mode.
AnnaBridge 165:e614a9f1c9e2 1563 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData
AnnaBridge 165:e614a9f1c9e2 1564 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1565 * @param TypeAcknowledge This parameter can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1566 * @arg @ref LL_I2C_ACK
AnnaBridge 165:e614a9f1c9e2 1567 * @arg @ref LL_I2C_NACK
AnnaBridge 165:e614a9f1c9e2 1568 * @retval None
AnnaBridge 165:e614a9f1c9e2 1569 */
AnnaBridge 165:e614a9f1c9e2 1570 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
AnnaBridge 165:e614a9f1c9e2 1571 {
AnnaBridge 165:e614a9f1c9e2 1572 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
AnnaBridge 165:e614a9f1c9e2 1573 }
AnnaBridge 165:e614a9f1c9e2 1574
AnnaBridge 165:e614a9f1c9e2 1575 /**
AnnaBridge 165:e614a9f1c9e2 1576 * @brief Generate a START or RESTART condition
AnnaBridge 165:e614a9f1c9e2 1577 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
AnnaBridge 165:e614a9f1c9e2 1578 * This action has no effect when RELOAD is set.
AnnaBridge 165:e614a9f1c9e2 1579 * @rmtoll CR1 START LL_I2C_GenerateStartCondition
AnnaBridge 165:e614a9f1c9e2 1580 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1581 * @retval None
AnnaBridge 165:e614a9f1c9e2 1582 */
AnnaBridge 165:e614a9f1c9e2 1583 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1584 {
AnnaBridge 165:e614a9f1c9e2 1585 SET_BIT(I2Cx->CR1, I2C_CR1_START);
AnnaBridge 165:e614a9f1c9e2 1586 }
AnnaBridge 165:e614a9f1c9e2 1587
AnnaBridge 165:e614a9f1c9e2 1588 /**
AnnaBridge 165:e614a9f1c9e2 1589 * @brief Generate a STOP condition after the current byte transfer (master mode).
AnnaBridge 165:e614a9f1c9e2 1590 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition
AnnaBridge 165:e614a9f1c9e2 1591 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1592 * @retval None
AnnaBridge 165:e614a9f1c9e2 1593 */
AnnaBridge 165:e614a9f1c9e2 1594 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1595 {
AnnaBridge 165:e614a9f1c9e2 1596 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
AnnaBridge 165:e614a9f1c9e2 1597 }
AnnaBridge 165:e614a9f1c9e2 1598
AnnaBridge 165:e614a9f1c9e2 1599 /**
AnnaBridge 165:e614a9f1c9e2 1600 * @brief Enable bit POS (master/host mode).
AnnaBridge 165:e614a9f1c9e2 1601 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC.
AnnaBridge 165:e614a9f1c9e2 1602 * @rmtoll CR1 POS LL_I2C_EnableBitPOS
AnnaBridge 165:e614a9f1c9e2 1603 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1604 * @retval None
AnnaBridge 165:e614a9f1c9e2 1605 */
AnnaBridge 165:e614a9f1c9e2 1606 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1607 {
AnnaBridge 165:e614a9f1c9e2 1608 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge 165:e614a9f1c9e2 1609 }
AnnaBridge 165:e614a9f1c9e2 1610
AnnaBridge 165:e614a9f1c9e2 1611 /**
AnnaBridge 165:e614a9f1c9e2 1612 * @brief Disable bit POS (master/host mode).
AnnaBridge 165:e614a9f1c9e2 1613 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC.
AnnaBridge 165:e614a9f1c9e2 1614 * @rmtoll CR1 POS LL_I2C_DisableBitPOS
AnnaBridge 165:e614a9f1c9e2 1615 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1616 * @retval None
AnnaBridge 165:e614a9f1c9e2 1617 */
AnnaBridge 165:e614a9f1c9e2 1618 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1619 {
AnnaBridge 165:e614a9f1c9e2 1620 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
AnnaBridge 165:e614a9f1c9e2 1621 }
AnnaBridge 165:e614a9f1c9e2 1622
AnnaBridge 165:e614a9f1c9e2 1623 /**
AnnaBridge 165:e614a9f1c9e2 1624 * @brief Check if bit POS is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 1625 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS
AnnaBridge 165:e614a9f1c9e2 1626 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1627 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1628 */
AnnaBridge 165:e614a9f1c9e2 1629 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1630 {
AnnaBridge 165:e614a9f1c9e2 1631 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
AnnaBridge 165:e614a9f1c9e2 1632 }
AnnaBridge 165:e614a9f1c9e2 1633
AnnaBridge 165:e614a9f1c9e2 1634 /**
AnnaBridge 165:e614a9f1c9e2 1635 * @brief Indicate the value of transfer direction.
AnnaBridge 165:e614a9f1c9e2 1636 * @note RESET: Bus is in read transfer (peripheral point of view).
AnnaBridge 165:e614a9f1c9e2 1637 * SET: Bus is in write transfer (peripheral point of view).
AnnaBridge 165:e614a9f1c9e2 1638 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection
AnnaBridge 165:e614a9f1c9e2 1639 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1640 * @retval Returned value can be one of the following values:
AnnaBridge 165:e614a9f1c9e2 1641 * @arg @ref LL_I2C_DIRECTION_WRITE
AnnaBridge 165:e614a9f1c9e2 1642 * @arg @ref LL_I2C_DIRECTION_READ
AnnaBridge 165:e614a9f1c9e2 1643 */
AnnaBridge 165:e614a9f1c9e2 1644 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1645 {
AnnaBridge 165:e614a9f1c9e2 1646 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
AnnaBridge 165:e614a9f1c9e2 1647 }
AnnaBridge 165:e614a9f1c9e2 1648
AnnaBridge 165:e614a9f1c9e2 1649 /**
AnnaBridge 165:e614a9f1c9e2 1650 * @brief Enable DMA last transfer.
AnnaBridge 165:e614a9f1c9e2 1651 * @note This action mean that next DMA EOT is the last transfer.
AnnaBridge 165:e614a9f1c9e2 1652 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA
AnnaBridge 165:e614a9f1c9e2 1653 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1654 * @retval None
AnnaBridge 165:e614a9f1c9e2 1655 */
AnnaBridge 165:e614a9f1c9e2 1656 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1657 {
AnnaBridge 165:e614a9f1c9e2 1658 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge 165:e614a9f1c9e2 1659 }
AnnaBridge 165:e614a9f1c9e2 1660
AnnaBridge 165:e614a9f1c9e2 1661 /**
AnnaBridge 165:e614a9f1c9e2 1662 * @brief Disable DMA last transfer.
AnnaBridge 165:e614a9f1c9e2 1663 * @note This action mean that next DMA EOT is not the last transfer.
AnnaBridge 165:e614a9f1c9e2 1664 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA
AnnaBridge 165:e614a9f1c9e2 1665 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1666 * @retval None
AnnaBridge 165:e614a9f1c9e2 1667 */
AnnaBridge 165:e614a9f1c9e2 1668 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1669 {
AnnaBridge 165:e614a9f1c9e2 1670 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
AnnaBridge 165:e614a9f1c9e2 1671 }
AnnaBridge 165:e614a9f1c9e2 1672
AnnaBridge 165:e614a9f1c9e2 1673 /**
AnnaBridge 165:e614a9f1c9e2 1674 * @brief Check if DMA last transfer is enabled or disabled.
AnnaBridge 165:e614a9f1c9e2 1675 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA
AnnaBridge 165:e614a9f1c9e2 1676 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1677 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1678 */
AnnaBridge 165:e614a9f1c9e2 1679 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1680 {
AnnaBridge 165:e614a9f1c9e2 1681 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
AnnaBridge 165:e614a9f1c9e2 1682 }
AnnaBridge 165:e614a9f1c9e2 1683
AnnaBridge 165:e614a9f1c9e2 1684 /**
AnnaBridge 165:e614a9f1c9e2 1685 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge 165:e614a9f1c9e2 1686 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1687 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1688 * @note This feature is cleared by hardware when the PEC byte is transferred or compared,
AnnaBridge 165:e614a9f1c9e2 1689 * or by a START or STOP condition, it is also cleared by software.
AnnaBridge 165:e614a9f1c9e2 1690 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare
AnnaBridge 165:e614a9f1c9e2 1691 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1692 * @retval None
AnnaBridge 165:e614a9f1c9e2 1693 */
AnnaBridge 165:e614a9f1c9e2 1694 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1695 {
AnnaBridge 165:e614a9f1c9e2 1696 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge 165:e614a9f1c9e2 1697 }
AnnaBridge 165:e614a9f1c9e2 1698
AnnaBridge 165:e614a9f1c9e2 1699 /**
AnnaBridge 165:e614a9f1c9e2 1700 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode).
AnnaBridge 165:e614a9f1c9e2 1701 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1702 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1703 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare
AnnaBridge 165:e614a9f1c9e2 1704 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1705 * @retval None
AnnaBridge 165:e614a9f1c9e2 1706 */
AnnaBridge 165:e614a9f1c9e2 1707 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1708 {
AnnaBridge 165:e614a9f1c9e2 1709 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
AnnaBridge 165:e614a9f1c9e2 1710 }
AnnaBridge 165:e614a9f1c9e2 1711
AnnaBridge 165:e614a9f1c9e2 1712 /**
AnnaBridge 165:e614a9f1c9e2 1713 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not.
AnnaBridge 165:e614a9f1c9e2 1714 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1715 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1716 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare
AnnaBridge 165:e614a9f1c9e2 1717 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1718 * @retval State of bit (1 or 0).
AnnaBridge 165:e614a9f1c9e2 1719 */
AnnaBridge 165:e614a9f1c9e2 1720 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1721 {
AnnaBridge 165:e614a9f1c9e2 1722 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
AnnaBridge 165:e614a9f1c9e2 1723 }
AnnaBridge 165:e614a9f1c9e2 1724
AnnaBridge 165:e614a9f1c9e2 1725 /**
AnnaBridge 165:e614a9f1c9e2 1726 * @brief Get the SMBus Packet Error byte calculated.
AnnaBridge 165:e614a9f1c9e2 1727 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
AnnaBridge 165:e614a9f1c9e2 1728 * SMBus feature is supported by the I2Cx Instance.
AnnaBridge 165:e614a9f1c9e2 1729 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC
AnnaBridge 165:e614a9f1c9e2 1730 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1731 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
AnnaBridge 165:e614a9f1c9e2 1732 */
AnnaBridge 165:e614a9f1c9e2 1733 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1734 {
AnnaBridge 165:e614a9f1c9e2 1735 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
AnnaBridge 165:e614a9f1c9e2 1736 }
AnnaBridge 165:e614a9f1c9e2 1737
AnnaBridge 165:e614a9f1c9e2 1738 /**
AnnaBridge 165:e614a9f1c9e2 1739 * @brief Read Receive Data register.
AnnaBridge 165:e614a9f1c9e2 1740 * @rmtoll DR DR LL_I2C_ReceiveData8
AnnaBridge 165:e614a9f1c9e2 1741 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1742 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge 165:e614a9f1c9e2 1743 */
AnnaBridge 165:e614a9f1c9e2 1744 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
AnnaBridge 165:e614a9f1c9e2 1745 {
AnnaBridge 165:e614a9f1c9e2 1746 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
AnnaBridge 165:e614a9f1c9e2 1747 }
AnnaBridge 165:e614a9f1c9e2 1748
AnnaBridge 165:e614a9f1c9e2 1749 /**
AnnaBridge 165:e614a9f1c9e2 1750 * @brief Write in Transmit Data Register .
AnnaBridge 165:e614a9f1c9e2 1751 * @rmtoll DR DR LL_I2C_TransmitData8
AnnaBridge 165:e614a9f1c9e2 1752 * @param I2Cx I2C Instance.
AnnaBridge 165:e614a9f1c9e2 1753 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF
AnnaBridge 165:e614a9f1c9e2 1754 * @retval None
AnnaBridge 165:e614a9f1c9e2 1755 */
AnnaBridge 165:e614a9f1c9e2 1756 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
AnnaBridge 165:e614a9f1c9e2 1757 {
AnnaBridge 165:e614a9f1c9e2 1758 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
AnnaBridge 165:e614a9f1c9e2 1759 }
AnnaBridge 165:e614a9f1c9e2 1760
AnnaBridge 165:e614a9f1c9e2 1761 /**
AnnaBridge 165:e614a9f1c9e2 1762 * @}
AnnaBridge 165:e614a9f1c9e2 1763 */
AnnaBridge 165:e614a9f1c9e2 1764
AnnaBridge 165:e614a9f1c9e2 1765 #if defined(USE_FULL_LL_DRIVER)
AnnaBridge 165:e614a9f1c9e2 1766 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 1767 * @{
AnnaBridge 165:e614a9f1c9e2 1768 */
AnnaBridge 165:e614a9f1c9e2 1769
AnnaBridge 165:e614a9f1c9e2 1770 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge 165:e614a9f1c9e2 1771 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
AnnaBridge 165:e614a9f1c9e2 1772 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
AnnaBridge 165:e614a9f1c9e2 1773
AnnaBridge 165:e614a9f1c9e2 1774
AnnaBridge 165:e614a9f1c9e2 1775 /**
AnnaBridge 165:e614a9f1c9e2 1776 * @}
AnnaBridge 165:e614a9f1c9e2 1777 */
AnnaBridge 165:e614a9f1c9e2 1778 #endif /* USE_FULL_LL_DRIVER */
AnnaBridge 165:e614a9f1c9e2 1779
AnnaBridge 165:e614a9f1c9e2 1780 /**
AnnaBridge 165:e614a9f1c9e2 1781 * @}
AnnaBridge 165:e614a9f1c9e2 1782 */
AnnaBridge 165:e614a9f1c9e2 1783
AnnaBridge 165:e614a9f1c9e2 1784 /**
AnnaBridge 165:e614a9f1c9e2 1785 * @}
AnnaBridge 165:e614a9f1c9e2 1786 */
AnnaBridge 165:e614a9f1c9e2 1787
AnnaBridge 165:e614a9f1c9e2 1788 #endif /* I2C1 || I2C2 */
AnnaBridge 165:e614a9f1c9e2 1789
AnnaBridge 165:e614a9f1c9e2 1790 /**
AnnaBridge 165:e614a9f1c9e2 1791 * @}
AnnaBridge 165:e614a9f1c9e2 1792 */
AnnaBridge 165:e614a9f1c9e2 1793
AnnaBridge 165:e614a9f1c9e2 1794 #ifdef __cplusplus
AnnaBridge 165:e614a9f1c9e2 1795 }
AnnaBridge 165:e614a9f1c9e2 1796 #endif
AnnaBridge 165:e614a9f1c9e2 1797
AnnaBridge 165:e614a9f1c9e2 1798 #endif /* __STM32F1xx_LL_I2C_H */
AnnaBridge 165:e614a9f1c9e2 1799
AnnaBridge 165:e614a9f1c9e2 1800 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/