mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_ll_fsmc.c@165:e614a9f1c9e2, 2017-05-26 (annotated)

Committer:
AnnaBridge
Date:
Fri May 26 12:39:01 2017 +0100
Revision:
165:e614a9f1c9e2
Parent:
154:37f96f9d4de2
Child:
187:0387e8f68319
This updates the lib to the mbed lib v 143

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_ll_fsmc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
AnnaBridge 165:e614a9f1c9e2 5 * @version V1.1.0
AnnaBridge 165:e614a9f1c9e2 6 * @date 14-April-2017
<> 144:ef7eb2e8f9f7 7 * @brief FSMC Low Layer HAL module driver.
<> 144:ef7eb2e8f9f7 8 *
<> 144:ef7eb2e8f9f7 9 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 10 * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
<> 144:ef7eb2e8f9f7 11 * + Initialization/de-initialization functions
<> 144:ef7eb2e8f9f7 12 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 13 * + Peripheral State functions
<> 144:ef7eb2e8f9f7 14 *
<> 144:ef7eb2e8f9f7 15 @verbatim
<> 144:ef7eb2e8f9f7 16 =============================================================================
<> 144:ef7eb2e8f9f7 17 ##### FSMC peripheral features #####
<> 144:ef7eb2e8f9f7 18 =============================================================================
<> 144:ef7eb2e8f9f7 19 [..] The Flexible static memory controller (FSMC) includes following memory controllers:
<> 144:ef7eb2e8f9f7 20 (+) The NOR/PSRAM memory controller
<> 144:ef7eb2e8f9f7 21 (+) The PC Card memory controller
<> 144:ef7eb2e8f9f7 22 (+) The NAND memory controller
<> 144:ef7eb2e8f9f7 23 (PC Card and NAND controllers available only on STM32F101xE, STM32F103xE, STM32F101xG and STM32F103xG)
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 [..] The FSMC functional block makes the interface with synchronous and asynchronous static
<> 144:ef7eb2e8f9f7 26 memories and 16-bit PC memory cards. Its main purposes are:
<> 144:ef7eb2e8f9f7 27 (+) to translate AHB transactions into the appropriate external device protocol.
<> 144:ef7eb2e8f9f7 28 (+) to meet the access time requirements of the external memory devices.
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 [..] All external memories share the addresses, data and control signals with the controller.
<> 144:ef7eb2e8f9f7 31 Each external device is accessed by means of a unique Chip Select. The FSMC performs
<> 144:ef7eb2e8f9f7 32 only one access at a time to an external device.
<> 144:ef7eb2e8f9f7 33 The main features of the FSMC controller are the following:
<> 144:ef7eb2e8f9f7 34 (+) Interface with static-memory mapped devices including:
<> 144:ef7eb2e8f9f7 35 (++) Static random access memory (SRAM).
<> 144:ef7eb2e8f9f7 36 (++) NOR Flash memory.
<> 144:ef7eb2e8f9f7 37 (++) PSRAM (4 memory banks).
AnnaBridge 165:e614a9f1c9e2 38 (++) 16-bit PC Card compatible devices.
<> 144:ef7eb2e8f9f7 39 (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of
AnnaBridge 165:e614a9f1c9e2 40 data.
AnnaBridge 165:e614a9f1c9e2 41 (+) Independent Chip Select control for each memory bank.
AnnaBridge 165:e614a9f1c9e2 42 (+) Independent configuration for each memory bank.
AnnaBridge 165:e614a9f1c9e2 43
<> 144:ef7eb2e8f9f7 44 @endverbatim
<> 144:ef7eb2e8f9f7 45 ******************************************************************************
<> 144:ef7eb2e8f9f7 46 * @attention
<> 144:ef7eb2e8f9f7 47 *
AnnaBridge 165:e614a9f1c9e2 48 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 49 *
<> 144:ef7eb2e8f9f7 50 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 51 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 52 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 53 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 54 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 55 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 56 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 57 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 58 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 59 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 60 *
<> 144:ef7eb2e8f9f7 61 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 62 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 64 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 67 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 68 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 69 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 70 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 ******************************************************************************
<> 144:ef7eb2e8f9f7 73 */
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 76 #include "stm32f1xx_hal.h"
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 79 * @{
<> 144:ef7eb2e8f9f7 80 */
<> 144:ef7eb2e8f9f7 81
AnnaBridge 165:e614a9f1c9e2 82 #if defined(FSMC_BANK1)
<> 144:ef7eb2e8f9f7 83
AnnaBridge 165:e614a9f1c9e2 84 #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED)
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /** @defgroup FSMC_LL FSMC Low Layer
<> 144:ef7eb2e8f9f7 87 * @brief FSMC driver modules
<> 144:ef7eb2e8f9f7 88 * @{
<> 144:ef7eb2e8f9f7 89 */
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 92 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 93 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 94 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions
<> 144:ef7eb2e8f9f7 99 * @{
<> 144:ef7eb2e8f9f7 100 */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 103 * @brief NORSRAM Controller functions
<> 144:ef7eb2e8f9f7 104 *
<> 144:ef7eb2e8f9f7 105 @verbatim
<> 144:ef7eb2e8f9f7 106 ==============================================================================
<> 144:ef7eb2e8f9f7 107 ##### How to use NORSRAM device driver #####
<> 144:ef7eb2e8f9f7 108 ==============================================================================
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 [..]
<> 144:ef7eb2e8f9f7 111 This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
<> 144:ef7eb2e8f9f7 112 to run the NORSRAM external devices.
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit()
<> 144:ef7eb2e8f9f7 115 (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
<> 144:ef7eb2e8f9f7 116 (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
<> 144:ef7eb2e8f9f7 117 (+) FSMC NORSRAM bank extended timing configuration using the function
<> 144:ef7eb2e8f9f7 118 FSMC_NORSRAM_Extended_Timing_Init()
<> 144:ef7eb2e8f9f7 119 (+) FSMC NORSRAM bank enable/disable write operation using the functions
<> 144:ef7eb2e8f9f7 120 FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
<> 144:ef7eb2e8f9f7 121
<> 144:ef7eb2e8f9f7 122 @endverbatim
<> 144:ef7eb2e8f9f7 123 * @{
<> 144:ef7eb2e8f9f7 124 */
AnnaBridge 165:e614a9f1c9e2 125
AnnaBridge 165:e614a9f1c9e2 126 /** @addtogroup FSMC_LL_NORSRAM_Private_Functions_Group1
AnnaBridge 165:e614a9f1c9e2 127 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 128 *
<> 144:ef7eb2e8f9f7 129 @verbatim
<> 144:ef7eb2e8f9f7 130 ==============================================================================
<> 144:ef7eb2e8f9f7 131 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 132 ==============================================================================
<> 144:ef7eb2e8f9f7 133 [..]
<> 144:ef7eb2e8f9f7 134 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 135 (+) Initialize and configure the FSMC NORSRAM interface
<> 144:ef7eb2e8f9f7 136 (+) De-initialize the FSMC NORSRAM interface
<> 144:ef7eb2e8f9f7 137 (+) Configure the FSMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 @endverbatim
<> 144:ef7eb2e8f9f7 140 * @{
<> 144:ef7eb2e8f9f7 141 */
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @brief Initialize the FSMC_NORSRAM device according to the specified
<> 144:ef7eb2e8f9f7 145 * control parameters in the FSMC_NORSRAM_InitTypeDef
<> 144:ef7eb2e8f9f7 146 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 147 * @param Init: Pointer to NORSRAM Initialization structure
<> 144:ef7eb2e8f9f7 148 * @retval HAL status
<> 144:ef7eb2e8f9f7 149 */
<> 144:ef7eb2e8f9f7 150 HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 151 {
<> 144:ef7eb2e8f9f7 152 /* Check the parameters */
<> 144:ef7eb2e8f9f7 153 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 154 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
<> 144:ef7eb2e8f9f7 155 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
<> 144:ef7eb2e8f9f7 156 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
<> 144:ef7eb2e8f9f7 157 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 158 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
<> 144:ef7eb2e8f9f7 159 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
<> 144:ef7eb2e8f9f7 160 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
<> 144:ef7eb2e8f9f7 161 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
<> 144:ef7eb2e8f9f7 162 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
<> 144:ef7eb2e8f9f7 163 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
<> 144:ef7eb2e8f9f7 164 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
<> 144:ef7eb2e8f9f7 165 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
<> 144:ef7eb2e8f9f7 166 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 /* Disable NORSRAM Device */
<> 144:ef7eb2e8f9f7 169 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /* Set NORSRAM device control parameters */
<> 144:ef7eb2e8f9f7 172 if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
<> 144:ef7eb2e8f9f7 173 {
<> 144:ef7eb2e8f9f7 174 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE
<> 144:ef7eb2e8f9f7 175 | Init->DataAddressMux
<> 144:ef7eb2e8f9f7 176 | Init->MemoryType
<> 144:ef7eb2e8f9f7 177 | Init->MemoryDataWidth
<> 144:ef7eb2e8f9f7 178 | Init->BurstAccessMode
<> 144:ef7eb2e8f9f7 179 | Init->WaitSignalPolarity
<> 144:ef7eb2e8f9f7 180 | Init->WrapMode
<> 144:ef7eb2e8f9f7 181 | Init->WaitSignalActive
<> 144:ef7eb2e8f9f7 182 | Init->WriteOperation
<> 144:ef7eb2e8f9f7 183 | Init->WaitSignal
<> 144:ef7eb2e8f9f7 184 | Init->ExtendedMode
<> 144:ef7eb2e8f9f7 185 | Init->AsynchronousWait
<> 144:ef7eb2e8f9f7 186 | Init->WriteBurst
<> 144:ef7eb2e8f9f7 187 )
<> 144:ef7eb2e8f9f7 188 );
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190 else
<> 144:ef7eb2e8f9f7 191 {
<> 144:ef7eb2e8f9f7 192 MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE
<> 144:ef7eb2e8f9f7 193 | Init->DataAddressMux
<> 144:ef7eb2e8f9f7 194 | Init->MemoryType
<> 144:ef7eb2e8f9f7 195 | Init->MemoryDataWidth
<> 144:ef7eb2e8f9f7 196 | Init->BurstAccessMode
<> 144:ef7eb2e8f9f7 197 | Init->WaitSignalPolarity
<> 144:ef7eb2e8f9f7 198 | Init->WrapMode
<> 144:ef7eb2e8f9f7 199 | Init->WaitSignalActive
<> 144:ef7eb2e8f9f7 200 | Init->WriteOperation
<> 144:ef7eb2e8f9f7 201 | Init->WaitSignal
<> 144:ef7eb2e8f9f7 202 | Init->ExtendedMode
<> 144:ef7eb2e8f9f7 203 | Init->AsynchronousWait
<> 144:ef7eb2e8f9f7 204 | Init->WriteBurst
<> 144:ef7eb2e8f9f7 205 )
<> 144:ef7eb2e8f9f7 206 );
<> 144:ef7eb2e8f9f7 207 }
<> 144:ef7eb2e8f9f7 208
<> 144:ef7eb2e8f9f7 209 return HAL_OK;
<> 144:ef7eb2e8f9f7 210 }
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /**
AnnaBridge 165:e614a9f1c9e2 213 * @brief DeInitialize the FSMC_NORSRAM peripheral
<> 144:ef7eb2e8f9f7 214 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 215 * @param ExDevice: Pointer to NORSRAM extended mode device instance
AnnaBridge 165:e614a9f1c9e2 216 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 217 * @retval HAL status
<> 144:ef7eb2e8f9f7 218 */
<> 144:ef7eb2e8f9f7 219 HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
<> 144:ef7eb2e8f9f7 220 {
<> 144:ef7eb2e8f9f7 221 /* Check the parameters */
<> 144:ef7eb2e8f9f7 222 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 223 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
<> 144:ef7eb2e8f9f7 224 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /* Disable the FSMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 227 __FSMC_NORSRAM_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 228
<> 144:ef7eb2e8f9f7 229 /* De-initialize the FSMC_NORSRAM device */
<> 144:ef7eb2e8f9f7 230 /* FSMC_NORSRAM_BANK1 */
AnnaBridge 165:e614a9f1c9e2 231 if(Bank == FSMC_NORSRAM_BANK1)
<> 144:ef7eb2e8f9f7 232 {
AnnaBridge 165:e614a9f1c9e2 233 Device->BTCR[Bank] = 0x000030DBU;
<> 144:ef7eb2e8f9f7 234 }
<> 144:ef7eb2e8f9f7 235 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
<> 144:ef7eb2e8f9f7 236 else
AnnaBridge 165:e614a9f1c9e2 237 {
AnnaBridge 165:e614a9f1c9e2 238 Device->BTCR[Bank] = 0x000030D2U;
<> 144:ef7eb2e8f9f7 239 }
AnnaBridge 165:e614a9f1c9e2 240
AnnaBridge 165:e614a9f1c9e2 241 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
AnnaBridge 165:e614a9f1c9e2 242 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
AnnaBridge 165:e614a9f1c9e2 243
<> 144:ef7eb2e8f9f7 244 return HAL_OK;
<> 144:ef7eb2e8f9f7 245 }
<> 144:ef7eb2e8f9f7 246
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /**
<> 144:ef7eb2e8f9f7 249 * @brief Initialize the FSMC_NORSRAM Timing according to the specified
<> 144:ef7eb2e8f9f7 250 * parameters in the FSMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 251 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 252 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 253 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 254 * @retval HAL status
<> 144:ef7eb2e8f9f7 255 */
<> 144:ef7eb2e8f9f7 256 HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 257 {
<> 144:ef7eb2e8f9f7 258 /* Check the parameters */
<> 144:ef7eb2e8f9f7 259 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 260 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 261 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 262 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
<> 144:ef7eb2e8f9f7 263 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 264 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 265 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 266 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 267 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /* Set FSMC_NORSRAM device timing parameters */
AnnaBridge 165:e614a9f1c9e2 270 MODIFY_REG(Device->BTCR[Bank + 1U], \
AnnaBridge 165:e614a9f1c9e2 271 BTR_CLEAR_MASK, \
AnnaBridge 165:e614a9f1c9e2 272 (uint32_t)(Timing->AddressSetupTime | \
AnnaBridge 165:e614a9f1c9e2 273 ((Timing->AddressHoldTime) << FSMC_BTRx_ADDHLD_Pos) | \
AnnaBridge 165:e614a9f1c9e2 274 ((Timing->DataSetupTime) << FSMC_BTRx_DATAST_Pos) | \
AnnaBridge 165:e614a9f1c9e2 275 ((Timing->BusTurnAroundDuration) << FSMC_BTRx_BUSTURN_Pos) | \
AnnaBridge 165:e614a9f1c9e2 276 (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
AnnaBridge 165:e614a9f1c9e2 277 (((Timing->DataLatency) - 2U) << FSMC_BTRx_DATLAT_Pos) | \
<> 144:ef7eb2e8f9f7 278 (Timing->AccessMode)));
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 return HAL_OK;
<> 144:ef7eb2e8f9f7 281 }
<> 144:ef7eb2e8f9f7 282
<> 144:ef7eb2e8f9f7 283 /**
<> 144:ef7eb2e8f9f7 284 * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
<> 144:ef7eb2e8f9f7 285 * parameters in the FSMC_NORSRAM_TimingTypeDef
<> 144:ef7eb2e8f9f7 286 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 287 * @param Timing: Pointer to NORSRAM Timing structure
<> 144:ef7eb2e8f9f7 288 * @param Bank: NORSRAM bank number
AnnaBridge 165:e614a9f1c9e2 289 * @param ExtendedMode FSMC Extended Mode
<> 144:ef7eb2e8f9f7 290 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 291 * @arg FSMC_EXTENDED_MODE_DISABLE
<> 144:ef7eb2e8f9f7 292 * @arg FSMC_EXTENDED_MODE_ENABLE
<> 144:ef7eb2e8f9f7 293 * @retval HAL status
<> 144:ef7eb2e8f9f7 294 */
<> 144:ef7eb2e8f9f7 295 HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
<> 144:ef7eb2e8f9f7 296 {
<> 144:ef7eb2e8f9f7 297 /* Check the parameters */
<> 144:ef7eb2e8f9f7 298 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
<> 144:ef7eb2e8f9f7 299
<> 144:ef7eb2e8f9f7 300 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
AnnaBridge 165:e614a9f1c9e2 301 if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Check the parameters */
<> 144:ef7eb2e8f9f7 304 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
<> 144:ef7eb2e8f9f7 305 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
<> 144:ef7eb2e8f9f7 306 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
<> 144:ef7eb2e8f9f7 307 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
AnnaBridge 165:e614a9f1c9e2 308 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
<> 144:ef7eb2e8f9f7 309 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
<> 144:ef7eb2e8f9f7 310 #else
<> 144:ef7eb2e8f9f7 311 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
<> 144:ef7eb2e8f9f7 312 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
<> 144:ef7eb2e8f9f7 313 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 314 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
<> 144:ef7eb2e8f9f7 315 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
AnnaBridge 165:e614a9f1c9e2 318 #if defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)
AnnaBridge 165:e614a9f1c9e2 319 MODIFY_REG(Device->BWTR[Bank], \
AnnaBridge 165:e614a9f1c9e2 320 BWTR_CLEAR_MASK, \
AnnaBridge 165:e614a9f1c9e2 321 (uint32_t)(Timing->AddressSetupTime | \
AnnaBridge 165:e614a9f1c9e2 322 ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
AnnaBridge 165:e614a9f1c9e2 323 ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
AnnaBridge 165:e614a9f1c9e2 324 Timing->AccessMode | \
AnnaBridge 165:e614a9f1c9e2 325 ((Timing->BusTurnAroundDuration) << FSMC_BWTRx_BUSTURN_Pos)));
<> 144:ef7eb2e8f9f7 326 #else
AnnaBridge 165:e614a9f1c9e2 327 MODIFY_REG(Device->BWTR[Bank], \
AnnaBridge 165:e614a9f1c9e2 328 BWTR_CLEAR_MASK, \
AnnaBridge 165:e614a9f1c9e2 329 (uint32_t)(Timing->AddressSetupTime | \
AnnaBridge 165:e614a9f1c9e2 330 ((Timing->AddressHoldTime) << FSMC_BWTRx_ADDHLD_Pos) | \
AnnaBridge 165:e614a9f1c9e2 331 ((Timing->DataSetupTime) << FSMC_BWTRx_DATAST_Pos) | \
AnnaBridge 165:e614a9f1c9e2 332 Timing->AccessMode | \
AnnaBridge 165:e614a9f1c9e2 333 (((Timing->CLKDivision) - 1U) << FSMC_BTRx_CLKDIV_Pos) | \
AnnaBridge 165:e614a9f1c9e2 334 (((Timing->DataLatency) - 2U) << FSMC_BWTRx_DATLAT_Pos)));
<> 144:ef7eb2e8f9f7 335 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 336 }
<> 144:ef7eb2e8f9f7 337 else
<> 144:ef7eb2e8f9f7 338 {
AnnaBridge 165:e614a9f1c9e2 339 Device->BWTR[Bank] = 0x0FFFFFFFU;
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 return HAL_OK;
<> 144:ef7eb2e8f9f7 343 }
<> 144:ef7eb2e8f9f7 344 /**
<> 144:ef7eb2e8f9f7 345 * @}
<> 144:ef7eb2e8f9f7 346 */
<> 144:ef7eb2e8f9f7 347
<> 144:ef7eb2e8f9f7 348 /** @defgroup FSMC_NORSRAM_Group2 Control functions
AnnaBridge 165:e614a9f1c9e2 349 * @brief management functions
AnnaBridge 165:e614a9f1c9e2 350 *
<> 144:ef7eb2e8f9f7 351 @verbatim
<> 144:ef7eb2e8f9f7 352 ==============================================================================
<> 144:ef7eb2e8f9f7 353 ##### FSMC_NORSRAM Control functions #####
<> 144:ef7eb2e8f9f7 354 ==============================================================================
<> 144:ef7eb2e8f9f7 355 [..]
<> 144:ef7eb2e8f9f7 356 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 357 the FSMC NORSRAM interface.
<> 144:ef7eb2e8f9f7 358
<> 144:ef7eb2e8f9f7 359 @endverbatim
<> 144:ef7eb2e8f9f7 360 * @{
<> 144:ef7eb2e8f9f7 361 */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 /**
<> 144:ef7eb2e8f9f7 364 * @brief Enables dynamically FSMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 365 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 366 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 367 * @retval HAL status
<> 144:ef7eb2e8f9f7 368 */
<> 144:ef7eb2e8f9f7 369 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 370 {
<> 144:ef7eb2e8f9f7 371 /* Check the parameters */
<> 144:ef7eb2e8f9f7 372 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 373 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 374
<> 144:ef7eb2e8f9f7 375 /* Enable write operation */
<> 144:ef7eb2e8f9f7 376 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 return HAL_OK;
<> 144:ef7eb2e8f9f7 379 }
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 /**
<> 144:ef7eb2e8f9f7 382 * @brief Disables dynamically FSMC_NORSRAM write operation.
<> 144:ef7eb2e8f9f7 383 * @param Device: Pointer to NORSRAM device instance
<> 144:ef7eb2e8f9f7 384 * @param Bank: NORSRAM bank number
<> 144:ef7eb2e8f9f7 385 * @retval HAL status
<> 144:ef7eb2e8f9f7 386 */
<> 144:ef7eb2e8f9f7 387 HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 388 {
<> 144:ef7eb2e8f9f7 389 /* Check the parameters */
<> 144:ef7eb2e8f9f7 390 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
<> 144:ef7eb2e8f9f7 391 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Disable write operation */
<> 144:ef7eb2e8f9f7 394 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 return HAL_OK;
<> 144:ef7eb2e8f9f7 397 }
<> 144:ef7eb2e8f9f7 398 /**
<> 144:ef7eb2e8f9f7 399 * @}
<> 144:ef7eb2e8f9f7 400 */
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 /**
<> 144:ef7eb2e8f9f7 403 * @}
<> 144:ef7eb2e8f9f7 404 */
AnnaBridge 165:e614a9f1c9e2 405
<> 144:ef7eb2e8f9f7 406 #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG))
<> 144:ef7eb2e8f9f7 407 /** @defgroup FSMC_NAND FSMC NAND Controller functions
<> 144:ef7eb2e8f9f7 408 * @brief NAND Controller functions
<> 144:ef7eb2e8f9f7 409 *
<> 144:ef7eb2e8f9f7 410 @verbatim
<> 144:ef7eb2e8f9f7 411 ==============================================================================
<> 144:ef7eb2e8f9f7 412 ##### How to use NAND device driver #####
<> 144:ef7eb2e8f9f7 413 ==============================================================================
<> 144:ef7eb2e8f9f7 414 [..]
<> 144:ef7eb2e8f9f7 415 This driver contains a set of APIs to interface with the FSMC NAND banks in order
<> 144:ef7eb2e8f9f7 416 to run the NAND external devices.
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit()
<> 144:ef7eb2e8f9f7 419 (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init()
<> 144:ef7eb2e8f9f7 420 (+) FSMC NAND bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 421 FSMC_NAND_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 422 (+) FSMC NAND bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 423 FSMC_NAND_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 424 (+) FSMC NAND bank enable/disable ECC correction feature using the functions
<> 144:ef7eb2e8f9f7 425 FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable()
<> 144:ef7eb2e8f9f7 426 (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC()
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 @endverbatim
<> 144:ef7eb2e8f9f7 429 * @{
<> 144:ef7eb2e8f9f7 430 */
<> 144:ef7eb2e8f9f7 431
<> 144:ef7eb2e8f9f7 432 /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 433 * @brief Initialization and Configuration functions
AnnaBridge 165:e614a9f1c9e2 434 *
<> 144:ef7eb2e8f9f7 435 @verbatim
<> 144:ef7eb2e8f9f7 436 ==============================================================================
<> 144:ef7eb2e8f9f7 437 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 438 ==============================================================================
<> 144:ef7eb2e8f9f7 439 [..]
<> 144:ef7eb2e8f9f7 440 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 441 (+) Initialize and configure the FSMC NAND interface
<> 144:ef7eb2e8f9f7 442 (+) De-initialize the FSMC NAND interface
<> 144:ef7eb2e8f9f7 443 (+) Configure the FSMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 @endverbatim
<> 144:ef7eb2e8f9f7 446 * @{
<> 144:ef7eb2e8f9f7 447 */
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /**
<> 144:ef7eb2e8f9f7 450 * @brief Initializes the FSMC_NAND device according to the specified
<> 144:ef7eb2e8f9f7 451 * control parameters in the FSMC_NAND_HandleTypeDef
<> 144:ef7eb2e8f9f7 452 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 453 * @param Init: Pointer to NAND Initialization structure
<> 144:ef7eb2e8f9f7 454 * @retval HAL status
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456 HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 457 {
<> 144:ef7eb2e8f9f7 458 /* Check the parameters */
<> 144:ef7eb2e8f9f7 459 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 460 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
<> 144:ef7eb2e8f9f7 461 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 462 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
<> 144:ef7eb2e8f9f7 463 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
<> 144:ef7eb2e8f9f7 464 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
<> 144:ef7eb2e8f9f7 465 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 466 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 467
<> 144:ef7eb2e8f9f7 468 /* Set NAND device control parameters */
<> 144:ef7eb2e8f9f7 469 if (Init->NandBank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 470 {
<> 144:ef7eb2e8f9f7 471 /* NAND bank 2 registers configuration */
AnnaBridge 165:e614a9f1c9e2 472 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
AnnaBridge 165:e614a9f1c9e2 473 FSMC_PCR_MEMORY_TYPE_NAND |
AnnaBridge 165:e614a9f1c9e2 474 Init->MemoryDataWidth |
AnnaBridge 165:e614a9f1c9e2 475 Init->EccComputation |
AnnaBridge 165:e614a9f1c9e2 476 Init->ECCPageSize |
AnnaBridge 165:e614a9f1c9e2 477 ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
AnnaBridge 165:e614a9f1c9e2 478 ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480 else
<> 144:ef7eb2e8f9f7 481 {
<> 144:ef7eb2e8f9f7 482 /* NAND bank 3 registers configuration */
AnnaBridge 165:e614a9f1c9e2 483 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
AnnaBridge 165:e614a9f1c9e2 484 FSMC_PCR_MEMORY_TYPE_NAND |
AnnaBridge 165:e614a9f1c9e2 485 Init->MemoryDataWidth |
AnnaBridge 165:e614a9f1c9e2 486 Init->EccComputation |
AnnaBridge 165:e614a9f1c9e2 487 Init->ECCPageSize |
AnnaBridge 165:e614a9f1c9e2 488 ((Init->TCLRSetupTime) << FSMC_PCRx_TCLR_Pos) |
AnnaBridge 165:e614a9f1c9e2 489 ((Init->TARSetupTime) << FSMC_PCRx_TAR_Pos)));
<> 144:ef7eb2e8f9f7 490 }
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 return HAL_OK;
<> 144:ef7eb2e8f9f7 493 }
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /**
<> 144:ef7eb2e8f9f7 496 * @brief Initializes the FSMC_NAND Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 497 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 498 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 499 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 500 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 501 * @retval HAL status
<> 144:ef7eb2e8f9f7 502 */
<> 144:ef7eb2e8f9f7 503 HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 504 {
<> 144:ef7eb2e8f9f7 505 /* Check the parameters */
<> 144:ef7eb2e8f9f7 506 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 507 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 508 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 509 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 510 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 511 assert_param(IS_FSMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 /* Set FMC_NAND device timing parameters */
AnnaBridge 165:e614a9f1c9e2 514 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 515 {
<> 144:ef7eb2e8f9f7 516 /* NAND bank 2 registers configuration */
AnnaBridge 165:e614a9f1c9e2 517 MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \
AnnaBridge 165:e614a9f1c9e2 518 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 519 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 520 ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
<> 144:ef7eb2e8f9f7 521 }
<> 144:ef7eb2e8f9f7 522 else
<> 144:ef7eb2e8f9f7 523 {
<> 144:ef7eb2e8f9f7 524 /* NAND bank 3 registers configuration */
AnnaBridge 165:e614a9f1c9e2 525 MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \
AnnaBridge 165:e614a9f1c9e2 526 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 527 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 528 ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
<> 144:ef7eb2e8f9f7 529 }
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 return HAL_OK;
<> 144:ef7eb2e8f9f7 532 }
<> 144:ef7eb2e8f9f7 533
<> 144:ef7eb2e8f9f7 534 /**
<> 144:ef7eb2e8f9f7 535 * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 536 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 537 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 538 * @param Timing: Pointer to NAND timing structure
<> 144:ef7eb2e8f9f7 539 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 540 * @retval HAL status
<> 144:ef7eb2e8f9f7 541 */
<> 144:ef7eb2e8f9f7 542 HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 /* Check the parameters */
<> 144:ef7eb2e8f9f7 545 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 546 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 547 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 548 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 549 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 550 assert_param(IS_FSMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 /* Set FMC_NAND device timing parameters */
AnnaBridge 165:e614a9f1c9e2 553 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 554 {
<> 144:ef7eb2e8f9f7 555 /* NAND bank 2 registers configuration */
AnnaBridge 165:e614a9f1c9e2 556 MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \
AnnaBridge 165:e614a9f1c9e2 557 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 558 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 559 ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
<> 144:ef7eb2e8f9f7 560 }
<> 144:ef7eb2e8f9f7 561 else
<> 144:ef7eb2e8f9f7 562 {
<> 144:ef7eb2e8f9f7 563 /* NAND bank 3 registers configuration */
AnnaBridge 165:e614a9f1c9e2 564 MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \
AnnaBridge 165:e614a9f1c9e2 565 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 566 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 567 ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
<> 144:ef7eb2e8f9f7 568 }
<> 144:ef7eb2e8f9f7 569
<> 144:ef7eb2e8f9f7 570 return HAL_OK;
<> 144:ef7eb2e8f9f7 571 }
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573
<> 144:ef7eb2e8f9f7 574 /**
AnnaBridge 165:e614a9f1c9e2 575 * @brief DeInitializes the FSMC_NAND device
<> 144:ef7eb2e8f9f7 576 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 577 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 578 * @retval HAL status
<> 144:ef7eb2e8f9f7 579 */
<> 144:ef7eb2e8f9f7 580 HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 /* Check the parameters */
<> 144:ef7eb2e8f9f7 583 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 584 assert_param(IS_FSMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Disable the NAND Bank */
<> 144:ef7eb2e8f9f7 587 __FSMC_NAND_DISABLE(Device, Bank);
<> 144:ef7eb2e8f9f7 588
<> 144:ef7eb2e8f9f7 589 /* De-initialize the NAND Bank */
AnnaBridge 165:e614a9f1c9e2 590 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 591 {
<> 144:ef7eb2e8f9f7 592 /* Set the FSMC_NAND_BANK2 registers to their reset values */
AnnaBridge 165:e614a9f1c9e2 593 WRITE_REG(Device->PCR2, 0x00000018U);
AnnaBridge 165:e614a9f1c9e2 594 WRITE_REG(Device->SR2, 0x00000040U);
AnnaBridge 165:e614a9f1c9e2 595 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
AnnaBridge 165:e614a9f1c9e2 596 WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
<> 144:ef7eb2e8f9f7 597 }
<> 144:ef7eb2e8f9f7 598 /* FSMC_Bank3_NAND */
<> 144:ef7eb2e8f9f7 599 else
<> 144:ef7eb2e8f9f7 600 {
<> 144:ef7eb2e8f9f7 601 /* Set the FSMC_NAND_BANK3 registers to their reset values */
AnnaBridge 165:e614a9f1c9e2 602 WRITE_REG(Device->PCR3, 0x00000018U);
AnnaBridge 165:e614a9f1c9e2 603 WRITE_REG(Device->SR3, 0x00000040U);
AnnaBridge 165:e614a9f1c9e2 604 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
AnnaBridge 165:e614a9f1c9e2 605 WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
<> 144:ef7eb2e8f9f7 606 }
<> 144:ef7eb2e8f9f7 607
<> 144:ef7eb2e8f9f7 608 return HAL_OK;
<> 144:ef7eb2e8f9f7 609 }
<> 144:ef7eb2e8f9f7 610
<> 144:ef7eb2e8f9f7 611 /**
<> 144:ef7eb2e8f9f7 612 * @}
<> 144:ef7eb2e8f9f7 613 */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions
AnnaBridge 165:e614a9f1c9e2 617 * @brief management functions
AnnaBridge 165:e614a9f1c9e2 618 *
<> 144:ef7eb2e8f9f7 619 @verbatim
<> 144:ef7eb2e8f9f7 620 ==============================================================================
<> 144:ef7eb2e8f9f7 621 ##### FSMC_NAND Control functions #####
<> 144:ef7eb2e8f9f7 622 ==============================================================================
<> 144:ef7eb2e8f9f7 623 [..]
<> 144:ef7eb2e8f9f7 624 This subsection provides a set of functions allowing to control dynamically
<> 144:ef7eb2e8f9f7 625 the FSMC NAND interface.
<> 144:ef7eb2e8f9f7 626
<> 144:ef7eb2e8f9f7 627 @endverbatim
<> 144:ef7eb2e8f9f7 628 * @{
<> 144:ef7eb2e8f9f7 629 */
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /**
<> 144:ef7eb2e8f9f7 632 * @brief Enables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 633 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 634 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 635 * @retval HAL status
<> 144:ef7eb2e8f9f7 636 */
<> 144:ef7eb2e8f9f7 637 HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 638 {
<> 144:ef7eb2e8f9f7 639 /* Check the parameters */
<> 144:ef7eb2e8f9f7 640 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 641 assert_param(IS_FSMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 642
<> 144:ef7eb2e8f9f7 643 /* Enable ECC feature */
AnnaBridge 165:e614a9f1c9e2 644 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 645 {
<> 144:ef7eb2e8f9f7 646 SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
<> 144:ef7eb2e8f9f7 647 }
<> 144:ef7eb2e8f9f7 648 else
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
<> 144:ef7eb2e8f9f7 651 }
<> 144:ef7eb2e8f9f7 652
<> 144:ef7eb2e8f9f7 653 return HAL_OK;
<> 144:ef7eb2e8f9f7 654 }
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /**
<> 144:ef7eb2e8f9f7 657 * @brief Disables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 658 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 659 * @param Bank: NAND bank number
<> 144:ef7eb2e8f9f7 660 * @retval HAL status
<> 144:ef7eb2e8f9f7 661 */
<> 144:ef7eb2e8f9f7 662 HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
<> 144:ef7eb2e8f9f7 663 {
<> 144:ef7eb2e8f9f7 664 /* Check the parameters */
<> 144:ef7eb2e8f9f7 665 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 666 assert_param(IS_FSMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Disable ECC feature */
AnnaBridge 165:e614a9f1c9e2 669 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 670 {
<> 144:ef7eb2e8f9f7 671 CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN);
<> 144:ef7eb2e8f9f7 672 }
<> 144:ef7eb2e8f9f7 673 else
<> 144:ef7eb2e8f9f7 674 {
<> 144:ef7eb2e8f9f7 675 CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN);
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 return HAL_OK;
<> 144:ef7eb2e8f9f7 679 }
<> 144:ef7eb2e8f9f7 680
<> 144:ef7eb2e8f9f7 681 /**
<> 144:ef7eb2e8f9f7 682 * @brief Disables dynamically FSMC_NAND ECC feature.
<> 144:ef7eb2e8f9f7 683 * @param Device: Pointer to NAND device instance
<> 144:ef7eb2e8f9f7 684 * @param ECCval: Pointer to ECC value
<> 144:ef7eb2e8f9f7 685 * @param Bank: NAND bank number
AnnaBridge 165:e614a9f1c9e2 686 * @param Timeout: Timeout wait value
<> 144:ef7eb2e8f9f7 687 * @retval HAL status
<> 144:ef7eb2e8f9f7 688 */
<> 144:ef7eb2e8f9f7 689 HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
<> 144:ef7eb2e8f9f7 690 {
AnnaBridge 165:e614a9f1c9e2 691 uint32_t tickstart = 0U;
AnnaBridge 165:e614a9f1c9e2 692
<> 144:ef7eb2e8f9f7 693 /* Check the parameters */
<> 144:ef7eb2e8f9f7 694 assert_param(IS_FSMC_NAND_DEVICE(Device));
<> 144:ef7eb2e8f9f7 695 assert_param(IS_FSMC_NAND_BANK(Bank));
<> 144:ef7eb2e8f9f7 696
<> 144:ef7eb2e8f9f7 697 /* Get tick */
<> 144:ef7eb2e8f9f7 698 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 699
AnnaBridge 165:e614a9f1c9e2 700 /* Wait until FIFO is empty */
AnnaBridge 165:e614a9f1c9e2 701 while(__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 /* Check for the Timeout */
AnnaBridge 165:e614a9f1c9e2 704 if(Timeout != HAL_MAX_DELAY)
<> 144:ef7eb2e8f9f7 705 {
AnnaBridge 165:e614a9f1c9e2 706 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
<> 144:ef7eb2e8f9f7 707 {
<> 144:ef7eb2e8f9f7 708 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 709 }
<> 144:ef7eb2e8f9f7 710 }
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712
AnnaBridge 165:e614a9f1c9e2 713 if(Bank == FSMC_NAND_BANK2)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 /* Get the ECCR2 register value */
<> 144:ef7eb2e8f9f7 716 *ECCval = (uint32_t)Device->ECCR2;
<> 144:ef7eb2e8f9f7 717 }
<> 144:ef7eb2e8f9f7 718 else
<> 144:ef7eb2e8f9f7 719 {
<> 144:ef7eb2e8f9f7 720 /* Get the ECCR3 register value */
<> 144:ef7eb2e8f9f7 721 *ECCval = (uint32_t)Device->ECCR3;
<> 144:ef7eb2e8f9f7 722 }
<> 144:ef7eb2e8f9f7 723
<> 144:ef7eb2e8f9f7 724 return HAL_OK;
<> 144:ef7eb2e8f9f7 725 }
<> 144:ef7eb2e8f9f7 726
<> 144:ef7eb2e8f9f7 727 /**
<> 144:ef7eb2e8f9f7 728 * @}
<> 144:ef7eb2e8f9f7 729 */
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 /**
<> 144:ef7eb2e8f9f7 732 * @}
<> 144:ef7eb2e8f9f7 733 */
<> 144:ef7eb2e8f9f7 734
<> 144:ef7eb2e8f9f7 735 /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions
<> 144:ef7eb2e8f9f7 736 * @brief PCCARD Controller functions
<> 144:ef7eb2e8f9f7 737 *
<> 144:ef7eb2e8f9f7 738 @verbatim
<> 144:ef7eb2e8f9f7 739 ==============================================================================
<> 144:ef7eb2e8f9f7 740 ##### How to use PCCARD device driver #####
<> 144:ef7eb2e8f9f7 741 ==============================================================================
<> 144:ef7eb2e8f9f7 742 [..]
<> 144:ef7eb2e8f9f7 743 This driver contains a set of APIs to interface with the FSMC PCCARD bank in order
<> 144:ef7eb2e8f9f7 744 to run the PCCARD/compact flash external devices.
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit()
<> 144:ef7eb2e8f9f7 747 (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init()
<> 144:ef7eb2e8f9f7 748 (+) FSMC PCCARD bank common space timing configuration using the function
<> 144:ef7eb2e8f9f7 749 FSMC_PCCARD_CommonSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 750 (+) FSMC PCCARD bank attribute space timing configuration using the function
<> 144:ef7eb2e8f9f7 751 FSMC_PCCARD_AttributeSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 752 (+) FSMC PCCARD bank IO space timing configuration using the function
<> 144:ef7eb2e8f9f7 753 FSMC_PCCARD_IOSpace_Timing_Init()
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 @endverbatim
<> 144:ef7eb2e8f9f7 756 * @{
<> 144:ef7eb2e8f9f7 757 */
<> 144:ef7eb2e8f9f7 758
<> 144:ef7eb2e8f9f7 759 /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge 165:e614a9f1c9e2 760 * @brief Initialization and Configuration functions
AnnaBridge 165:e614a9f1c9e2 761 *
<> 144:ef7eb2e8f9f7 762 @verbatim
<> 144:ef7eb2e8f9f7 763 ==============================================================================
<> 144:ef7eb2e8f9f7 764 ##### Initialization and de_initialization functions #####
<> 144:ef7eb2e8f9f7 765 ==============================================================================
<> 144:ef7eb2e8f9f7 766 [..]
<> 144:ef7eb2e8f9f7 767 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 768 (+) Initialize and configure the FSMC PCCARD interface
<> 144:ef7eb2e8f9f7 769 (+) De-initialize the FSMC PCCARD interface
<> 144:ef7eb2e8f9f7 770 (+) Configure the FSMC clock and associated GPIOs
<> 144:ef7eb2e8f9f7 771
<> 144:ef7eb2e8f9f7 772 @endverbatim
<> 144:ef7eb2e8f9f7 773 * @{
<> 144:ef7eb2e8f9f7 774 */
<> 144:ef7eb2e8f9f7 775
<> 144:ef7eb2e8f9f7 776 /**
<> 144:ef7eb2e8f9f7 777 * @brief Initializes the FSMC_PCCARD device according to the specified
<> 144:ef7eb2e8f9f7 778 * control parameters in the FSMC_PCCARD_HandleTypeDef
<> 144:ef7eb2e8f9f7 779 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 780 * @param Init: Pointer to PCCARD Initialization structure
<> 144:ef7eb2e8f9f7 781 * @retval HAL status
<> 144:ef7eb2e8f9f7 782 */
<> 144:ef7eb2e8f9f7 783 HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
<> 144:ef7eb2e8f9f7 784 {
<> 144:ef7eb2e8f9f7 785 /* Check the parameters */
<> 144:ef7eb2e8f9f7 786 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 787 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
<> 144:ef7eb2e8f9f7 788 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
<> 144:ef7eb2e8f9f7 789 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Set FSMC_PCCARD device control parameters */
AnnaBridge 165:e614a9f1c9e2 792 MODIFY_REG(Device->PCR4,
<> 144:ef7eb2e8f9f7 793 (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID |
AnnaBridge 165:e614a9f1c9e2 794 FSMC_PCRx_TCLR | FSMC_PCRx_TAR),
AnnaBridge 165:e614a9f1c9e2 795 (FSMC_PCR_MEMORY_TYPE_PCCARD |
AnnaBridge 165:e614a9f1c9e2 796 Init->Waitfeature |
AnnaBridge 165:e614a9f1c9e2 797 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
AnnaBridge 165:e614a9f1c9e2 798 (Init->TCLRSetupTime << FSMC_PCRx_TCLR_Pos) |
AnnaBridge 165:e614a9f1c9e2 799 (Init->TARSetupTime << FSMC_PCRx_TAR_Pos)));
<> 144:ef7eb2e8f9f7 800
<> 144:ef7eb2e8f9f7 801 return HAL_OK;
<> 144:ef7eb2e8f9f7 802
<> 144:ef7eb2e8f9f7 803 }
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /**
<> 144:ef7eb2e8f9f7 806 * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
<> 144:ef7eb2e8f9f7 807 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 808 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 809 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 810 * @retval HAL status
<> 144:ef7eb2e8f9f7 811 */
<> 144:ef7eb2e8f9f7 812 HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 813 {
<> 144:ef7eb2e8f9f7 814 /* Check the parameters */
<> 144:ef7eb2e8f9f7 815 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 816 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 817 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 818 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 819 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /* Set PCCARD timing parameters */
AnnaBridge 165:e614a9f1c9e2 822 MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK,
AnnaBridge 165:e614a9f1c9e2 823 (Timing->SetupTime |
AnnaBridge 165:e614a9f1c9e2 824 ((Timing->WaitSetupTime) << FSMC_PMEMx_MEMWAITx_Pos) |
AnnaBridge 165:e614a9f1c9e2 825 ((Timing->HoldSetupTime) << FSMC_PMEMx_MEMHOLDx_Pos) |
AnnaBridge 165:e614a9f1c9e2 826 ((Timing->HiZSetupTime) << FSMC_PMEMx_MEMHIZx_Pos)));
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 return HAL_OK;
<> 144:ef7eb2e8f9f7 829 }
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /**
<> 144:ef7eb2e8f9f7 832 * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
<> 144:ef7eb2e8f9f7 833 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 834 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 835 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 836 * @retval HAL status
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838 HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 839 {
<> 144:ef7eb2e8f9f7 840 /* Check the parameters */
<> 144:ef7eb2e8f9f7 841 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 842 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 843 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 844 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 845 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 846
<> 144:ef7eb2e8f9f7 847 /* Set PCCARD timing parameters */
<> 144:ef7eb2e8f9f7 848 MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \
AnnaBridge 165:e614a9f1c9e2 849 (Timing->SetupTime | \
AnnaBridge 165:e614a9f1c9e2 850 ((Timing->WaitSetupTime) << FSMC_PATTx_ATTWAITx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 851 ((Timing->HoldSetupTime) << FSMC_PATTx_ATTHOLDx_Pos) | \
AnnaBridge 165:e614a9f1c9e2 852 ((Timing->HiZSetupTime) << FSMC_PATTx_ATTHIZx_Pos)));
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 return HAL_OK;
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /**
<> 144:ef7eb2e8f9f7 858 * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
<> 144:ef7eb2e8f9f7 859 * parameters in the FSMC_NAND_PCC_TimingTypeDef
<> 144:ef7eb2e8f9f7 860 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 861 * @param Timing: Pointer to PCCARD timing structure
<> 144:ef7eb2e8f9f7 862 * @retval HAL status
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
<> 144:ef7eb2e8f9f7 865 {
<> 144:ef7eb2e8f9f7 866 /* Check the parameters */
<> 144:ef7eb2e8f9f7 867 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 868 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
<> 144:ef7eb2e8f9f7 869 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
<> 144:ef7eb2e8f9f7 870 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
<> 144:ef7eb2e8f9f7 871 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
<> 144:ef7eb2e8f9f7 872
<> 144:ef7eb2e8f9f7 873 /* Set FSMC_PCCARD device timing parameters */
AnnaBridge 165:e614a9f1c9e2 874 MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \
AnnaBridge 165:e614a9f1c9e2 875 (Timing->SetupTime | \
AnnaBridge 165:e614a9f1c9e2 876 (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) | \
AnnaBridge 165:e614a9f1c9e2 877 (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) | \
AnnaBridge 165:e614a9f1c9e2 878 (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
<> 144:ef7eb2e8f9f7 879
<> 144:ef7eb2e8f9f7 880 return HAL_OK;
<> 144:ef7eb2e8f9f7 881 }
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 /**
<> 144:ef7eb2e8f9f7 884 * @brief DeInitializes the FSMC_PCCARD device
<> 144:ef7eb2e8f9f7 885 * @param Device: Pointer to PCCARD device instance
<> 144:ef7eb2e8f9f7 886 * @retval HAL status
<> 144:ef7eb2e8f9f7 887 */
<> 144:ef7eb2e8f9f7 888 HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
<> 144:ef7eb2e8f9f7 889 {
<> 144:ef7eb2e8f9f7 890 /* Check the parameters */
<> 144:ef7eb2e8f9f7 891 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 /* Disable the FSMC_PCCARD device */
<> 144:ef7eb2e8f9f7 894 __FSMC_PCCARD_DISABLE(Device);
<> 144:ef7eb2e8f9f7 895
<> 144:ef7eb2e8f9f7 896 /* De-initialize the FSMC_PCCARD device */
AnnaBridge 165:e614a9f1c9e2 897 WRITE_REG(Device->PCR4, 0x00000018U);
AnnaBridge 165:e614a9f1c9e2 898 WRITE_REG(Device->SR4, 0x00000040U);
AnnaBridge 165:e614a9f1c9e2 899 WRITE_REG(Device->PMEM4, 0xFCFCFCFCU);
AnnaBridge 165:e614a9f1c9e2 900 WRITE_REG(Device->PATT4, 0xFCFCFCFCU);
AnnaBridge 165:e614a9f1c9e2 901 WRITE_REG(Device->PIO4, 0xFCFCFCFCU);
<> 144:ef7eb2e8f9f7 902
<> 144:ef7eb2e8f9f7 903 return HAL_OK;
<> 144:ef7eb2e8f9f7 904 }
<> 144:ef7eb2e8f9f7 905
<> 144:ef7eb2e8f9f7 906 /**
<> 144:ef7eb2e8f9f7 907 * @}
<> 144:ef7eb2e8f9f7 908 */
<> 144:ef7eb2e8f9f7 909
<> 144:ef7eb2e8f9f7 910 /**
<> 144:ef7eb2e8f9f7 911 * @}
<> 144:ef7eb2e8f9f7 912 */
<> 144:ef7eb2e8f9f7 913 #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */
<> 144:ef7eb2e8f9f7 914
<> 144:ef7eb2e8f9f7 915 /**
<> 144:ef7eb2e8f9f7 916 * @}
<> 144:ef7eb2e8f9f7 917 */
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 /**
<> 144:ef7eb2e8f9f7 920 * @}
<> 144:ef7eb2e8f9f7 921 */
<> 144:ef7eb2e8f9f7 922
AnnaBridge 165:e614a9f1c9e2 923 #endif /* HAL_SRAM_MODULE_ENABLED || HAL_NOR_MODULE_ENABLED || HAL_NAND_MODULE_ENABLED || HAL_PCCARD_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 924
AnnaBridge 165:e614a9f1c9e2 925 #endif /* FSMC_BANK1 */
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @}
<> 144:ef7eb2e8f9f7 929 */
<> 144:ef7eb2e8f9f7 930
<> 144:ef7eb2e8f9f7 931 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/