mbed library sources. Supersedes mbed-src.
Dependents: Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more
targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_ll_fsmc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)
- Committer:
- <>
- Date:
- Fri Sep 02 15:07:44 2016 +0100
- Revision:
- 144:ef7eb2e8f9f7
- Parent:
- 124:6a4a5b7d7324
This updates the lib to the mbed lib v125
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /** |
<> | 144:ef7eb2e8f9f7 | 2 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 3 | * @file stm32f1xx_ll_fsmc.c |
<> | 144:ef7eb2e8f9f7 | 4 | * @author MCD Application Team |
<> | 144:ef7eb2e8f9f7 | 5 | * @version V1.0.4 |
<> | 144:ef7eb2e8f9f7 | 6 | * @date 29-April-2016 |
<> | 144:ef7eb2e8f9f7 | 7 | * @brief FSMC Low Layer HAL module driver. |
<> | 144:ef7eb2e8f9f7 | 8 | * |
<> | 144:ef7eb2e8f9f7 | 9 | * This file provides firmware functions to manage the following |
<> | 144:ef7eb2e8f9f7 | 10 | * functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories: |
<> | 144:ef7eb2e8f9f7 | 11 | * + Initialization/de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 12 | * + Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 13 | * + Peripheral State functions |
<> | 144:ef7eb2e8f9f7 | 14 | * |
<> | 144:ef7eb2e8f9f7 | 15 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 16 | ============================================================================= |
<> | 144:ef7eb2e8f9f7 | 17 | ##### FSMC peripheral features ##### |
<> | 144:ef7eb2e8f9f7 | 18 | ============================================================================= |
<> | 144:ef7eb2e8f9f7 | 19 | [..] The Flexible static memory controller (FSMC) includes following memory controllers: |
<> | 144:ef7eb2e8f9f7 | 20 | (+) The NOR/PSRAM memory controller |
<> | 144:ef7eb2e8f9f7 | 21 | (+) The PC Card memory controller |
<> | 144:ef7eb2e8f9f7 | 22 | (+) The NAND memory controller |
<> | 144:ef7eb2e8f9f7 | 23 | (PC Card and NAND controllers available only on STM32F101xE, STM32F103xE, STM32F101xG and STM32F103xG) |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | [..] The FSMC functional block makes the interface with synchronous and asynchronous static |
<> | 144:ef7eb2e8f9f7 | 26 | memories and 16-bit PC memory cards. Its main purposes are: |
<> | 144:ef7eb2e8f9f7 | 27 | (+) to translate AHB transactions into the appropriate external device protocol. |
<> | 144:ef7eb2e8f9f7 | 28 | (+) to meet the access time requirements of the external memory devices. |
<> | 144:ef7eb2e8f9f7 | 29 | |
<> | 144:ef7eb2e8f9f7 | 30 | [..] All external memories share the addresses, data and control signals with the controller. |
<> | 144:ef7eb2e8f9f7 | 31 | Each external device is accessed by means of a unique Chip Select. The FSMC performs |
<> | 144:ef7eb2e8f9f7 | 32 | only one access at a time to an external device. |
<> | 144:ef7eb2e8f9f7 | 33 | The main features of the FSMC controller are the following: |
<> | 144:ef7eb2e8f9f7 | 34 | (+) Interface with static-memory mapped devices including: |
<> | 144:ef7eb2e8f9f7 | 35 | (++) Static random access memory (SRAM). |
<> | 144:ef7eb2e8f9f7 | 36 | (++) NOR Flash memory. |
<> | 144:ef7eb2e8f9f7 | 37 | (++) PSRAM (4 memory banks). |
<> | 144:ef7eb2e8f9f7 | 38 | (++) 16-bit PC Card compatible devices |
<> | 144:ef7eb2e8f9f7 | 39 | (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of |
<> | 144:ef7eb2e8f9f7 | 40 | data |
<> | 144:ef7eb2e8f9f7 | 41 | (+) Independent Chip Select control for each memory bank |
<> | 144:ef7eb2e8f9f7 | 42 | (+) Independent configuration for each memory bank |
<> | 144:ef7eb2e8f9f7 | 43 | |
<> | 144:ef7eb2e8f9f7 | 44 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 45 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 46 | * @attention |
<> | 144:ef7eb2e8f9f7 | 47 | * |
<> | 144:ef7eb2e8f9f7 | 48 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
<> | 144:ef7eb2e8f9f7 | 49 | * |
<> | 144:ef7eb2e8f9f7 | 50 | * Redistribution and use in source and binary forms, with or without modification, |
<> | 144:ef7eb2e8f9f7 | 51 | * are permitted provided that the following conditions are met: |
<> | 144:ef7eb2e8f9f7 | 52 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 53 | * this list of conditions and the following disclaimer. |
<> | 144:ef7eb2e8f9f7 | 54 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 144:ef7eb2e8f9f7 | 55 | * this list of conditions and the following disclaimer in the documentation |
<> | 144:ef7eb2e8f9f7 | 56 | * and/or other materials provided with the distribution. |
<> | 144:ef7eb2e8f9f7 | 57 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 144:ef7eb2e8f9f7 | 58 | * may be used to endorse or promote products derived from this software |
<> | 144:ef7eb2e8f9f7 | 59 | * without specific prior written permission. |
<> | 144:ef7eb2e8f9f7 | 60 | * |
<> | 144:ef7eb2e8f9f7 | 61 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 144:ef7eb2e8f9f7 | 62 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 144:ef7eb2e8f9f7 | 63 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 144:ef7eb2e8f9f7 | 64 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 144:ef7eb2e8f9f7 | 65 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 144:ef7eb2e8f9f7 | 66 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 144:ef7eb2e8f9f7 | 67 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 144:ef7eb2e8f9f7 | 68 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 144:ef7eb2e8f9f7 | 69 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 144:ef7eb2e8f9f7 | 70 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 144:ef7eb2e8f9f7 | 71 | * |
<> | 144:ef7eb2e8f9f7 | 72 | ****************************************************************************** |
<> | 144:ef7eb2e8f9f7 | 73 | */ |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | /* Includes ------------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 76 | #include "stm32f1xx_hal.h" |
<> | 144:ef7eb2e8f9f7 | 77 | |
<> | 144:ef7eb2e8f9f7 | 78 | /** @addtogroup STM32F1xx_HAL_Driver |
<> | 144:ef7eb2e8f9f7 | 79 | * @{ |
<> | 144:ef7eb2e8f9f7 | 80 | */ |
<> | 144:ef7eb2e8f9f7 | 81 | |
<> | 144:ef7eb2e8f9f7 | 82 | #if defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) |
<> | 144:ef7eb2e8f9f7 | 83 | |
<> | 144:ef7eb2e8f9f7 | 84 | #if defined(FSMC_BANK1) |
<> | 144:ef7eb2e8f9f7 | 85 | |
<> | 144:ef7eb2e8f9f7 | 86 | /** @defgroup FSMC_LL FSMC Low Layer |
<> | 144:ef7eb2e8f9f7 | 87 | * @brief FSMC driver modules |
<> | 144:ef7eb2e8f9f7 | 88 | * @{ |
<> | 144:ef7eb2e8f9f7 | 89 | */ |
<> | 144:ef7eb2e8f9f7 | 90 | |
<> | 144:ef7eb2e8f9f7 | 91 | /* Private typedef -----------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 92 | /* Private define ------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 93 | /** @defgroup FSMC_LL_Private_Constants FSMC Low Layer Private Constants |
<> | 144:ef7eb2e8f9f7 | 94 | * @{ |
<> | 144:ef7eb2e8f9f7 | 95 | */ |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | /* ----------------------- FSMC registers bit mask --------------------------- */ |
<> | 144:ef7eb2e8f9f7 | 98 | /* --- PCR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 99 | /* PCR register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 100 | #define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCRx_PWAITEN | FSMC_PCRx_PBKEN | \ |
<> | 144:ef7eb2e8f9f7 | 101 | FSMC_PCRx_PTYP | FSMC_PCRx_PWID | \ |
<> | 144:ef7eb2e8f9f7 | 102 | FSMC_PCRx_ECCEN | FSMC_PCRx_TCLR | \ |
<> | 144:ef7eb2e8f9f7 | 103 | FSMC_PCRx_TAR | FSMC_PCRx_ECCPS)) |
<> | 144:ef7eb2e8f9f7 | 104 | |
<> | 144:ef7eb2e8f9f7 | 105 | /* --- SR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 106 | /* SR register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 107 | #define SR_CLEAR_MASK ((uint32_t)(FSMC_SRx_IRS | FSMC_SRx_ILS | FSMC_SRx_IFS | \ |
<> | 144:ef7eb2e8f9f7 | 108 | FSMC_SRx_IREN | FSMC_SRx_ILEN | FSMC_SRx_IFEN)) |
<> | 144:ef7eb2e8f9f7 | 109 | |
<> | 144:ef7eb2e8f9f7 | 110 | /* --- PMEM Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 111 | /* PMEM register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 112 | #define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEMx_MEMSETx | FSMC_PMEMx_MEMWAITx |\ |
<> | 144:ef7eb2e8f9f7 | 113 | FSMC_PMEMx_MEMHOLDx | FSMC_PMEMx_MEMHIZx)) |
<> | 144:ef7eb2e8f9f7 | 114 | |
<> | 144:ef7eb2e8f9f7 | 115 | /* --- PATT Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 116 | /* PATT register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 117 | #define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATTx_ATTSETx | FSMC_PATTx_ATTWAITx |\ |
<> | 144:ef7eb2e8f9f7 | 118 | FSMC_PATTx_ATTHOLDx | FSMC_PATTx_ATTHIZx)) |
<> | 144:ef7eb2e8f9f7 | 119 | |
<> | 144:ef7eb2e8f9f7 | 120 | /* --- BCR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 121 | /* BCR register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 122 | #define BCR_CLEAR_MASK ((uint32_t)(FSMC_BCRx_FACCEN | FSMC_BCRx_MUXEN | \ |
<> | 144:ef7eb2e8f9f7 | 123 | FSMC_BCRx_MTYP | FSMC_BCRx_MWID | \ |
<> | 144:ef7eb2e8f9f7 | 124 | FSMC_BCRx_BURSTEN | FSMC_BCRx_WAITPOL | \ |
<> | 144:ef7eb2e8f9f7 | 125 | FSMC_BCRx_WRAPMOD | FSMC_BCRx_WAITCFG | \ |
<> | 144:ef7eb2e8f9f7 | 126 | FSMC_BCRx_WREN | FSMC_BCRx_WAITEN | \ |
<> | 144:ef7eb2e8f9f7 | 127 | FSMC_BCRx_EXTMOD | FSMC_BCRx_ASYNCWAIT | \ |
<> | 144:ef7eb2e8f9f7 | 128 | FSMC_BCRx_CBURSTRW)) |
<> | 144:ef7eb2e8f9f7 | 129 | /* --- BTR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 130 | /* BTR register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 131 | #define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTRx_ADDSET | FSMC_BTRx_ADDHLD |\ |
<> | 144:ef7eb2e8f9f7 | 132 | FSMC_BTRx_DATAST | FSMC_BTRx_BUSTURN |\ |
<> | 144:ef7eb2e8f9f7 | 133 | FSMC_BTRx_CLKDIV | FSMC_BTRx_DATLAT |\ |
<> | 144:ef7eb2e8f9f7 | 134 | FSMC_BTRx_ACCMOD)) |
<> | 144:ef7eb2e8f9f7 | 135 | |
<> | 144:ef7eb2e8f9f7 | 136 | /* --- BWTR Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 137 | /* BWTR register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 138 | #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) |
<> | 144:ef7eb2e8f9f7 | 139 | #define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \ |
<> | 144:ef7eb2e8f9f7 | 140 | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \ |
<> | 144:ef7eb2e8f9f7 | 141 | FSMC_BWTRx_BUSTURN)) |
<> | 144:ef7eb2e8f9f7 | 142 | #else |
<> | 144:ef7eb2e8f9f7 | 143 | #define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTRx_ADDSET | FSMC_BWTRx_ADDHLD | \ |
<> | 144:ef7eb2e8f9f7 | 144 | FSMC_BWTRx_DATAST | FSMC_BWTRx_ACCMOD | \ |
<> | 144:ef7eb2e8f9f7 | 145 | FSMC_BWTRx_CLKDIV | FSMC_BWTRx_DATLAT)) |
<> | 144:ef7eb2e8f9f7 | 146 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | /* --- PIO4 Register ---*/ |
<> | 144:ef7eb2e8f9f7 | 149 | /* PIO4 register clear mask */ |
<> | 144:ef7eb2e8f9f7 | 150 | #define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \ |
<> | 144:ef7eb2e8f9f7 | 151 | FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4)) |
<> | 144:ef7eb2e8f9f7 | 152 | /** |
<> | 144:ef7eb2e8f9f7 | 153 | * @} |
<> | 144:ef7eb2e8f9f7 | 154 | */ |
<> | 144:ef7eb2e8f9f7 | 155 | |
<> | 144:ef7eb2e8f9f7 | 156 | /* Private macro -------------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 157 | /** @defgroup FSMC_LL_Private_Macros FSMC Low Layer Private Macros |
<> | 144:ef7eb2e8f9f7 | 158 | * @{ |
<> | 144:ef7eb2e8f9f7 | 159 | */ |
<> | 144:ef7eb2e8f9f7 | 160 | |
<> | 144:ef7eb2e8f9f7 | 161 | /** |
<> | 144:ef7eb2e8f9f7 | 162 | * @} |
<> | 144:ef7eb2e8f9f7 | 163 | */ |
<> | 144:ef7eb2e8f9f7 | 164 | |
<> | 144:ef7eb2e8f9f7 | 165 | /* Private variables ---------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 166 | /* Private function prototypes -----------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 167 | /* Exported functions --------------------------------------------------------*/ |
<> | 144:ef7eb2e8f9f7 | 168 | |
<> | 144:ef7eb2e8f9f7 | 169 | /** @defgroup FSMC_LL_Exported_Functions FSMC Low Layer Exported Functions |
<> | 144:ef7eb2e8f9f7 | 170 | * @{ |
<> | 144:ef7eb2e8f9f7 | 171 | */ |
<> | 144:ef7eb2e8f9f7 | 172 | |
<> | 144:ef7eb2e8f9f7 | 173 | /** @defgroup FSMC_NORSRAM FSMC NORSRAM Controller functions |
<> | 144:ef7eb2e8f9f7 | 174 | * @brief NORSRAM Controller functions |
<> | 144:ef7eb2e8f9f7 | 175 | * |
<> | 144:ef7eb2e8f9f7 | 176 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 177 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 178 | ##### How to use NORSRAM device driver ##### |
<> | 144:ef7eb2e8f9f7 | 179 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | [..] |
<> | 144:ef7eb2e8f9f7 | 182 | This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order |
<> | 144:ef7eb2e8f9f7 | 183 | to run the NORSRAM external devices. |
<> | 144:ef7eb2e8f9f7 | 184 | |
<> | 144:ef7eb2e8f9f7 | 185 | (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() |
<> | 144:ef7eb2e8f9f7 | 186 | (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init() |
<> | 144:ef7eb2e8f9f7 | 187 | (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init() |
<> | 144:ef7eb2e8f9f7 | 188 | (+) FSMC NORSRAM bank extended timing configuration using the function |
<> | 144:ef7eb2e8f9f7 | 189 | FSMC_NORSRAM_Extended_Timing_Init() |
<> | 144:ef7eb2e8f9f7 | 190 | (+) FSMC NORSRAM bank enable/disable write operation using the functions |
<> | 144:ef7eb2e8f9f7 | 191 | FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable() |
<> | 144:ef7eb2e8f9f7 | 192 | |
<> | 144:ef7eb2e8f9f7 | 193 | |
<> | 144:ef7eb2e8f9f7 | 194 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 195 | * @{ |
<> | 144:ef7eb2e8f9f7 | 196 | */ |
<> | 144:ef7eb2e8f9f7 | 197 | |
<> | 144:ef7eb2e8f9f7 | 198 | /** @defgroup FSMC_NORSRAM_Group1 Initialization/de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 199 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 200 | * |
<> | 144:ef7eb2e8f9f7 | 201 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 202 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 203 | ##### Initialization and de_initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 204 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 205 | [..] |
<> | 144:ef7eb2e8f9f7 | 206 | This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 207 | (+) Initialize and configure the FSMC NORSRAM interface |
<> | 144:ef7eb2e8f9f7 | 208 | (+) De-initialize the FSMC NORSRAM interface |
<> | 144:ef7eb2e8f9f7 | 209 | (+) Configure the FSMC clock and associated GPIOs |
<> | 144:ef7eb2e8f9f7 | 210 | |
<> | 144:ef7eb2e8f9f7 | 211 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 212 | * @{ |
<> | 144:ef7eb2e8f9f7 | 213 | */ |
<> | 144:ef7eb2e8f9f7 | 214 | |
<> | 144:ef7eb2e8f9f7 | 215 | /** |
<> | 144:ef7eb2e8f9f7 | 216 | * @brief Initialize the FSMC_NORSRAM device according to the specified |
<> | 144:ef7eb2e8f9f7 | 217 | * control parameters in the FSMC_NORSRAM_InitTypeDef |
<> | 144:ef7eb2e8f9f7 | 218 | * @param Device: Pointer to NORSRAM device instance |
<> | 144:ef7eb2e8f9f7 | 219 | * @param Init: Pointer to NORSRAM Initialization structure |
<> | 144:ef7eb2e8f9f7 | 220 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 221 | */ |
<> | 144:ef7eb2e8f9f7 | 222 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef *Init) |
<> | 144:ef7eb2e8f9f7 | 223 | { |
<> | 144:ef7eb2e8f9f7 | 224 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 225 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 226 | assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank)); |
<> | 144:ef7eb2e8f9f7 | 227 | assert_param(IS_FSMC_MUX(Init->DataAddressMux)); |
<> | 144:ef7eb2e8f9f7 | 228 | assert_param(IS_FSMC_MEMORY(Init->MemoryType)); |
<> | 144:ef7eb2e8f9f7 | 229 | assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); |
<> | 144:ef7eb2e8f9f7 | 230 | assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode)); |
<> | 144:ef7eb2e8f9f7 | 231 | assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity)); |
<> | 144:ef7eb2e8f9f7 | 232 | assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode)); |
<> | 144:ef7eb2e8f9f7 | 233 | assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); |
<> | 144:ef7eb2e8f9f7 | 234 | assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation)); |
<> | 144:ef7eb2e8f9f7 | 235 | assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal)); |
<> | 144:ef7eb2e8f9f7 | 236 | assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode)); |
<> | 144:ef7eb2e8f9f7 | 237 | assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait)); |
<> | 144:ef7eb2e8f9f7 | 238 | assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst)); |
<> | 144:ef7eb2e8f9f7 | 239 | |
<> | 144:ef7eb2e8f9f7 | 240 | /* Disable NORSRAM Device */ |
<> | 144:ef7eb2e8f9f7 | 241 | __FSMC_NORSRAM_DISABLE(Device, Init->NSBank); |
<> | 144:ef7eb2e8f9f7 | 242 | |
<> | 144:ef7eb2e8f9f7 | 243 | /* Set NORSRAM device control parameters */ |
<> | 144:ef7eb2e8f9f7 | 244 | if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR) |
<> | 144:ef7eb2e8f9f7 | 245 | { |
<> | 144:ef7eb2e8f9f7 | 246 | MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_ENABLE |
<> | 144:ef7eb2e8f9f7 | 247 | | Init->DataAddressMux |
<> | 144:ef7eb2e8f9f7 | 248 | | Init->MemoryType |
<> | 144:ef7eb2e8f9f7 | 249 | | Init->MemoryDataWidth |
<> | 144:ef7eb2e8f9f7 | 250 | | Init->BurstAccessMode |
<> | 144:ef7eb2e8f9f7 | 251 | | Init->WaitSignalPolarity |
<> | 144:ef7eb2e8f9f7 | 252 | | Init->WrapMode |
<> | 144:ef7eb2e8f9f7 | 253 | | Init->WaitSignalActive |
<> | 144:ef7eb2e8f9f7 | 254 | | Init->WriteOperation |
<> | 144:ef7eb2e8f9f7 | 255 | | Init->WaitSignal |
<> | 144:ef7eb2e8f9f7 | 256 | | Init->ExtendedMode |
<> | 144:ef7eb2e8f9f7 | 257 | | Init->AsynchronousWait |
<> | 144:ef7eb2e8f9f7 | 258 | | Init->WriteBurst |
<> | 144:ef7eb2e8f9f7 | 259 | ) |
<> | 144:ef7eb2e8f9f7 | 260 | ); |
<> | 144:ef7eb2e8f9f7 | 261 | } |
<> | 144:ef7eb2e8f9f7 | 262 | else |
<> | 144:ef7eb2e8f9f7 | 263 | { |
<> | 144:ef7eb2e8f9f7 | 264 | MODIFY_REG(Device->BTCR[Init->NSBank], BCR_CLEAR_MASK, (uint32_t)(FSMC_NORSRAM_FLASH_ACCESS_DISABLE |
<> | 144:ef7eb2e8f9f7 | 265 | | Init->DataAddressMux |
<> | 144:ef7eb2e8f9f7 | 266 | | Init->MemoryType |
<> | 144:ef7eb2e8f9f7 | 267 | | Init->MemoryDataWidth |
<> | 144:ef7eb2e8f9f7 | 268 | | Init->BurstAccessMode |
<> | 144:ef7eb2e8f9f7 | 269 | | Init->WaitSignalPolarity |
<> | 144:ef7eb2e8f9f7 | 270 | | Init->WrapMode |
<> | 144:ef7eb2e8f9f7 | 271 | | Init->WaitSignalActive |
<> | 144:ef7eb2e8f9f7 | 272 | | Init->WriteOperation |
<> | 144:ef7eb2e8f9f7 | 273 | | Init->WaitSignal |
<> | 144:ef7eb2e8f9f7 | 274 | | Init->ExtendedMode |
<> | 144:ef7eb2e8f9f7 | 275 | | Init->AsynchronousWait |
<> | 144:ef7eb2e8f9f7 | 276 | | Init->WriteBurst |
<> | 144:ef7eb2e8f9f7 | 277 | ) |
<> | 144:ef7eb2e8f9f7 | 278 | ); |
<> | 144:ef7eb2e8f9f7 | 279 | } |
<> | 144:ef7eb2e8f9f7 | 280 | |
<> | 144:ef7eb2e8f9f7 | 281 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 282 | } |
<> | 144:ef7eb2e8f9f7 | 283 | |
<> | 144:ef7eb2e8f9f7 | 284 | |
<> | 144:ef7eb2e8f9f7 | 285 | /** |
<> | 144:ef7eb2e8f9f7 | 286 | * @brief DeInitialize the FSMC_NORSRAM peripheral |
<> | 144:ef7eb2e8f9f7 | 287 | * @param Device: Pointer to NORSRAM device instance |
<> | 144:ef7eb2e8f9f7 | 288 | * @param ExDevice: Pointer to NORSRAM extended mode device instance |
<> | 144:ef7eb2e8f9f7 | 289 | * @param Bank: NORSRAM bank number |
<> | 144:ef7eb2e8f9f7 | 290 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 291 | */ |
<> | 144:ef7eb2e8f9f7 | 292 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 293 | { |
<> | 144:ef7eb2e8f9f7 | 294 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 295 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 296 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); |
<> | 144:ef7eb2e8f9f7 | 297 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | /* Disable the FSMC_NORSRAM device */ |
<> | 144:ef7eb2e8f9f7 | 300 | __FSMC_NORSRAM_DISABLE(Device, Bank); |
<> | 144:ef7eb2e8f9f7 | 301 | |
<> | 144:ef7eb2e8f9f7 | 302 | /* De-initialize the FSMC_NORSRAM device */ |
<> | 144:ef7eb2e8f9f7 | 303 | /* FSMC_NORSRAM_BANK1 */ |
<> | 144:ef7eb2e8f9f7 | 304 | if (Bank == FSMC_NORSRAM_BANK1) |
<> | 144:ef7eb2e8f9f7 | 305 | { |
<> | 144:ef7eb2e8f9f7 | 306 | Device->BTCR[Bank] = 0x000030DB; |
<> | 144:ef7eb2e8f9f7 | 307 | } |
<> | 144:ef7eb2e8f9f7 | 308 | /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */ |
<> | 144:ef7eb2e8f9f7 | 309 | else |
<> | 144:ef7eb2e8f9f7 | 310 | { |
<> | 144:ef7eb2e8f9f7 | 311 | Device->BTCR[Bank] = 0x000030D2; |
<> | 144:ef7eb2e8f9f7 | 312 | } |
<> | 144:ef7eb2e8f9f7 | 313 | |
<> | 144:ef7eb2e8f9f7 | 314 | Device->BTCR[Bank + 1] = 0x0FFFFFFF; |
<> | 144:ef7eb2e8f9f7 | 315 | ExDevice->BWTR[Bank] = 0x0FFFFFFF; |
<> | 144:ef7eb2e8f9f7 | 316 | |
<> | 144:ef7eb2e8f9f7 | 317 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 318 | } |
<> | 144:ef7eb2e8f9f7 | 319 | |
<> | 144:ef7eb2e8f9f7 | 320 | |
<> | 144:ef7eb2e8f9f7 | 321 | /** |
<> | 144:ef7eb2e8f9f7 | 322 | * @brief Initialize the FSMC_NORSRAM Timing according to the specified |
<> | 144:ef7eb2e8f9f7 | 323 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
<> | 144:ef7eb2e8f9f7 | 324 | * @param Device: Pointer to NORSRAM device instance |
<> | 144:ef7eb2e8f9f7 | 325 | * @param Timing: Pointer to NORSRAM Timing structure |
<> | 144:ef7eb2e8f9f7 | 326 | * @param Bank: NORSRAM bank number |
<> | 144:ef7eb2e8f9f7 | 327 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 328 | */ |
<> | 144:ef7eb2e8f9f7 | 329 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 330 | { |
<> | 144:ef7eb2e8f9f7 | 331 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 332 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 333 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 334 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
<> | 144:ef7eb2e8f9f7 | 335 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 336 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
<> | 144:ef7eb2e8f9f7 | 337 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
<> | 144:ef7eb2e8f9f7 | 338 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
<> | 144:ef7eb2e8f9f7 | 339 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
<> | 144:ef7eb2e8f9f7 | 340 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 341 | |
<> | 144:ef7eb2e8f9f7 | 342 | /* Set FSMC_NORSRAM device timing parameters */ |
<> | 144:ef7eb2e8f9f7 | 343 | MODIFY_REG(Device->BTCR[Bank + 1], \ |
<> | 144:ef7eb2e8f9f7 | 344 | BTR_CLEAR_MASK, \ |
<> | 144:ef7eb2e8f9f7 | 345 | (uint32_t)(Timing->AddressSetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 346 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BTRx_ADDHLD)) | \ |
<> | 144:ef7eb2e8f9f7 | 347 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BTRx_DATAST)) | \ |
<> | 144:ef7eb2e8f9f7 | 348 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BTRx_BUSTURN)) | \ |
<> | 144:ef7eb2e8f9f7 | 349 | (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ |
<> | 144:ef7eb2e8f9f7 | 350 | (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BTRx_DATLAT)) | \ |
<> | 144:ef7eb2e8f9f7 | 351 | (Timing->AccessMode))); |
<> | 144:ef7eb2e8f9f7 | 352 | |
<> | 144:ef7eb2e8f9f7 | 353 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 354 | } |
<> | 144:ef7eb2e8f9f7 | 355 | |
<> | 144:ef7eb2e8f9f7 | 356 | /** |
<> | 144:ef7eb2e8f9f7 | 357 | * @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified |
<> | 144:ef7eb2e8f9f7 | 358 | * parameters in the FSMC_NORSRAM_TimingTypeDef |
<> | 144:ef7eb2e8f9f7 | 359 | * @param Device: Pointer to NORSRAM device instance |
<> | 144:ef7eb2e8f9f7 | 360 | * @param Timing: Pointer to NORSRAM Timing structure |
<> | 144:ef7eb2e8f9f7 | 361 | * @param Bank: NORSRAM bank number |
<> | 144:ef7eb2e8f9f7 | 362 | * @param ExtendedMode: FSMC Extended Mode |
<> | 144:ef7eb2e8f9f7 | 363 | * This parameter can be one of the following values: |
<> | 144:ef7eb2e8f9f7 | 364 | * @arg FSMC_EXTENDED_MODE_DISABLE |
<> | 144:ef7eb2e8f9f7 | 365 | * @arg FSMC_EXTENDED_MODE_ENABLE |
<> | 144:ef7eb2e8f9f7 | 366 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 367 | */ |
<> | 144:ef7eb2e8f9f7 | 368 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) |
<> | 144:ef7eb2e8f9f7 | 369 | { |
<> | 144:ef7eb2e8f9f7 | 370 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 371 | assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode)); |
<> | 144:ef7eb2e8f9f7 | 372 | |
<> | 144:ef7eb2e8f9f7 | 373 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
<> | 144:ef7eb2e8f9f7 | 374 | if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE) |
<> | 144:ef7eb2e8f9f7 | 375 | { |
<> | 144:ef7eb2e8f9f7 | 376 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 377 | assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 378 | assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 379 | assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); |
<> | 144:ef7eb2e8f9f7 | 380 | assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 381 | #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) |
<> | 144:ef7eb2e8f9f7 | 382 | assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); |
<> | 144:ef7eb2e8f9f7 | 383 | #else |
<> | 144:ef7eb2e8f9f7 | 384 | assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision)); |
<> | 144:ef7eb2e8f9f7 | 385 | assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency)); |
<> | 144:ef7eb2e8f9f7 | 386 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
<> | 144:ef7eb2e8f9f7 | 387 | assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode)); |
<> | 144:ef7eb2e8f9f7 | 388 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 389 | |
<> | 144:ef7eb2e8f9f7 | 390 | /* Set NORSRAM device timing register for write configuration, if extended mode is used */ |
<> | 144:ef7eb2e8f9f7 | 391 | #if (defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) |
<> | 144:ef7eb2e8f9f7 | 392 | MODIFY_REG(Device->BWTR[Bank], \ |
<> | 144:ef7eb2e8f9f7 | 393 | BWTR_CLEAR_MASK, \ |
<> | 144:ef7eb2e8f9f7 | 394 | (uint32_t)(Timing->AddressSetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 395 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ |
<> | 144:ef7eb2e8f9f7 | 396 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ |
<> | 144:ef7eb2e8f9f7 | 397 | Timing->AccessMode | \ |
<> | 144:ef7eb2e8f9f7 | 398 | ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN)))); |
<> | 144:ef7eb2e8f9f7 | 399 | #else |
<> | 144:ef7eb2e8f9f7 | 400 | MODIFY_REG(Device->BWTR[Bank], \ |
<> | 144:ef7eb2e8f9f7 | 401 | BWTR_CLEAR_MASK, \ |
<> | 144:ef7eb2e8f9f7 | 402 | (uint32_t)(Timing->AddressSetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 403 | ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD)) | \ |
<> | 144:ef7eb2e8f9f7 | 404 | ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST)) | \ |
<> | 144:ef7eb2e8f9f7 | 405 | Timing->AccessMode | \ |
<> | 144:ef7eb2e8f9f7 | 406 | (((Timing->CLKDivision) - 1) << POSITION_VAL(FSMC_BTRx_CLKDIV)) | \ |
<> | 144:ef7eb2e8f9f7 | 407 | (((Timing->DataLatency) - 2) << POSITION_VAL(FSMC_BWTRx_DATLAT)))); |
<> | 144:ef7eb2e8f9f7 | 408 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
<> | 144:ef7eb2e8f9f7 | 409 | } |
<> | 144:ef7eb2e8f9f7 | 410 | else |
<> | 144:ef7eb2e8f9f7 | 411 | { |
<> | 144:ef7eb2e8f9f7 | 412 | Device->BWTR[Bank] = 0x0FFFFFFF; |
<> | 144:ef7eb2e8f9f7 | 413 | } |
<> | 144:ef7eb2e8f9f7 | 414 | |
<> | 144:ef7eb2e8f9f7 | 415 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 416 | } |
<> | 144:ef7eb2e8f9f7 | 417 | |
<> | 144:ef7eb2e8f9f7 | 418 | |
<> | 144:ef7eb2e8f9f7 | 419 | /** |
<> | 144:ef7eb2e8f9f7 | 420 | * @} |
<> | 144:ef7eb2e8f9f7 | 421 | */ |
<> | 144:ef7eb2e8f9f7 | 422 | |
<> | 144:ef7eb2e8f9f7 | 423 | |
<> | 144:ef7eb2e8f9f7 | 424 | /** @defgroup FSMC_NORSRAM_Group2 Control functions |
<> | 144:ef7eb2e8f9f7 | 425 | * @brief management functions |
<> | 144:ef7eb2e8f9f7 | 426 | * |
<> | 144:ef7eb2e8f9f7 | 427 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 428 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 429 | ##### FSMC_NORSRAM Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 430 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 431 | [..] |
<> | 144:ef7eb2e8f9f7 | 432 | This subsection provides a set of functions allowing to control dynamically |
<> | 144:ef7eb2e8f9f7 | 433 | the FSMC NORSRAM interface. |
<> | 144:ef7eb2e8f9f7 | 434 | |
<> | 144:ef7eb2e8f9f7 | 435 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 436 | * @{ |
<> | 144:ef7eb2e8f9f7 | 437 | */ |
<> | 144:ef7eb2e8f9f7 | 438 | |
<> | 144:ef7eb2e8f9f7 | 439 | /** |
<> | 144:ef7eb2e8f9f7 | 440 | * @brief Enables dynamically FSMC_NORSRAM write operation. |
<> | 144:ef7eb2e8f9f7 | 441 | * @param Device: Pointer to NORSRAM device instance |
<> | 144:ef7eb2e8f9f7 | 442 | * @param Bank: NORSRAM bank number |
<> | 144:ef7eb2e8f9f7 | 443 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 444 | */ |
<> | 144:ef7eb2e8f9f7 | 445 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 446 | { |
<> | 144:ef7eb2e8f9f7 | 447 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 448 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 449 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 450 | |
<> | 144:ef7eb2e8f9f7 | 451 | /* Enable write operation */ |
<> | 144:ef7eb2e8f9f7 | 452 | SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); |
<> | 144:ef7eb2e8f9f7 | 453 | |
<> | 144:ef7eb2e8f9f7 | 454 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 455 | } |
<> | 144:ef7eb2e8f9f7 | 456 | |
<> | 144:ef7eb2e8f9f7 | 457 | /** |
<> | 144:ef7eb2e8f9f7 | 458 | * @brief Disables dynamically FSMC_NORSRAM write operation. |
<> | 144:ef7eb2e8f9f7 | 459 | * @param Device: Pointer to NORSRAM device instance |
<> | 144:ef7eb2e8f9f7 | 460 | * @param Bank: NORSRAM bank number |
<> | 144:ef7eb2e8f9f7 | 461 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 462 | */ |
<> | 144:ef7eb2e8f9f7 | 463 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 464 | { |
<> | 144:ef7eb2e8f9f7 | 465 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 466 | assert_param(IS_FSMC_NORSRAM_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 467 | assert_param(IS_FSMC_NORSRAM_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 468 | |
<> | 144:ef7eb2e8f9f7 | 469 | /* Disable write operation */ |
<> | 144:ef7eb2e8f9f7 | 470 | CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE); |
<> | 144:ef7eb2e8f9f7 | 471 | |
<> | 144:ef7eb2e8f9f7 | 472 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 473 | } |
<> | 144:ef7eb2e8f9f7 | 474 | |
<> | 144:ef7eb2e8f9f7 | 475 | /** |
<> | 144:ef7eb2e8f9f7 | 476 | * @} |
<> | 144:ef7eb2e8f9f7 | 477 | */ |
<> | 144:ef7eb2e8f9f7 | 478 | |
<> | 144:ef7eb2e8f9f7 | 479 | /** |
<> | 144:ef7eb2e8f9f7 | 480 | * @} |
<> | 144:ef7eb2e8f9f7 | 481 | */ |
<> | 144:ef7eb2e8f9f7 | 482 | #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) |
<> | 144:ef7eb2e8f9f7 | 483 | /** @defgroup FSMC_NAND FSMC NAND Controller functions |
<> | 144:ef7eb2e8f9f7 | 484 | * @brief NAND Controller functions |
<> | 144:ef7eb2e8f9f7 | 485 | * |
<> | 144:ef7eb2e8f9f7 | 486 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 487 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 488 | ##### How to use NAND device driver ##### |
<> | 144:ef7eb2e8f9f7 | 489 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 490 | [..] |
<> | 144:ef7eb2e8f9f7 | 491 | This driver contains a set of APIs to interface with the FSMC NAND banks in order |
<> | 144:ef7eb2e8f9f7 | 492 | to run the NAND external devices. |
<> | 144:ef7eb2e8f9f7 | 493 | |
<> | 144:ef7eb2e8f9f7 | 494 | (+) FSMC NAND bank reset using the function FSMC_NAND_DeInit() |
<> | 144:ef7eb2e8f9f7 | 495 | (+) FSMC NAND bank control configuration using the function FSMC_NAND_Init() |
<> | 144:ef7eb2e8f9f7 | 496 | (+) FSMC NAND bank common space timing configuration using the function |
<> | 144:ef7eb2e8f9f7 | 497 | FSMC_NAND_CommonSpace_Timing_Init() |
<> | 144:ef7eb2e8f9f7 | 498 | (+) FSMC NAND bank attribute space timing configuration using the function |
<> | 144:ef7eb2e8f9f7 | 499 | FSMC_NAND_AttributeSpace_Timing_Init() |
<> | 144:ef7eb2e8f9f7 | 500 | (+) FSMC NAND bank enable/disable ECC correction feature using the functions |
<> | 144:ef7eb2e8f9f7 | 501 | FSMC_NAND_ECC_Enable()/FSMC_NAND_ECC_Disable() |
<> | 144:ef7eb2e8f9f7 | 502 | (+) FSMC NAND bank get ECC correction code using the function FSMC_NAND_GetECC() |
<> | 144:ef7eb2e8f9f7 | 503 | |
<> | 144:ef7eb2e8f9f7 | 504 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 505 | * @{ |
<> | 144:ef7eb2e8f9f7 | 506 | */ |
<> | 144:ef7eb2e8f9f7 | 507 | |
<> | 144:ef7eb2e8f9f7 | 508 | /** @defgroup FSMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 509 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 510 | * |
<> | 144:ef7eb2e8f9f7 | 511 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 512 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 513 | ##### Initialization and de_initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 514 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 515 | [..] |
<> | 144:ef7eb2e8f9f7 | 516 | This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 517 | (+) Initialize and configure the FSMC NAND interface |
<> | 144:ef7eb2e8f9f7 | 518 | (+) De-initialize the FSMC NAND interface |
<> | 144:ef7eb2e8f9f7 | 519 | (+) Configure the FSMC clock and associated GPIOs |
<> | 144:ef7eb2e8f9f7 | 520 | |
<> | 144:ef7eb2e8f9f7 | 521 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 522 | * @{ |
<> | 144:ef7eb2e8f9f7 | 523 | */ |
<> | 144:ef7eb2e8f9f7 | 524 | |
<> | 144:ef7eb2e8f9f7 | 525 | /** |
<> | 144:ef7eb2e8f9f7 | 526 | * @brief Initializes the FSMC_NAND device according to the specified |
<> | 144:ef7eb2e8f9f7 | 527 | * control parameters in the FSMC_NAND_HandleTypeDef |
<> | 144:ef7eb2e8f9f7 | 528 | * @param Device: Pointer to NAND device instance |
<> | 144:ef7eb2e8f9f7 | 529 | * @param Init: Pointer to NAND Initialization structure |
<> | 144:ef7eb2e8f9f7 | 530 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 531 | */ |
<> | 144:ef7eb2e8f9f7 | 532 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init) |
<> | 144:ef7eb2e8f9f7 | 533 | { |
<> | 144:ef7eb2e8f9f7 | 534 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 535 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 536 | assert_param(IS_FSMC_NAND_BANK(Init->NandBank)); |
<> | 144:ef7eb2e8f9f7 | 537 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
<> | 144:ef7eb2e8f9f7 | 538 | assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); |
<> | 144:ef7eb2e8f9f7 | 539 | assert_param(IS_FSMC_ECC_STATE(Init->EccComputation)); |
<> | 144:ef7eb2e8f9f7 | 540 | assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize)); |
<> | 144:ef7eb2e8f9f7 | 541 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 542 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 543 | |
<> | 144:ef7eb2e8f9f7 | 544 | /* Set NAND device control parameters */ |
<> | 144:ef7eb2e8f9f7 | 545 | if (Init->NandBank == FSMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 546 | { |
<> | 144:ef7eb2e8f9f7 | 547 | /* NAND bank 2 registers configuration */ |
<> | 144:ef7eb2e8f9f7 | 548 | MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature | \ |
<> | 144:ef7eb2e8f9f7 | 549 | FSMC_PCR_MEMORY_TYPE_NAND | \ |
<> | 144:ef7eb2e8f9f7 | 550 | Init->MemoryDataWidth | \ |
<> | 144:ef7eb2e8f9f7 | 551 | Init->EccComputation | \ |
<> | 144:ef7eb2e8f9f7 | 552 | Init->ECCPageSize | \ |
<> | 144:ef7eb2e8f9f7 | 553 | ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) | \ |
<> | 144:ef7eb2e8f9f7 | 554 | ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); |
<> | 144:ef7eb2e8f9f7 | 555 | } |
<> | 144:ef7eb2e8f9f7 | 556 | else |
<> | 144:ef7eb2e8f9f7 | 557 | { |
<> | 144:ef7eb2e8f9f7 | 558 | /* NAND bank 3 registers configuration */ |
<> | 144:ef7eb2e8f9f7 | 559 | MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature | \ |
<> | 144:ef7eb2e8f9f7 | 560 | FSMC_PCR_MEMORY_TYPE_NAND | \ |
<> | 144:ef7eb2e8f9f7 | 561 | Init->MemoryDataWidth | \ |
<> | 144:ef7eb2e8f9f7 | 562 | Init->EccComputation | \ |
<> | 144:ef7eb2e8f9f7 | 563 | Init->ECCPageSize | \ |
<> | 144:ef7eb2e8f9f7 | 564 | ((Init->TCLRSetupTime) << POSITION_VAL(FSMC_PCRx_TCLR)) | \ |
<> | 144:ef7eb2e8f9f7 | 565 | ((Init->TARSetupTime) << POSITION_VAL(FSMC_PCRx_TAR)))); |
<> | 144:ef7eb2e8f9f7 | 566 | } |
<> | 144:ef7eb2e8f9f7 | 567 | |
<> | 144:ef7eb2e8f9f7 | 568 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 569 | |
<> | 144:ef7eb2e8f9f7 | 570 | } |
<> | 144:ef7eb2e8f9f7 | 571 | |
<> | 144:ef7eb2e8f9f7 | 572 | /** |
<> | 144:ef7eb2e8f9f7 | 573 | * @brief Initializes the FSMC_NAND Common space Timing according to the specified |
<> | 144:ef7eb2e8f9f7 | 574 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
<> | 144:ef7eb2e8f9f7 | 575 | * @param Device: Pointer to NAND device instance |
<> | 144:ef7eb2e8f9f7 | 576 | * @param Timing: Pointer to NAND timing structure |
<> | 144:ef7eb2e8f9f7 | 577 | * @param Bank: NAND bank number |
<> | 144:ef7eb2e8f9f7 | 578 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 579 | */ |
<> | 144:ef7eb2e8f9f7 | 580 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 581 | { |
<> | 144:ef7eb2e8f9f7 | 582 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 583 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 584 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
<> | 144:ef7eb2e8f9f7 | 585 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 586 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 587 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 588 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 589 | |
<> | 144:ef7eb2e8f9f7 | 590 | /* Set FMC_NAND device timing parameters */ |
<> | 144:ef7eb2e8f9f7 | 591 | if (Bank == FSMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 592 | { |
<> | 144:ef7eb2e8f9f7 | 593 | /* NAND bank 2 registers configuration */ |
<> | 144:ef7eb2e8f9f7 | 594 | MODIFY_REG(Device->PMEM2, PMEM_CLEAR_MASK, (Timing->SetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 595 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \ |
<> | 144:ef7eb2e8f9f7 | 596 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \ |
<> | 144:ef7eb2e8f9f7 | 597 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); |
<> | 144:ef7eb2e8f9f7 | 598 | } |
<> | 144:ef7eb2e8f9f7 | 599 | else |
<> | 144:ef7eb2e8f9f7 | 600 | { |
<> | 144:ef7eb2e8f9f7 | 601 | /* NAND bank 3 registers configuration */ |
<> | 144:ef7eb2e8f9f7 | 602 | MODIFY_REG(Device->PMEM3, PMEM_CLEAR_MASK, (Timing->SetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 603 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \ |
<> | 144:ef7eb2e8f9f7 | 604 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \ |
<> | 144:ef7eb2e8f9f7 | 605 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); |
<> | 144:ef7eb2e8f9f7 | 606 | } |
<> | 144:ef7eb2e8f9f7 | 607 | |
<> | 144:ef7eb2e8f9f7 | 608 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 609 | } |
<> | 144:ef7eb2e8f9f7 | 610 | |
<> | 144:ef7eb2e8f9f7 | 611 | /** |
<> | 144:ef7eb2e8f9f7 | 612 | * @brief Initializes the FSMC_NAND Attribute space Timing according to the specified |
<> | 144:ef7eb2e8f9f7 | 613 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
<> | 144:ef7eb2e8f9f7 | 614 | * @param Device: Pointer to NAND device instance |
<> | 144:ef7eb2e8f9f7 | 615 | * @param Timing: Pointer to NAND timing structure |
<> | 144:ef7eb2e8f9f7 | 616 | * @param Bank: NAND bank number |
<> | 144:ef7eb2e8f9f7 | 617 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 618 | */ |
<> | 144:ef7eb2e8f9f7 | 619 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 620 | { |
<> | 144:ef7eb2e8f9f7 | 621 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 622 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 623 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
<> | 144:ef7eb2e8f9f7 | 624 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 625 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 626 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 627 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 628 | |
<> | 144:ef7eb2e8f9f7 | 629 | /* Set FMC_NAND device timing parameters */ |
<> | 144:ef7eb2e8f9f7 | 630 | if (Bank == FSMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 631 | { |
<> | 144:ef7eb2e8f9f7 | 632 | /* NAND bank 2 registers configuration */ |
<> | 144:ef7eb2e8f9f7 | 633 | MODIFY_REG(Device->PATT2, PATT_CLEAR_MASK, (Timing->SetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 634 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \ |
<> | 144:ef7eb2e8f9f7 | 635 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \ |
<> | 144:ef7eb2e8f9f7 | 636 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); |
<> | 144:ef7eb2e8f9f7 | 637 | } |
<> | 144:ef7eb2e8f9f7 | 638 | else |
<> | 144:ef7eb2e8f9f7 | 639 | { |
<> | 144:ef7eb2e8f9f7 | 640 | /* NAND bank 3 registers configuration */ |
<> | 144:ef7eb2e8f9f7 | 641 | MODIFY_REG(Device->PATT3, PATT_CLEAR_MASK, (Timing->SetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 642 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \ |
<> | 144:ef7eb2e8f9f7 | 643 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \ |
<> | 144:ef7eb2e8f9f7 | 644 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); |
<> | 144:ef7eb2e8f9f7 | 645 | } |
<> | 144:ef7eb2e8f9f7 | 646 | |
<> | 144:ef7eb2e8f9f7 | 647 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 648 | } |
<> | 144:ef7eb2e8f9f7 | 649 | |
<> | 144:ef7eb2e8f9f7 | 650 | |
<> | 144:ef7eb2e8f9f7 | 651 | /** |
<> | 144:ef7eb2e8f9f7 | 652 | * @brief DeInitializes the FSMC_NAND device |
<> | 144:ef7eb2e8f9f7 | 653 | * @param Device: Pointer to NAND device instance |
<> | 144:ef7eb2e8f9f7 | 654 | * @param Bank: NAND bank number |
<> | 144:ef7eb2e8f9f7 | 655 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 656 | */ |
<> | 144:ef7eb2e8f9f7 | 657 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 658 | { |
<> | 144:ef7eb2e8f9f7 | 659 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 660 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 661 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 662 | |
<> | 144:ef7eb2e8f9f7 | 663 | /* Disable the NAND Bank */ |
<> | 144:ef7eb2e8f9f7 | 664 | __FSMC_NAND_DISABLE(Device, Bank); |
<> | 144:ef7eb2e8f9f7 | 665 | |
<> | 144:ef7eb2e8f9f7 | 666 | /* De-initialize the NAND Bank */ |
<> | 144:ef7eb2e8f9f7 | 667 | if (Bank == FSMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 668 | { |
<> | 144:ef7eb2e8f9f7 | 669 | /* Set the FSMC_NAND_BANK2 registers to their reset values */ |
<> | 144:ef7eb2e8f9f7 | 670 | WRITE_REG(Device->PCR2, 0x00000018); |
<> | 144:ef7eb2e8f9f7 | 671 | WRITE_REG(Device->SR2, 0x00000040); |
<> | 144:ef7eb2e8f9f7 | 672 | WRITE_REG(Device->PMEM2, 0xFCFCFCFC); |
<> | 144:ef7eb2e8f9f7 | 673 | WRITE_REG(Device->PATT2, 0xFCFCFCFC); |
<> | 144:ef7eb2e8f9f7 | 674 | } |
<> | 144:ef7eb2e8f9f7 | 675 | /* FSMC_Bank3_NAND */ |
<> | 144:ef7eb2e8f9f7 | 676 | else |
<> | 144:ef7eb2e8f9f7 | 677 | { |
<> | 144:ef7eb2e8f9f7 | 678 | /* Set the FSMC_NAND_BANK3 registers to their reset values */ |
<> | 144:ef7eb2e8f9f7 | 679 | WRITE_REG(Device->PCR3, 0x00000018); |
<> | 144:ef7eb2e8f9f7 | 680 | WRITE_REG(Device->SR3, 0x00000040); |
<> | 144:ef7eb2e8f9f7 | 681 | WRITE_REG(Device->PMEM3, 0xFCFCFCFC); |
<> | 144:ef7eb2e8f9f7 | 682 | WRITE_REG(Device->PATT3, 0xFCFCFCFC); |
<> | 144:ef7eb2e8f9f7 | 683 | } |
<> | 144:ef7eb2e8f9f7 | 684 | |
<> | 144:ef7eb2e8f9f7 | 685 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 686 | } |
<> | 144:ef7eb2e8f9f7 | 687 | |
<> | 144:ef7eb2e8f9f7 | 688 | /** |
<> | 144:ef7eb2e8f9f7 | 689 | * @} |
<> | 144:ef7eb2e8f9f7 | 690 | */ |
<> | 144:ef7eb2e8f9f7 | 691 | |
<> | 144:ef7eb2e8f9f7 | 692 | |
<> | 144:ef7eb2e8f9f7 | 693 | /** @defgroup FSMC_NAND_Exported_Functions_Group2 Peripheral Control functions |
<> | 144:ef7eb2e8f9f7 | 694 | * @brief management functions |
<> | 144:ef7eb2e8f9f7 | 695 | * |
<> | 144:ef7eb2e8f9f7 | 696 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 697 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 698 | ##### FSMC_NAND Control functions ##### |
<> | 144:ef7eb2e8f9f7 | 699 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 700 | [..] |
<> | 144:ef7eb2e8f9f7 | 701 | This subsection provides a set of functions allowing to control dynamically |
<> | 144:ef7eb2e8f9f7 | 702 | the FSMC NAND interface. |
<> | 144:ef7eb2e8f9f7 | 703 | |
<> | 144:ef7eb2e8f9f7 | 704 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 705 | * @{ |
<> | 144:ef7eb2e8f9f7 | 706 | */ |
<> | 144:ef7eb2e8f9f7 | 707 | |
<> | 144:ef7eb2e8f9f7 | 708 | |
<> | 144:ef7eb2e8f9f7 | 709 | /** |
<> | 144:ef7eb2e8f9f7 | 710 | * @brief Enables dynamically FSMC_NAND ECC feature. |
<> | 144:ef7eb2e8f9f7 | 711 | * @param Device: Pointer to NAND device instance |
<> | 144:ef7eb2e8f9f7 | 712 | * @param Bank: NAND bank number |
<> | 144:ef7eb2e8f9f7 | 713 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 714 | */ |
<> | 144:ef7eb2e8f9f7 | 715 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 716 | { |
<> | 144:ef7eb2e8f9f7 | 717 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 718 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 719 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 720 | |
<> | 144:ef7eb2e8f9f7 | 721 | /* Enable ECC feature */ |
<> | 144:ef7eb2e8f9f7 | 722 | if (Bank == FSMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 723 | { |
<> | 144:ef7eb2e8f9f7 | 724 | SET_BIT(Device->PCR2, FSMC_PCRx_ECCEN); |
<> | 144:ef7eb2e8f9f7 | 725 | } |
<> | 144:ef7eb2e8f9f7 | 726 | else |
<> | 144:ef7eb2e8f9f7 | 727 | { |
<> | 144:ef7eb2e8f9f7 | 728 | SET_BIT(Device->PCR3, FSMC_PCRx_ECCEN); |
<> | 144:ef7eb2e8f9f7 | 729 | } |
<> | 144:ef7eb2e8f9f7 | 730 | |
<> | 144:ef7eb2e8f9f7 | 731 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 732 | } |
<> | 144:ef7eb2e8f9f7 | 733 | |
<> | 144:ef7eb2e8f9f7 | 734 | |
<> | 144:ef7eb2e8f9f7 | 735 | /** |
<> | 144:ef7eb2e8f9f7 | 736 | * @brief Disables dynamically FSMC_NAND ECC feature. |
<> | 144:ef7eb2e8f9f7 | 737 | * @param Device: Pointer to NAND device instance |
<> | 144:ef7eb2e8f9f7 | 738 | * @param Bank: NAND bank number |
<> | 144:ef7eb2e8f9f7 | 739 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 740 | */ |
<> | 144:ef7eb2e8f9f7 | 741 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank) |
<> | 144:ef7eb2e8f9f7 | 742 | { |
<> | 144:ef7eb2e8f9f7 | 743 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 744 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 745 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 746 | |
<> | 144:ef7eb2e8f9f7 | 747 | /* Disable ECC feature */ |
<> | 144:ef7eb2e8f9f7 | 748 | if (Bank == FSMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 749 | { |
<> | 144:ef7eb2e8f9f7 | 750 | CLEAR_BIT(Device->PCR2, FSMC_PCRx_ECCEN); |
<> | 144:ef7eb2e8f9f7 | 751 | } |
<> | 144:ef7eb2e8f9f7 | 752 | else |
<> | 144:ef7eb2e8f9f7 | 753 | { |
<> | 144:ef7eb2e8f9f7 | 754 | CLEAR_BIT(Device->PCR3, FSMC_PCRx_ECCEN); |
<> | 144:ef7eb2e8f9f7 | 755 | } |
<> | 144:ef7eb2e8f9f7 | 756 | |
<> | 144:ef7eb2e8f9f7 | 757 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 758 | } |
<> | 144:ef7eb2e8f9f7 | 759 | |
<> | 144:ef7eb2e8f9f7 | 760 | /** |
<> | 144:ef7eb2e8f9f7 | 761 | * @brief Disables dynamically FSMC_NAND ECC feature. |
<> | 144:ef7eb2e8f9f7 | 762 | * @param Device: Pointer to NAND device instance |
<> | 144:ef7eb2e8f9f7 | 763 | * @param ECCval: Pointer to ECC value |
<> | 144:ef7eb2e8f9f7 | 764 | * @param Bank: NAND bank number |
<> | 144:ef7eb2e8f9f7 | 765 | * @param Timeout: Timeout wait value |
<> | 144:ef7eb2e8f9f7 | 766 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 767 | */ |
<> | 144:ef7eb2e8f9f7 | 768 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) |
<> | 144:ef7eb2e8f9f7 | 769 | { |
<> | 144:ef7eb2e8f9f7 | 770 | uint32_t tickstart = 0; |
<> | 144:ef7eb2e8f9f7 | 771 | |
<> | 144:ef7eb2e8f9f7 | 772 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 773 | assert_param(IS_FSMC_NAND_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 774 | assert_param(IS_FSMC_NAND_BANK(Bank)); |
<> | 144:ef7eb2e8f9f7 | 775 | |
<> | 144:ef7eb2e8f9f7 | 776 | /* Get tick */ |
<> | 144:ef7eb2e8f9f7 | 777 | tickstart = HAL_GetTick(); |
<> | 144:ef7eb2e8f9f7 | 778 | |
<> | 144:ef7eb2e8f9f7 | 779 | /* Wait untill FIFO is empty */ |
<> | 144:ef7eb2e8f9f7 | 780 | while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET) |
<> | 144:ef7eb2e8f9f7 | 781 | { |
<> | 144:ef7eb2e8f9f7 | 782 | /* Check for the Timeout */ |
<> | 144:ef7eb2e8f9f7 | 783 | if (Timeout != HAL_MAX_DELAY) |
<> | 144:ef7eb2e8f9f7 | 784 | { |
<> | 144:ef7eb2e8f9f7 | 785 | if ((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) |
<> | 144:ef7eb2e8f9f7 | 786 | { |
<> | 144:ef7eb2e8f9f7 | 787 | return HAL_TIMEOUT; |
<> | 144:ef7eb2e8f9f7 | 788 | } |
<> | 144:ef7eb2e8f9f7 | 789 | } |
<> | 144:ef7eb2e8f9f7 | 790 | } |
<> | 144:ef7eb2e8f9f7 | 791 | |
<> | 144:ef7eb2e8f9f7 | 792 | if (Bank == FSMC_NAND_BANK2) |
<> | 144:ef7eb2e8f9f7 | 793 | { |
<> | 144:ef7eb2e8f9f7 | 794 | /* Get the ECCR2 register value */ |
<> | 144:ef7eb2e8f9f7 | 795 | *ECCval = (uint32_t)Device->ECCR2; |
<> | 144:ef7eb2e8f9f7 | 796 | } |
<> | 144:ef7eb2e8f9f7 | 797 | else |
<> | 144:ef7eb2e8f9f7 | 798 | { |
<> | 144:ef7eb2e8f9f7 | 799 | /* Get the ECCR3 register value */ |
<> | 144:ef7eb2e8f9f7 | 800 | *ECCval = (uint32_t)Device->ECCR3; |
<> | 144:ef7eb2e8f9f7 | 801 | } |
<> | 144:ef7eb2e8f9f7 | 802 | |
<> | 144:ef7eb2e8f9f7 | 803 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 804 | } |
<> | 144:ef7eb2e8f9f7 | 805 | |
<> | 144:ef7eb2e8f9f7 | 806 | /** |
<> | 144:ef7eb2e8f9f7 | 807 | * @} |
<> | 144:ef7eb2e8f9f7 | 808 | */ |
<> | 144:ef7eb2e8f9f7 | 809 | |
<> | 144:ef7eb2e8f9f7 | 810 | /** |
<> | 144:ef7eb2e8f9f7 | 811 | * @} |
<> | 144:ef7eb2e8f9f7 | 812 | */ |
<> | 144:ef7eb2e8f9f7 | 813 | |
<> | 144:ef7eb2e8f9f7 | 814 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
<> | 144:ef7eb2e8f9f7 | 815 | #if (defined (STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG)) |
<> | 144:ef7eb2e8f9f7 | 816 | /** @defgroup FSMC_PCCARD FSMC PCCARD Controller functions |
<> | 144:ef7eb2e8f9f7 | 817 | * @brief PCCARD Controller functions |
<> | 144:ef7eb2e8f9f7 | 818 | * |
<> | 144:ef7eb2e8f9f7 | 819 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 820 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 821 | ##### How to use PCCARD device driver ##### |
<> | 144:ef7eb2e8f9f7 | 822 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 823 | [..] |
<> | 144:ef7eb2e8f9f7 | 824 | This driver contains a set of APIs to interface with the FSMC PCCARD bank in order |
<> | 144:ef7eb2e8f9f7 | 825 | to run the PCCARD/compact flash external devices. |
<> | 144:ef7eb2e8f9f7 | 826 | |
<> | 144:ef7eb2e8f9f7 | 827 | (+) FSMC PCCARD bank reset using the function FSMC_PCCARD_DeInit() |
<> | 144:ef7eb2e8f9f7 | 828 | (+) FSMC PCCARD bank control configuration using the function FSMC_PCCARD_Init() |
<> | 144:ef7eb2e8f9f7 | 829 | (+) FSMC PCCARD bank common space timing configuration using the function |
<> | 144:ef7eb2e8f9f7 | 830 | FSMC_PCCARD_CommonSpace_Timing_Init() |
<> | 144:ef7eb2e8f9f7 | 831 | (+) FSMC PCCARD bank attribute space timing configuration using the function |
<> | 144:ef7eb2e8f9f7 | 832 | FSMC_PCCARD_AttributeSpace_Timing_Init() |
<> | 144:ef7eb2e8f9f7 | 833 | (+) FSMC PCCARD bank IO space timing configuration using the function |
<> | 144:ef7eb2e8f9f7 | 834 | FSMC_PCCARD_IOSpace_Timing_Init() |
<> | 144:ef7eb2e8f9f7 | 835 | |
<> | 144:ef7eb2e8f9f7 | 836 | |
<> | 144:ef7eb2e8f9f7 | 837 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 838 | * @{ |
<> | 144:ef7eb2e8f9f7 | 839 | */ |
<> | 144:ef7eb2e8f9f7 | 840 | |
<> | 144:ef7eb2e8f9f7 | 841 | /** @defgroup FSMC_PCCARD_Exported_Functions_Group1 Initialization and de-initialization functions |
<> | 144:ef7eb2e8f9f7 | 842 | * @brief Initialization and Configuration functions |
<> | 144:ef7eb2e8f9f7 | 843 | * |
<> | 144:ef7eb2e8f9f7 | 844 | @verbatim |
<> | 144:ef7eb2e8f9f7 | 845 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 846 | ##### Initialization and de_initialization functions ##### |
<> | 144:ef7eb2e8f9f7 | 847 | ============================================================================== |
<> | 144:ef7eb2e8f9f7 | 848 | [..] |
<> | 144:ef7eb2e8f9f7 | 849 | This section provides functions allowing to: |
<> | 144:ef7eb2e8f9f7 | 850 | (+) Initialize and configure the FSMC PCCARD interface |
<> | 144:ef7eb2e8f9f7 | 851 | (+) De-initialize the FSMC PCCARD interface |
<> | 144:ef7eb2e8f9f7 | 852 | (+) Configure the FSMC clock and associated GPIOs |
<> | 144:ef7eb2e8f9f7 | 853 | |
<> | 144:ef7eb2e8f9f7 | 854 | @endverbatim |
<> | 144:ef7eb2e8f9f7 | 855 | * @{ |
<> | 144:ef7eb2e8f9f7 | 856 | */ |
<> | 144:ef7eb2e8f9f7 | 857 | |
<> | 144:ef7eb2e8f9f7 | 858 | /** |
<> | 144:ef7eb2e8f9f7 | 859 | * @brief Initializes the FSMC_PCCARD device according to the specified |
<> | 144:ef7eb2e8f9f7 | 860 | * control parameters in the FSMC_PCCARD_HandleTypeDef |
<> | 144:ef7eb2e8f9f7 | 861 | * @param Device: Pointer to PCCARD device instance |
<> | 144:ef7eb2e8f9f7 | 862 | * @param Init: Pointer to PCCARD Initialization structure |
<> | 144:ef7eb2e8f9f7 | 863 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 864 | */ |
<> | 144:ef7eb2e8f9f7 | 865 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init) |
<> | 144:ef7eb2e8f9f7 | 866 | { |
<> | 144:ef7eb2e8f9f7 | 867 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 868 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 869 | assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature)); |
<> | 144:ef7eb2e8f9f7 | 870 | assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 871 | assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 872 | |
<> | 144:ef7eb2e8f9f7 | 873 | /* Set FSMC_PCCARD device control parameters */ |
<> | 144:ef7eb2e8f9f7 | 874 | MODIFY_REG(Device->PCR4, \ |
<> | 144:ef7eb2e8f9f7 | 875 | (FSMC_PCRx_PTYP | FSMC_PCRx_PWAITEN | FSMC_PCRx_PWID | |
<> | 144:ef7eb2e8f9f7 | 876 | FSMC_PCRx_TCLR | FSMC_PCRx_TAR), \ |
<> | 144:ef7eb2e8f9f7 | 877 | (FSMC_PCR_MEMORY_TYPE_PCCARD | \ |
<> | 144:ef7eb2e8f9f7 | 878 | Init->Waitfeature | \ |
<> | 144:ef7eb2e8f9f7 | 879 | FSMC_NAND_PCC_MEM_BUS_WIDTH_16 | \ |
<> | 144:ef7eb2e8f9f7 | 880 | (Init->TCLRSetupTime << POSITION_VAL(FSMC_PCRx_TCLR)) | \ |
<> | 144:ef7eb2e8f9f7 | 881 | (Init->TARSetupTime << POSITION_VAL(FSMC_PCRx_TAR)))); |
<> | 144:ef7eb2e8f9f7 | 882 | |
<> | 144:ef7eb2e8f9f7 | 883 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 884 | |
<> | 144:ef7eb2e8f9f7 | 885 | } |
<> | 144:ef7eb2e8f9f7 | 886 | |
<> | 144:ef7eb2e8f9f7 | 887 | /** |
<> | 144:ef7eb2e8f9f7 | 888 | * @brief Initializes the FSMC_PCCARD Common space Timing according to the specified |
<> | 144:ef7eb2e8f9f7 | 889 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
<> | 144:ef7eb2e8f9f7 | 890 | * @param Device: Pointer to PCCARD device instance |
<> | 144:ef7eb2e8f9f7 | 891 | * @param Timing: Pointer to PCCARD timing structure |
<> | 144:ef7eb2e8f9f7 | 892 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 893 | */ |
<> | 144:ef7eb2e8f9f7 | 894 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
<> | 144:ef7eb2e8f9f7 | 895 | { |
<> | 144:ef7eb2e8f9f7 | 896 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 897 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 898 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
<> | 144:ef7eb2e8f9f7 | 899 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 900 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 901 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 902 | |
<> | 144:ef7eb2e8f9f7 | 903 | /* Set PCCARD timing parameters */ |
<> | 144:ef7eb2e8f9f7 | 904 | MODIFY_REG(Device->PMEM4, PMEM_CLEAR_MASK, \ |
<> | 144:ef7eb2e8f9f7 | 905 | (Timing->SetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 906 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMWAITx)) | \ |
<> | 144:ef7eb2e8f9f7 | 907 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHOLDx)) | \ |
<> | 144:ef7eb2e8f9f7 | 908 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PMEMx_MEMHIZx)))); |
<> | 144:ef7eb2e8f9f7 | 909 | |
<> | 144:ef7eb2e8f9f7 | 910 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 911 | } |
<> | 144:ef7eb2e8f9f7 | 912 | |
<> | 144:ef7eb2e8f9f7 | 913 | /** |
<> | 144:ef7eb2e8f9f7 | 914 | * @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified |
<> | 144:ef7eb2e8f9f7 | 915 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
<> | 144:ef7eb2e8f9f7 | 916 | * @param Device: Pointer to PCCARD device instance |
<> | 144:ef7eb2e8f9f7 | 917 | * @param Timing: Pointer to PCCARD timing structure |
<> | 144:ef7eb2e8f9f7 | 918 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 919 | */ |
<> | 144:ef7eb2e8f9f7 | 920 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
<> | 144:ef7eb2e8f9f7 | 921 | { |
<> | 144:ef7eb2e8f9f7 | 922 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 923 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 924 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
<> | 144:ef7eb2e8f9f7 | 925 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 926 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 927 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 928 | |
<> | 144:ef7eb2e8f9f7 | 929 | /* Set PCCARD timing parameters */ |
<> | 144:ef7eb2e8f9f7 | 930 | MODIFY_REG(Device->PATT4, PATT_CLEAR_MASK, \ |
<> | 144:ef7eb2e8f9f7 | 931 | (Timing->SetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 932 | ((Timing->WaitSetupTime) << POSITION_VAL(FSMC_PATTx_ATTWAITx)) | \ |
<> | 144:ef7eb2e8f9f7 | 933 | ((Timing->HoldSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHOLDx)) | \ |
<> | 144:ef7eb2e8f9f7 | 934 | ((Timing->HiZSetupTime) << POSITION_VAL(FSMC_PATTx_ATTHIZx)))); |
<> | 144:ef7eb2e8f9f7 | 935 | |
<> | 144:ef7eb2e8f9f7 | 936 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 937 | } |
<> | 144:ef7eb2e8f9f7 | 938 | |
<> | 144:ef7eb2e8f9f7 | 939 | /** |
<> | 144:ef7eb2e8f9f7 | 940 | * @brief Initializes the FSMC_PCCARD IO space Timing according to the specified |
<> | 144:ef7eb2e8f9f7 | 941 | * parameters in the FSMC_NAND_PCC_TimingTypeDef |
<> | 144:ef7eb2e8f9f7 | 942 | * @param Device: Pointer to PCCARD device instance |
<> | 144:ef7eb2e8f9f7 | 943 | * @param Timing: Pointer to PCCARD timing structure |
<> | 144:ef7eb2e8f9f7 | 944 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 945 | */ |
<> | 144:ef7eb2e8f9f7 | 946 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing) |
<> | 144:ef7eb2e8f9f7 | 947 | { |
<> | 144:ef7eb2e8f9f7 | 948 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 949 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 950 | assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime)); |
<> | 144:ef7eb2e8f9f7 | 951 | assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 952 | assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 953 | assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime)); |
<> | 144:ef7eb2e8f9f7 | 954 | |
<> | 144:ef7eb2e8f9f7 | 955 | /* Set FSMC_PCCARD device timing parameters */ |
<> | 144:ef7eb2e8f9f7 | 956 | MODIFY_REG(Device->PIO4, PIO4_CLEAR_MASK, \ |
<> | 144:ef7eb2e8f9f7 | 957 | (Timing->SetupTime | \ |
<> | 144:ef7eb2e8f9f7 | 958 | (Timing->WaitSetupTime << POSITION_VAL(FSMC_PIO4_IOWAIT4)) | \ |
<> | 144:ef7eb2e8f9f7 | 959 | (Timing->HoldSetupTime << POSITION_VAL(FSMC_PIO4_IOHOLD4)) | \ |
<> | 144:ef7eb2e8f9f7 | 960 | (Timing->HiZSetupTime << POSITION_VAL(FSMC_PIO4_IOHIZ4)))); |
<> | 144:ef7eb2e8f9f7 | 961 | |
<> | 144:ef7eb2e8f9f7 | 962 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 963 | } |
<> | 144:ef7eb2e8f9f7 | 964 | |
<> | 144:ef7eb2e8f9f7 | 965 | /** |
<> | 144:ef7eb2e8f9f7 | 966 | * @brief DeInitializes the FSMC_PCCARD device |
<> | 144:ef7eb2e8f9f7 | 967 | * @param Device: Pointer to PCCARD device instance |
<> | 144:ef7eb2e8f9f7 | 968 | * @retval HAL status |
<> | 144:ef7eb2e8f9f7 | 969 | */ |
<> | 144:ef7eb2e8f9f7 | 970 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device) |
<> | 144:ef7eb2e8f9f7 | 971 | { |
<> | 144:ef7eb2e8f9f7 | 972 | /* Check the parameters */ |
<> | 144:ef7eb2e8f9f7 | 973 | assert_param(IS_FSMC_PCCARD_DEVICE(Device)); |
<> | 144:ef7eb2e8f9f7 | 974 | |
<> | 144:ef7eb2e8f9f7 | 975 | /* Disable the FSMC_PCCARD device */ |
<> | 144:ef7eb2e8f9f7 | 976 | __FSMC_PCCARD_DISABLE(Device); |
<> | 144:ef7eb2e8f9f7 | 977 | |
<> | 144:ef7eb2e8f9f7 | 978 | /* De-initialize the FSMC_PCCARD device */ |
<> | 144:ef7eb2e8f9f7 | 979 | WRITE_REG(Device->PCR4, 0x00000018); |
<> | 144:ef7eb2e8f9f7 | 980 | WRITE_REG(Device->SR4, 0x00000040); |
<> | 144:ef7eb2e8f9f7 | 981 | WRITE_REG(Device->PMEM4, 0xFCFCFCFC); |
<> | 144:ef7eb2e8f9f7 | 982 | WRITE_REG(Device->PATT4, 0xFCFCFCFC); |
<> | 144:ef7eb2e8f9f7 | 983 | WRITE_REG(Device->PIO4, 0xFCFCFCFC); |
<> | 144:ef7eb2e8f9f7 | 984 | |
<> | 144:ef7eb2e8f9f7 | 985 | return HAL_OK; |
<> | 144:ef7eb2e8f9f7 | 986 | } |
<> | 144:ef7eb2e8f9f7 | 987 | |
<> | 144:ef7eb2e8f9f7 | 988 | /** |
<> | 144:ef7eb2e8f9f7 | 989 | * @} |
<> | 144:ef7eb2e8f9f7 | 990 | */ |
<> | 144:ef7eb2e8f9f7 | 991 | |
<> | 144:ef7eb2e8f9f7 | 992 | /** |
<> | 144:ef7eb2e8f9f7 | 993 | * @} |
<> | 144:ef7eb2e8f9f7 | 994 | */ |
<> | 144:ef7eb2e8f9f7 | 995 | #endif /* STM32F101xE || STM32F103xE || STM32F101xG || STM32F103xG */ |
<> | 144:ef7eb2e8f9f7 | 996 | |
<> | 144:ef7eb2e8f9f7 | 997 | /** |
<> | 144:ef7eb2e8f9f7 | 998 | * @} |
<> | 144:ef7eb2e8f9f7 | 999 | */ |
<> | 144:ef7eb2e8f9f7 | 1000 | |
<> | 144:ef7eb2e8f9f7 | 1001 | /** |
<> | 144:ef7eb2e8f9f7 | 1002 | * @} |
<> | 144:ef7eb2e8f9f7 | 1003 | */ |
<> | 144:ef7eb2e8f9f7 | 1004 | |
<> | 144:ef7eb2e8f9f7 | 1005 | #endif /* FSMC_BANK1 */ |
<> | 144:ef7eb2e8f9f7 | 1006 | |
<> | 144:ef7eb2e8f9f7 | 1007 | #endif /* defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) */ |
<> | 144:ef7eb2e8f9f7 | 1008 | |
<> | 144:ef7eb2e8f9f7 | 1009 | /** |
<> | 144:ef7eb2e8f9f7 | 1010 | * @} |
<> | 144:ef7eb2e8f9f7 | 1011 | */ |
<> | 144:ef7eb2e8f9f7 | 1012 | |
<> | 144:ef7eb2e8f9f7 | 1013 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |