mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c@174:b96e65c34a4d, 2017-10-02 (annotated)

Committer:
AnnaBridge
Date:
Mon Oct 02 15:33:19 2017 +0100
Revision:
174:b96e65c34a4d
Parent:
173:e131a1973e81
Child:
177:d650f5d4c87a
This updates the lib to the mbed lib v 152

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:e84263d55307 1 /*
AnnaBridge 167:e84263d55307 2 * Copyright (c) 2013-2016 Realtek Semiconductor Corp.
AnnaBridge 167:e84263d55307 3 *
AnnaBridge 167:e84263d55307 4 * Licensed under the Apache License, Version 2.0 (the "License");
AnnaBridge 167:e84263d55307 5 * you may not use this file except in compliance with the License.
AnnaBridge 167:e84263d55307 6 * You may obtain a copy of the License at
AnnaBridge 167:e84263d55307 7 *
AnnaBridge 167:e84263d55307 8 * http://www.apache.org/licenses/LICENSE-2.0
AnnaBridge 167:e84263d55307 9 *
AnnaBridge 167:e84263d55307 10 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 167:e84263d55307 11 * distributed under the License is distributed on an "AS IS" BASIS,
AnnaBridge 167:e84263d55307 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 167:e84263d55307 13 * See the License for the specific language governing permissions and
AnnaBridge 167:e84263d55307 14 * limitations under the License.
AnnaBridge 167:e84263d55307 15 */
AnnaBridge 167:e84263d55307 16 #include "rtl8195a.h"
AnnaBridge 173:e131a1973e81 17
AnnaBridge 173:e131a1973e81 18 #if defined(__CC_ARM)
AnnaBridge 173:e131a1973e81 19 #include "cmsis_armcc.h"
AnnaBridge 174:b96e65c34a4d 20 #elif (defined(__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
AnnaBridge 174:b96e65c34a4d 21 #include "cmsis_armclang.h"
AnnaBridge 173:e131a1973e81 22 #elif defined(__GNUC__)
AnnaBridge 173:e131a1973e81 23 #include "cmsis_gcc.h"
AnnaBridge 173:e131a1973e81 24 #else
AnnaBridge 173:e131a1973e81 25 #include <cmsis_iar.h>
AnnaBridge 173:e131a1973e81 26 #endif
AnnaBridge 173:e131a1973e81 27
AnnaBridge 173:e131a1973e81 28
AnnaBridge 173:e131a1973e81 29 #if defined(__CC_ARM) || \
AnnaBridge 173:e131a1973e81 30 (defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
AnnaBridge 167:e84263d55307 31
AnnaBridge 173:e131a1973e81 32 extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
AnnaBridge 173:e131a1973e81 33 extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
AnnaBridge 173:e131a1973e81 34 extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
AnnaBridge 173:e131a1973e81 35 extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
AnnaBridge 173:e131a1973e81 36 extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
AnnaBridge 173:e131a1973e81 37 extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
AnnaBridge 173:e131a1973e81 38 #define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base
AnnaBridge 173:e131a1973e81 39 #define __bss_sram_end__ Image$$RW_IRAM2$$ZI$$Limit
AnnaBridge 173:e131a1973e81 40 #define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
AnnaBridge 173:e131a1973e81 41 #define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
AnnaBridge 173:e131a1973e81 42 #define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
AnnaBridge 173:e131a1973e81 43 #define __bss_dram_end__ Image$$RW_DRAM2$$ZI$$Limit
AnnaBridge 173:e131a1973e81 44
AnnaBridge 173:e131a1973e81 45 #elif defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 46
AnnaBridge 167:e84263d55307 47 #pragma section=".ram.bss"
AnnaBridge 167:e84263d55307 48
AnnaBridge 167:e84263d55307 49 uint8_t *__bss_start__;
AnnaBridge 167:e84263d55307 50 uint8_t *__bss_end__;
AnnaBridge 167:e84263d55307 51
AnnaBridge 167:e84263d55307 52 void __iar_data_init_app(void)
AnnaBridge 167:e84263d55307 53 {
AnnaBridge 167:e84263d55307 54 __bss_start__ = (uint8_t *)__section_begin(".ram.bss");
AnnaBridge 167:e84263d55307 55 __bss_end__ = (uint8_t *)__section_end(".ram.bss");
AnnaBridge 167:e84263d55307 56 }
AnnaBridge 173:e131a1973e81 57
AnnaBridge 167:e84263d55307 58 #else
AnnaBridge 173:e131a1973e81 59
AnnaBridge 173:e131a1973e81 60 extern uint8_t __bss_sram_start__[];
AnnaBridge 173:e131a1973e81 61 extern uint8_t __bss_sram_end__[];
AnnaBridge 173:e131a1973e81 62 extern uint8_t __bss_dtcm_start__[];
AnnaBridge 173:e131a1973e81 63 extern uint8_t __bss_dtcm_end__[];
AnnaBridge 173:e131a1973e81 64 extern uint8_t __bss_dram_start__[];
AnnaBridge 173:e131a1973e81 65 extern uint8_t __bss_dram_end__[];
AnnaBridge 173:e131a1973e81 66
AnnaBridge 167:e84263d55307 67 #endif
AnnaBridge 167:e84263d55307 68
AnnaBridge 167:e84263d55307 69 extern VECTOR_Func NewVectorTable[];
AnnaBridge 167:e84263d55307 70 extern void SystemCoreClockUpdate(void);
AnnaBridge 167:e84263d55307 71 extern void PLAT_Start(void);
AnnaBridge 167:e84263d55307 72 extern void PLAT_Main(void);
AnnaBridge 173:e131a1973e81 73
AnnaBridge 173:e131a1973e81 74 IMAGE2_START_RAM_FUN_SECTION
AnnaBridge 173:e131a1973e81 75 const RAM_START_FUNCTION gImage2EntryFun0 = {
AnnaBridge 167:e84263d55307 76 PLAT_Start
AnnaBridge 167:e84263d55307 77 };
AnnaBridge 167:e84263d55307 78
AnnaBridge 173:e131a1973e81 79 IMAGE2_VALID_PATTEN_SECTION
AnnaBridge 173:e131a1973e81 80 const uint8_t IMAGE2_SIGNATURE[20] = {
AnnaBridge 167:e84263d55307 81 'R', 'T', 'K', 'W', 'i', 'n', 0x0, 0xff,
AnnaBridge 167:e84263d55307 82 (FW_VERSION&0xff), ((FW_VERSION >> 8)&0xff),
AnnaBridge 167:e84263d55307 83 (FW_SUBVERSION&0xff), ((FW_SUBVERSION >> 8)&0xff),
AnnaBridge 167:e84263d55307 84 (FW_CHIP_ID&0xff), ((FW_CHIP_ID >> 8)&0xff),
AnnaBridge 167:e84263d55307 85 (FW_CHIP_VER),
AnnaBridge 167:e84263d55307 86 (FW_BUS_TYPE),
AnnaBridge 167:e84263d55307 87 (FW_INFO_RSV1),
AnnaBridge 167:e84263d55307 88 (FW_INFO_RSV2),
AnnaBridge 167:e84263d55307 89 (FW_INFO_RSV3),
AnnaBridge 167:e84263d55307 90 (FW_INFO_RSV4)
AnnaBridge 167:e84263d55307 91 };
AnnaBridge 167:e84263d55307 92
AnnaBridge 167:e84263d55307 93 void TRAP_NMIHandler(void)
AnnaBridge 167:e84263d55307 94 {
AnnaBridge 167:e84263d55307 95 #ifdef CONFIG_WDG_NORMAL
AnnaBridge 167:e84263d55307 96 uint32_t val;
AnnaBridge 167:e84263d55307 97 WDG_REG *ctl;
AnnaBridge 167:e84263d55307 98
AnnaBridge 167:e84263d55307 99 // Check if this NMI is triggered by Watchdog Timer
AnnaBridge 167:e84263d55307 100 val = __RTK_READ32(VENDOR_REG_BASE, 0);
AnnaBridge 167:e84263d55307 101 ctl = (WDG_REG*) &val;
AnnaBridge 167:e84263d55307 102 if (ctl->WdgToISR) {
AnnaBridge 167:e84263d55307 103 INTR_WatchdogHandler();
AnnaBridge 167:e84263d55307 104 }
AnnaBridge 167:e84263d55307 105 #endif
AnnaBridge 167:e84263d55307 106 }
AnnaBridge 167:e84263d55307 107
AnnaBridge 173:e131a1973e81 108 #if defined (__ICCARM__)
AnnaBridge 167:e84263d55307 109 void __TRAP_HardFaultHandler_Patch(uint32_t addr)
AnnaBridge 167:e84263d55307 110 {
AnnaBridge 167:e84263d55307 111 uint32_t cfsr;
AnnaBridge 167:e84263d55307 112 uint32_t bfar;
AnnaBridge 167:e84263d55307 113
AnnaBridge 167:e84263d55307 114 uint32_t stackpc;
AnnaBridge 167:e84263d55307 115 uint16_t asmcode;
AnnaBridge 167:e84263d55307 116
AnnaBridge 167:e84263d55307 117 cfsr = HAL_READ32(0xE000ED28, 0x0);
AnnaBridge 167:e84263d55307 118
AnnaBridge 167:e84263d55307 119 // Violation to memory access protection
AnnaBridge 167:e84263d55307 120 if (cfsr & 0x82) {
AnnaBridge 167:e84263d55307 121
AnnaBridge 167:e84263d55307 122 bfar = HAL_READ32(0xE000ED38, 0x0);
AnnaBridge 167:e84263d55307 123
AnnaBridge 167:e84263d55307 124 // invalid access to wifi register, usually happened in LPS 32K or IPS
AnnaBridge 167:e84263d55307 125 if (bfar >= WIFI_REG_BASE && bfar < WIFI_REG_BASE + 0x40000) {
AnnaBridge 167:e84263d55307 126
AnnaBridge 167:e84263d55307 127 //__BKPT(0);
AnnaBridge 167:e84263d55307 128
AnnaBridge 167:e84263d55307 129 /* Get the MemManage fault PC, and step to next command.
AnnaBridge 167:e84263d55307 130 * Otherwise it will keep hitting MemMange Fault on the same assembly code.
AnnaBridge 167:e84263d55307 131 *
AnnaBridge 167:e84263d55307 132 * To step to next command, we need parse the assembly code to check if
AnnaBridge 173:e131a1973e81 133 * it is 16-bit or 32-bit command.
AnnaBridge 167:e84263d55307 134 * Ref: ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
AnnaBridge 173:e131a1973e81 135 * Chapter A6 - Thumb Instruction Set Encoding
AnnaBridge 167:e84263d55307 136 *
AnnaBridge 167:e84263d55307 137 * However, the fault assembly code (Ex. LDR or ADR) is not actually executed,
AnnaBridge 167:e84263d55307 138 * So the register value is un-predictable.
AnnaBridge 167:e84263d55307 139 **/
AnnaBridge 167:e84263d55307 140 stackpc = HAL_READ32(addr, 0x18);
AnnaBridge 167:e84263d55307 141 asmcode = HAL_READ16(stackpc, 0);
AnnaBridge 167:e84263d55307 142 if ((asmcode & 0xF800) > 0xE000) {
AnnaBridge 167:e84263d55307 143 // 32-bit instruction, (opcode[15:11] = 0b11111, 0b11110, 0b11101)
AnnaBridge 167:e84263d55307 144 HAL_WRITE32(addr, 0x18, stackpc + 4);
AnnaBridge 167:e84263d55307 145 } else {
AnnaBridge 167:e84263d55307 146 // 16-bit instruction
AnnaBridge 167:e84263d55307 147 HAL_WRITE32(addr, 0x18, stackpc + 2);
AnnaBridge 167:e84263d55307 148 }
AnnaBridge 167:e84263d55307 149
AnnaBridge 167:e84263d55307 150 // clear Hard Fault Status Register
AnnaBridge 167:e84263d55307 151 HAL_WRITE32(0xE000ED2C, 0x0, HAL_READ32(0xE000ED2C, 0x0));
AnnaBridge 167:e84263d55307 152 return;
AnnaBridge 167:e84263d55307 153 }
AnnaBridge 167:e84263d55307 154 }
AnnaBridge 167:e84263d55307 155
AnnaBridge 167:e84263d55307 156 __TRAP_HardFaultHandler(addr);
AnnaBridge 167:e84263d55307 157 }
AnnaBridge 167:e84263d55307 158
AnnaBridge 167:e84263d55307 159 void TRAP_HardFaultHandler_Patch(void)
AnnaBridge 167:e84263d55307 160 {
AnnaBridge 167:e84263d55307 161 __asm("TST LR, #4 \n"
AnnaBridge 167:e84263d55307 162 "ITE EQ \n"
AnnaBridge 167:e84263d55307 163 "MRSEQ R0, MSP \n"
AnnaBridge 167:e84263d55307 164 "MRSNE R0, PSP \n"
AnnaBridge 167:e84263d55307 165 "B __TRAP_HardFaultHandler_Patch ");
AnnaBridge 167:e84263d55307 166 }
AnnaBridge 167:e84263d55307 167 #endif
AnnaBridge 167:e84263d55307 168
AnnaBridge 173:e131a1973e81 169 extern _LONG_CALL_ void * __rtl_memset_v1_00(void * m , int c , size_t n);
AnnaBridge 173:e131a1973e81 170 // Image2 Entry Function
AnnaBridge 174:b96e65c34a4d 171 void PLAT_Init(void)
AnnaBridge 167:e84263d55307 172 {
AnnaBridge 167:e84263d55307 173 uint32_t val;
AnnaBridge 167:e84263d55307 174
AnnaBridge 174:b96e65c34a4d 175 // Overwrite vector table
AnnaBridge 174:b96e65c34a4d 176 NewVectorTable[2] = (VECTOR_Func) TRAP_NMIHandler;
AnnaBridge 174:b96e65c34a4d 177 #if defined ( __ICCARM__ )
AnnaBridge 174:b96e65c34a4d 178 NewVectorTable[3] = (VECTOR_Func) TRAP_HardFaultHandler_Patch;
AnnaBridge 173:e131a1973e81 179 #endif
AnnaBridge 173:e131a1973e81 180
AnnaBridge 173:e131a1973e81 181 // Clear RAM BSS
AnnaBridge 173:e131a1973e81 182 #if defined (__ICCARM__)
AnnaBridge 174:b96e65c34a4d 183 __iar_data_init_app();
AnnaBridge 173:e131a1973e81 184 __rtl_memset_v1_00((void *)__bss_start__, 0, __bss_end__ - __bss_start__);
AnnaBridge 173:e131a1973e81 185 #else
AnnaBridge 173:e131a1973e81 186 __rtl_memset_v1_00((void *)__bss_sram_start__, 0, __bss_sram_end__ - __bss_sram_start__);
AnnaBridge 173:e131a1973e81 187 __rtl_memset_v1_00((void *)__bss_dtcm_start__, 0, __bss_dtcm_end__ - __bss_dtcm_start__);
AnnaBridge 173:e131a1973e81 188 __rtl_memset_v1_00((void *)__bss_dram_start__, 0, __bss_dram_end__ - __bss_dram_start__);
AnnaBridge 173:e131a1973e81 189 #endif
AnnaBridge 173:e131a1973e81 190
AnnaBridge 173:e131a1973e81 191 extern HAL_TIMER_OP_EXT HalTimerOpExt;
AnnaBridge 173:e131a1973e81 192 __rtl_memset_v1_00((void *)&HalTimerOpExt, 0, sizeof(HalTimerOpExt));
AnnaBridge 173:e131a1973e81 193 __rtl_memset_v1_00((void *)&HalTimerOp, 0, sizeof(HalTimerOp));
AnnaBridge 173:e131a1973e81 194
AnnaBridge 173:e131a1973e81 195 HalTimerOpInit_Patch(&HalTimerOp);
AnnaBridge 173:e131a1973e81 196 SystemCoreClockUpdate();
AnnaBridge 173:e131a1973e81 197
AnnaBridge 173:e131a1973e81 198 // Set SPS lower voltage
AnnaBridge 167:e84263d55307 199 val = __RTK_CTRL_READ32(REG_SYS_EFUSE_SYSCFG0);
AnnaBridge 167:e84263d55307 200 val &= 0xf0ffffff;
AnnaBridge 167:e84263d55307 201 val |= 0x6000000;
AnnaBridge 167:e84263d55307 202 __RTK_CTRL_WRITE32(REG_SYS_EFUSE_SYSCFG0, val);
AnnaBridge 173:e131a1973e81 203
AnnaBridge 173:e131a1973e81 204 // xtal buffer driving current
AnnaBridge 167:e84263d55307 205 val = __RTK_CTRL_READ32(REG_SYS_XTAL_CTRL1);
AnnaBridge 167:e84263d55307 206 val &= ~(BIT_MASK_SYS_XTAL_DRV_RF1 << BIT_SHIFT_SYS_XTAL_DRV_RF1);
AnnaBridge 167:e84263d55307 207 val |= BIT_SYS_XTAL_DRV_RF1(1);
AnnaBridge 167:e84263d55307 208 __RTK_CTRL_WRITE32(REG_SYS_XTAL_CTRL1, val);
AnnaBridge 167:e84263d55307 209
AnnaBridge 173:e131a1973e81 210 // Initialize SPIC, then disable it for power saving.
AnnaBridge 173:e131a1973e81 211 if ((HAL_PERI_ON_READ32(REG_SOC_FUNC_EN) & BIT_SOC_FLASH_EN) != 0) {
AnnaBridge 173:e131a1973e81 212 SpicNVMCalLoadAll();
AnnaBridge 173:e131a1973e81 213 SpicReadIDRtl8195A();
AnnaBridge 173:e131a1973e81 214 SpicDisableRtl8195A();
AnnaBridge 173:e131a1973e81 215 }
AnnaBridge 167:e84263d55307 216
AnnaBridge 167:e84263d55307 217 #ifdef CONFIG_TIMER_MODULE
AnnaBridge 173:e131a1973e81 218 Calibration32k();
AnnaBridge 167:e84263d55307 219 #endif
AnnaBridge 167:e84263d55307 220
AnnaBridge 167:e84263d55307 221 #ifndef CONFIG_SDIO_DEVICE_EN
AnnaBridge 167:e84263d55307 222 SDIO_DEV_Disable();
AnnaBridge 167:e84263d55307 223 #endif
AnnaBridge 167:e84263d55307 224
AnnaBridge 167:e84263d55307 225 // Enter App start function
AnnaBridge 167:e84263d55307 226 PLAT_Main();
AnnaBridge 167:e84263d55307 227 }
AnnaBridge 167:e84263d55307 228
AnnaBridge 167:e84263d55307 229 extern void SVC_Handler(void);
AnnaBridge 167:e84263d55307 230 extern void PendSV_Handler(void);
AnnaBridge 167:e84263d55307 231 extern void SysTick_Handler(void);
AnnaBridge 167:e84263d55307 232
AnnaBridge 173:e131a1973e81 233 // The Main App entry point
AnnaBridge 167:e84263d55307 234 #if defined (__CC_ARM)
AnnaBridge 167:e84263d55307 235 __asm void ARM_PLAT_Main(void)
AnnaBridge 167:e84263d55307 236 {
AnnaBridge 173:e131a1973e81 237 IMPORT SystemInit
AnnaBridge 173:e131a1973e81 238 IMPORT __main
AnnaBridge 173:e131a1973e81 239 BL SystemInit
AnnaBridge 173:e131a1973e81 240 BL __main
AnnaBridge 173:e131a1973e81 241 }
AnnaBridge 173:e131a1973e81 242 #elif defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 243 extern void __iar_program_start(void);
AnnaBridge 173:e131a1973e81 244
AnnaBridge 173:e131a1973e81 245 void IAR_PLAT_Main(void)
AnnaBridge 173:e131a1973e81 246 {
AnnaBridge 173:e131a1973e81 247 SystemInit();
AnnaBridge 173:e131a1973e81 248 __iar_program_start();
AnnaBridge 167:e84263d55307 249 }
AnnaBridge 167:e84263d55307 250 #endif
AnnaBridge 167:e84263d55307 251
AnnaBridge 167:e84263d55307 252 void PLAT_Main(void)
AnnaBridge 167:e84263d55307 253 {
AnnaBridge 167:e84263d55307 254 TRAP_Init((void *)SVC_Handler, (void *)PendSV_Handler, (void *)SysTick_Handler);
AnnaBridge 167:e84263d55307 255
AnnaBridge 173:e131a1973e81 256 #if defined (__CC_ARM)
AnnaBridge 173:e131a1973e81 257 ARM_PLAT_Main();
AnnaBridge 173:e131a1973e81 258 #elif defined (__ICCARM__)
AnnaBridge 173:e131a1973e81 259 IAR_PLAT_Main();
AnnaBridge 173:e131a1973e81 260 #else
AnnaBridge 173:e131a1973e81 261 __asm ("ldr r0, =SystemInit \n"
AnnaBridge 167:e84263d55307 262 "blx r0 \n"
AnnaBridge 174:b96e65c34a4d 263 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
AnnaBridge 174:b96e65c34a4d 264 "ldr r0, =__main \n"
AnnaBridge 174:b96e65c34a4d 265 #else
AnnaBridge 167:e84263d55307 266 "ldr r0, =_start \n"
AnnaBridge 174:b96e65c34a4d 267 #endif
AnnaBridge 167:e84263d55307 268 "bx r0 \n"
AnnaBridge 167:e84263d55307 269 );
AnnaBridge 167:e84263d55307 270 #endif
AnnaBridge 173:e131a1973e81 271
AnnaBridge 167:e84263d55307 272 // Never reached
AnnaBridge 173:e131a1973e81 273 for (;;);
AnnaBridge 167:e84263d55307 274 }