mbed official / mbed-dev

mbed library sources. Supersedes mbed-src.

Dependents:   Nucleo_Hello_Encoder BLE_iBeaconScan AM1805_DEMO DISCO-F429ZI_ExportTemplate1 ... more

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_uart_ex.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Parent:
149:156823d33999
Child:
180:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f0xx_hal_uart_ex.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.5.0
<> 156:95d6b41a828b 6 * @date 04-November-2016
<> 156:95d6b41a828b 7 * @brief Header file of UART HAL Extended module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F0xx_HAL_UART_EX_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F0xx_HAL_UART_EX_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f0xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F0xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 /** @addtogroup UARTEx
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 */
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 58 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 59 /** @defgroup UARTEx_Exported_Types UARTEx Exported Types
<> 144:ef7eb2e8f9f7 60 * @{
<> 144:ef7eb2e8f9f7 61 */
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 /**
<> 144:ef7eb2e8f9f7 64 * @brief UART wake up from stop mode parameters
<> 144:ef7eb2e8f9f7 65 */
<> 144:ef7eb2e8f9f7 66 typedef struct
<> 144:ef7eb2e8f9f7 67 {
<> 144:ef7eb2e8f9f7 68 uint32_t WakeUpEvent; /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
<> 144:ef7eb2e8f9f7 69 This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
<> 144:ef7eb2e8f9f7 70 If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
<> 144:ef7eb2e8f9f7 71 be filled up. */
<> 144:ef7eb2e8f9f7 72
<> 144:ef7eb2e8f9f7 73 uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
<> 156:95d6b41a828b 74 This parameter can be a value of @ref UART_WakeUp_Address_Length. */
<> 144:ef7eb2e8f9f7 75
<> 156:95d6b41a828b 76 uint8_t Address; /*!< UART/USART node address (7-bit long max). */
<> 144:ef7eb2e8f9f7 77 } UART_WakeUpTypeDef;
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 /**
<> 144:ef7eb2e8f9f7 80 * @}
<> 144:ef7eb2e8f9f7 81 */
<> 144:ef7eb2e8f9f7 82 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 85 /** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
<> 144:ef7eb2e8f9f7 86 * @{
<> 144:ef7eb2e8f9f7 87 */
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /** @defgroup UARTEx_Word_Length UARTEx Word Length
<> 144:ef7eb2e8f9f7 90 * @{
<> 144:ef7eb2e8f9f7 91 */
<> 144:ef7eb2e8f9f7 92 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 93 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 94 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 156:95d6b41a828b 95 #define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long UART frame */
<> 156:95d6b41a828b 96 #define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
<> 156:95d6b41a828b 97 #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long UART frame */
<> 144:ef7eb2e8f9f7 98 #else
<> 156:95d6b41a828b 99 #define UART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long UART frame */
<> 156:95d6b41a828b 100 #define UART_WORDLENGTH_9B ((uint32_t)USART_CR1_M) /*!< 9-bit long UART frame */
<> 144:ef7eb2e8f9f7 101 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 102 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 103 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 104 /**
<> 144:ef7eb2e8f9f7 105 * @}
<> 144:ef7eb2e8f9f7 106 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /** @defgroup UARTEx_AutoBaud_Rate_Mode UARTEx Advanced Feature AutoBaud Rate Mode
<> 144:ef7eb2e8f9f7 109 * @{
<> 144:ef7eb2e8f9f7 110 */
<> 144:ef7eb2e8f9f7 111 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 112 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 113 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 156:95d6b41a828b 114 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */
<> 144:ef7eb2e8f9f7 115 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
<> 144:ef7eb2e8f9f7 116 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /*!< Auto Baud rate detection on 0x7F frame detection */
<> 144:ef7eb2e8f9f7 117 #define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /*!< Auto Baud rate detection on 0x55 frame detection */
<> 144:ef7eb2e8f9f7 118 #else
<> 156:95d6b41a828b 119 #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT (0x00000000U) /*!< Auto Baud rate detection on start bit */
<> 144:ef7eb2e8f9f7 120 #define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /*!< Auto Baud rate detection on falling edge */
<> 144:ef7eb2e8f9f7 121 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 122 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 123 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 124 /**
<> 144:ef7eb2e8f9f7 125 * @}
<> 156:95d6b41a828b 126 */
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 129 /** @defgroup UARTEx_LIN UARTEx Local Interconnection Network mode
<> 144:ef7eb2e8f9f7 130 * @{
<> 144:ef7eb2e8f9f7 131 */
<> 156:95d6b41a828b 132 #define UART_LIN_DISABLE (0x00000000U) /*!< Local Interconnect Network disable */
<> 144:ef7eb2e8f9f7 133 #define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /*!< Local Interconnect Network enable */
<> 144:ef7eb2e8f9f7 134 /**
<> 144:ef7eb2e8f9f7 135 * @}
<> 156:95d6b41a828b 136 */
<> 156:95d6b41a828b 137
<> 144:ef7eb2e8f9f7 138 /** @defgroup UARTEx_LIN_Break_Detection UARTEx LIN Break Detection
<> 144:ef7eb2e8f9f7 139 * @{
<> 144:ef7eb2e8f9f7 140 */
<> 156:95d6b41a828b 141 #define UART_LINBREAKDETECTLENGTH_10B (0x00000000U) /*!< LIN 10-bit break detection length */
<> 144:ef7eb2e8f9f7 142 #define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /*!< LIN 11-bit break detection length */
<> 144:ef7eb2e8f9f7 143 /**
<> 144:ef7eb2e8f9f7 144 * @}
<> 156:95d6b41a828b 145 */
<> 144:ef7eb2e8f9f7 146 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /** @defgroup UART_Flags UARTEx Status Flags
<> 144:ef7eb2e8f9f7 149 * Elements values convention: 0xXXXX
<> 144:ef7eb2e8f9f7 150 * - 0xXXXX : Flag mask in the ISR register
<> 144:ef7eb2e8f9f7 151 * @{
<> 144:ef7eb2e8f9f7 152 */
<> 144:ef7eb2e8f9f7 153 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 154 #define UART_FLAG_REACK (0x00400000U) /*!< UART receive enable acknowledge flag */
<> 144:ef7eb2e8f9f7 155 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 156 #define UART_FLAG_TEACK (0x00200000U) /*!< UART transmit enable acknowledge flag */
<> 144:ef7eb2e8f9f7 157 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 158 #define UART_FLAG_WUF (0x00100000U) /*!< UART wake-up from stop mode flag */
<> 144:ef7eb2e8f9f7 159 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 160 #define UART_FLAG_RWU (0x00080000U) /*!< UART receiver wake-up from mute mode flag */
<> 156:95d6b41a828b 161 #define UART_FLAG_SBKF (0x00040000U) /*!< UART send break flag */
<> 156:95d6b41a828b 162 #define UART_FLAG_CMF (0x00020000U) /*!< UART character match flag */
<> 156:95d6b41a828b 163 #define UART_FLAG_BUSY (0x00010000U) /*!< UART busy flag */
<> 156:95d6b41a828b 164 #define UART_FLAG_ABRF (0x00008000U) /*!< UART auto Baud rate flag */
<> 156:95d6b41a828b 165 #define UART_FLAG_ABRE (0x00004000U) /*!< UART auto Baud rate error */
<> 144:ef7eb2e8f9f7 166 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 167 #define UART_FLAG_EOBF (0x00001000U) /*!< UART end of block flag */
<> 144:ef7eb2e8f9f7 168 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 169 #define UART_FLAG_RTOF (0x00000800U) /*!< UART receiver timeout flag */
<> 156:95d6b41a828b 170 #define UART_FLAG_CTS (0x00000400U) /*!< UART clear to send flag */
<> 156:95d6b41a828b 171 #define UART_FLAG_CTSIF (0x00000200U) /*!< UART clear to send interrupt flag */
<> 144:ef7eb2e8f9f7 172 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 173 #define UART_FLAG_LBDF (0x00000100U) /*!< UART LIN break detection flag (not available on F030xx devices)*/
<> 144:ef7eb2e8f9f7 174 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 175 #define UART_FLAG_TXE (0x00000080U) /*!< UART transmit data register empty */
<> 156:95d6b41a828b 176 #define UART_FLAG_TC (0x00000040U) /*!< UART transmission complete */
<> 156:95d6b41a828b 177 #define UART_FLAG_RXNE (0x00000020U) /*!< UART read data register not empty */
<> 156:95d6b41a828b 178 #define UART_FLAG_IDLE (0x00000010U) /*!< UART idle flag */
<> 156:95d6b41a828b 179 #define UART_FLAG_ORE (0x00000008U) /*!< UART overrun error */
<> 156:95d6b41a828b 180 #define UART_FLAG_NE (0x00000004U) /*!< UART noise error */
<> 156:95d6b41a828b 181 #define UART_FLAG_FE (0x00000002U) /*!< UART frame error */
<> 156:95d6b41a828b 182 #define UART_FLAG_PE (0x00000001U) /*!< UART parity error */
<> 144:ef7eb2e8f9f7 183 /**
<> 144:ef7eb2e8f9f7 184 * @}
<> 144:ef7eb2e8f9f7 185 */
<> 144:ef7eb2e8f9f7 186
<> 144:ef7eb2e8f9f7 187 /** @defgroup UART_Interrupt_definition UARTEx Interrupts Definition
<> 156:95d6b41a828b 188 * Elements values convention: 000ZZZZZ0XXYYYYYb
<> 144:ef7eb2e8f9f7 189 * - YYYYY : Interrupt source position in the XX register (5bits)
<> 144:ef7eb2e8f9f7 190 * - XX : Interrupt source register (2bits)
<> 144:ef7eb2e8f9f7 191 * - 01: CR1 register
<> 144:ef7eb2e8f9f7 192 * - 10: CR2 register
<> 144:ef7eb2e8f9f7 193 * - 11: CR3 register
<> 144:ef7eb2e8f9f7 194 * - ZZZZZ : Flag position in the ISR register(5bits)
<> 156:95d6b41a828b 195 * @{
<> 156:95d6b41a828b 196 */
<> 156:95d6b41a828b 197 #define UART_IT_PE (0x0028U) /*!< UART parity error interruption */
<> 156:95d6b41a828b 198 #define UART_IT_TXE (0x0727U) /*!< UART transmit data register empty interruption */
<> 156:95d6b41a828b 199 #define UART_IT_TC (0x0626U) /*!< UART transmission complete interruption */
<> 156:95d6b41a828b 200 #define UART_IT_RXNE (0x0525U) /*!< UART read data register not empty interruption */
<> 156:95d6b41a828b 201 #define UART_IT_IDLE (0x0424U) /*!< UART idle interruption */
<> 144:ef7eb2e8f9f7 202 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 203 #define UART_IT_LBD (0x0846U) /*!< UART LIN break detection interruption */
<> 144:ef7eb2e8f9f7 204 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 205 #define UART_IT_CTS (0x096AU) /*!< UART CTS interruption */
<> 156:95d6b41a828b 206 #define UART_IT_CM (0x112EU) /*!< UART character match interruption */
<> 144:ef7eb2e8f9f7 207 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 208 #define UART_IT_WUF (0x1476U) /*!< UART wake-up from stop mode interruption */
<> 144:ef7eb2e8f9f7 209 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 210 /**
<> 144:ef7eb2e8f9f7 211 * @}
<> 144:ef7eb2e8f9f7 212 */
<> 144:ef7eb2e8f9f7 213
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /** @defgroup UART_IT_CLEAR_Flags UARTEx Interruption Clear Flags
<> 144:ef7eb2e8f9f7 216 * @{
<> 144:ef7eb2e8f9f7 217 */
<> 156:95d6b41a828b 218 #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */
<> 156:95d6b41a828b 219 #define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */
<> 156:95d6b41a828b 220 #define UART_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */
<> 156:95d6b41a828b 221 #define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */
<> 156:95d6b41a828b 222 #define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */
<> 156:95d6b41a828b 223 #define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */
<> 144:ef7eb2e8f9f7 224 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 225 #define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag (not available on F030xx devices)*/
<> 144:ef7eb2e8f9f7 226 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 227 #define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */
<> 156:95d6b41a828b 228 #define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */
<> 144:ef7eb2e8f9f7 229 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 230 #define UART_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */
<> 144:ef7eb2e8f9f7 231 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 156:95d6b41a828b 232 #define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */
<> 144:ef7eb2e8f9f7 233 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 234 #define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */
<> 144:ef7eb2e8f9f7 235 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 236 /**
<> 144:ef7eb2e8f9f7 237 * @}
<> 156:95d6b41a828b 238 */
<> 144:ef7eb2e8f9f7 239
<> 144:ef7eb2e8f9f7 240 /** @defgroup UART_Request_Parameters UARTEx Request Parameters
<> 144:ef7eb2e8f9f7 241 * @{
<> 144:ef7eb2e8f9f7 242 */
<> 156:95d6b41a828b 243 #define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */
<> 156:95d6b41a828b 244 #define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /*!< Send Break Request */
<> 156:95d6b41a828b 245 #define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /*!< Mute Mode Request */
<> 156:95d6b41a828b 246 #define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */
<> 144:ef7eb2e8f9f7 247 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 156:95d6b41a828b 248 #define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */
<> 144:ef7eb2e8f9f7 249 #else
<> 144:ef7eb2e8f9f7 250 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 251 /**
<> 144:ef7eb2e8f9f7 252 * @}
<> 144:ef7eb2e8f9f7 253 */
<> 144:ef7eb2e8f9f7 254
<> 144:ef7eb2e8f9f7 255 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 256 /** @defgroup UART_Stop_Mode_Enable UARTEx Advanced Feature Stop Mode Enable
<> 144:ef7eb2e8f9f7 257 * @{
<> 144:ef7eb2e8f9f7 258 */
<> 156:95d6b41a828b 259 #define UART_ADVFEATURE_STOPMODE_DISABLE (0x00000000U) /*!< UART stop mode disable */
<> 144:ef7eb2e8f9f7 260 #define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /*!< UART stop mode enable */
<> 144:ef7eb2e8f9f7 261 /**
<> 144:ef7eb2e8f9f7 262 * @}
<> 156:95d6b41a828b 263 */
<> 144:ef7eb2e8f9f7 264
<> 144:ef7eb2e8f9f7 265 /** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
<> 144:ef7eb2e8f9f7 266 * @{
<> 144:ef7eb2e8f9f7 267 */
<> 156:95d6b41a828b 268 #define UART_WAKEUP_ON_ADDRESS (0x00000000U) /*!< UART wake-up on address */
<> 144:ef7eb2e8f9f7 269 #define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /*!< UART wake-up on start bit */
<> 144:ef7eb2e8f9f7 270 #define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /*!< UART wake-up on receive data register not empty */
<> 144:ef7eb2e8f9f7 271 /**
<> 144:ef7eb2e8f9f7 272 * @}
<> 144:ef7eb2e8f9f7 273 */
<> 144:ef7eb2e8f9f7 274 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /**
<> 144:ef7eb2e8f9f7 277 * @}
<> 144:ef7eb2e8f9f7 278 */
<> 144:ef7eb2e8f9f7 279
<> 144:ef7eb2e8f9f7 280 /* Exported macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 281 /** @defgroup UARTEx_Exported_Macros UARTEx Exported Macros
<> 144:ef7eb2e8f9f7 282 * @{
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /** @brief Flush the UART Data registers.
<> 144:ef7eb2e8f9f7 286 * @param __HANDLE__: specifies the UART Handle.
<> 156:95d6b41a828b 287 * @retval None
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289 #if !defined(STM32F030x6) && !defined(STM32F030x8)
<> 144:ef7eb2e8f9f7 290 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 291 do{ \
<> 144:ef7eb2e8f9f7 292 SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 293 SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 294 } while(0)
<> 144:ef7eb2e8f9f7 295 #else
<> 144:ef7eb2e8f9f7 296 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
<> 144:ef7eb2e8f9f7 297 do{ \
<> 144:ef7eb2e8f9f7 298 SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
<> 144:ef7eb2e8f9f7 299 } while(0)
<> 144:ef7eb2e8f9f7 300 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) */
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /**
<> 144:ef7eb2e8f9f7 303 * @}
<> 144:ef7eb2e8f9f7 304 */
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /* Private macros ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 307 /** @defgroup UARTEx_Private_Macros UARTEx Private Macros
<> 144:ef7eb2e8f9f7 308 * @{
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /** @brief Report the UART clock source.
<> 144:ef7eb2e8f9f7 312 * @param __HANDLE__: specifies the UART Handle.
<> 144:ef7eb2e8f9f7 313 * @param __CLOCKSOURCE__: output variable.
<> 144:ef7eb2e8f9f7 314 * @retval UART clocking source, written in __CLOCKSOURCE__.
<> 144:ef7eb2e8f9f7 315 */
<> 144:ef7eb2e8f9f7 316 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
<> 144:ef7eb2e8f9f7 317 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 318 do { \
<> 144:ef7eb2e8f9f7 319 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 320 { \
<> 144:ef7eb2e8f9f7 321 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 322 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 323 break; \
<> 144:ef7eb2e8f9f7 324 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 325 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 326 break; \
<> 144:ef7eb2e8f9f7 327 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 328 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 329 break; \
<> 144:ef7eb2e8f9f7 330 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 331 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 332 break; \
<> 144:ef7eb2e8f9f7 333 default: \
<> 144:ef7eb2e8f9f7 334 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 335 break; \
<> 144:ef7eb2e8f9f7 336 } \
<> 144:ef7eb2e8f9f7 337 } while(0)
<> 144:ef7eb2e8f9f7 338 #elif defined (STM32F030x8) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 339 defined (STM32F042x6) || defined (STM32F048xx) || \
<> 144:ef7eb2e8f9f7 340 defined (STM32F051x8) || defined (STM32F058xx)
<> 144:ef7eb2e8f9f7 341 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 342 do { \
<> 144:ef7eb2e8f9f7 343 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 344 { \
<> 144:ef7eb2e8f9f7 345 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 346 { \
<> 144:ef7eb2e8f9f7 347 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 348 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 349 break; \
<> 144:ef7eb2e8f9f7 350 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 351 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 352 break; \
<> 144:ef7eb2e8f9f7 353 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 354 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 355 break; \
<> 144:ef7eb2e8f9f7 356 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 357 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 358 break; \
<> 144:ef7eb2e8f9f7 359 default: \
<> 144:ef7eb2e8f9f7 360 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 361 break; \
<> 144:ef7eb2e8f9f7 362 } \
<> 144:ef7eb2e8f9f7 363 } \
<> 144:ef7eb2e8f9f7 364 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 365 { \
<> 144:ef7eb2e8f9f7 366 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 367 } \
<> 144:ef7eb2e8f9f7 368 else \
<> 144:ef7eb2e8f9f7 369 { \
<> 144:ef7eb2e8f9f7 370 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 371 } \
<> 144:ef7eb2e8f9f7 372 } while(0)
<> 144:ef7eb2e8f9f7 373 #elif defined(STM32F070xB)
<> 144:ef7eb2e8f9f7 374 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 375 do { \
<> 144:ef7eb2e8f9f7 376 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 377 { \
<> 144:ef7eb2e8f9f7 378 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 379 { \
<> 144:ef7eb2e8f9f7 380 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 381 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 382 break; \
<> 144:ef7eb2e8f9f7 383 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 384 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 385 break; \
<> 144:ef7eb2e8f9f7 386 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 387 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 388 break; \
<> 144:ef7eb2e8f9f7 389 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 390 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 391 break; \
<> 144:ef7eb2e8f9f7 392 default: \
<> 144:ef7eb2e8f9f7 393 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 394 break; \
<> 144:ef7eb2e8f9f7 395 } \
<> 144:ef7eb2e8f9f7 396 } \
<> 144:ef7eb2e8f9f7 397 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 398 { \
<> 144:ef7eb2e8f9f7 399 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 400 } \
<> 144:ef7eb2e8f9f7 401 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 402 { \
<> 144:ef7eb2e8f9f7 403 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 404 } \
<> 144:ef7eb2e8f9f7 405 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 406 { \
<> 144:ef7eb2e8f9f7 407 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 408 } \
<> 144:ef7eb2e8f9f7 409 else \
<> 144:ef7eb2e8f9f7 410 { \
<> 144:ef7eb2e8f9f7 411 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 412 } \
<> 144:ef7eb2e8f9f7 413 } while(0)
<> 144:ef7eb2e8f9f7 414 #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
<> 144:ef7eb2e8f9f7 415 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 416 do { \
<> 144:ef7eb2e8f9f7 417 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 418 { \
<> 144:ef7eb2e8f9f7 419 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 420 { \
<> 144:ef7eb2e8f9f7 421 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 422 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 423 break; \
<> 144:ef7eb2e8f9f7 424 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 425 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 426 break; \
<> 144:ef7eb2e8f9f7 427 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 428 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 429 break; \
<> 144:ef7eb2e8f9f7 430 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 431 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 432 break; \
<> 144:ef7eb2e8f9f7 433 default: \
<> 144:ef7eb2e8f9f7 434 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 435 break; \
<> 144:ef7eb2e8f9f7 436 } \
<> 144:ef7eb2e8f9f7 437 } \
<> 144:ef7eb2e8f9f7 438 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 439 { \
<> 144:ef7eb2e8f9f7 440 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 441 { \
<> 144:ef7eb2e8f9f7 442 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 443 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 444 break; \
<> 144:ef7eb2e8f9f7 445 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 446 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 447 break; \
<> 144:ef7eb2e8f9f7 448 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 449 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 450 break; \
<> 144:ef7eb2e8f9f7 451 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 452 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 453 break; \
<> 144:ef7eb2e8f9f7 454 default: \
<> 144:ef7eb2e8f9f7 455 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 456 break; \
<> 144:ef7eb2e8f9f7 457 } \
<> 144:ef7eb2e8f9f7 458 } \
<> 144:ef7eb2e8f9f7 459 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 460 { \
<> 144:ef7eb2e8f9f7 461 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 462 } \
<> 144:ef7eb2e8f9f7 463 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 464 { \
<> 144:ef7eb2e8f9f7 465 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 466 } \
<> 144:ef7eb2e8f9f7 467 else \
<> 144:ef7eb2e8f9f7 468 { \
<> 144:ef7eb2e8f9f7 469 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 470 } \
<> 144:ef7eb2e8f9f7 471 } while(0)
<> 144:ef7eb2e8f9f7 472 #elif defined(STM32F091xC) || defined (STM32F098xx)
<> 144:ef7eb2e8f9f7 473 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 474 do { \
<> 144:ef7eb2e8f9f7 475 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 476 { \
<> 144:ef7eb2e8f9f7 477 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 478 { \
<> 144:ef7eb2e8f9f7 479 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 480 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 481 break; \
<> 144:ef7eb2e8f9f7 482 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 483 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 484 break; \
<> 144:ef7eb2e8f9f7 485 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 486 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 487 break; \
<> 144:ef7eb2e8f9f7 488 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 489 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 490 break; \
<> 144:ef7eb2e8f9f7 491 default: \
<> 144:ef7eb2e8f9f7 492 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 493 break; \
<> 144:ef7eb2e8f9f7 494 } \
<> 144:ef7eb2e8f9f7 495 } \
<> 144:ef7eb2e8f9f7 496 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 497 { \
<> 144:ef7eb2e8f9f7 498 switch(__HAL_RCC_GET_USART2_SOURCE()) \
<> 144:ef7eb2e8f9f7 499 { \
<> 144:ef7eb2e8f9f7 500 case RCC_USART2CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 501 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 502 break; \
<> 144:ef7eb2e8f9f7 503 case RCC_USART2CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 504 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 505 break; \
<> 144:ef7eb2e8f9f7 506 case RCC_USART2CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 507 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 508 break; \
<> 144:ef7eb2e8f9f7 509 case RCC_USART2CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 510 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 511 break; \
<> 144:ef7eb2e8f9f7 512 default: \
<> 144:ef7eb2e8f9f7 513 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 514 break; \
<> 144:ef7eb2e8f9f7 515 } \
<> 144:ef7eb2e8f9f7 516 } \
<> 144:ef7eb2e8f9f7 517 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 518 { \
<> 144:ef7eb2e8f9f7 519 switch(__HAL_RCC_GET_USART3_SOURCE()) \
<> 144:ef7eb2e8f9f7 520 { \
<> 144:ef7eb2e8f9f7 521 case RCC_USART3CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 522 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 523 break; \
<> 144:ef7eb2e8f9f7 524 case RCC_USART3CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 525 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 526 break; \
<> 144:ef7eb2e8f9f7 527 case RCC_USART3CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 528 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 529 break; \
<> 144:ef7eb2e8f9f7 530 case RCC_USART3CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 531 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 532 break; \
<> 144:ef7eb2e8f9f7 533 default: \
<> 144:ef7eb2e8f9f7 534 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 535 break; \
<> 144:ef7eb2e8f9f7 536 } \
<> 144:ef7eb2e8f9f7 537 } \
<> 144:ef7eb2e8f9f7 538 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 539 { \
<> 144:ef7eb2e8f9f7 540 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 541 } \
<> 144:ef7eb2e8f9f7 542 else if((__HANDLE__)->Instance == USART5) \
<> 144:ef7eb2e8f9f7 543 { \
<> 144:ef7eb2e8f9f7 544 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 545 } \
<> 144:ef7eb2e8f9f7 546 else if((__HANDLE__)->Instance == USART6) \
<> 144:ef7eb2e8f9f7 547 { \
<> 144:ef7eb2e8f9f7 548 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 549 } \
<> 144:ef7eb2e8f9f7 550 else if((__HANDLE__)->Instance == USART7) \
<> 144:ef7eb2e8f9f7 551 { \
<> 144:ef7eb2e8f9f7 552 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 553 } \
<> 144:ef7eb2e8f9f7 554 else if((__HANDLE__)->Instance == USART8) \
<> 144:ef7eb2e8f9f7 555 { \
<> 144:ef7eb2e8f9f7 556 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 557 } \
<> 144:ef7eb2e8f9f7 558 else \
<> 144:ef7eb2e8f9f7 559 { \
<> 144:ef7eb2e8f9f7 560 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 561 } \
<> 144:ef7eb2e8f9f7 562 } while(0)
<> 144:ef7eb2e8f9f7 563 #elif defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 564 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
<> 144:ef7eb2e8f9f7 565 do { \
<> 144:ef7eb2e8f9f7 566 if((__HANDLE__)->Instance == USART1) \
<> 144:ef7eb2e8f9f7 567 { \
<> 144:ef7eb2e8f9f7 568 switch(__HAL_RCC_GET_USART1_SOURCE()) \
<> 144:ef7eb2e8f9f7 569 { \
<> 144:ef7eb2e8f9f7 570 case RCC_USART1CLKSOURCE_PCLK1: \
<> 144:ef7eb2e8f9f7 571 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 572 break; \
<> 144:ef7eb2e8f9f7 573 case RCC_USART1CLKSOURCE_HSI: \
<> 144:ef7eb2e8f9f7 574 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
<> 144:ef7eb2e8f9f7 575 break; \
<> 144:ef7eb2e8f9f7 576 case RCC_USART1CLKSOURCE_SYSCLK: \
<> 144:ef7eb2e8f9f7 577 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
<> 144:ef7eb2e8f9f7 578 break; \
<> 144:ef7eb2e8f9f7 579 case RCC_USART1CLKSOURCE_LSE: \
<> 144:ef7eb2e8f9f7 580 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
<> 144:ef7eb2e8f9f7 581 break; \
<> 144:ef7eb2e8f9f7 582 default: \
<> 144:ef7eb2e8f9f7 583 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 584 break; \
<> 144:ef7eb2e8f9f7 585 } \
<> 144:ef7eb2e8f9f7 586 } \
<> 144:ef7eb2e8f9f7 587 else if((__HANDLE__)->Instance == USART2) \
<> 144:ef7eb2e8f9f7 588 { \
<> 144:ef7eb2e8f9f7 589 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 590 } \
<> 144:ef7eb2e8f9f7 591 else if((__HANDLE__)->Instance == USART3) \
<> 144:ef7eb2e8f9f7 592 { \
<> 144:ef7eb2e8f9f7 593 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 594 } \
<> 144:ef7eb2e8f9f7 595 else if((__HANDLE__)->Instance == USART4) \
<> 144:ef7eb2e8f9f7 596 { \
<> 144:ef7eb2e8f9f7 597 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 598 } \
<> 144:ef7eb2e8f9f7 599 else if((__HANDLE__)->Instance == USART5) \
<> 144:ef7eb2e8f9f7 600 { \
<> 144:ef7eb2e8f9f7 601 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 602 } \
<> 144:ef7eb2e8f9f7 603 else if((__HANDLE__)->Instance == USART6) \
<> 144:ef7eb2e8f9f7 604 { \
<> 144:ef7eb2e8f9f7 605 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
<> 144:ef7eb2e8f9f7 606 } \
<> 144:ef7eb2e8f9f7 607 else \
<> 144:ef7eb2e8f9f7 608 { \
<> 144:ef7eb2e8f9f7 609 (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
<> 144:ef7eb2e8f9f7 610 } \
<> 144:ef7eb2e8f9f7 611 } while(0)
<> 144:ef7eb2e8f9f7 612
<> 144:ef7eb2e8f9f7 613 #endif /* defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) */
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /** @brief Compute the UART mask to apply to retrieve the received data
<> 144:ef7eb2e8f9f7 617 * according to the word length and to the parity bits activation.
<> 144:ef7eb2e8f9f7 618 * @note If PCE = 1, the parity bit is not included in the data extracted
<> 144:ef7eb2e8f9f7 619 * by the reception API().
<> 144:ef7eb2e8f9f7 620 * This masking operation is not carried out in the case of
<> 144:ef7eb2e8f9f7 621 * DMA transfers.
<> 144:ef7eb2e8f9f7 622 * @param __HANDLE__: specifies the UART Handle.
<> 144:ef7eb2e8f9f7 623 * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
<> 144:ef7eb2e8f9f7 624 */
<> 144:ef7eb2e8f9f7 625 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 626 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 627 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 628 #define UART_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 629 do { \
<> 144:ef7eb2e8f9f7 630 if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 631 { \
<> 144:ef7eb2e8f9f7 632 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 633 { \
<> 156:95d6b41a828b 634 (__HANDLE__)->Mask = 0x01FFU; \
<> 144:ef7eb2e8f9f7 635 } \
<> 144:ef7eb2e8f9f7 636 else \
<> 144:ef7eb2e8f9f7 637 { \
<> 156:95d6b41a828b 638 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 639 } \
<> 144:ef7eb2e8f9f7 640 } \
<> 144:ef7eb2e8f9f7 641 else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 642 { \
<> 144:ef7eb2e8f9f7 643 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 644 { \
<> 156:95d6b41a828b 645 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 646 } \
<> 144:ef7eb2e8f9f7 647 else \
<> 144:ef7eb2e8f9f7 648 { \
<> 156:95d6b41a828b 649 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 650 } \
<> 144:ef7eb2e8f9f7 651 } \
<> 144:ef7eb2e8f9f7 652 else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
<> 144:ef7eb2e8f9f7 653 { \
<> 144:ef7eb2e8f9f7 654 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 655 { \
<> 156:95d6b41a828b 656 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 657 } \
<> 144:ef7eb2e8f9f7 658 else \
<> 144:ef7eb2e8f9f7 659 { \
<> 156:95d6b41a828b 660 (__HANDLE__)->Mask = 0x003FU; \
<> 144:ef7eb2e8f9f7 661 } \
<> 144:ef7eb2e8f9f7 662 } \
<> 144:ef7eb2e8f9f7 663 } while(0)
<> 144:ef7eb2e8f9f7 664 #else
<> 144:ef7eb2e8f9f7 665 #define UART_MASK_COMPUTATION(__HANDLE__) \
<> 144:ef7eb2e8f9f7 666 do { \
<> 144:ef7eb2e8f9f7 667 if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
<> 144:ef7eb2e8f9f7 668 { \
<> 144:ef7eb2e8f9f7 669 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 670 { \
<> 156:95d6b41a828b 671 (__HANDLE__)->Mask = 0x01FFU; \
<> 144:ef7eb2e8f9f7 672 } \
<> 144:ef7eb2e8f9f7 673 else \
<> 144:ef7eb2e8f9f7 674 { \
<> 156:95d6b41a828b 675 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 676 } \
<> 144:ef7eb2e8f9f7 677 } \
<> 144:ef7eb2e8f9f7 678 else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
<> 144:ef7eb2e8f9f7 679 { \
<> 144:ef7eb2e8f9f7 680 if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
<> 144:ef7eb2e8f9f7 681 { \
<> 156:95d6b41a828b 682 (__HANDLE__)->Mask = 0x00FFU; \
<> 144:ef7eb2e8f9f7 683 } \
<> 144:ef7eb2e8f9f7 684 else \
<> 144:ef7eb2e8f9f7 685 { \
<> 156:95d6b41a828b 686 (__HANDLE__)->Mask = 0x007FU; \
<> 144:ef7eb2e8f9f7 687 } \
<> 144:ef7eb2e8f9f7 688 } \
<> 144:ef7eb2e8f9f7 689 } while(0)
<> 144:ef7eb2e8f9f7 690 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 691 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 692 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /**
<> 144:ef7eb2e8f9f7 695 * @brief Ensure that UART frame length is valid.
<> 144:ef7eb2e8f9f7 696 * @param __LENGTH__: UART frame length.
<> 144:ef7eb2e8f9f7 697 * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 700 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 701 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 702 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
<> 144:ef7eb2e8f9f7 703 ((__LENGTH__) == UART_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 704 ((__LENGTH__) == UART_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 705 #else
<> 144:ef7eb2e8f9f7 706 #define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_8B) || \
<> 144:ef7eb2e8f9f7 707 ((__LENGTH__) == UART_WORDLENGTH_9B))
<> 144:ef7eb2e8f9f7 708 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 709 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 710 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 711
<> 144:ef7eb2e8f9f7 712 /**
<> 144:ef7eb2e8f9f7 713 * @brief Ensure that UART auto Baud rate detection mode is valid.
<> 144:ef7eb2e8f9f7 714 * @param __MODE__: UART auto Baud rate detection mode.
<> 144:ef7eb2e8f9f7 715 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<> 144:ef7eb2e8f9f7 716 */
<> 144:ef7eb2e8f9f7 717 #if defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 718 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 719 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC)
<> 144:ef7eb2e8f9f7 720 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
<> 144:ef7eb2e8f9f7 721 ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
<> 144:ef7eb2e8f9f7 722 ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \
<> 144:ef7eb2e8f9f7 723 ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
<> 144:ef7eb2e8f9f7 724 #else
<> 144:ef7eb2e8f9f7 725 #define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \
<> 144:ef7eb2e8f9f7 726 ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE))
<> 144:ef7eb2e8f9f7 727 #endif /* defined (STM32F042x6) || defined (STM32F048xx) || defined (STM32F070x6) || \
<> 144:ef7eb2e8f9f7 728 defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || defined (STM32F070xB) || \
<> 144:ef7eb2e8f9f7 729 defined (STM32F091xC) || defined (STM32F098xx) || defined (STM32F030xC) */
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 733 /**
<> 144:ef7eb2e8f9f7 734 * @brief Ensure that UART LIN state is valid.
<> 144:ef7eb2e8f9f7 735 * @param __LIN__: UART LIN state.
<> 144:ef7eb2e8f9f7 736 * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
<> 144:ef7eb2e8f9f7 737 */
<> 144:ef7eb2e8f9f7 738 #define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \
<> 144:ef7eb2e8f9f7 739 ((__LIN__) == UART_LIN_ENABLE))
<> 144:ef7eb2e8f9f7 740
<> 144:ef7eb2e8f9f7 741 /**
<> 144:ef7eb2e8f9f7 742 * @brief Ensure that UART LIN break detection length is valid.
<> 144:ef7eb2e8f9f7 743 * @param __LENGTH__: UART LIN break detection length.
<> 144:ef7eb2e8f9f7 744 * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
<> 144:ef7eb2e8f9f7 745 */
<> 144:ef7eb2e8f9f7 746 #define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
<> 144:ef7eb2e8f9f7 747 ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
<> 144:ef7eb2e8f9f7 748 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750 /**
<> 144:ef7eb2e8f9f7 751 * @brief Ensure that UART request parameter is valid.
<> 144:ef7eb2e8f9f7 752 * @param __PARAM__: UART request parameter.
<> 144:ef7eb2e8f9f7 753 * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
<> 144:ef7eb2e8f9f7 754 */
<> 144:ef7eb2e8f9f7 755 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 756 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
<> 144:ef7eb2e8f9f7 757 ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
<> 144:ef7eb2e8f9f7 758 ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
<> 144:ef7eb2e8f9f7 759 ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
<> 144:ef7eb2e8f9f7 760 ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
<> 144:ef7eb2e8f9f7 761 #else
<> 144:ef7eb2e8f9f7 762 #define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \
<> 144:ef7eb2e8f9f7 763 ((__PARAM__) == UART_SENDBREAK_REQUEST) || \
<> 144:ef7eb2e8f9f7 764 ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \
<> 144:ef7eb2e8f9f7 765 ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST))
<> 144:ef7eb2e8f9f7 766 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 #if !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 769 /**
<> 144:ef7eb2e8f9f7 770 * @brief Ensure that UART stop mode state is valid.
<> 144:ef7eb2e8f9f7 771 * @param __STOPMODE__: UART stop mode state.
<> 144:ef7eb2e8f9f7 772 * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 #define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
<> 144:ef7eb2e8f9f7 775 ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
<> 156:95d6b41a828b 776
<> 144:ef7eb2e8f9f7 777 /**
<> 144:ef7eb2e8f9f7 778 * @brief Ensure that UART wake-up selection is valid.
<> 144:ef7eb2e8f9f7 779 * @param __WAKE__: UART wake-up selection.
<> 144:ef7eb2e8f9f7 780 * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
<> 144:ef7eb2e8f9f7 781 */
<> 144:ef7eb2e8f9f7 782 #define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \
<> 144:ef7eb2e8f9f7 783 ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \
<> 144:ef7eb2e8f9f7 784 ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
<> 144:ef7eb2e8f9f7 785 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8) && !defined(STM32F070x6) && !defined(STM32F070xB) && !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 786
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @}
<> 144:ef7eb2e8f9f7 789 */
<> 144:ef7eb2e8f9f7 790
<> 144:ef7eb2e8f9f7 791 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 792 /** @addtogroup UARTEx_Exported_Functions
<> 144:ef7eb2e8f9f7 793 * @{
<> 144:ef7eb2e8f9f7 794 */
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /** @addtogroup UARTEx_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 797 * @brief Extended Initialization and Configuration Functions
<> 144:ef7eb2e8f9f7 798 * @{
<> 144:ef7eb2e8f9f7 799 */
<> 144:ef7eb2e8f9f7 800 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 801 HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
<> 144:ef7eb2e8f9f7 802 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 803 HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
<> 144:ef7eb2e8f9f7 804 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 805 /**
<> 144:ef7eb2e8f9f7 806 * @}
<> 144:ef7eb2e8f9f7 807 */
<> 144:ef7eb2e8f9f7 808
<> 144:ef7eb2e8f9f7 809 /** @addtogroup UARTEx_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 810 * @brief Extended UART Interrupt handling function
<> 144:ef7eb2e8f9f7 811 * @{
<> 144:ef7eb2e8f9f7 812 */
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 /* IO operation functions ***************************************************/
<> 144:ef7eb2e8f9f7 815 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 816 void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 817 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 818 /**
<> 144:ef7eb2e8f9f7 819 * @}
<> 144:ef7eb2e8f9f7 820 */
<> 144:ef7eb2e8f9f7 821
<> 144:ef7eb2e8f9f7 822 /** @addtogroup UARTEx_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 823 * @brief Extended Peripheral Control functions
<> 144:ef7eb2e8f9f7 824 * @{
<> 144:ef7eb2e8f9f7 825 */
<> 144:ef7eb2e8f9f7 826
<> 144:ef7eb2e8f9f7 827 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 828 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
<> 144:ef7eb2e8f9f7 829 #if !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6) && !defined(STM32F030xC)
<> 144:ef7eb2e8f9f7 830 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
<> 144:ef7eb2e8f9f7 831 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 832 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 833 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
<> 144:ef7eb2e8f9f7 834 #endif /* !defined(STM32F030x6) && !defined(STM32F030x8)&& !defined(STM32F070xB)&& !defined(STM32F070x6)&& !defined(STM32F030xC) */
<> 144:ef7eb2e8f9f7 835 /**
<> 144:ef7eb2e8f9f7 836 * @}
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 839
<> 144:ef7eb2e8f9f7 840 /**
<> 144:ef7eb2e8f9f7 841 * @}
<> 144:ef7eb2e8f9f7 842 */
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 /* Private functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /**
<> 144:ef7eb2e8f9f7 847 * @}
<> 144:ef7eb2e8f9f7 848 */
<> 144:ef7eb2e8f9f7 849
<> 144:ef7eb2e8f9f7 850 /**
<> 144:ef7eb2e8f9f7 851 * @}
<> 144:ef7eb2e8f9f7 852 */
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 855 }
<> 144:ef7eb2e8f9f7 856 #endif
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 #endif /* __STM32F0xx_HAL_UART_EX_H */
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
<> 144:ef7eb2e8f9f7 861