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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Child:
184:08ed48f1de7f
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_dma.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @version V1.2.0
<> 149:156823d33999 6 * @date 01-July-2016
<> 149:156823d33999 7 * @brief DMA HAL module driver.
<> 149:156823d33999 8 * This file provides firmware functions to manage the following
<> 149:156823d33999 9 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 149:156823d33999 10 * + Initialization and de-initialization functions
<> 149:156823d33999 11 * + IO operation functions
<> 149:156823d33999 12 * + Peripheral State and errors functions
<> 149:156823d33999 13 @verbatim
<> 149:156823d33999 14 ==============================================================================
<> 149:156823d33999 15 ##### How to use this driver #####
<> 149:156823d33999 16 ==============================================================================
<> 149:156823d33999 17 [..]
<> 149:156823d33999 18 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 149:156823d33999 19 (except for internal SRAM / FLASH memories: no initialization is
<> 149:156823d33999 20 necessary). Please refer to the Reference manual for connection between peripherals
<> 149:156823d33999 21 and DMA requests.
<> 149:156823d33999 22
<> 149:156823d33999 23 (#) For a given Channel, program the required configuration through the following parameters:
<> 149:156823d33999 24 Channel request, Transfer Direction, Source and Destination data formats,
<> 149:156823d33999 25 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
<> 149:156823d33999 26 using HAL_DMA_Init() function.
<> 149:156823d33999 27
<> 149:156823d33999 28 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 149:156823d33999 29 detection.
<> 149:156823d33999 30
<> 149:156823d33999 31 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 149:156823d33999 32
<> 149:156823d33999 33 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 149:156823d33999 34 *** Polling mode IO operation ***
<> 149:156823d33999 35 =================================
<> 149:156823d33999 36 [..]
<> 149:156823d33999 37 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 149:156823d33999 38 address and destination address and the Length of data to be transferred
<> 149:156823d33999 39 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 149:156823d33999 40 case a fixed Timeout can be configured by User depending from his application.
<> 149:156823d33999 41
<> 149:156823d33999 42 *** Interrupt mode IO operation ***
<> 149:156823d33999 43 ===================================
<> 149:156823d33999 44 [..]
<> 149:156823d33999 45 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 149:156823d33999 46 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 149:156823d33999 47 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 149:156823d33999 48 Source address and destination address and the Length of data to be transferred.
<> 149:156823d33999 49 In this case the DMA interrupt is configured
<> 149:156823d33999 50 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 149:156823d33999 51 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 149:156823d33999 52 add his own function by customization of function pointer XferCpltCallback and
<> 149:156823d33999 53 XferErrorCallback (i.e. a member of DMA handle structure).
<> 149:156823d33999 54
<> 149:156823d33999 55 *** DMA HAL driver macros list ***
<> 149:156823d33999 56 =============================================
<> 149:156823d33999 57 [..]
<> 149:156823d33999 58 Below the list of most used macros in DMA HAL driver.
<> 149:156823d33999 59
<> 149:156823d33999 60 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 149:156823d33999 61 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 149:156823d33999 62 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 149:156823d33999 63 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 149:156823d33999 64 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 149:156823d33999 65 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
<> 149:156823d33999 66 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
<> 149:156823d33999 67
<> 149:156823d33999 68 [..]
<> 149:156823d33999 69 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 149:156823d33999 70
<> 149:156823d33999 71 @endverbatim
<> 149:156823d33999 72 ******************************************************************************
<> 149:156823d33999 73 * @attention
<> 149:156823d33999 74 *
<> 149:156823d33999 75 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 149:156823d33999 76 *
<> 149:156823d33999 77 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 78 * are permitted provided that the following conditions are met:
<> 149:156823d33999 79 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 80 * this list of conditions and the following disclaimer.
<> 149:156823d33999 81 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 82 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 83 * and/or other materials provided with the distribution.
<> 149:156823d33999 84 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 85 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 86 * without specific prior written permission.
<> 149:156823d33999 87 *
<> 149:156823d33999 88 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 89 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 90 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 91 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 92 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 93 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 94 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 95 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 96 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 97 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 98 *
<> 149:156823d33999 99 ******************************************************************************
<> 149:156823d33999 100 */
<> 149:156823d33999 101
<> 149:156823d33999 102 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 103 #include "stm32l1xx_hal.h"
<> 149:156823d33999 104
<> 149:156823d33999 105 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 106 * @{
<> 149:156823d33999 107 */
<> 149:156823d33999 108
<> 149:156823d33999 109 /** @defgroup DMA DMA
<> 149:156823d33999 110 * @brief DMA HAL module driver
<> 149:156823d33999 111 * @{
<> 149:156823d33999 112 */
<> 149:156823d33999 113
<> 149:156823d33999 114 #ifdef HAL_DMA_MODULE_ENABLED
<> 149:156823d33999 115
<> 149:156823d33999 116 /* Private typedef -----------------------------------------------------------*/
<> 149:156823d33999 117 /* Private define ------------------------------------------------------------*/
<> 149:156823d33999 118 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 119 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 120 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 121 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 149:156823d33999 122 * @{
<> 149:156823d33999 123 */
<> 149:156823d33999 124 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 149:156823d33999 125
<> 149:156823d33999 126 /**
<> 149:156823d33999 127 * @}
<> 149:156823d33999 128 */
<> 149:156823d33999 129
<> 149:156823d33999 130 /* Exported functions ---------------------------------------------------------*/
<> 149:156823d33999 131
<> 149:156823d33999 132 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 149:156823d33999 133 * @{
<> 149:156823d33999 134 */
<> 149:156823d33999 135
<> 149:156823d33999 136 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 149:156823d33999 137 * @brief Initialization and de-initialization functions
<> 149:156823d33999 138 *
<> 149:156823d33999 139 @verbatim
<> 149:156823d33999 140 ===============================================================================
<> 149:156823d33999 141 ##### Initialization and de-initialization functions #####
<> 149:156823d33999 142 ===============================================================================
<> 149:156823d33999 143 [..]
<> 149:156823d33999 144 This section provides functions allowing to initialize the DMA Channel source
<> 149:156823d33999 145 and destination addresses, incrementation and data sizes, transfer direction,
<> 149:156823d33999 146 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 149:156823d33999 147 [..]
<> 149:156823d33999 148 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 149:156823d33999 149 reference manual.
<> 149:156823d33999 150
<> 149:156823d33999 151 @endverbatim
<> 149:156823d33999 152 * @{
<> 149:156823d33999 153 */
<> 149:156823d33999 154
<> 149:156823d33999 155 /**
<> 149:156823d33999 156 * @brief Initialize the DMA according to the specified
<> 149:156823d33999 157 * parameters in the DMA_InitTypeDef and initialize the associated handle.
<> 149:156823d33999 158 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 159 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 160 * @retval HAL status
<> 149:156823d33999 161 */
<> 149:156823d33999 162 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 163 {
<> 149:156823d33999 164 uint32_t tmp = 0;
<> 149:156823d33999 165
<> 149:156823d33999 166 /* Check the DMA handle allocation */
<> 149:156823d33999 167 if(hdma == NULL)
<> 149:156823d33999 168 {
<> 149:156823d33999 169 return HAL_ERROR;
<> 149:156823d33999 170 }
<> 149:156823d33999 171
<> 149:156823d33999 172 /* Check the parameters */
<> 149:156823d33999 173 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 149:156823d33999 174 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 149:156823d33999 175 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 149:156823d33999 176 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 149:156823d33999 177 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 149:156823d33999 178 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 149:156823d33999 179 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 149:156823d33999 180 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 149:156823d33999 181
<> 149:156823d33999 182 #if defined (DMA2)
<> 149:156823d33999 183 /* calculation of the channel index */
<> 149:156823d33999 184 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 149:156823d33999 185 {
<> 149:156823d33999 186 /* DMA1 */
<> 149:156823d33999 187 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 188 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 189 }
<> 149:156823d33999 190 else
<> 149:156823d33999 191 {
<> 149:156823d33999 192 /* DMA2 */
<> 149:156823d33999 193 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 149:156823d33999 194 hdma->DmaBaseAddress = DMA2;
<> 149:156823d33999 195 }
<> 149:156823d33999 196 #else
<> 149:156823d33999 197 /* calculation of the channel index */
<> 149:156823d33999 198 /* DMA1 */
<> 149:156823d33999 199 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 200 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 201 #endif
<> 149:156823d33999 202
<> 149:156823d33999 203 /* Change DMA peripheral state */
<> 149:156823d33999 204 hdma->State = HAL_DMA_STATE_BUSY;
<> 149:156823d33999 205
<> 149:156823d33999 206 /* Get the CR register value */
<> 149:156823d33999 207 tmp = hdma->Instance->CCR;
<> 149:156823d33999 208
<> 149:156823d33999 209 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 149:156823d33999 210 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 149:156823d33999 211 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 149:156823d33999 212 DMA_CCR_DIR));
<> 149:156823d33999 213
<> 149:156823d33999 214 /* Prepare the DMA Channel configuration */
<> 149:156823d33999 215 tmp |= hdma->Init.Direction |
<> 149:156823d33999 216 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 149:156823d33999 217 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 149:156823d33999 218 hdma->Init.Mode | hdma->Init.Priority;
<> 149:156823d33999 219
<> 149:156823d33999 220 /* Write to DMA Channel CR register */
<> 149:156823d33999 221 hdma->Instance->CCR = tmp;
<> 149:156823d33999 222
<> 149:156823d33999 223 /* Clean callbacks */
<> 149:156823d33999 224 hdma->XferCpltCallback = NULL;
<> 149:156823d33999 225 hdma->XferHalfCpltCallback = NULL;
<> 149:156823d33999 226 hdma->XferErrorCallback = NULL;
<> 149:156823d33999 227 hdma->XferAbortCallback = NULL;
<> 149:156823d33999 228
<> 149:156823d33999 229 /* Initialise the error code */
<> 149:156823d33999 230 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 231
<> 149:156823d33999 232 /* Initialize the DMA state*/
<> 149:156823d33999 233 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 234
<> 149:156823d33999 235 /* Allocate lock resource and initialize it */
<> 149:156823d33999 236 hdma->Lock = HAL_UNLOCKED;
<> 149:156823d33999 237
<> 149:156823d33999 238 return HAL_OK;
<> 149:156823d33999 239 }
<> 149:156823d33999 240
<> 149:156823d33999 241 /**
<> 149:156823d33999 242 * @brief DeInitialize the DMA peripheral.
<> 149:156823d33999 243 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 244 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 245 * @retval HAL status
<> 149:156823d33999 246 */
<> 149:156823d33999 247 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 248 {
<> 149:156823d33999 249 /* Check the DMA handle allocation */
<> 149:156823d33999 250 if (NULL == hdma )
<> 149:156823d33999 251 {
<> 149:156823d33999 252 return HAL_ERROR;
<> 149:156823d33999 253 }
<> 149:156823d33999 254
<> 149:156823d33999 255 /* Check the parameters */
<> 149:156823d33999 256 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 149:156823d33999 257
<> 149:156823d33999 258 /* Disable the selected DMA Channelx */
<> 149:156823d33999 259 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 260
<> 149:156823d33999 261 #if defined (DMA2)
<> 149:156823d33999 262 /* calculation of the channel index */
<> 149:156823d33999 263 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 149:156823d33999 264 {
<> 149:156823d33999 265 /* DMA1 */
<> 149:156823d33999 266 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 267 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 268 }
<> 149:156823d33999 269 else
<> 149:156823d33999 270 {
<> 149:156823d33999 271 /* DMA2 */
<> 149:156823d33999 272 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 149:156823d33999 273 hdma->DmaBaseAddress = DMA2;
<> 149:156823d33999 274 }
<> 149:156823d33999 275 #else
<> 149:156823d33999 276 /* calculation of the channel index */
<> 149:156823d33999 277 /* DMA1 */
<> 149:156823d33999 278 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 279 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 280 #endif
<> 149:156823d33999 281
<> 149:156823d33999 282 /* Reset DMA Channel control register */
<> 149:156823d33999 283 hdma->Instance->CCR = 0;
<> 149:156823d33999 284
<> 149:156823d33999 285 /* Reset DMA Channel Number of Data to Transfer register */
<> 149:156823d33999 286 hdma->Instance->CNDTR = 0;
<> 149:156823d33999 287
<> 149:156823d33999 288 /* Reset DMA Channel peripheral address register */
<> 149:156823d33999 289 hdma->Instance->CPAR = 0;
<> 149:156823d33999 290
<> 149:156823d33999 291 /* Reset DMA Channel memory address register */
<> 149:156823d33999 292 hdma->Instance->CMAR = 0;
<> 149:156823d33999 293
<> 149:156823d33999 294 /* Clear all flags */
<> 149:156823d33999 295 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 296
<> 149:156823d33999 297 /* Initialise the error code */
<> 149:156823d33999 298 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 299
<> 149:156823d33999 300 /* Initialize the DMA state */
<> 149:156823d33999 301 hdma->State = HAL_DMA_STATE_RESET;
<> 149:156823d33999 302
<> 149:156823d33999 303 /* Release Lock */
<> 149:156823d33999 304 __HAL_UNLOCK(hdma);
<> 149:156823d33999 305
<> 149:156823d33999 306 return HAL_OK;
<> 149:156823d33999 307 }
<> 149:156823d33999 308
<> 149:156823d33999 309 /**
<> 149:156823d33999 310 * @}
<> 149:156823d33999 311 */
<> 149:156823d33999 312
<> 149:156823d33999 313 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 149:156823d33999 314 * @brief Input and Output operation functions
<> 149:156823d33999 315 *
<> 149:156823d33999 316 @verbatim
<> 149:156823d33999 317 ===============================================================================
<> 149:156823d33999 318 ##### IO operation functions #####
<> 149:156823d33999 319 ===============================================================================
<> 149:156823d33999 320 [..] This section provides functions allowing to:
<> 149:156823d33999 321 (+) Configure the source, destination address and data length and Start DMA transfer
<> 149:156823d33999 322 (+) Configure the source, destination address and data length and
<> 149:156823d33999 323 Start DMA transfer with interrupt
<> 149:156823d33999 324 (+) Abort DMA transfer
<> 149:156823d33999 325 (+) Poll for transfer complete
<> 149:156823d33999 326 (+) Handle DMA interrupt request
<> 149:156823d33999 327
<> 149:156823d33999 328 @endverbatim
<> 149:156823d33999 329 * @{
<> 149:156823d33999 330 */
<> 149:156823d33999 331
<> 149:156823d33999 332 /**
<> 149:156823d33999 333 * @brief Start the DMA Transfer.
<> 149:156823d33999 334 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 335 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 336 * @param SrcAddress: The source memory Buffer address
<> 149:156823d33999 337 * @param DstAddress: The destination memory Buffer address
<> 149:156823d33999 338 * @param DataLength: The length of data to be transferred from source to destination
<> 149:156823d33999 339 * @retval HAL status
<> 149:156823d33999 340 */
<> 149:156823d33999 341 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 149:156823d33999 342 {
<> 149:156823d33999 343 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 344
<> 149:156823d33999 345 /* Check the parameters */
<> 149:156823d33999 346 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 149:156823d33999 347
<> 149:156823d33999 348 /* Process locked */
<> 149:156823d33999 349 __HAL_LOCK(hdma);
<> 149:156823d33999 350
<> 149:156823d33999 351 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 352 {
<> 149:156823d33999 353 /* Change DMA peripheral state */
<> 149:156823d33999 354 hdma->State = HAL_DMA_STATE_BUSY;
<> 149:156823d33999 355 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 356
<> 149:156823d33999 357 /* Disable the peripheral */
<> 149:156823d33999 358 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 359
<> 149:156823d33999 360 /* Configure the source, destination address and the data length & clear flags*/
<> 149:156823d33999 361 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 149:156823d33999 362
<> 149:156823d33999 363 /* Enable the Peripheral */
<> 149:156823d33999 364 __HAL_DMA_ENABLE(hdma);
<> 149:156823d33999 365 }
<> 149:156823d33999 366 else
<> 149:156823d33999 367 {
<> 149:156823d33999 368 /* Process Unlocked */
<> 149:156823d33999 369 __HAL_UNLOCK(hdma);
<> 149:156823d33999 370 status = HAL_BUSY;
<> 149:156823d33999 371 }
<> 149:156823d33999 372 return status;
<> 149:156823d33999 373 }
<> 149:156823d33999 374
<> 149:156823d33999 375 /**
<> 149:156823d33999 376 * @brief Start the DMA Transfer with interrupt enabled.
<> 149:156823d33999 377 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 378 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 379 * @param SrcAddress: The source memory Buffer address
<> 149:156823d33999 380 * @param DstAddress: The destination memory Buffer address
<> 149:156823d33999 381 * @param DataLength: The length of data to be transferred from source to destination
<> 149:156823d33999 382 * @retval HAL status
<> 149:156823d33999 383 */
<> 149:156823d33999 384 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 149:156823d33999 385 {
<> 149:156823d33999 386 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 387
<> 149:156823d33999 388 /* Check the parameters */
<> 149:156823d33999 389 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 149:156823d33999 390
<> 149:156823d33999 391 /* Process locked */
<> 149:156823d33999 392 __HAL_LOCK(hdma);
<> 149:156823d33999 393
<> 149:156823d33999 394 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 395 {
<> 149:156823d33999 396 /* Change DMA peripheral state */
<> 149:156823d33999 397 hdma->State = HAL_DMA_STATE_BUSY;
<> 149:156823d33999 398 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 399
<> 149:156823d33999 400 /* Disable the peripheral */
<> 149:156823d33999 401 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 402
<> 149:156823d33999 403 /* Configure the source, destination address and the data length & clear flags*/
<> 149:156823d33999 404 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 149:156823d33999 405
<> 149:156823d33999 406 /* Enable the transfer complete interrupt */
<> 149:156823d33999 407 /* Enable the transfer Error interrupt */
<> 149:156823d33999 408 if(NULL != hdma->XferHalfCpltCallback )
<> 149:156823d33999 409 {
<> 149:156823d33999 410 /* Enable the Half transfer complete interrupt as well */
<> 149:156823d33999 411 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 412 }
<> 149:156823d33999 413 else
<> 149:156823d33999 414 {
<> 149:156823d33999 415 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 149:156823d33999 416 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
<> 149:156823d33999 417 }
<> 149:156823d33999 418 /* Enable the Peripheral */
<> 149:156823d33999 419 __HAL_DMA_ENABLE(hdma);
<> 149:156823d33999 420 }
<> 149:156823d33999 421 else
<> 149:156823d33999 422 {
<> 149:156823d33999 423 /* Process Unlocked */
<> 149:156823d33999 424 __HAL_UNLOCK(hdma);
<> 149:156823d33999 425
<> 149:156823d33999 426 /* Remain BUSY */
<> 149:156823d33999 427 status = HAL_BUSY;
<> 149:156823d33999 428 }
<> 149:156823d33999 429 return status;
<> 149:156823d33999 430 }
<> 149:156823d33999 431
<> 149:156823d33999 432 /**
<> 149:156823d33999 433 * @brief Abort the DMA Transfer.
<> 149:156823d33999 434 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 435 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 436 * @retval HAL status
<> 149:156823d33999 437 */
<> 149:156823d33999 438 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 439 {
<> 149:156823d33999 440 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 441
<> 149:156823d33999 442 /* Disable DMA IT */
<> 149:156823d33999 443 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 444
<> 149:156823d33999 445 /* Disable the channel */
<> 149:156823d33999 446 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 447
<> 149:156823d33999 448 /* Clear all flags */
<> 149:156823d33999 449 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 450
<> 149:156823d33999 451 /* Change the DMA state */
<> 149:156823d33999 452 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 453
<> 149:156823d33999 454 /* Process Unlocked */
<> 149:156823d33999 455 __HAL_UNLOCK(hdma);
<> 149:156823d33999 456
<> 149:156823d33999 457 return status;
<> 149:156823d33999 458 }
<> 149:156823d33999 459
<> 149:156823d33999 460 /**
<> 149:156823d33999 461 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 149:156823d33999 462 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 463 * the configuration information for the specified DMA Stream.
<> 149:156823d33999 464 * @retval HAL status
<> 149:156823d33999 465 */
<> 149:156823d33999 466 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 467 {
<> 149:156823d33999 468 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 469
<> 149:156823d33999 470 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 149:156823d33999 471 {
<> 149:156823d33999 472 /* no transfer ongoing */
<> 149:156823d33999 473 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 149:156823d33999 474
<> 149:156823d33999 475 status = HAL_ERROR;
<> 149:156823d33999 476 }
<> 149:156823d33999 477 else
<> 149:156823d33999 478 {
<> 149:156823d33999 479 /* Disable DMA IT */
<> 149:156823d33999 480 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 481
<> 149:156823d33999 482 /* Disable the channel */
<> 149:156823d33999 483 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 484
<> 149:156823d33999 485 /* Clear all flags */
<> 149:156823d33999 486 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 487
<> 149:156823d33999 488 /* Change the DMA state */
<> 149:156823d33999 489 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 490
<> 149:156823d33999 491 /* Process Unlocked */
<> 149:156823d33999 492 __HAL_UNLOCK(hdma);
<> 149:156823d33999 493
<> 149:156823d33999 494 /* Call User Abort callback */
<> 149:156823d33999 495 if(hdma->XferAbortCallback != NULL)
<> 149:156823d33999 496 {
<> 149:156823d33999 497 hdma->XferAbortCallback(hdma);
<> 149:156823d33999 498 }
<> 149:156823d33999 499 }
<> 149:156823d33999 500 return status;
<> 149:156823d33999 501 }
<> 149:156823d33999 502
<> 149:156823d33999 503 /**
<> 149:156823d33999 504 * @brief Polling for transfer complete.
<> 149:156823d33999 505 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 506 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 507 * @param CompleteLevel: Specifies the DMA level complete.
<> 149:156823d33999 508 * @param Timeout: Timeout duration.
<> 149:156823d33999 509 * @retval HAL status
<> 149:156823d33999 510 */
<> 149:156823d33999 511 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 149:156823d33999 512 {
<> 149:156823d33999 513 uint32_t temp;
<> 149:156823d33999 514 uint32_t tickstart = 0;
<> 149:156823d33999 515
<> 149:156823d33999 516 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 149:156823d33999 517 {
<> 149:156823d33999 518 /* no transfer ongoing */
<> 149:156823d33999 519 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 149:156823d33999 520 __HAL_UNLOCK(hdma);
<> 149:156823d33999 521 return HAL_ERROR;
<> 149:156823d33999 522 }
<> 149:156823d33999 523
<> 149:156823d33999 524 /* Polling mode not supported in circular mode */
<> 149:156823d33999 525 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
<> 149:156823d33999 526 {
<> 149:156823d33999 527 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 149:156823d33999 528 return HAL_ERROR;
<> 149:156823d33999 529 }
<> 149:156823d33999 530
<> 149:156823d33999 531 /* Get the level transfer complete flag */
<> 149:156823d33999 532 if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 149:156823d33999 533 {
<> 149:156823d33999 534 /* Transfer Complete flag */
<> 149:156823d33999 535 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 149:156823d33999 536 }
<> 149:156823d33999 537 else
<> 149:156823d33999 538 {
<> 149:156823d33999 539 /* Half Transfer Complete flag */
<> 149:156823d33999 540 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 149:156823d33999 541 }
<> 149:156823d33999 542
<> 149:156823d33999 543 /* Get tick */
<> 149:156823d33999 544 tickstart = HAL_GetTick();
<> 149:156823d33999 545
<> 149:156823d33999 546 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
<> 149:156823d33999 547 {
<> 149:156823d33999 548 if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))
<> 149:156823d33999 549 {
<> 149:156823d33999 550 /* When a DMA transfer error occurs */
<> 149:156823d33999 551 /* A hardware clear of its EN bits is performed */
<> 149:156823d33999 552 /* Clear all flags */
<> 149:156823d33999 553 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 554
<> 149:156823d33999 555 /* Update error code */
<> 149:156823d33999 556 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 149:156823d33999 557
<> 149:156823d33999 558 /* Change the DMA state */
<> 149:156823d33999 559 hdma->State= HAL_DMA_STATE_READY;
<> 149:156823d33999 560
<> 149:156823d33999 561 /* Process Unlocked */
<> 149:156823d33999 562 __HAL_UNLOCK(hdma);
<> 149:156823d33999 563
<> 149:156823d33999 564 return HAL_ERROR;
<> 149:156823d33999 565 }
<> 149:156823d33999 566 /* Check for the Timeout */
<> 149:156823d33999 567 if(Timeout != HAL_MAX_DELAY)
<> 149:156823d33999 568 {
<> 149:156823d33999 569 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 149:156823d33999 570 {
<> 149:156823d33999 571 /* Update error code */
<> 149:156823d33999 572 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 149:156823d33999 573
<> 149:156823d33999 574 /* Change the DMA state */
<> 149:156823d33999 575 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 576
<> 149:156823d33999 577 /* Process Unlocked */
<> 149:156823d33999 578 __HAL_UNLOCK(hdma);
<> 149:156823d33999 579
<> 149:156823d33999 580 return HAL_ERROR;
<> 149:156823d33999 581 }
<> 149:156823d33999 582 }
<> 149:156823d33999 583 }
<> 149:156823d33999 584
<> 149:156823d33999 585 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 149:156823d33999 586 {
<> 149:156823d33999 587 /* Clear the transfer complete flag */
<> 149:156823d33999 588 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex);
<> 149:156823d33999 589
<> 149:156823d33999 590 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 149:156823d33999 591 all transfers are complete) */
<> 149:156823d33999 592 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 593 }
<> 149:156823d33999 594 else
<> 149:156823d33999 595 {
<> 149:156823d33999 596 /* Clear the half transfer complete flag */
<> 149:156823d33999 597 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex);
<> 149:156823d33999 598 }
<> 149:156823d33999 599
<> 149:156823d33999 600 /* Process unlocked */
<> 149:156823d33999 601 __HAL_UNLOCK(hdma);
<> 149:156823d33999 602
<> 149:156823d33999 603 return HAL_OK;
<> 149:156823d33999 604 }
<> 149:156823d33999 605
<> 149:156823d33999 606 /**
<> 149:156823d33999 607 * @brief Handle DMA interrupt request.
<> 149:156823d33999 608 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 609 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 610 * @retval None
<> 149:156823d33999 611 */
<> 149:156823d33999 612 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 613 {
<> 149:156823d33999 614 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
<> 149:156823d33999 615 uint32_t source_it = hdma->Instance->CCR;
<> 149:156823d33999 616
<> 149:156823d33999 617 /* Half Transfer Complete Interrupt management ******************************/
<> 149:156823d33999 618 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
<> 149:156823d33999 619 {
<> 149:156823d33999 620 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 149:156823d33999 621 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 149:156823d33999 622 {
<> 149:156823d33999 623 /* Disable the half transfer interrupt */
<> 149:156823d33999 624 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 149:156823d33999 625 }
<> 149:156823d33999 626 /* Clear the half transfer complete flag */
<> 149:156823d33999 627 hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex);
<> 149:156823d33999 628
<> 149:156823d33999 629 /* DMA peripheral state is not updated in Half Transfer */
<> 149:156823d33999 630 /* but in Transfer Complete case */
<> 149:156823d33999 631
<> 149:156823d33999 632 if(hdma->XferHalfCpltCallback != NULL)
<> 149:156823d33999 633 {
<> 149:156823d33999 634 /* Half transfer callback */
<> 149:156823d33999 635 hdma->XferHalfCpltCallback(hdma);
<> 149:156823d33999 636 }
<> 149:156823d33999 637 }
<> 149:156823d33999 638
<> 149:156823d33999 639 /* Transfer Complete Interrupt management ***********************************/
<> 149:156823d33999 640 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
<> 149:156823d33999 641 {
<> 149:156823d33999 642 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 149:156823d33999 643 {
<> 149:156823d33999 644 /* Disable TE & TC */
<> 149:156823d33999 645 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
<> 149:156823d33999 646
<> 149:156823d33999 647 /* Change the DMA state */
<> 149:156823d33999 648 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 649 }
<> 149:156823d33999 650
<> 149:156823d33999 651 /* Clear the transfer complete flag */
<> 149:156823d33999 652 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex);
<> 149:156823d33999 653
<> 149:156823d33999 654 /* Process Unlocked */
<> 149:156823d33999 655 __HAL_UNLOCK(hdma);
<> 149:156823d33999 656
<> 149:156823d33999 657 if(hdma->XferCpltCallback != NULL)
<> 149:156823d33999 658 {
<> 149:156823d33999 659 /* Transfer complete callback */
<> 149:156823d33999 660 hdma->XferCpltCallback(hdma);
<> 149:156823d33999 661 }
<> 149:156823d33999 662 }
<> 149:156823d33999 663
<> 149:156823d33999 664 /* Transfer Error Interrupt management **************************************/
<> 149:156823d33999 665 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 149:156823d33999 666 {
<> 149:156823d33999 667 /* When a DMA transfer error occurs */
<> 149:156823d33999 668 /* A hardware clear of its EN bits is performed */
<> 149:156823d33999 669 /* Disable ALL DMA IT */
<> 149:156823d33999 670 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 671
<> 149:156823d33999 672 /* Clear all flags */
<> 149:156823d33999 673 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 149:156823d33999 674
<> 149:156823d33999 675 /* Update error code */
<> 149:156823d33999 676 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 149:156823d33999 677
<> 149:156823d33999 678 /* Change the DMA state */
<> 149:156823d33999 679 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 680
<> 149:156823d33999 681 /* Process Unlocked */
<> 149:156823d33999 682 __HAL_UNLOCK(hdma);
<> 149:156823d33999 683
<> 149:156823d33999 684 if (hdma->XferErrorCallback != NULL)
<> 149:156823d33999 685 {
<> 149:156823d33999 686 /* Transfer error callback */
<> 149:156823d33999 687 hdma->XferErrorCallback(hdma);
<> 149:156823d33999 688 }
<> 149:156823d33999 689 }
<> 149:156823d33999 690 return;
<> 149:156823d33999 691 }
<> 149:156823d33999 692
<> 149:156823d33999 693 /**
<> 149:156823d33999 694 * @brief Register callbacks
<> 149:156823d33999 695 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 696 * the configuration information for the specified DMA Stream.
<> 149:156823d33999 697 * @param CallbackID: User Callback identifer
<> 149:156823d33999 698 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 149:156823d33999 699 * @param pCallback: pointer to private callbacsk function which has pointer to
<> 149:156823d33999 700 * a DMA_HandleTypeDef structure as parameter.
<> 149:156823d33999 701 * @retval HAL status
<> 149:156823d33999 702 */
<> 149:156823d33999 703 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
<> 149:156823d33999 704 {
<> 149:156823d33999 705 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 706
<> 149:156823d33999 707 /* Process locked */
<> 149:156823d33999 708 __HAL_LOCK(hdma);
<> 149:156823d33999 709
<> 149:156823d33999 710 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 711 {
<> 149:156823d33999 712 switch (CallbackID)
<> 149:156823d33999 713 {
<> 149:156823d33999 714 case HAL_DMA_XFER_CPLT_CB_ID:
<> 149:156823d33999 715 hdma->XferCpltCallback = pCallback;
<> 149:156823d33999 716 break;
<> 149:156823d33999 717
<> 149:156823d33999 718 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 149:156823d33999 719 hdma->XferHalfCpltCallback = pCallback;
<> 149:156823d33999 720 break;
<> 149:156823d33999 721
<> 149:156823d33999 722 case HAL_DMA_XFER_ERROR_CB_ID:
<> 149:156823d33999 723 hdma->XferErrorCallback = pCallback;
<> 149:156823d33999 724 break;
<> 149:156823d33999 725
<> 149:156823d33999 726 case HAL_DMA_XFER_ABORT_CB_ID:
<> 149:156823d33999 727 hdma->XferAbortCallback = pCallback;
<> 149:156823d33999 728 break;
<> 149:156823d33999 729
<> 149:156823d33999 730 default:
<> 149:156823d33999 731 status = HAL_ERROR;
<> 149:156823d33999 732 break;
<> 149:156823d33999 733 }
<> 149:156823d33999 734 }
<> 149:156823d33999 735 else
<> 149:156823d33999 736 {
<> 149:156823d33999 737 status = HAL_ERROR;
<> 149:156823d33999 738 }
<> 149:156823d33999 739
<> 149:156823d33999 740 /* Release Lock */
<> 149:156823d33999 741 __HAL_UNLOCK(hdma);
<> 149:156823d33999 742
<> 149:156823d33999 743 return status;
<> 149:156823d33999 744 }
<> 149:156823d33999 745
<> 149:156823d33999 746 /**
<> 149:156823d33999 747 * @brief UnRegister callbacks
<> 149:156823d33999 748 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 749 * the configuration information for the specified DMA Stream.
<> 149:156823d33999 750 * @param CallbackID: User Callback identifer
<> 149:156823d33999 751 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 149:156823d33999 752 * @retval HAL status
<> 149:156823d33999 753 */
<> 149:156823d33999 754 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 149:156823d33999 755 {
<> 149:156823d33999 756 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 757
<> 149:156823d33999 758 /* Process locked */
<> 149:156823d33999 759 __HAL_LOCK(hdma);
<> 149:156823d33999 760
<> 149:156823d33999 761 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 762 {
<> 149:156823d33999 763 switch (CallbackID)
<> 149:156823d33999 764 {
<> 149:156823d33999 765 case HAL_DMA_XFER_CPLT_CB_ID:
<> 149:156823d33999 766 hdma->XferCpltCallback = NULL;
<> 149:156823d33999 767 break;
<> 149:156823d33999 768
<> 149:156823d33999 769 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 149:156823d33999 770 hdma->XferHalfCpltCallback = NULL;
<> 149:156823d33999 771 break;
<> 149:156823d33999 772
<> 149:156823d33999 773 case HAL_DMA_XFER_ERROR_CB_ID:
<> 149:156823d33999 774 hdma->XferErrorCallback = NULL;
<> 149:156823d33999 775 break;
<> 149:156823d33999 776
<> 149:156823d33999 777 case HAL_DMA_XFER_ABORT_CB_ID:
<> 149:156823d33999 778 hdma->XferAbortCallback = NULL;
<> 149:156823d33999 779 break;
<> 149:156823d33999 780
<> 149:156823d33999 781 case HAL_DMA_XFER_ALL_CB_ID:
<> 149:156823d33999 782 hdma->XferCpltCallback = NULL;
<> 149:156823d33999 783 hdma->XferHalfCpltCallback = NULL;
<> 149:156823d33999 784 hdma->XferErrorCallback = NULL;
<> 149:156823d33999 785 hdma->XferAbortCallback = NULL;
<> 149:156823d33999 786 break;
<> 149:156823d33999 787
<> 149:156823d33999 788 default:
<> 149:156823d33999 789 status = HAL_ERROR;
<> 149:156823d33999 790 break;
<> 149:156823d33999 791 }
<> 149:156823d33999 792 }
<> 149:156823d33999 793 else
<> 149:156823d33999 794 {
<> 149:156823d33999 795 status = HAL_ERROR;
<> 149:156823d33999 796 }
<> 149:156823d33999 797
<> 149:156823d33999 798 /* Release Lock */
<> 149:156823d33999 799 __HAL_UNLOCK(hdma);
<> 149:156823d33999 800
<> 149:156823d33999 801 return status;
<> 149:156823d33999 802 }
<> 149:156823d33999 803
<> 149:156823d33999 804 /**
<> 149:156823d33999 805 * @}
<> 149:156823d33999 806 */
<> 149:156823d33999 807
<> 149:156823d33999 808
<> 149:156823d33999 809
<> 149:156823d33999 810 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
<> 149:156823d33999 811 * @brief Peripheral State and Errors functions
<> 149:156823d33999 812 *
<> 149:156823d33999 813 @verbatim
<> 149:156823d33999 814 ===============================================================================
<> 149:156823d33999 815 ##### Peripheral State and Errors functions #####
<> 149:156823d33999 816 ===============================================================================
<> 149:156823d33999 817 [..]
<> 149:156823d33999 818 This subsection provides functions allowing to
<> 149:156823d33999 819 (+) Check the DMA state
<> 149:156823d33999 820 (+) Get error code
<> 149:156823d33999 821
<> 149:156823d33999 822 @endverbatim
<> 149:156823d33999 823 * @{
<> 149:156823d33999 824 */
<> 149:156823d33999 825
<> 149:156823d33999 826 /**
<> 149:156823d33999 827 * @brief Return the DMA hande state.
<> 149:156823d33999 828 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 829 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 830 * @retval HAL state
<> 149:156823d33999 831 */
<> 149:156823d33999 832 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 833 {
<> 149:156823d33999 834 /* Return DMA handle state */
<> 149:156823d33999 835 return hdma->State;
<> 149:156823d33999 836 }
<> 149:156823d33999 837
<> 149:156823d33999 838 /**
<> 149:156823d33999 839 * @brief Return the DMA error code.
<> 149:156823d33999 840 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 841 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 842 * @retval DMA Error Code
<> 149:156823d33999 843 */
<> 149:156823d33999 844 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 845 {
<> 149:156823d33999 846 return hdma->ErrorCode;
<> 149:156823d33999 847 }
<> 149:156823d33999 848
<> 149:156823d33999 849 /**
<> 149:156823d33999 850 * @}
<> 149:156823d33999 851 */
<> 149:156823d33999 852
<> 149:156823d33999 853 /**
<> 149:156823d33999 854 * @}
<> 149:156823d33999 855 */
<> 149:156823d33999 856
<> 149:156823d33999 857 /** @addtogroup DMA_Private_Functions
<> 149:156823d33999 858 * @{
<> 149:156823d33999 859 */
<> 149:156823d33999 860
<> 149:156823d33999 861 /**
<> 149:156823d33999 862 * @brief Sets the DMA Transfer parameter.
<> 149:156823d33999 863 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 864 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 865 * @param SrcAddress: The source memory Buffer address
<> 149:156823d33999 866 * @param DstAddress: The destination memory Buffer address
<> 149:156823d33999 867 * @param DataLength: The length of data to be transferred from source to destination
<> 149:156823d33999 868 * @retval HAL status
<> 149:156823d33999 869 */
<> 149:156823d33999 870 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 149:156823d33999 871 {
<> 149:156823d33999 872 /* Clear all flags */
<> 149:156823d33999 873 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 149:156823d33999 874
<> 149:156823d33999 875 /* Configure DMA Channel data length */
<> 149:156823d33999 876 hdma->Instance->CNDTR = DataLength;
<> 149:156823d33999 877
<> 149:156823d33999 878 /* Peripheral to Memory */
<> 149:156823d33999 879 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 149:156823d33999 880 {
<> 149:156823d33999 881 /* Configure DMA Channel destination address */
<> 149:156823d33999 882 hdma->Instance->CPAR = DstAddress;
<> 149:156823d33999 883
<> 149:156823d33999 884 /* Configure DMA Channel source address */
<> 149:156823d33999 885 hdma->Instance->CMAR = SrcAddress;
<> 149:156823d33999 886 }
<> 149:156823d33999 887 /* Memory to Peripheral */
<> 149:156823d33999 888 else
<> 149:156823d33999 889 {
<> 149:156823d33999 890 /* Configure DMA Channel source address */
<> 149:156823d33999 891 hdma->Instance->CPAR = SrcAddress;
<> 149:156823d33999 892
<> 149:156823d33999 893 /* Configure DMA Channel destination address */
<> 149:156823d33999 894 hdma->Instance->CMAR = DstAddress;
<> 149:156823d33999 895 }
<> 149:156823d33999 896 }
<> 149:156823d33999 897
<> 149:156823d33999 898 /**
<> 149:156823d33999 899 * @}
<> 149:156823d33999 900 */
<> 149:156823d33999 901
<> 149:156823d33999 902 /**
<> 149:156823d33999 903 * @}
<> 149:156823d33999 904 */
<> 149:156823d33999 905
<> 149:156823d33999 906 #endif /* HAL_DMA_MODULE_ENABLED */
<> 149:156823d33999 907 /**
<> 149:156823d33999 908 * @}
<> 149:156823d33999 909 */
<> 149:156823d33999 910
<> 149:156823d33999 911 /**
<> 149:156823d33999 912 * @}
<> 149:156823d33999 913 */
<> 149:156823d33999 914
<> 149:156823d33999 915 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/