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mbed library sources. Supersedes mbed-src.

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targets/TARGET_STM/TARGET_STM32L1/device/stm32l1xx_hal_dma.c@184:08ed48f1de7f, 2018-04-19 (annotated)

Committer:
AnnaBridge
Date:
Thu Apr 19 17:12:19 2018 +0100
Revision:
184:08ed48f1de7f
Parent:
149:156823d33999 
mbed-dev library. Release version 161

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /**
<> 149:156823d33999 2 ******************************************************************************
<> 149:156823d33999 3 * @file stm32l1xx_hal_dma.c
<> 149:156823d33999 4 * @author MCD Application Team
<> 149:156823d33999 5 * @brief DMA HAL module driver.
<> 149:156823d33999 6 * This file provides firmware functions to manage the following
<> 149:156823d33999 7 * functionalities of the Direct Memory Access (DMA) peripheral:
<> 149:156823d33999 8 * + Initialization and de-initialization functions
<> 149:156823d33999 9 * + IO operation functions
<> 149:156823d33999 10 * + Peripheral State and errors functions
<> 149:156823d33999 11 @verbatim
<> 149:156823d33999 12 ==============================================================================
<> 149:156823d33999 13 ##### How to use this driver #####
<> 149:156823d33999 14 ==============================================================================
<> 149:156823d33999 15 [..]
<> 149:156823d33999 16 (#) Enable and configure the peripheral to be connected to the DMA Channel
<> 149:156823d33999 17 (except for internal SRAM / FLASH memories: no initialization is
<> 149:156823d33999 18 necessary). Please refer to the Reference manual for connection between peripherals
<> 149:156823d33999 19 and DMA requests.
<> 149:156823d33999 20
<> 149:156823d33999 21 (#) For a given Channel, program the required configuration through the following parameters:
<> 149:156823d33999 22 Channel request, Transfer Direction, Source and Destination data formats,
<> 149:156823d33999 23 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
<> 149:156823d33999 24 using HAL_DMA_Init() function.
<> 149:156823d33999 25
<> 149:156823d33999 26 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
<> 149:156823d33999 27 detection.
<> 149:156823d33999 28
<> 149:156823d33999 29 (#) Use HAL_DMA_Abort() function to abort the current transfer
<> 149:156823d33999 30
<> 149:156823d33999 31 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
<> 149:156823d33999 32 *** Polling mode IO operation ***
<> 149:156823d33999 33 =================================
<> 149:156823d33999 34 [..]
<> 149:156823d33999 35 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
<> 149:156823d33999 36 address and destination address and the Length of data to be transferred
<> 149:156823d33999 37 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
<> 149:156823d33999 38 case a fixed Timeout can be configured by User depending from his application.
<> 149:156823d33999 39
<> 149:156823d33999 40 *** Interrupt mode IO operation ***
<> 149:156823d33999 41 ===================================
<> 149:156823d33999 42 [..]
<> 149:156823d33999 43 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
<> 149:156823d33999 44 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
<> 149:156823d33999 45 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
<> 149:156823d33999 46 Source address and destination address and the Length of data to be transferred.
<> 149:156823d33999 47 In this case the DMA interrupt is configured
<> 149:156823d33999 48 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
<> 149:156823d33999 49 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
<> 149:156823d33999 50 add his own function by customization of function pointer XferCpltCallback and
<> 149:156823d33999 51 XferErrorCallback (i.e. a member of DMA handle structure).
<> 149:156823d33999 52
<> 149:156823d33999 53 *** DMA HAL driver macros list ***
<> 149:156823d33999 54 =============================================
<> 149:156823d33999 55 [..]
<> 149:156823d33999 56 Below the list of most used macros in DMA HAL driver.
<> 149:156823d33999 57
<> 149:156823d33999 58 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
<> 149:156823d33999 59 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
<> 149:156823d33999 60 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
<> 149:156823d33999 61 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
<> 149:156823d33999 62 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
<> 149:156823d33999 63 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
<> 149:156823d33999 64 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not.
<> 149:156823d33999 65
<> 149:156823d33999 66 [..]
<> 149:156823d33999 67 (@) You can refer to the DMA HAL driver header file for more useful macros
<> 149:156823d33999 68
<> 149:156823d33999 69 @endverbatim
<> 149:156823d33999 70 ******************************************************************************
<> 149:156823d33999 71 * @attention
<> 149:156823d33999 72 *
AnnaBridge 184:08ed48f1de7f 73 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
<> 149:156823d33999 74 *
<> 149:156823d33999 75 * Redistribution and use in source and binary forms, with or without modification,
<> 149:156823d33999 76 * are permitted provided that the following conditions are met:
<> 149:156823d33999 77 * 1. Redistributions of source code must retain the above copyright notice,
<> 149:156823d33999 78 * this list of conditions and the following disclaimer.
<> 149:156823d33999 79 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 149:156823d33999 80 * this list of conditions and the following disclaimer in the documentation
<> 149:156823d33999 81 * and/or other materials provided with the distribution.
<> 149:156823d33999 82 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 149:156823d33999 83 * may be used to endorse or promote products derived from this software
<> 149:156823d33999 84 * without specific prior written permission.
<> 149:156823d33999 85 *
<> 149:156823d33999 86 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 149:156823d33999 87 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 149:156823d33999 88 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 149:156823d33999 89 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 149:156823d33999 90 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 149:156823d33999 91 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 149:156823d33999 92 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 149:156823d33999 93 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 149:156823d33999 94 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 149:156823d33999 95 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 149:156823d33999 96 *
<> 149:156823d33999 97 ******************************************************************************
<> 149:156823d33999 98 */
<> 149:156823d33999 99
<> 149:156823d33999 100 /* Includes ------------------------------------------------------------------*/
<> 149:156823d33999 101 #include "stm32l1xx_hal.h"
<> 149:156823d33999 102
<> 149:156823d33999 103 /** @addtogroup STM32L1xx_HAL_Driver
<> 149:156823d33999 104 * @{
<> 149:156823d33999 105 */
<> 149:156823d33999 106
<> 149:156823d33999 107 /** @defgroup DMA DMA
<> 149:156823d33999 108 * @brief DMA HAL module driver
<> 149:156823d33999 109 * @{
<> 149:156823d33999 110 */
<> 149:156823d33999 111
<> 149:156823d33999 112 #ifdef HAL_DMA_MODULE_ENABLED
<> 149:156823d33999 113
<> 149:156823d33999 114 /* Private typedef -----------------------------------------------------------*/
<> 149:156823d33999 115 /* Private define ------------------------------------------------------------*/
<> 149:156823d33999 116 /* Private macro -------------------------------------------------------------*/
<> 149:156823d33999 117 /* Private variables ---------------------------------------------------------*/
<> 149:156823d33999 118 /* Private function prototypes -----------------------------------------------*/
<> 149:156823d33999 119 /** @defgroup DMA_Private_Functions DMA Private Functions
<> 149:156823d33999 120 * @{
<> 149:156823d33999 121 */
<> 149:156823d33999 122 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
<> 149:156823d33999 123
<> 149:156823d33999 124 /**
<> 149:156823d33999 125 * @}
<> 149:156823d33999 126 */
<> 149:156823d33999 127
<> 149:156823d33999 128 /* Exported functions ---------------------------------------------------------*/
<> 149:156823d33999 129
<> 149:156823d33999 130 /** @defgroup DMA_Exported_Functions DMA Exported Functions
<> 149:156823d33999 131 * @{
<> 149:156823d33999 132 */
<> 149:156823d33999 133
<> 149:156823d33999 134 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
<> 149:156823d33999 135 * @brief Initialization and de-initialization functions
<> 149:156823d33999 136 *
<> 149:156823d33999 137 @verbatim
<> 149:156823d33999 138 ===============================================================================
<> 149:156823d33999 139 ##### Initialization and de-initialization functions #####
<> 149:156823d33999 140 ===============================================================================
<> 149:156823d33999 141 [..]
<> 149:156823d33999 142 This section provides functions allowing to initialize the DMA Channel source
<> 149:156823d33999 143 and destination addresses, incrementation and data sizes, transfer direction,
<> 149:156823d33999 144 circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
<> 149:156823d33999 145 [..]
<> 149:156823d33999 146 The HAL_DMA_Init() function follows the DMA configuration procedures as described in
<> 149:156823d33999 147 reference manual.
<> 149:156823d33999 148
<> 149:156823d33999 149 @endverbatim
<> 149:156823d33999 150 * @{
<> 149:156823d33999 151 */
<> 149:156823d33999 152
<> 149:156823d33999 153 /**
<> 149:156823d33999 154 * @brief Initialize the DMA according to the specified
<> 149:156823d33999 155 * parameters in the DMA_InitTypeDef and initialize the associated handle.
<> 149:156823d33999 156 * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 157 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 158 * @retval HAL status
<> 149:156823d33999 159 */
<> 149:156823d33999 160 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 161 {
<> 149:156823d33999 162 uint32_t tmp = 0;
<> 149:156823d33999 163
<> 149:156823d33999 164 /* Check the DMA handle allocation */
<> 149:156823d33999 165 if(hdma == NULL)
<> 149:156823d33999 166 {
<> 149:156823d33999 167 return HAL_ERROR;
<> 149:156823d33999 168 }
<> 149:156823d33999 169
<> 149:156823d33999 170 /* Check the parameters */
<> 149:156823d33999 171 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 149:156823d33999 172 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
<> 149:156823d33999 173 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
<> 149:156823d33999 174 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
<> 149:156823d33999 175 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
<> 149:156823d33999 176 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
<> 149:156823d33999 177 assert_param(IS_DMA_MODE(hdma->Init.Mode));
<> 149:156823d33999 178 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
<> 149:156823d33999 179
<> 149:156823d33999 180 #if defined (DMA2)
<> 149:156823d33999 181 /* calculation of the channel index */
<> 149:156823d33999 182 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 149:156823d33999 183 {
<> 149:156823d33999 184 /* DMA1 */
<> 149:156823d33999 185 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 186 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 187 }
<> 149:156823d33999 188 else
<> 149:156823d33999 189 {
<> 149:156823d33999 190 /* DMA2 */
<> 149:156823d33999 191 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 149:156823d33999 192 hdma->DmaBaseAddress = DMA2;
<> 149:156823d33999 193 }
<> 149:156823d33999 194 #else
<> 149:156823d33999 195 /* calculation of the channel index */
<> 149:156823d33999 196 /* DMA1 */
<> 149:156823d33999 197 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 198 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 199 #endif
<> 149:156823d33999 200
<> 149:156823d33999 201 /* Change DMA peripheral state */
<> 149:156823d33999 202 hdma->State = HAL_DMA_STATE_BUSY;
<> 149:156823d33999 203
<> 149:156823d33999 204 /* Get the CR register value */
<> 149:156823d33999 205 tmp = hdma->Instance->CCR;
<> 149:156823d33999 206
<> 149:156823d33999 207 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
<> 149:156823d33999 208 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
<> 149:156823d33999 209 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \
<> 149:156823d33999 210 DMA_CCR_DIR));
<> 149:156823d33999 211
<> 149:156823d33999 212 /* Prepare the DMA Channel configuration */
<> 149:156823d33999 213 tmp |= hdma->Init.Direction |
<> 149:156823d33999 214 hdma->Init.PeriphInc | hdma->Init.MemInc |
<> 149:156823d33999 215 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
<> 149:156823d33999 216 hdma->Init.Mode | hdma->Init.Priority;
<> 149:156823d33999 217
<> 149:156823d33999 218 /* Write to DMA Channel CR register */
<> 149:156823d33999 219 hdma->Instance->CCR = tmp;
<> 149:156823d33999 220
<> 149:156823d33999 221 /* Clean callbacks */
<> 149:156823d33999 222 hdma->XferCpltCallback = NULL;
<> 149:156823d33999 223 hdma->XferHalfCpltCallback = NULL;
<> 149:156823d33999 224 hdma->XferErrorCallback = NULL;
<> 149:156823d33999 225 hdma->XferAbortCallback = NULL;
<> 149:156823d33999 226
<> 149:156823d33999 227 /* Initialise the error code */
<> 149:156823d33999 228 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 229
<> 149:156823d33999 230 /* Initialize the DMA state*/
<> 149:156823d33999 231 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 232
<> 149:156823d33999 233 /* Allocate lock resource and initialize it */
<> 149:156823d33999 234 hdma->Lock = HAL_UNLOCKED;
<> 149:156823d33999 235
<> 149:156823d33999 236 return HAL_OK;
<> 149:156823d33999 237 }
<> 149:156823d33999 238
<> 149:156823d33999 239 /**
<> 149:156823d33999 240 * @brief DeInitialize the DMA peripheral.
<> 149:156823d33999 241 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 242 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 243 * @retval HAL status
<> 149:156823d33999 244 */
<> 149:156823d33999 245 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 246 {
<> 149:156823d33999 247 /* Check the DMA handle allocation */
<> 149:156823d33999 248 if (NULL == hdma )
<> 149:156823d33999 249 {
<> 149:156823d33999 250 return HAL_ERROR;
<> 149:156823d33999 251 }
<> 149:156823d33999 252
<> 149:156823d33999 253 /* Check the parameters */
<> 149:156823d33999 254 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
<> 149:156823d33999 255
<> 149:156823d33999 256 /* Disable the selected DMA Channelx */
<> 149:156823d33999 257 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 258
<> 149:156823d33999 259 #if defined (DMA2)
<> 149:156823d33999 260 /* calculation of the channel index */
<> 149:156823d33999 261 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
<> 149:156823d33999 262 {
<> 149:156823d33999 263 /* DMA1 */
<> 149:156823d33999 264 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 265 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 266 }
<> 149:156823d33999 267 else
<> 149:156823d33999 268 {
<> 149:156823d33999 269 /* DMA2 */
<> 149:156823d33999 270 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
<> 149:156823d33999 271 hdma->DmaBaseAddress = DMA2;
<> 149:156823d33999 272 }
<> 149:156823d33999 273 #else
<> 149:156823d33999 274 /* calculation of the channel index */
<> 149:156823d33999 275 /* DMA1 */
<> 149:156823d33999 276 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
<> 149:156823d33999 277 hdma->DmaBaseAddress = DMA1;
<> 149:156823d33999 278 #endif
<> 149:156823d33999 279
<> 149:156823d33999 280 /* Reset DMA Channel control register */
<> 149:156823d33999 281 hdma->Instance->CCR = 0;
<> 149:156823d33999 282
<> 149:156823d33999 283 /* Reset DMA Channel Number of Data to Transfer register */
<> 149:156823d33999 284 hdma->Instance->CNDTR = 0;
<> 149:156823d33999 285
<> 149:156823d33999 286 /* Reset DMA Channel peripheral address register */
<> 149:156823d33999 287 hdma->Instance->CPAR = 0;
<> 149:156823d33999 288
<> 149:156823d33999 289 /* Reset DMA Channel memory address register */
<> 149:156823d33999 290 hdma->Instance->CMAR = 0;
<> 149:156823d33999 291
<> 149:156823d33999 292 /* Clear all flags */
<> 149:156823d33999 293 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 294
<> 149:156823d33999 295 /* Initialise the error code */
<> 149:156823d33999 296 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 297
<> 149:156823d33999 298 /* Initialize the DMA state */
<> 149:156823d33999 299 hdma->State = HAL_DMA_STATE_RESET;
<> 149:156823d33999 300
<> 149:156823d33999 301 /* Release Lock */
<> 149:156823d33999 302 __HAL_UNLOCK(hdma);
<> 149:156823d33999 303
<> 149:156823d33999 304 return HAL_OK;
<> 149:156823d33999 305 }
<> 149:156823d33999 306
<> 149:156823d33999 307 /**
<> 149:156823d33999 308 * @}
<> 149:156823d33999 309 */
<> 149:156823d33999 310
<> 149:156823d33999 311 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
<> 149:156823d33999 312 * @brief Input and Output operation functions
<> 149:156823d33999 313 *
<> 149:156823d33999 314 @verbatim
<> 149:156823d33999 315 ===============================================================================
<> 149:156823d33999 316 ##### IO operation functions #####
<> 149:156823d33999 317 ===============================================================================
<> 149:156823d33999 318 [..] This section provides functions allowing to:
<> 149:156823d33999 319 (+) Configure the source, destination address and data length and Start DMA transfer
<> 149:156823d33999 320 (+) Configure the source, destination address and data length and
<> 149:156823d33999 321 Start DMA transfer with interrupt
<> 149:156823d33999 322 (+) Abort DMA transfer
<> 149:156823d33999 323 (+) Poll for transfer complete
<> 149:156823d33999 324 (+) Handle DMA interrupt request
<> 149:156823d33999 325
<> 149:156823d33999 326 @endverbatim
<> 149:156823d33999 327 * @{
<> 149:156823d33999 328 */
<> 149:156823d33999 329
<> 149:156823d33999 330 /**
<> 149:156823d33999 331 * @brief Start the DMA Transfer.
<> 149:156823d33999 332 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 333 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 334 * @param SrcAddress: The source memory Buffer address
<> 149:156823d33999 335 * @param DstAddress: The destination memory Buffer address
<> 149:156823d33999 336 * @param DataLength: The length of data to be transferred from source to destination
<> 149:156823d33999 337 * @retval HAL status
<> 149:156823d33999 338 */
<> 149:156823d33999 339 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 149:156823d33999 340 {
<> 149:156823d33999 341 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 342
<> 149:156823d33999 343 /* Check the parameters */
<> 149:156823d33999 344 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 149:156823d33999 345
<> 149:156823d33999 346 /* Process locked */
<> 149:156823d33999 347 __HAL_LOCK(hdma);
<> 149:156823d33999 348
<> 149:156823d33999 349 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 350 {
<> 149:156823d33999 351 /* Change DMA peripheral state */
<> 149:156823d33999 352 hdma->State = HAL_DMA_STATE_BUSY;
<> 149:156823d33999 353 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 354
<> 149:156823d33999 355 /* Disable the peripheral */
<> 149:156823d33999 356 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 357
<> 149:156823d33999 358 /* Configure the source, destination address and the data length & clear flags*/
<> 149:156823d33999 359 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 149:156823d33999 360
<> 149:156823d33999 361 /* Enable the Peripheral */
<> 149:156823d33999 362 __HAL_DMA_ENABLE(hdma);
<> 149:156823d33999 363 }
<> 149:156823d33999 364 else
<> 149:156823d33999 365 {
<> 149:156823d33999 366 /* Process Unlocked */
<> 149:156823d33999 367 __HAL_UNLOCK(hdma);
<> 149:156823d33999 368 status = HAL_BUSY;
<> 149:156823d33999 369 }
<> 149:156823d33999 370 return status;
<> 149:156823d33999 371 }
<> 149:156823d33999 372
<> 149:156823d33999 373 /**
<> 149:156823d33999 374 * @brief Start the DMA Transfer with interrupt enabled.
<> 149:156823d33999 375 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 376 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 377 * @param SrcAddress: The source memory Buffer address
<> 149:156823d33999 378 * @param DstAddress: The destination memory Buffer address
<> 149:156823d33999 379 * @param DataLength: The length of data to be transferred from source to destination
<> 149:156823d33999 380 * @retval HAL status
<> 149:156823d33999 381 */
<> 149:156823d33999 382 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 149:156823d33999 383 {
<> 149:156823d33999 384 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 385
<> 149:156823d33999 386 /* Check the parameters */
<> 149:156823d33999 387 assert_param(IS_DMA_BUFFER_SIZE(DataLength));
<> 149:156823d33999 388
<> 149:156823d33999 389 /* Process locked */
<> 149:156823d33999 390 __HAL_LOCK(hdma);
<> 149:156823d33999 391
<> 149:156823d33999 392 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 393 {
<> 149:156823d33999 394 /* Change DMA peripheral state */
<> 149:156823d33999 395 hdma->State = HAL_DMA_STATE_BUSY;
<> 149:156823d33999 396 hdma->ErrorCode = HAL_DMA_ERROR_NONE;
<> 149:156823d33999 397
<> 149:156823d33999 398 /* Disable the peripheral */
<> 149:156823d33999 399 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 400
<> 149:156823d33999 401 /* Configure the source, destination address and the data length & clear flags*/
<> 149:156823d33999 402 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
<> 149:156823d33999 403
<> 149:156823d33999 404 /* Enable the transfer complete interrupt */
<> 149:156823d33999 405 /* Enable the transfer Error interrupt */
<> 149:156823d33999 406 if(NULL != hdma->XferHalfCpltCallback )
<> 149:156823d33999 407 {
<> 149:156823d33999 408 /* Enable the Half transfer complete interrupt as well */
<> 149:156823d33999 409 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 410 }
<> 149:156823d33999 411 else
<> 149:156823d33999 412 {
<> 149:156823d33999 413 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 149:156823d33999 414 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
<> 149:156823d33999 415 }
<> 149:156823d33999 416 /* Enable the Peripheral */
<> 149:156823d33999 417 __HAL_DMA_ENABLE(hdma);
<> 149:156823d33999 418 }
<> 149:156823d33999 419 else
<> 149:156823d33999 420 {
<> 149:156823d33999 421 /* Process Unlocked */
<> 149:156823d33999 422 __HAL_UNLOCK(hdma);
<> 149:156823d33999 423
<> 149:156823d33999 424 /* Remain BUSY */
<> 149:156823d33999 425 status = HAL_BUSY;
<> 149:156823d33999 426 }
<> 149:156823d33999 427 return status;
<> 149:156823d33999 428 }
<> 149:156823d33999 429
<> 149:156823d33999 430 /**
<> 149:156823d33999 431 * @brief Abort the DMA Transfer.
<> 149:156823d33999 432 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 433 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 434 * @retval HAL status
<> 149:156823d33999 435 */
<> 149:156823d33999 436 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 437 {
<> 149:156823d33999 438 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 439
<> 149:156823d33999 440 /* Disable DMA IT */
<> 149:156823d33999 441 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 442
<> 149:156823d33999 443 /* Disable the channel */
<> 149:156823d33999 444 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 445
<> 149:156823d33999 446 /* Clear all flags */
<> 149:156823d33999 447 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 448
<> 149:156823d33999 449 /* Change the DMA state */
<> 149:156823d33999 450 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 451
<> 149:156823d33999 452 /* Process Unlocked */
<> 149:156823d33999 453 __HAL_UNLOCK(hdma);
<> 149:156823d33999 454
<> 149:156823d33999 455 return status;
<> 149:156823d33999 456 }
<> 149:156823d33999 457
<> 149:156823d33999 458 /**
<> 149:156823d33999 459 * @brief Aborts the DMA Transfer in Interrupt mode.
<> 149:156823d33999 460 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 461 * the configuration information for the specified DMA Stream.
<> 149:156823d33999 462 * @retval HAL status
<> 149:156823d33999 463 */
<> 149:156823d33999 464 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 465 {
<> 149:156823d33999 466 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 467
<> 149:156823d33999 468 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 149:156823d33999 469 {
<> 149:156823d33999 470 /* no transfer ongoing */
<> 149:156823d33999 471 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 149:156823d33999 472
<> 149:156823d33999 473 status = HAL_ERROR;
<> 149:156823d33999 474 }
<> 149:156823d33999 475 else
<> 149:156823d33999 476 {
<> 149:156823d33999 477 /* Disable DMA IT */
<> 149:156823d33999 478 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 479
<> 149:156823d33999 480 /* Disable the channel */
<> 149:156823d33999 481 __HAL_DMA_DISABLE(hdma);
<> 149:156823d33999 482
<> 149:156823d33999 483 /* Clear all flags */
<> 149:156823d33999 484 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 485
<> 149:156823d33999 486 /* Change the DMA state */
<> 149:156823d33999 487 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 488
<> 149:156823d33999 489 /* Process Unlocked */
<> 149:156823d33999 490 __HAL_UNLOCK(hdma);
<> 149:156823d33999 491
<> 149:156823d33999 492 /* Call User Abort callback */
<> 149:156823d33999 493 if(hdma->XferAbortCallback != NULL)
<> 149:156823d33999 494 {
<> 149:156823d33999 495 hdma->XferAbortCallback(hdma);
<> 149:156823d33999 496 }
<> 149:156823d33999 497 }
<> 149:156823d33999 498 return status;
<> 149:156823d33999 499 }
<> 149:156823d33999 500
<> 149:156823d33999 501 /**
<> 149:156823d33999 502 * @brief Polling for transfer complete.
<> 149:156823d33999 503 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 504 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 505 * @param CompleteLevel: Specifies the DMA level complete.
<> 149:156823d33999 506 * @param Timeout: Timeout duration.
<> 149:156823d33999 507 * @retval HAL status
<> 149:156823d33999 508 */
<> 149:156823d33999 509 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
<> 149:156823d33999 510 {
<> 149:156823d33999 511 uint32_t temp;
<> 149:156823d33999 512 uint32_t tickstart = 0;
<> 149:156823d33999 513
<> 149:156823d33999 514 if(HAL_DMA_STATE_BUSY != hdma->State)
<> 149:156823d33999 515 {
<> 149:156823d33999 516 /* no transfer ongoing */
<> 149:156823d33999 517 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
<> 149:156823d33999 518 __HAL_UNLOCK(hdma);
<> 149:156823d33999 519 return HAL_ERROR;
<> 149:156823d33999 520 }
<> 149:156823d33999 521
<> 149:156823d33999 522 /* Polling mode not supported in circular mode */
<> 149:156823d33999 523 if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC))
<> 149:156823d33999 524 {
<> 149:156823d33999 525 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
<> 149:156823d33999 526 return HAL_ERROR;
<> 149:156823d33999 527 }
<> 149:156823d33999 528
<> 149:156823d33999 529 /* Get the level transfer complete flag */
<> 149:156823d33999 530 if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 149:156823d33999 531 {
<> 149:156823d33999 532 /* Transfer Complete flag */
<> 149:156823d33999 533 temp = DMA_FLAG_TC1 << hdma->ChannelIndex;
<> 149:156823d33999 534 }
<> 149:156823d33999 535 else
<> 149:156823d33999 536 {
<> 149:156823d33999 537 /* Half Transfer Complete flag */
<> 149:156823d33999 538 temp = DMA_FLAG_HT1 << hdma->ChannelIndex;
<> 149:156823d33999 539 }
<> 149:156823d33999 540
<> 149:156823d33999 541 /* Get tick */
<> 149:156823d33999 542 tickstart = HAL_GetTick();
<> 149:156823d33999 543
<> 149:156823d33999 544 while(RESET == (hdma->DmaBaseAddress->ISR & temp))
<> 149:156823d33999 545 {
<> 149:156823d33999 546 if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex))))
<> 149:156823d33999 547 {
<> 149:156823d33999 548 /* When a DMA transfer error occurs */
<> 149:156823d33999 549 /* A hardware clear of its EN bits is performed */
<> 149:156823d33999 550 /* Clear all flags */
<> 149:156823d33999 551 hdma->DmaBaseAddress->IFCR = ((DMA_ISR_GIF1) << (hdma->ChannelIndex));
<> 149:156823d33999 552
<> 149:156823d33999 553 /* Update error code */
<> 149:156823d33999 554 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 149:156823d33999 555
<> 149:156823d33999 556 /* Change the DMA state */
<> 149:156823d33999 557 hdma->State= HAL_DMA_STATE_READY;
<> 149:156823d33999 558
<> 149:156823d33999 559 /* Process Unlocked */
<> 149:156823d33999 560 __HAL_UNLOCK(hdma);
<> 149:156823d33999 561
<> 149:156823d33999 562 return HAL_ERROR;
<> 149:156823d33999 563 }
<> 149:156823d33999 564 /* Check for the Timeout */
<> 149:156823d33999 565 if(Timeout != HAL_MAX_DELAY)
<> 149:156823d33999 566 {
<> 149:156823d33999 567 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
<> 149:156823d33999 568 {
<> 149:156823d33999 569 /* Update error code */
<> 149:156823d33999 570 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
<> 149:156823d33999 571
<> 149:156823d33999 572 /* Change the DMA state */
<> 149:156823d33999 573 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 574
<> 149:156823d33999 575 /* Process Unlocked */
<> 149:156823d33999 576 __HAL_UNLOCK(hdma);
<> 149:156823d33999 577
<> 149:156823d33999 578 return HAL_ERROR;
<> 149:156823d33999 579 }
<> 149:156823d33999 580 }
<> 149:156823d33999 581 }
<> 149:156823d33999 582
<> 149:156823d33999 583 if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
<> 149:156823d33999 584 {
<> 149:156823d33999 585 /* Clear the transfer complete flag */
<> 149:156823d33999 586 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex);
<> 149:156823d33999 587
<> 149:156823d33999 588 /* The selected Channelx EN bit is cleared (DMA is disabled and
<> 149:156823d33999 589 all transfers are complete) */
<> 149:156823d33999 590 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 591 }
<> 149:156823d33999 592 else
<> 149:156823d33999 593 {
<> 149:156823d33999 594 /* Clear the half transfer complete flag */
<> 149:156823d33999 595 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex);
<> 149:156823d33999 596 }
<> 149:156823d33999 597
<> 149:156823d33999 598 /* Process unlocked */
<> 149:156823d33999 599 __HAL_UNLOCK(hdma);
<> 149:156823d33999 600
<> 149:156823d33999 601 return HAL_OK;
<> 149:156823d33999 602 }
<> 149:156823d33999 603
<> 149:156823d33999 604 /**
<> 149:156823d33999 605 * @brief Handle DMA interrupt request.
<> 149:156823d33999 606 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 607 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 608 * @retval None
<> 149:156823d33999 609 */
<> 149:156823d33999 610 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 611 {
<> 149:156823d33999 612 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
<> 149:156823d33999 613 uint32_t source_it = hdma->Instance->CCR;
<> 149:156823d33999 614
<> 149:156823d33999 615 /* Half Transfer Complete Interrupt management ******************************/
<> 149:156823d33999 616 if ((RESET != (flag_it & (DMA_FLAG_HT1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_HT)))
<> 149:156823d33999 617 {
<> 149:156823d33999 618 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
<> 149:156823d33999 619 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 149:156823d33999 620 {
<> 149:156823d33999 621 /* Disable the half transfer interrupt */
<> 149:156823d33999 622 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
<> 149:156823d33999 623 }
<> 149:156823d33999 624 /* Clear the half transfer complete flag */
<> 149:156823d33999 625 hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << hdma->ChannelIndex);
<> 149:156823d33999 626
<> 149:156823d33999 627 /* DMA peripheral state is not updated in Half Transfer */
<> 149:156823d33999 628 /* but in Transfer Complete case */
<> 149:156823d33999 629
<> 149:156823d33999 630 if(hdma->XferHalfCpltCallback != NULL)
<> 149:156823d33999 631 {
<> 149:156823d33999 632 /* Half transfer callback */
<> 149:156823d33999 633 hdma->XferHalfCpltCallback(hdma);
<> 149:156823d33999 634 }
<> 149:156823d33999 635 }
<> 149:156823d33999 636
<> 149:156823d33999 637 /* Transfer Complete Interrupt management ***********************************/
<> 149:156823d33999 638 else if ((RESET != (flag_it & (DMA_FLAG_TC1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TC)))
<> 149:156823d33999 639 {
<> 149:156823d33999 640 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
<> 149:156823d33999 641 {
<> 149:156823d33999 642 /* Disable TE & TC */
<> 149:156823d33999 643 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
<> 149:156823d33999 644
<> 149:156823d33999 645 /* Change the DMA state */
<> 149:156823d33999 646 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 647 }
<> 149:156823d33999 648
<> 149:156823d33999 649 /* Clear the transfer complete flag */
<> 149:156823d33999 650 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << hdma->ChannelIndex);
<> 149:156823d33999 651
<> 149:156823d33999 652 /* Process Unlocked */
<> 149:156823d33999 653 __HAL_UNLOCK(hdma);
<> 149:156823d33999 654
<> 149:156823d33999 655 if(hdma->XferCpltCallback != NULL)
<> 149:156823d33999 656 {
<> 149:156823d33999 657 /* Transfer complete callback */
<> 149:156823d33999 658 hdma->XferCpltCallback(hdma);
<> 149:156823d33999 659 }
<> 149:156823d33999 660 }
<> 149:156823d33999 661
<> 149:156823d33999 662 /* Transfer Error Interrupt management **************************************/
<> 149:156823d33999 663 else if (( RESET != (flag_it & (DMA_FLAG_TE1 << hdma->ChannelIndex))) && (RESET != (source_it & DMA_IT_TE)))
<> 149:156823d33999 664 {
<> 149:156823d33999 665 /* When a DMA transfer error occurs */
<> 149:156823d33999 666 /* A hardware clear of its EN bits is performed */
<> 149:156823d33999 667 /* Disable ALL DMA IT */
<> 149:156823d33999 668 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
<> 149:156823d33999 669
<> 149:156823d33999 670 /* Clear all flags */
<> 149:156823d33999 671 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 149:156823d33999 672
<> 149:156823d33999 673 /* Update error code */
<> 149:156823d33999 674 hdma->ErrorCode = HAL_DMA_ERROR_TE;
<> 149:156823d33999 675
<> 149:156823d33999 676 /* Change the DMA state */
<> 149:156823d33999 677 hdma->State = HAL_DMA_STATE_READY;
<> 149:156823d33999 678
<> 149:156823d33999 679 /* Process Unlocked */
<> 149:156823d33999 680 __HAL_UNLOCK(hdma);
<> 149:156823d33999 681
<> 149:156823d33999 682 if (hdma->XferErrorCallback != NULL)
<> 149:156823d33999 683 {
<> 149:156823d33999 684 /* Transfer error callback */
<> 149:156823d33999 685 hdma->XferErrorCallback(hdma);
<> 149:156823d33999 686 }
<> 149:156823d33999 687 }
<> 149:156823d33999 688 return;
<> 149:156823d33999 689 }
<> 149:156823d33999 690
<> 149:156823d33999 691 /**
<> 149:156823d33999 692 * @brief Register callbacks
<> 149:156823d33999 693 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 694 * the configuration information for the specified DMA Stream.
<> 149:156823d33999 695 * @param CallbackID: User Callback identifer
<> 149:156823d33999 696 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 149:156823d33999 697 * @param pCallback: pointer to private callbacsk function which has pointer to
<> 149:156823d33999 698 * a DMA_HandleTypeDef structure as parameter.
<> 149:156823d33999 699 * @retval HAL status
<> 149:156823d33999 700 */
<> 149:156823d33999 701 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
<> 149:156823d33999 702 {
<> 149:156823d33999 703 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 704
<> 149:156823d33999 705 /* Process locked */
<> 149:156823d33999 706 __HAL_LOCK(hdma);
<> 149:156823d33999 707
<> 149:156823d33999 708 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 709 {
<> 149:156823d33999 710 switch (CallbackID)
<> 149:156823d33999 711 {
<> 149:156823d33999 712 case HAL_DMA_XFER_CPLT_CB_ID:
<> 149:156823d33999 713 hdma->XferCpltCallback = pCallback;
<> 149:156823d33999 714 break;
<> 149:156823d33999 715
<> 149:156823d33999 716 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 149:156823d33999 717 hdma->XferHalfCpltCallback = pCallback;
<> 149:156823d33999 718 break;
<> 149:156823d33999 719
<> 149:156823d33999 720 case HAL_DMA_XFER_ERROR_CB_ID:
<> 149:156823d33999 721 hdma->XferErrorCallback = pCallback;
<> 149:156823d33999 722 break;
<> 149:156823d33999 723
<> 149:156823d33999 724 case HAL_DMA_XFER_ABORT_CB_ID:
<> 149:156823d33999 725 hdma->XferAbortCallback = pCallback;
<> 149:156823d33999 726 break;
<> 149:156823d33999 727
<> 149:156823d33999 728 default:
<> 149:156823d33999 729 status = HAL_ERROR;
<> 149:156823d33999 730 break;
<> 149:156823d33999 731 }
<> 149:156823d33999 732 }
<> 149:156823d33999 733 else
<> 149:156823d33999 734 {
<> 149:156823d33999 735 status = HAL_ERROR;
<> 149:156823d33999 736 }
<> 149:156823d33999 737
<> 149:156823d33999 738 /* Release Lock */
<> 149:156823d33999 739 __HAL_UNLOCK(hdma);
<> 149:156823d33999 740
<> 149:156823d33999 741 return status;
<> 149:156823d33999 742 }
<> 149:156823d33999 743
<> 149:156823d33999 744 /**
<> 149:156823d33999 745 * @brief UnRegister callbacks
<> 149:156823d33999 746 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 747 * the configuration information for the specified DMA Stream.
<> 149:156823d33999 748 * @param CallbackID: User Callback identifer
<> 149:156823d33999 749 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
<> 149:156823d33999 750 * @retval HAL status
<> 149:156823d33999 751 */
<> 149:156823d33999 752 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
<> 149:156823d33999 753 {
<> 149:156823d33999 754 HAL_StatusTypeDef status = HAL_OK;
<> 149:156823d33999 755
<> 149:156823d33999 756 /* Process locked */
<> 149:156823d33999 757 __HAL_LOCK(hdma);
<> 149:156823d33999 758
<> 149:156823d33999 759 if(HAL_DMA_STATE_READY == hdma->State)
<> 149:156823d33999 760 {
<> 149:156823d33999 761 switch (CallbackID)
<> 149:156823d33999 762 {
<> 149:156823d33999 763 case HAL_DMA_XFER_CPLT_CB_ID:
<> 149:156823d33999 764 hdma->XferCpltCallback = NULL;
<> 149:156823d33999 765 break;
<> 149:156823d33999 766
<> 149:156823d33999 767 case HAL_DMA_XFER_HALFCPLT_CB_ID:
<> 149:156823d33999 768 hdma->XferHalfCpltCallback = NULL;
<> 149:156823d33999 769 break;
<> 149:156823d33999 770
<> 149:156823d33999 771 case HAL_DMA_XFER_ERROR_CB_ID:
<> 149:156823d33999 772 hdma->XferErrorCallback = NULL;
<> 149:156823d33999 773 break;
<> 149:156823d33999 774
<> 149:156823d33999 775 case HAL_DMA_XFER_ABORT_CB_ID:
<> 149:156823d33999 776 hdma->XferAbortCallback = NULL;
<> 149:156823d33999 777 break;
<> 149:156823d33999 778
<> 149:156823d33999 779 case HAL_DMA_XFER_ALL_CB_ID:
<> 149:156823d33999 780 hdma->XferCpltCallback = NULL;
<> 149:156823d33999 781 hdma->XferHalfCpltCallback = NULL;
<> 149:156823d33999 782 hdma->XferErrorCallback = NULL;
<> 149:156823d33999 783 hdma->XferAbortCallback = NULL;
<> 149:156823d33999 784 break;
<> 149:156823d33999 785
<> 149:156823d33999 786 default:
<> 149:156823d33999 787 status = HAL_ERROR;
<> 149:156823d33999 788 break;
<> 149:156823d33999 789 }
<> 149:156823d33999 790 }
<> 149:156823d33999 791 else
<> 149:156823d33999 792 {
<> 149:156823d33999 793 status = HAL_ERROR;
<> 149:156823d33999 794 }
<> 149:156823d33999 795
<> 149:156823d33999 796 /* Release Lock */
<> 149:156823d33999 797 __HAL_UNLOCK(hdma);
<> 149:156823d33999 798
<> 149:156823d33999 799 return status;
<> 149:156823d33999 800 }
<> 149:156823d33999 801
<> 149:156823d33999 802 /**
<> 149:156823d33999 803 * @}
<> 149:156823d33999 804 */
<> 149:156823d33999 805
<> 149:156823d33999 806
<> 149:156823d33999 807
<> 149:156823d33999 808 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
<> 149:156823d33999 809 * @brief Peripheral State and Errors functions
<> 149:156823d33999 810 *
<> 149:156823d33999 811 @verbatim
<> 149:156823d33999 812 ===============================================================================
<> 149:156823d33999 813 ##### Peripheral State and Errors functions #####
<> 149:156823d33999 814 ===============================================================================
<> 149:156823d33999 815 [..]
<> 149:156823d33999 816 This subsection provides functions allowing to
<> 149:156823d33999 817 (+) Check the DMA state
<> 149:156823d33999 818 (+) Get error code
<> 149:156823d33999 819
<> 149:156823d33999 820 @endverbatim
<> 149:156823d33999 821 * @{
<> 149:156823d33999 822 */
<> 149:156823d33999 823
<> 149:156823d33999 824 /**
<> 149:156823d33999 825 * @brief Return the DMA hande state.
<> 149:156823d33999 826 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 827 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 828 * @retval HAL state
<> 149:156823d33999 829 */
<> 149:156823d33999 830 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 831 {
<> 149:156823d33999 832 /* Return DMA handle state */
<> 149:156823d33999 833 return hdma->State;
<> 149:156823d33999 834 }
<> 149:156823d33999 835
<> 149:156823d33999 836 /**
<> 149:156823d33999 837 * @brief Return the DMA error code.
<> 149:156823d33999 838 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 839 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 840 * @retval DMA Error Code
<> 149:156823d33999 841 */
<> 149:156823d33999 842 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
<> 149:156823d33999 843 {
<> 149:156823d33999 844 return hdma->ErrorCode;
<> 149:156823d33999 845 }
<> 149:156823d33999 846
<> 149:156823d33999 847 /**
<> 149:156823d33999 848 * @}
<> 149:156823d33999 849 */
<> 149:156823d33999 850
<> 149:156823d33999 851 /**
<> 149:156823d33999 852 * @}
<> 149:156823d33999 853 */
<> 149:156823d33999 854
<> 149:156823d33999 855 /** @addtogroup DMA_Private_Functions
<> 149:156823d33999 856 * @{
<> 149:156823d33999 857 */
<> 149:156823d33999 858
<> 149:156823d33999 859 /**
<> 149:156823d33999 860 * @brief Sets the DMA Transfer parameter.
<> 149:156823d33999 861 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 149:156823d33999 862 * the configuration information for the specified DMA Channel.
<> 149:156823d33999 863 * @param SrcAddress: The source memory Buffer address
<> 149:156823d33999 864 * @param DstAddress: The destination memory Buffer address
<> 149:156823d33999 865 * @param DataLength: The length of data to be transferred from source to destination
<> 149:156823d33999 866 * @retval HAL status
<> 149:156823d33999 867 */
<> 149:156823d33999 868 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
<> 149:156823d33999 869 {
<> 149:156823d33999 870 /* Clear all flags */
<> 149:156823d33999 871 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
<> 149:156823d33999 872
<> 149:156823d33999 873 /* Configure DMA Channel data length */
<> 149:156823d33999 874 hdma->Instance->CNDTR = DataLength;
<> 149:156823d33999 875
<> 149:156823d33999 876 /* Peripheral to Memory */
<> 149:156823d33999 877 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
<> 149:156823d33999 878 {
<> 149:156823d33999 879 /* Configure DMA Channel destination address */
<> 149:156823d33999 880 hdma->Instance->CPAR = DstAddress;
<> 149:156823d33999 881
<> 149:156823d33999 882 /* Configure DMA Channel source address */
<> 149:156823d33999 883 hdma->Instance->CMAR = SrcAddress;
<> 149:156823d33999 884 }
<> 149:156823d33999 885 /* Memory to Peripheral */
<> 149:156823d33999 886 else
<> 149:156823d33999 887 {
<> 149:156823d33999 888 /* Configure DMA Channel source address */
<> 149:156823d33999 889 hdma->Instance->CPAR = SrcAddress;
<> 149:156823d33999 890
<> 149:156823d33999 891 /* Configure DMA Channel destination address */
<> 149:156823d33999 892 hdma->Instance->CMAR = DstAddress;
<> 149:156823d33999 893 }
<> 149:156823d33999 894 }
<> 149:156823d33999 895
<> 149:156823d33999 896 /**
<> 149:156823d33999 897 * @}
<> 149:156823d33999 898 */
<> 149:156823d33999 899
<> 149:156823d33999 900 /**
<> 149:156823d33999 901 * @}
<> 149:156823d33999 902 */
<> 149:156823d33999 903
<> 149:156823d33999 904 #endif /* HAL_DMA_MODULE_ENABLED */
<> 149:156823d33999 905 /**
<> 149:156823d33999 906 * @}
<> 149:156823d33999 907 */
<> 149:156823d33999 908
<> 149:156823d33999 909 /**
<> 149:156823d33999 910 * @}
<> 149:156823d33999 911 */
<> 149:156823d33999 912
<> 149:156823d33999 913 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/