36372 mbed / Mbed 2 deprecated SP14P1_skeleton

skeleton for lab1

Dependencies:   AvailableMemory mbed-rtos mbed

Fork of helloaabbc by 32314 mbed

mbed-rtos/rtx/HAL_CM.c@1:55e99f6e2aa5, 2014-04-04 (annotated)

Committer:
mbed36372
Date:
Fri Apr 04 21:31:22 2014 +0000
Revision:
1:55e99f6e2aa5
Parent:
0:1c8f2727e9f5 
SP14_lab1

Who changed what in which revision?

UserRevisionLine numberNew contents of line
y7jin 0:1c8f2727e9f5 1 /*----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 2 * RL-ARM - RTX
y7jin 0:1c8f2727e9f5 3 *----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 4 * Name: HAL_CM.C
y7jin 0:1c8f2727e9f5 5 * Purpose: Hardware Abstraction Layer for Cortex-M
y7jin 0:1c8f2727e9f5 6 * Rev.: V4.60
y7jin 0:1c8f2727e9f5 7 *----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 8 *
y7jin 0:1c8f2727e9f5 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
y7jin 0:1c8f2727e9f5 10 * All rights reserved.
y7jin 0:1c8f2727e9f5 11 * Redistribution and use in source and binary forms, with or without
y7jin 0:1c8f2727e9f5 12 * modification, are permitted provided that the following conditions are met:
y7jin 0:1c8f2727e9f5 13 * - Redistributions of source code must retain the above copyright
y7jin 0:1c8f2727e9f5 14 * notice, this list of conditions and the following disclaimer.
y7jin 0:1c8f2727e9f5 15 * - Redistributions in binary form must reproduce the above copyright
y7jin 0:1c8f2727e9f5 16 * notice, this list of conditions and the following disclaimer in the
y7jin 0:1c8f2727e9f5 17 * documentation and/or other materials provided with the distribution.
y7jin 0:1c8f2727e9f5 18 * - Neither the name of ARM nor the names of its contributors may be used
y7jin 0:1c8f2727e9f5 19 * to endorse or promote products derived from this software without
y7jin 0:1c8f2727e9f5 20 * specific prior written permission.
y7jin 0:1c8f2727e9f5 21 *
y7jin 0:1c8f2727e9f5 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
y7jin 0:1c8f2727e9f5 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
y7jin 0:1c8f2727e9f5 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
y7jin 0:1c8f2727e9f5 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
y7jin 0:1c8f2727e9f5 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
y7jin 0:1c8f2727e9f5 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
y7jin 0:1c8f2727e9f5 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
y7jin 0:1c8f2727e9f5 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
y7jin 0:1c8f2727e9f5 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
y7jin 0:1c8f2727e9f5 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
y7jin 0:1c8f2727e9f5 32 * POSSIBILITY OF SUCH DAMAGE.
y7jin 0:1c8f2727e9f5 33 *---------------------------------------------------------------------------*/
y7jin 0:1c8f2727e9f5 34
y7jin 0:1c8f2727e9f5 35 #include "rt_TypeDef.h"
y7jin 0:1c8f2727e9f5 36 #include "RTX_Config.h"
y7jin 0:1c8f2727e9f5 37 #include "rt_HAL_CM.h"
y7jin 0:1c8f2727e9f5 38
y7jin 0:1c8f2727e9f5 39
y7jin 0:1c8f2727e9f5 40 /*----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 41 * Global Variables
y7jin 0:1c8f2727e9f5 42 *---------------------------------------------------------------------------*/
y7jin 0:1c8f2727e9f5 43
y7jin 0:1c8f2727e9f5 44 #ifdef DBG_MSG
y7jin 0:1c8f2727e9f5 45 BIT dbg_msg;
y7jin 0:1c8f2727e9f5 46 #endif
y7jin 0:1c8f2727e9f5 47
y7jin 0:1c8f2727e9f5 48 /*----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 49 * Functions
y7jin 0:1c8f2727e9f5 50 *---------------------------------------------------------------------------*/
y7jin 0:1c8f2727e9f5 51
y7jin 0:1c8f2727e9f5 52
y7jin 0:1c8f2727e9f5 53 /*--------------------------- rt_init_stack ---------------------------------*/
y7jin 0:1c8f2727e9f5 54
y7jin 0:1c8f2727e9f5 55 void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
y7jin 0:1c8f2727e9f5 56 /* Prepare TCB and saved context for a first time start of a task. */
y7jin 0:1c8f2727e9f5 57 U32 *stk,i,size;
y7jin 0:1c8f2727e9f5 58
y7jin 0:1c8f2727e9f5 59 /* Prepare a complete interrupt frame for first task start */
y7jin 0:1c8f2727e9f5 60 size = p_TCB->priv_stack >> 2;
y7jin 0:1c8f2727e9f5 61
y7jin 0:1c8f2727e9f5 62 /* Write to the top of stack. */
y7jin 0:1c8f2727e9f5 63 stk = &p_TCB->stack[size];
y7jin 0:1c8f2727e9f5 64
y7jin 0:1c8f2727e9f5 65 /* Auto correct to 8-byte ARM stack alignment. */
y7jin 0:1c8f2727e9f5 66 if ((U32)stk & 0x04) {
y7jin 0:1c8f2727e9f5 67 stk--;
y7jin 0:1c8f2727e9f5 68 }
y7jin 0:1c8f2727e9f5 69
y7jin 0:1c8f2727e9f5 70 stk -= 16;
y7jin 0:1c8f2727e9f5 71
y7jin 0:1c8f2727e9f5 72 /* Default xPSR and initial PC */
y7jin 0:1c8f2727e9f5 73 stk[15] = INITIAL_xPSR;
y7jin 0:1c8f2727e9f5 74 stk[14] = (U32)task_body;
y7jin 0:1c8f2727e9f5 75
y7jin 0:1c8f2727e9f5 76 /* Clear R4-R11,R0-R3,R12,LR registers. */
y7jin 0:1c8f2727e9f5 77 for (i = 0; i < 14; i++) {
y7jin 0:1c8f2727e9f5 78 stk[i] = 0;
y7jin 0:1c8f2727e9f5 79 }
y7jin 0:1c8f2727e9f5 80
y7jin 0:1c8f2727e9f5 81 /* Assign a void pointer to R0. */
y7jin 0:1c8f2727e9f5 82 stk[8] = (U32)p_TCB->msg;
y7jin 0:1c8f2727e9f5 83
y7jin 0:1c8f2727e9f5 84 /* Initial Task stack pointer. */
y7jin 0:1c8f2727e9f5 85 p_TCB->tsk_stack = (U32)stk;
y7jin 0:1c8f2727e9f5 86
y7jin 0:1c8f2727e9f5 87 /* Task entry point. */
y7jin 0:1c8f2727e9f5 88 p_TCB->ptask = task_body;
y7jin 0:1c8f2727e9f5 89
y7jin 0:1c8f2727e9f5 90 /* Set a magic word for checking of stack overflow.
y7jin 0:1c8f2727e9f5 91 For the main thread (ID: 0x01) the stack is in a memory area shared with the
y7jin 0:1c8f2727e9f5 92 heap, therefore the last word of the stack is a moving target.
y7jin 0:1c8f2727e9f5 93 We want to do stack/heap collision detection instead.
y7jin 0:1c8f2727e9f5 94 */
y7jin 0:1c8f2727e9f5 95 if (p_TCB->task_id != 0x01)
y7jin 0:1c8f2727e9f5 96 p_TCB->stack[0] = MAGIC_WORD;
y7jin 0:1c8f2727e9f5 97 }
y7jin 0:1c8f2727e9f5 98
y7jin 0:1c8f2727e9f5 99
y7jin 0:1c8f2727e9f5 100 /*--------------------------- rt_ret_val ----------------------------------*/
y7jin 0:1c8f2727e9f5 101
y7jin 0:1c8f2727e9f5 102 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
y7jin 0:1c8f2727e9f5 103 /* Get pointer to task return value registers (R0..R3) in Stack */
y7jin 0:1c8f2727e9f5 104 #if (__TARGET_FPU_VFP)
y7jin 0:1c8f2727e9f5 105 if (p_TCB->stack_frame) {
y7jin 0:1c8f2727e9f5 106 /* Extended Stack Frame: R4-R11,S16-S31,R0-R3,R12,LR,PC,xPSR,S0-S15,FPSCR */
y7jin 0:1c8f2727e9f5 107 return (U32 *)(p_TCB->tsk_stack + 8*4 + 16*4);
y7jin 0:1c8f2727e9f5 108 } else {
y7jin 0:1c8f2727e9f5 109 /* Basic Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
y7jin 0:1c8f2727e9f5 110 return (U32 *)(p_TCB->tsk_stack + 8*4);
y7jin 0:1c8f2727e9f5 111 }
y7jin 0:1c8f2727e9f5 112 #else
y7jin 0:1c8f2727e9f5 113 /* Stack Frame: R4-R11,R0-R3,R12,LR,PC,xPSR */
y7jin 0:1c8f2727e9f5 114 return (U32 *)(p_TCB->tsk_stack + 8*4);
y7jin 0:1c8f2727e9f5 115 #endif
y7jin 0:1c8f2727e9f5 116 }
y7jin 0:1c8f2727e9f5 117
y7jin 0:1c8f2727e9f5 118 void rt_ret_val (P_TCB p_TCB, U32 v0) {
y7jin 0:1c8f2727e9f5 119 U32 *ret;
y7jin 0:1c8f2727e9f5 120
y7jin 0:1c8f2727e9f5 121 ret = rt_ret_regs(p_TCB);
y7jin 0:1c8f2727e9f5 122 ret[0] = v0;
y7jin 0:1c8f2727e9f5 123 }
y7jin 0:1c8f2727e9f5 124
y7jin 0:1c8f2727e9f5 125 void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
y7jin 0:1c8f2727e9f5 126 U32 *ret;
y7jin 0:1c8f2727e9f5 127
y7jin 0:1c8f2727e9f5 128 ret = rt_ret_regs(p_TCB);
y7jin 0:1c8f2727e9f5 129 ret[0] = v0;
y7jin 0:1c8f2727e9f5 130 ret[1] = v1;
y7jin 0:1c8f2727e9f5 131 }
y7jin 0:1c8f2727e9f5 132
y7jin 0:1c8f2727e9f5 133
y7jin 0:1c8f2727e9f5 134 /*--------------------------- dbg_init --------------------------------------*/
y7jin 0:1c8f2727e9f5 135
y7jin 0:1c8f2727e9f5 136 #ifdef DBG_MSG
y7jin 0:1c8f2727e9f5 137 void dbg_init (void) {
y7jin 0:1c8f2727e9f5 138 if ((DEMCR & DEMCR_TRCENA) &&
y7jin 0:1c8f2727e9f5 139 (ITM_CONTROL & ITM_ITMENA) &&
y7jin 0:1c8f2727e9f5 140 (ITM_ENABLE & (1UL << 31))) {
y7jin 0:1c8f2727e9f5 141 dbg_msg = __TRUE;
y7jin 0:1c8f2727e9f5 142 }
y7jin 0:1c8f2727e9f5 143 }
y7jin 0:1c8f2727e9f5 144 #endif
y7jin 0:1c8f2727e9f5 145
y7jin 0:1c8f2727e9f5 146 /*--------------------------- dbg_task_notify -------------------------------*/
y7jin 0:1c8f2727e9f5 147
y7jin 0:1c8f2727e9f5 148 #ifdef DBG_MSG
y7jin 0:1c8f2727e9f5 149 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
y7jin 0:1c8f2727e9f5 150 while (ITM_PORT31_U32 == 0);
y7jin 0:1c8f2727e9f5 151 ITM_PORT31_U32 = (U32)p_tcb->ptask;
y7jin 0:1c8f2727e9f5 152 while (ITM_PORT31_U32 == 0);
y7jin 0:1c8f2727e9f5 153 ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
y7jin 0:1c8f2727e9f5 154 }
y7jin 0:1c8f2727e9f5 155 #endif
y7jin 0:1c8f2727e9f5 156
y7jin 0:1c8f2727e9f5 157 /*--------------------------- dbg_task_switch -------------------------------*/
y7jin 0:1c8f2727e9f5 158
y7jin 0:1c8f2727e9f5 159 #ifdef DBG_MSG
y7jin 0:1c8f2727e9f5 160 void dbg_task_switch (U32 task_id) {
y7jin 0:1c8f2727e9f5 161 while (ITM_PORT31_U32 == 0);
y7jin 0:1c8f2727e9f5 162 ITM_PORT31_U8 = task_id;
y7jin 0:1c8f2727e9f5 163 }
y7jin 0:1c8f2727e9f5 164 #endif
y7jin 0:1c8f2727e9f5 165
y7jin 0:1c8f2727e9f5 166
y7jin 0:1c8f2727e9f5 167 /*----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 168 * end of file
y7jin 0:1c8f2727e9f5 169 *---------------------------------------------------------------------------*/
y7jin 0:1c8f2727e9f5 170