36372 mbed / Mbed 2 deprecated SP14P1_skeleton

skeleton for lab1

Dependencies:   AvailableMemory mbed-rtos mbed

Fork of helloaabbc by 32314 mbed

mbed-rtos/rtx/rt_HAL_CM.h@0:1c8f2727e9f5, 2014-04-03 (annotated)

Committer:
y7jin
Date:
Thu Apr 03 22:56:32 2014 +0000
Revision:
0:1c8f2727e9f5
hello

Who changed what in which revision?

UserRevisionLine numberNew contents of line
y7jin 0:1c8f2727e9f5 1 /*----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 2 * RL-ARM - RTX
y7jin 0:1c8f2727e9f5 3 *----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 4 * Name: RT_HAL_CM.H
y7jin 0:1c8f2727e9f5 5 * Purpose: Hardware Abstraction Layer for Cortex-M definitions
y7jin 0:1c8f2727e9f5 6 * Rev.: V4.60
y7jin 0:1c8f2727e9f5 7 *----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 8 *
y7jin 0:1c8f2727e9f5 9 * Copyright (c) 1999-2009 KEIL, 2009-2012 ARM Germany GmbH
y7jin 0:1c8f2727e9f5 10 * All rights reserved.
y7jin 0:1c8f2727e9f5 11 * Redistribution and use in source and binary forms, with or without
y7jin 0:1c8f2727e9f5 12 * modification, are permitted provided that the following conditions are met:
y7jin 0:1c8f2727e9f5 13 * - Redistributions of source code must retain the above copyright
y7jin 0:1c8f2727e9f5 14 * notice, this list of conditions and the following disclaimer.
y7jin 0:1c8f2727e9f5 15 * - Redistributions in binary form must reproduce the above copyright
y7jin 0:1c8f2727e9f5 16 * notice, this list of conditions and the following disclaimer in the
y7jin 0:1c8f2727e9f5 17 * documentation and/or other materials provided with the distribution.
y7jin 0:1c8f2727e9f5 18 * - Neither the name of ARM nor the names of its contributors may be used
y7jin 0:1c8f2727e9f5 19 * to endorse or promote products derived from this software without
y7jin 0:1c8f2727e9f5 20 * specific prior written permission.
y7jin 0:1c8f2727e9f5 21 *
y7jin 0:1c8f2727e9f5 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
y7jin 0:1c8f2727e9f5 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
y7jin 0:1c8f2727e9f5 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
y7jin 0:1c8f2727e9f5 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
y7jin 0:1c8f2727e9f5 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
y7jin 0:1c8f2727e9f5 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
y7jin 0:1c8f2727e9f5 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
y7jin 0:1c8f2727e9f5 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
y7jin 0:1c8f2727e9f5 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
y7jin 0:1c8f2727e9f5 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
y7jin 0:1c8f2727e9f5 32 * POSSIBILITY OF SUCH DAMAGE.
y7jin 0:1c8f2727e9f5 33 *---------------------------------------------------------------------------*/
y7jin 0:1c8f2727e9f5 34
y7jin 0:1c8f2727e9f5 35 /* Definitions */
y7jin 0:1c8f2727e9f5 36 #define INITIAL_xPSR 0x01000000
y7jin 0:1c8f2727e9f5 37 #define DEMCR_TRCENA 0x01000000
y7jin 0:1c8f2727e9f5 38 #define ITM_ITMENA 0x00000001
y7jin 0:1c8f2727e9f5 39 #define MAGIC_WORD 0xE25A2EA5
y7jin 0:1c8f2727e9f5 40
y7jin 0:1c8f2727e9f5 41 #if defined (__CC_ARM) /* ARM Compiler */
y7jin 0:1c8f2727e9f5 42
y7jin 0:1c8f2727e9f5 43 #if ((__TARGET_ARCH_7_M || __TARGET_ARCH_7E_M) && !NO_EXCLUSIVE_ACCESS)
y7jin 0:1c8f2727e9f5 44 #define __USE_EXCLUSIVE_ACCESS
y7jin 0:1c8f2727e9f5 45 #else
y7jin 0:1c8f2727e9f5 46 #undef __USE_EXCLUSIVE_ACCESS
y7jin 0:1c8f2727e9f5 47 #endif
y7jin 0:1c8f2727e9f5 48
y7jin 0:1c8f2727e9f5 49 #elif defined (__GNUC__) /* GNU Compiler */
y7jin 0:1c8f2727e9f5 50
y7jin 0:1c8f2727e9f5 51 #undef __USE_EXCLUSIVE_ACCESS
y7jin 0:1c8f2727e9f5 52
y7jin 0:1c8f2727e9f5 53 #if defined (__CORTEX_M0)
y7jin 0:1c8f2727e9f5 54 #define __TARGET_ARCH_6S_M 1
y7jin 0:1c8f2727e9f5 55 #else
y7jin 0:1c8f2727e9f5 56 #define __TARGET_ARCH_6S_M 0
y7jin 0:1c8f2727e9f5 57 #endif
y7jin 0:1c8f2727e9f5 58
y7jin 0:1c8f2727e9f5 59 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
y7jin 0:1c8f2727e9f5 60 #define __TARGET_FPU_VFP 1
y7jin 0:1c8f2727e9f5 61 #else
y7jin 0:1c8f2727e9f5 62 #define __TARGET_FPU_VFP 0
y7jin 0:1c8f2727e9f5 63 #endif
y7jin 0:1c8f2727e9f5 64
y7jin 0:1c8f2727e9f5 65 #define __inline inline
y7jin 0:1c8f2727e9f5 66 #define __weak __attribute__((weak))
y7jin 0:1c8f2727e9f5 67
y7jin 0:1c8f2727e9f5 68 #ifndef __CMSIS_GENERIC
y7jin 0:1c8f2727e9f5 69
y7jin 0:1c8f2727e9f5 70 __attribute__((always_inline)) static inline void __enable_irq(void)
y7jin 0:1c8f2727e9f5 71 {
y7jin 0:1c8f2727e9f5 72 __asm volatile ("cpsie i");
y7jin 0:1c8f2727e9f5 73 }
y7jin 0:1c8f2727e9f5 74
y7jin 0:1c8f2727e9f5 75 __attribute__((always_inline)) static inline U32 __disable_irq(void)
y7jin 0:1c8f2727e9f5 76 {
y7jin 0:1c8f2727e9f5 77 U32 result;
y7jin 0:1c8f2727e9f5 78
y7jin 0:1c8f2727e9f5 79 __asm volatile ("mrs %0, primask" : "=r" (result));
y7jin 0:1c8f2727e9f5 80 __asm volatile ("cpsid i");
y7jin 0:1c8f2727e9f5 81 return(result & 1);
y7jin 0:1c8f2727e9f5 82 }
y7jin 0:1c8f2727e9f5 83
y7jin 0:1c8f2727e9f5 84 #endif
y7jin 0:1c8f2727e9f5 85
y7jin 0:1c8f2727e9f5 86 __attribute__(( always_inline)) static inline U8 __clz(U32 value)
y7jin 0:1c8f2727e9f5 87 {
y7jin 0:1c8f2727e9f5 88 U8 result;
y7jin 0:1c8f2727e9f5 89
y7jin 0:1c8f2727e9f5 90 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
y7jin 0:1c8f2727e9f5 91 return(result);
y7jin 0:1c8f2727e9f5 92 }
y7jin 0:1c8f2727e9f5 93
y7jin 0:1c8f2727e9f5 94 #elif defined (__ICCARM__) /* IAR Compiler */
y7jin 0:1c8f2727e9f5 95
y7jin 0:1c8f2727e9f5 96 #undef __USE_EXCLUSIVE_ACCESS
y7jin 0:1c8f2727e9f5 97
y7jin 0:1c8f2727e9f5 98 #if (__CORE__ == __ARM6M__)
y7jin 0:1c8f2727e9f5 99 #define __TARGET_ARCH_6S_M 1
y7jin 0:1c8f2727e9f5 100 #else
y7jin 0:1c8f2727e9f5 101 #define __TARGET_ARCH_6S_M 0
y7jin 0:1c8f2727e9f5 102 #endif
y7jin 0:1c8f2727e9f5 103
y7jin 0:1c8f2727e9f5 104 #if defined __ARMVFP__
y7jin 0:1c8f2727e9f5 105 #define __TARGET_FPU_VFP 1
y7jin 0:1c8f2727e9f5 106 #else
y7jin 0:1c8f2727e9f5 107 #define __TARGET_FPU_VFP 0
y7jin 0:1c8f2727e9f5 108 #endif
y7jin 0:1c8f2727e9f5 109
y7jin 0:1c8f2727e9f5 110 #define __inline inline
y7jin 0:1c8f2727e9f5 111
y7jin 0:1c8f2727e9f5 112 #ifndef __CMSIS_GENERIC
y7jin 0:1c8f2727e9f5 113
y7jin 0:1c8f2727e9f5 114 static inline void __enable_irq(void)
y7jin 0:1c8f2727e9f5 115 {
y7jin 0:1c8f2727e9f5 116 __asm volatile ("cpsie i");
y7jin 0:1c8f2727e9f5 117 }
y7jin 0:1c8f2727e9f5 118
y7jin 0:1c8f2727e9f5 119 static inline U32 __disable_irq(void)
y7jin 0:1c8f2727e9f5 120 {
y7jin 0:1c8f2727e9f5 121 U32 result;
y7jin 0:1c8f2727e9f5 122
y7jin 0:1c8f2727e9f5 123 __asm volatile ("mrs %0, primask" : "=r" (result));
y7jin 0:1c8f2727e9f5 124 __asm volatile ("cpsid i");
y7jin 0:1c8f2727e9f5 125 return(result & 1);
y7jin 0:1c8f2727e9f5 126 }
y7jin 0:1c8f2727e9f5 127
y7jin 0:1c8f2727e9f5 128 #endif
y7jin 0:1c8f2727e9f5 129
y7jin 0:1c8f2727e9f5 130 static inline U8 __clz(U32 value)
y7jin 0:1c8f2727e9f5 131 {
y7jin 0:1c8f2727e9f5 132 U8 result;
y7jin 0:1c8f2727e9f5 133
y7jin 0:1c8f2727e9f5 134 __asm volatile ("clz %0, %1" : "=r" (result) : "r" (value));
y7jin 0:1c8f2727e9f5 135 return(result);
y7jin 0:1c8f2727e9f5 136 }
y7jin 0:1c8f2727e9f5 137
y7jin 0:1c8f2727e9f5 138 #endif
y7jin 0:1c8f2727e9f5 139
y7jin 0:1c8f2727e9f5 140 /* NVIC registers */
y7jin 0:1c8f2727e9f5 141 #define NVIC_ST_CTRL (*((volatile U32 *)0xE000E010))
y7jin 0:1c8f2727e9f5 142 #define NVIC_ST_RELOAD (*((volatile U32 *)0xE000E014))
y7jin 0:1c8f2727e9f5 143 #define NVIC_ST_CURRENT (*((volatile U32 *)0xE000E018))
y7jin 0:1c8f2727e9f5 144 #define NVIC_ISER ((volatile U32 *)0xE000E100)
y7jin 0:1c8f2727e9f5 145 #define NVIC_ICER ((volatile U32 *)0xE000E180)
y7jin 0:1c8f2727e9f5 146 #if (__TARGET_ARCH_6S_M)
y7jin 0:1c8f2727e9f5 147 #define NVIC_IP ((volatile U32 *)0xE000E400)
y7jin 0:1c8f2727e9f5 148 #else
y7jin 0:1c8f2727e9f5 149 #define NVIC_IP ((volatile U8 *)0xE000E400)
y7jin 0:1c8f2727e9f5 150 #endif
y7jin 0:1c8f2727e9f5 151 #define NVIC_INT_CTRL (*((volatile U32 *)0xE000ED04))
y7jin 0:1c8f2727e9f5 152 #define NVIC_AIR_CTRL (*((volatile U32 *)0xE000ED0C))
y7jin 0:1c8f2727e9f5 153 #define NVIC_SYS_PRI2 (*((volatile U32 *)0xE000ED1C))
y7jin 0:1c8f2727e9f5 154 #define NVIC_SYS_PRI3 (*((volatile U32 *)0xE000ED20))
y7jin 0:1c8f2727e9f5 155
y7jin 0:1c8f2727e9f5 156 #define OS_PEND_IRQ() NVIC_INT_CTRL = (1<<28)
y7jin 0:1c8f2727e9f5 157 #define OS_PENDING ((NVIC_INT_CTRL >> 26) & (1<<2 | 1))
y7jin 0:1c8f2727e9f5 158 #define OS_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_PENDING) << 25
y7jin 0:1c8f2727e9f5 159 #define OS_PEND(fl,p) NVIC_INT_CTRL = (fl | p<<2) << 26
y7jin 0:1c8f2727e9f5 160 #define OS_LOCK() NVIC_ST_CTRL = 0x0005
y7jin 0:1c8f2727e9f5 161 #define OS_UNLOCK() NVIC_ST_CTRL = 0x0007
y7jin 0:1c8f2727e9f5 162
y7jin 0:1c8f2727e9f5 163 #define OS_X_PENDING ((NVIC_INT_CTRL >> 28) & 1)
y7jin 0:1c8f2727e9f5 164 #define OS_X_UNPEND(fl) NVIC_INT_CTRL = (*fl = OS_X_PENDING) << 27
y7jin 0:1c8f2727e9f5 165 #define OS_X_PEND(fl,p) NVIC_INT_CTRL = (fl | p) << 28
y7jin 0:1c8f2727e9f5 166 #if (__TARGET_ARCH_6S_M)
y7jin 0:1c8f2727e9f5 167 #define OS_X_INIT(n) NVIC_IP[n>>2] |= 0xFF << (8*(n & 0x03)); \
y7jin 0:1c8f2727e9f5 168 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
y7jin 0:1c8f2727e9f5 169 #else
y7jin 0:1c8f2727e9f5 170 #define OS_X_INIT(n) NVIC_IP[n] = 0xFF; \
y7jin 0:1c8f2727e9f5 171 NVIC_ISER[n>>5] = 1 << (n & 0x1F)
y7jin 0:1c8f2727e9f5 172 #endif
y7jin 0:1c8f2727e9f5 173 #define OS_X_LOCK(n) NVIC_ICER[n>>5] = 1 << (n & 0x1F)
y7jin 0:1c8f2727e9f5 174 #define OS_X_UNLOCK(n) NVIC_ISER[n>>5] = 1 << (n & 0x1F)
y7jin 0:1c8f2727e9f5 175
y7jin 0:1c8f2727e9f5 176 /* Core Debug registers */
y7jin 0:1c8f2727e9f5 177 #define DEMCR (*((volatile U32 *)0xE000EDFC))
y7jin 0:1c8f2727e9f5 178
y7jin 0:1c8f2727e9f5 179 /* ITM registers */
y7jin 0:1c8f2727e9f5 180 #define ITM_CONTROL (*((volatile U32 *)0xE0000E80))
y7jin 0:1c8f2727e9f5 181 #define ITM_ENABLE (*((volatile U32 *)0xE0000E00))
y7jin 0:1c8f2727e9f5 182 #define ITM_PORT30_U32 (*((volatile U32 *)0xE0000078))
y7jin 0:1c8f2727e9f5 183 #define ITM_PORT31_U32 (*((volatile U32 *)0xE000007C))
y7jin 0:1c8f2727e9f5 184 #define ITM_PORT31_U16 (*((volatile U16 *)0xE000007C))
y7jin 0:1c8f2727e9f5 185 #define ITM_PORT31_U8 (*((volatile U8 *)0xE000007C))
y7jin 0:1c8f2727e9f5 186
y7jin 0:1c8f2727e9f5 187 /* Variables */
y7jin 0:1c8f2727e9f5 188 extern BIT dbg_msg;
y7jin 0:1c8f2727e9f5 189
y7jin 0:1c8f2727e9f5 190 /* Functions */
y7jin 0:1c8f2727e9f5 191 #ifdef __USE_EXCLUSIVE_ACCESS
y7jin 0:1c8f2727e9f5 192 #define rt_inc(p) while(__strex((__ldrex(p)+1),p))
y7jin 0:1c8f2727e9f5 193 #define rt_dec(p) while(__strex((__ldrex(p)-1),p))
y7jin 0:1c8f2727e9f5 194 #else
y7jin 0:1c8f2727e9f5 195 #define rt_inc(p) __disable_irq();(*p)++;__enable_irq();
y7jin 0:1c8f2727e9f5 196 #define rt_dec(p) __disable_irq();(*p)--;__enable_irq();
y7jin 0:1c8f2727e9f5 197 #endif
y7jin 0:1c8f2727e9f5 198
y7jin 0:1c8f2727e9f5 199 __inline static U32 rt_inc_qi (U32 size, U8 *count, U8 *first) {
y7jin 0:1c8f2727e9f5 200 U32 cnt,c2;
y7jin 0:1c8f2727e9f5 201 #ifdef __USE_EXCLUSIVE_ACCESS
y7jin 0:1c8f2727e9f5 202 do {
y7jin 0:1c8f2727e9f5 203 if ((cnt = __ldrex(count)) == size) {
y7jin 0:1c8f2727e9f5 204 __clrex();
y7jin 0:1c8f2727e9f5 205 return (cnt); }
y7jin 0:1c8f2727e9f5 206 } while (__strex(cnt+1, count));
y7jin 0:1c8f2727e9f5 207 do {
y7jin 0:1c8f2727e9f5 208 c2 = (cnt = __ldrex(first)) + 1;
y7jin 0:1c8f2727e9f5 209 if (c2 == size) c2 = 0;
y7jin 0:1c8f2727e9f5 210 } while (__strex(c2, first));
y7jin 0:1c8f2727e9f5 211 #else
y7jin 0:1c8f2727e9f5 212 __disable_irq();
y7jin 0:1c8f2727e9f5 213 if ((cnt = *count) < size) {
y7jin 0:1c8f2727e9f5 214 *count = cnt+1;
y7jin 0:1c8f2727e9f5 215 c2 = (cnt = *first) + 1;
y7jin 0:1c8f2727e9f5 216 if (c2 == size) c2 = 0;
y7jin 0:1c8f2727e9f5 217 *first = c2;
y7jin 0:1c8f2727e9f5 218 }
y7jin 0:1c8f2727e9f5 219 __enable_irq ();
y7jin 0:1c8f2727e9f5 220 #endif
y7jin 0:1c8f2727e9f5 221 return (cnt);
y7jin 0:1c8f2727e9f5 222 }
y7jin 0:1c8f2727e9f5 223
y7jin 0:1c8f2727e9f5 224 __inline static void rt_systick_init (void) {
y7jin 0:1c8f2727e9f5 225 NVIC_ST_RELOAD = os_trv;
y7jin 0:1c8f2727e9f5 226 NVIC_ST_CURRENT = 0;
y7jin 0:1c8f2727e9f5 227 NVIC_ST_CTRL = 0x0007;
y7jin 0:1c8f2727e9f5 228 NVIC_SYS_PRI3 |= 0xFF000000;
y7jin 0:1c8f2727e9f5 229 }
y7jin 0:1c8f2727e9f5 230
y7jin 0:1c8f2727e9f5 231 __inline static void rt_svc_init (void) {
y7jin 0:1c8f2727e9f5 232 #if !(__TARGET_ARCH_6S_M)
y7jin 0:1c8f2727e9f5 233 int sh,prigroup;
y7jin 0:1c8f2727e9f5 234 #endif
y7jin 0:1c8f2727e9f5 235 NVIC_SYS_PRI3 |= 0x00FF0000;
y7jin 0:1c8f2727e9f5 236 #if (__TARGET_ARCH_6S_M)
y7jin 0:1c8f2727e9f5 237 NVIC_SYS_PRI2 |= (NVIC_SYS_PRI3<<(8+1)) & 0xFC000000;
y7jin 0:1c8f2727e9f5 238 #else
y7jin 0:1c8f2727e9f5 239 sh = 8 - __clz (~((NVIC_SYS_PRI3 << 8) & 0xFF000000));
y7jin 0:1c8f2727e9f5 240 prigroup = ((NVIC_AIR_CTRL >> 8) & 0x07);
y7jin 0:1c8f2727e9f5 241 if (prigroup >= sh) {
y7jin 0:1c8f2727e9f5 242 sh = prigroup + 1;
y7jin 0:1c8f2727e9f5 243 }
y7jin 0:1c8f2727e9f5 244 NVIC_SYS_PRI2 = ((0xFEFFFFFF << sh) & 0xFF000000) | (NVIC_SYS_PRI2 & 0x00FFFFFF);
y7jin 0:1c8f2727e9f5 245 #endif
y7jin 0:1c8f2727e9f5 246 }
y7jin 0:1c8f2727e9f5 247
y7jin 0:1c8f2727e9f5 248 extern void rt_set_PSP (U32 stack);
y7jin 0:1c8f2727e9f5 249 extern U32 rt_get_PSP (void);
y7jin 0:1c8f2727e9f5 250 extern void os_set_env (void);
y7jin 0:1c8f2727e9f5 251 extern void *_alloc_box (void *box_mem);
y7jin 0:1c8f2727e9f5 252 extern int _free_box (void *box_mem, void *box);
y7jin 0:1c8f2727e9f5 253
y7jin 0:1c8f2727e9f5 254 extern void rt_init_stack (P_TCB p_TCB, FUNCP task_body);
y7jin 0:1c8f2727e9f5 255 extern void rt_ret_val (P_TCB p_TCB, U32 v0);
y7jin 0:1c8f2727e9f5 256 extern void rt_ret_val2 (P_TCB p_TCB, U32 v0, U32 v1);
y7jin 0:1c8f2727e9f5 257
y7jin 0:1c8f2727e9f5 258 extern void dbg_init (void);
y7jin 0:1c8f2727e9f5 259 extern void dbg_task_notify (P_TCB p_tcb, BOOL create);
y7jin 0:1c8f2727e9f5 260 extern void dbg_task_switch (U32 task_id);
y7jin 0:1c8f2727e9f5 261
y7jin 0:1c8f2727e9f5 262 #ifdef DBG_MSG
y7jin 0:1c8f2727e9f5 263 #define DBG_INIT() dbg_init()
y7jin 0:1c8f2727e9f5 264 #define DBG_TASK_NOTIFY(p_tcb,create) if (dbg_msg) dbg_task_notify(p_tcb,create)
y7jin 0:1c8f2727e9f5 265 #define DBG_TASK_SWITCH(task_id) if (dbg_msg && (os_tsk.new_tsk != os_tsk.run)) \
y7jin 0:1c8f2727e9f5 266 dbg_task_switch(task_id)
y7jin 0:1c8f2727e9f5 267 #else
y7jin 0:1c8f2727e9f5 268 #define DBG_INIT()
y7jin 0:1c8f2727e9f5 269 #define DBG_TASK_NOTIFY(p_tcb,create)
y7jin 0:1c8f2727e9f5 270 #define DBG_TASK_SWITCH(task_id)
y7jin 0:1c8f2727e9f5 271 #endif
y7jin 0:1c8f2727e9f5 272
y7jin 0:1c8f2727e9f5 273 /*----------------------------------------------------------------------------
y7jin 0:1c8f2727e9f5 274 * end of file
y7jin 0:1c8f2727e9f5 275 *---------------------------------------------------------------------------*/
y7jin 0:1c8f2727e9f5 276