Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M451/dma_api.c@177:619788de047e, 2017-11-07 (annotated)

Committer:
maxxir
Date:
Tue Nov 07 16:46:29 2017 +0000
Revision:
177:619788de047e
Parent:
165:e614a9f1c9e2 
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..;  Used direct RTC register manipulation for STM32F1xx;  rtc_read() && rtc_write()  (native rtc_init() - works good);  also added stub for non-working on STM32F1xx rtc_read_subseconds().

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "dma_api.h"
<> 149:156823d33999 18 #include "string.h"
<> 149:156823d33999 19 #include "cmsis.h"
<> 149:156823d33999 20 #include "mbed_assert.h"
<> 149:156823d33999 21 #include "PeripheralNames.h"
<> 149:156823d33999 22 #include "nu_modutil.h"
<> 149:156823d33999 23 #include "nu_bitutil.h"
<> 149:156823d33999 24 #include "dma.h"
<> 149:156823d33999 25
AnnaBridge 165:e614a9f1c9e2 26 #define NU_PDMA_CH_MAX PDMA_CH_MAX /* Specify maximum channels of PDMA */
AnnaBridge 165:e614a9f1c9e2 27 #define NU_PDMA_CH_Pos 0 /* Specify first channel number of PDMA */
AnnaBridge 165:e614a9f1c9e2 28 #define NU_PDMA_CH_Msk (((1 << NU_PDMA_CH_MAX) - 1) << NU_PDMA_CH_Pos)
AnnaBridge 165:e614a9f1c9e2 29
<> 149:156823d33999 30 struct nu_dma_chn_s {
<> 149:156823d33999 31 void (*handler)(uint32_t, uint32_t);
<> 149:156823d33999 32 uint32_t id;
<> 149:156823d33999 33 uint32_t event;
<> 149:156823d33999 34 };
<> 149:156823d33999 35
<> 149:156823d33999 36 static int dma_inited = 0;
<> 149:156823d33999 37 static uint32_t dma_chn_mask = 0;
AnnaBridge 165:e614a9f1c9e2 38 static struct nu_dma_chn_s dma_chn_arr[NU_PDMA_CH_MAX];
<> 149:156823d33999 39
<> 149:156823d33999 40 static void pdma_vec(void);
<> 149:156823d33999 41 static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec};
<> 149:156823d33999 42
<> 149:156823d33999 43
<> 149:156823d33999 44 void dma_init(void)
<> 149:156823d33999 45 {
<> 149:156823d33999 46 if (dma_inited) {
<> 149:156823d33999 47 return;
<> 149:156823d33999 48 }
<> 149:156823d33999 49
<> 149:156823d33999 50 dma_inited = 1;
AnnaBridge 165:e614a9f1c9e2 51 dma_chn_mask = ~NU_PDMA_CH_Msk;
<> 149:156823d33999 52 memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
<> 149:156823d33999 53
<> 149:156823d33999 54 // Reset this module
<> 149:156823d33999 55 SYS_ResetModule(dma_modinit.rsetidx);
<> 149:156823d33999 56
<> 149:156823d33999 57 // Enable IP clock
<> 149:156823d33999 58 CLK_EnableModuleClock(dma_modinit.clkidx);
<> 149:156823d33999 59
<> 149:156823d33999 60 PDMA_Open(0);
<> 149:156823d33999 61
<> 149:156823d33999 62 NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
<> 149:156823d33999 63 NVIC_EnableIRQ(dma_modinit.irq_n);
<> 149:156823d33999 64 }
<> 149:156823d33999 65
<> 149:156823d33999 66 int dma_channel_allocate(uint32_t capabilities)
<> 149:156823d33999 67 {
<> 149:156823d33999 68 if (! dma_inited) {
<> 149:156823d33999 69 dma_init();
<> 149:156823d33999 70 }
<> 149:156823d33999 71
<> 149:156823d33999 72 int i = nu_cto(dma_chn_mask);
<> 149:156823d33999 73 if (i != 32) {
<> 149:156823d33999 74 dma_chn_mask |= 1 << i;
AnnaBridge 165:e614a9f1c9e2 75 memset(dma_chn_arr + i - NU_PDMA_CH_Pos, 0x00, sizeof (struct nu_dma_chn_s));
<> 149:156823d33999 76 return i;
<> 149:156823d33999 77 }
<> 149:156823d33999 78
<> 149:156823d33999 79 // No channel available
<> 149:156823d33999 80 return DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 81 }
<> 149:156823d33999 82
<> 149:156823d33999 83 int dma_channel_free(int channelid)
<> 149:156823d33999 84 {
<> 149:156823d33999 85 if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 86 dma_chn_mask &= ~(1 << channelid);
<> 149:156823d33999 87 }
<> 149:156823d33999 88
<> 149:156823d33999 89 return 0;
<> 149:156823d33999 90 }
<> 149:156823d33999 91
<> 149:156823d33999 92 void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
<> 149:156823d33999 93 {
<> 149:156823d33999 94 MBED_ASSERT(dma_chn_mask & (1 << channelid));
<> 149:156823d33999 95
AnnaBridge 165:e614a9f1c9e2 96 dma_chn_arr[channelid - NU_PDMA_CH_Pos].handler = (void (*)(uint32_t, uint32_t)) handler;
AnnaBridge 165:e614a9f1c9e2 97 dma_chn_arr[channelid - NU_PDMA_CH_Pos].id = id;
AnnaBridge 165:e614a9f1c9e2 98 dma_chn_arr[channelid - NU_PDMA_CH_Pos].event = event;
<> 149:156823d33999 99
<> 149:156823d33999 100 // Set interrupt vector if someone has removed it.
<> 149:156823d33999 101 NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
<> 149:156823d33999 102 NVIC_EnableIRQ(dma_modinit.irq_n);
<> 149:156823d33999 103 }
<> 149:156823d33999 104
<> 161:2cc1468da177 105 PDMA_T *dma_modbase(void)
<> 161:2cc1468da177 106 {
<> 161:2cc1468da177 107 return (PDMA_T *) NU_MODBASE(dma_modinit.modname);
<> 161:2cc1468da177 108 }
<> 161:2cc1468da177 109
<> 149:156823d33999 110 static void pdma_vec(void)
<> 149:156823d33999 111 {
<> 149:156823d33999 112 uint32_t intsts = PDMA_GET_INT_STATUS();
<> 149:156823d33999 113
<> 149:156823d33999 114 // Abort
<> 149:156823d33999 115 if (intsts & PDMA_INTSTS_ABTIF_Msk) {
<> 149:156823d33999 116 uint32_t abtsts = PDMA_GET_ABORT_STS();
<> 149:156823d33999 117 // Clear all Abort flags
<> 149:156823d33999 118 PDMA_CLR_ABORT_FLAG(abtsts);
<> 149:156823d33999 119
<> 149:156823d33999 120 while (abtsts) {
AnnaBridge 165:e614a9f1c9e2 121 int chn_id = nu_ctz(abtsts) - PDMA_ABTSTS_ABTIFn_Pos + NU_PDMA_CH_Pos;
<> 149:156823d33999 122 if (dma_chn_mask & (1 << chn_id)) {
AnnaBridge 165:e614a9f1c9e2 123 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos;
<> 149:156823d33999 124 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
<> 149:156823d33999 125 dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
<> 149:156823d33999 126 }
<> 149:156823d33999 127 }
AnnaBridge 165:e614a9f1c9e2 128 abtsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_ABTSTS_ABTIFn_Pos));
<> 149:156823d33999 129 }
<> 149:156823d33999 130 }
<> 149:156823d33999 131
<> 149:156823d33999 132 // Transfer done
<> 149:156823d33999 133 if (intsts & PDMA_INTSTS_TDIF_Msk) {
<> 149:156823d33999 134 uint32_t tdsts = PDMA_GET_TD_STS();
<> 149:156823d33999 135 // Clear all transfer done flags
<> 149:156823d33999 136 PDMA_CLR_TD_FLAG(tdsts);
<> 149:156823d33999 137
<> 149:156823d33999 138 while (tdsts) {
AnnaBridge 165:e614a9f1c9e2 139 int chn_id = nu_ctz(tdsts) - PDMA_TDSTS_TDIFn_Pos + NU_PDMA_CH_Pos;
<> 149:156823d33999 140 if (dma_chn_mask & (1 << chn_id)) {
AnnaBridge 165:e614a9f1c9e2 141 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos;
<> 149:156823d33999 142 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
<> 149:156823d33999 143 dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
<> 149:156823d33999 144 }
<> 149:156823d33999 145 }
AnnaBridge 165:e614a9f1c9e2 146 tdsts &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_TDSTS_TDIFn_Pos));
<> 149:156823d33999 147 }
<> 149:156823d33999 148 }
<> 149:156823d33999 149
<> 149:156823d33999 150 // Table empty
<> 149:156823d33999 151 if (intsts & PDMA_INTSTS_TEIF_Msk) {
<> 149:156823d33999 152 uint32_t scatsts = PDMA_GET_EMPTY_STS();
<> 149:156823d33999 153 // Clear all table empty flags
<> 149:156823d33999 154 PDMA_CLR_EMPTY_FLAG(scatsts);
<> 149:156823d33999 155 }
<> 149:156823d33999 156
<> 149:156823d33999 157 // Timeout
<> 149:156823d33999 158 uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk;
<> 149:156823d33999 159 if (reqto) {
<> 149:156823d33999 160 // Clear all Timeout flags
<> 149:156823d33999 161 PDMA->INTSTS = reqto;
<> 149:156823d33999 162
<> 149:156823d33999 163 while (reqto) {
AnnaBridge 165:e614a9f1c9e2 164 int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos + NU_PDMA_CH_Pos;
<> 149:156823d33999 165 if (dma_chn_mask & (1 << chn_id)) {
AnnaBridge 165:e614a9f1c9e2 166 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id - NU_PDMA_CH_Pos;
<> 149:156823d33999 167 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
<> 149:156823d33999 168 dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
<> 149:156823d33999 169 }
<> 149:156823d33999 170 }
AnnaBridge 165:e614a9f1c9e2 171 reqto &= ~(1 << (chn_id - NU_PDMA_CH_Pos + PDMA_INTSTS_REQTOFn_Pos));
<> 149:156823d33999 172 }
<> 149:156823d33999 173 }
<> 149:156823d33999 174 }