Maxim Ibragimov / mbed-dev

mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c

Dependents:   Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay

Fork of mbed-dev by mbed official

targets/TARGET_NUVOTON/TARGET_M451/dma_api.c@161:2cc1468da177, 2017-03-30 (annotated)

Committer:
<>
Date:
Thu Mar 30 13:45:57 2017 +0100
Revision:
161:2cc1468da177
Parent:
149:156823d33999
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v139

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 149:156823d33999 1 /* mbed Microcontroller Library
<> 149:156823d33999 2 * Copyright (c) 2015-2016 Nuvoton
<> 149:156823d33999 3 *
<> 149:156823d33999 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 149:156823d33999 5 * you may not use this file except in compliance with the License.
<> 149:156823d33999 6 * You may obtain a copy of the License at
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 149:156823d33999 9 *
<> 149:156823d33999 10 * Unless required by applicable law or agreed to in writing, software
<> 149:156823d33999 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 149:156823d33999 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 149:156823d33999 13 * See the License for the specific language governing permissions and
<> 149:156823d33999 14 * limitations under the License.
<> 149:156823d33999 15 */
<> 149:156823d33999 16
<> 149:156823d33999 17 #include "dma_api.h"
<> 149:156823d33999 18 #include "string.h"
<> 149:156823d33999 19 #include "cmsis.h"
<> 149:156823d33999 20 #include "mbed_assert.h"
<> 149:156823d33999 21 #include "PeripheralNames.h"
<> 149:156823d33999 22 #include "nu_modutil.h"
<> 149:156823d33999 23 #include "nu_bitutil.h"
<> 149:156823d33999 24 #include "dma.h"
<> 149:156823d33999 25
<> 149:156823d33999 26 struct nu_dma_chn_s {
<> 149:156823d33999 27 void (*handler)(uint32_t, uint32_t);
<> 149:156823d33999 28 uint32_t id;
<> 149:156823d33999 29 uint32_t event;
<> 149:156823d33999 30 };
<> 149:156823d33999 31
<> 149:156823d33999 32 static int dma_inited = 0;
<> 149:156823d33999 33 static uint32_t dma_chn_mask = 0;
<> 149:156823d33999 34 static struct nu_dma_chn_s dma_chn_arr[PDMA_CH_MAX];
<> 149:156823d33999 35
<> 149:156823d33999 36 static void pdma_vec(void);
<> 149:156823d33999 37 static const struct nu_modinit_s dma_modinit = {DMA_0, PDMA_MODULE, 0, 0, PDMA_RST, PDMA_IRQn, (void *) pdma_vec};
<> 149:156823d33999 38
<> 149:156823d33999 39
<> 149:156823d33999 40 void dma_init(void)
<> 149:156823d33999 41 {
<> 149:156823d33999 42 if (dma_inited) {
<> 149:156823d33999 43 return;
<> 149:156823d33999 44 }
<> 149:156823d33999 45
<> 149:156823d33999 46 dma_inited = 1;
<> 149:156823d33999 47 dma_chn_mask = 0;
<> 149:156823d33999 48 memset(dma_chn_arr, 0x00, sizeof (dma_chn_arr));
<> 149:156823d33999 49
<> 149:156823d33999 50 // Reset this module
<> 149:156823d33999 51 SYS_ResetModule(dma_modinit.rsetidx);
<> 149:156823d33999 52
<> 149:156823d33999 53 // Enable IP clock
<> 149:156823d33999 54 CLK_EnableModuleClock(dma_modinit.clkidx);
<> 149:156823d33999 55
<> 149:156823d33999 56 PDMA_Open(0);
<> 149:156823d33999 57
<> 149:156823d33999 58 NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
<> 149:156823d33999 59 NVIC_EnableIRQ(dma_modinit.irq_n);
<> 149:156823d33999 60 }
<> 149:156823d33999 61
<> 149:156823d33999 62 int dma_channel_allocate(uint32_t capabilities)
<> 149:156823d33999 63 {
<> 149:156823d33999 64 if (! dma_inited) {
<> 149:156823d33999 65 dma_init();
<> 149:156823d33999 66 }
<> 149:156823d33999 67
<> 149:156823d33999 68 #if 1
<> 149:156823d33999 69 int i = nu_cto(dma_chn_mask);
<> 149:156823d33999 70 if (i != 32) {
<> 149:156823d33999 71 dma_chn_mask |= 1 << i;
<> 149:156823d33999 72 memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
<> 149:156823d33999 73 return i;
<> 149:156823d33999 74 }
<> 149:156823d33999 75 #else
<> 149:156823d33999 76 int i;
<> 149:156823d33999 77
<> 149:156823d33999 78 for (i = 0; i < PDMA_CH_MAX; i ++) {
<> 149:156823d33999 79 if ((dma_chn_mask & (1 << i)) == 0) {
<> 149:156823d33999 80 // Channel available
<> 149:156823d33999 81 dma_chn_mask |= 1 << i;
<> 149:156823d33999 82 memset(dma_chn_arr + i, 0x00, sizeof (struct nu_dma_chn_s));
<> 149:156823d33999 83 return i;
<> 149:156823d33999 84 }
<> 149:156823d33999 85 }
<> 149:156823d33999 86 #endif
<> 149:156823d33999 87
<> 149:156823d33999 88 // No channel available
<> 149:156823d33999 89 return DMA_ERROR_OUT_OF_CHANNELS;
<> 149:156823d33999 90 }
<> 149:156823d33999 91
<> 149:156823d33999 92 int dma_channel_free(int channelid)
<> 149:156823d33999 93 {
<> 149:156823d33999 94 if (channelid != DMA_ERROR_OUT_OF_CHANNELS) {
<> 149:156823d33999 95 dma_chn_mask &= ~(1 << channelid);
<> 149:156823d33999 96 }
<> 149:156823d33999 97
<> 149:156823d33999 98 return 0;
<> 149:156823d33999 99 }
<> 149:156823d33999 100
<> 149:156823d33999 101 void dma_set_handler(int channelid, uint32_t handler, uint32_t id, uint32_t event)
<> 149:156823d33999 102 {
<> 149:156823d33999 103 MBED_ASSERT(dma_chn_mask & (1 << channelid));
<> 149:156823d33999 104
<> 149:156823d33999 105 dma_chn_arr[channelid].handler = (void (*)(uint32_t, uint32_t)) handler;
<> 149:156823d33999 106 dma_chn_arr[channelid].id = id;
<> 149:156823d33999 107 dma_chn_arr[channelid].event = event;
<> 149:156823d33999 108
<> 149:156823d33999 109 // Set interrupt vector if someone has removed it.
<> 149:156823d33999 110 NVIC_SetVector(dma_modinit.irq_n, (uint32_t) dma_modinit.var);
<> 149:156823d33999 111 NVIC_EnableIRQ(dma_modinit.irq_n);
<> 149:156823d33999 112 }
<> 149:156823d33999 113
<> 161:2cc1468da177 114 PDMA_T *dma_modbase(void)
<> 161:2cc1468da177 115 {
<> 161:2cc1468da177 116 return (PDMA_T *) NU_MODBASE(dma_modinit.modname);
<> 161:2cc1468da177 117 }
<> 161:2cc1468da177 118
<> 149:156823d33999 119 static void pdma_vec(void)
<> 149:156823d33999 120 {
<> 149:156823d33999 121 uint32_t intsts = PDMA_GET_INT_STATUS();
<> 149:156823d33999 122
<> 149:156823d33999 123 // Abort
<> 149:156823d33999 124 if (intsts & PDMA_INTSTS_ABTIF_Msk) {
<> 149:156823d33999 125 uint32_t abtsts = PDMA_GET_ABORT_STS();
<> 149:156823d33999 126 // Clear all Abort flags
<> 149:156823d33999 127 PDMA_CLR_ABORT_FLAG(abtsts);
<> 149:156823d33999 128
<> 149:156823d33999 129 while (abtsts) {
<> 149:156823d33999 130 int chn_id = nu_ctz(abtsts);
<> 149:156823d33999 131 if (dma_chn_mask & (1 << chn_id)) {
<> 149:156823d33999 132 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
<> 149:156823d33999 133 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_ABORT)) {
<> 149:156823d33999 134 dma_chn->handler(dma_chn->id, DMA_EVENT_ABORT);
<> 149:156823d33999 135 }
<> 149:156823d33999 136 }
<> 149:156823d33999 137 abtsts &= ~(1 << chn_id);
<> 149:156823d33999 138 }
<> 149:156823d33999 139 }
<> 149:156823d33999 140
<> 149:156823d33999 141 // Transfer done
<> 149:156823d33999 142 if (intsts & PDMA_INTSTS_TDIF_Msk) {
<> 149:156823d33999 143 uint32_t tdsts = PDMA_GET_TD_STS();
<> 149:156823d33999 144 // Clear all transfer done flags
<> 149:156823d33999 145 PDMA_CLR_TD_FLAG(tdsts);
<> 149:156823d33999 146
<> 149:156823d33999 147 while (tdsts) {
<> 149:156823d33999 148 int chn_id = nu_ctz(tdsts);
<> 149:156823d33999 149 if (dma_chn_mask & (1 << chn_id)) {
<> 149:156823d33999 150 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
<> 149:156823d33999 151 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TRANSFER_DONE)) {
<> 149:156823d33999 152 dma_chn->handler(dma_chn->id, DMA_EVENT_TRANSFER_DONE);
<> 149:156823d33999 153 }
<> 149:156823d33999 154 }
<> 149:156823d33999 155 tdsts &= ~(1 << chn_id);
<> 149:156823d33999 156 }
<> 149:156823d33999 157 }
<> 149:156823d33999 158
<> 149:156823d33999 159 // Table empty
<> 149:156823d33999 160 if (intsts & PDMA_INTSTS_TEIF_Msk) {
<> 149:156823d33999 161 uint32_t scatsts = PDMA_GET_EMPTY_STS();
<> 149:156823d33999 162 // Clear all table empty flags
<> 149:156823d33999 163 PDMA_CLR_EMPTY_FLAG(scatsts);
<> 149:156823d33999 164 }
<> 149:156823d33999 165
<> 149:156823d33999 166 // Timeout
<> 149:156823d33999 167 uint32_t reqto = intsts & PDMA_INTSTS_REQTOFn_Msk;
<> 149:156823d33999 168 if (reqto) {
<> 149:156823d33999 169 // Clear all Timeout flags
<> 149:156823d33999 170 PDMA->INTSTS = reqto;
<> 149:156823d33999 171
<> 149:156823d33999 172 while (reqto) {
<> 161:2cc1468da177 173 int chn_id = nu_ctz(reqto) - PDMA_INTSTS_REQTOFn_Pos;
<> 149:156823d33999 174 if (dma_chn_mask & (1 << chn_id)) {
<> 149:156823d33999 175 struct nu_dma_chn_s *dma_chn = dma_chn_arr + chn_id;
<> 149:156823d33999 176 if (dma_chn->handler && (dma_chn->event & DMA_EVENT_TIMEOUT)) {
<> 149:156823d33999 177 dma_chn->handler(dma_chn->id, DMA_EVENT_TIMEOUT);
<> 149:156823d33999 178 }
<> 149:156823d33999 179 }
<> 149:156823d33999 180 reqto &= ~(1 << (chn_id + PDMA_INTSTS_REQTOFn_Pos));
<> 149:156823d33999 181 }
<> 149:156823d33999 182 }
<> 149:156823d33999 183 }