mbed library sources. Supersedes mbed-src. Fixed broken STM32F1xx RTC on rtc_api.c
Dependents: Nucleo_F103RB_RTC_battery_bkup_pwr_off_okay
Fork of mbed-dev by
targets/TARGET_STM/stm_spi_api.c@177:619788de047e, 2017-11-07 (annotated)
- Committer:
- maxxir
- Date:
- Tue Nov 07 16:46:29 2017 +0000
- Revision:
- 177:619788de047e
- Parent:
- 173:e131a1973e81
To fix broken RTC on Nucleo_F103RB / STM32F103 BluePill etc..; Used direct RTC register manipulation for STM32F1xx; rtc_read() && rtc_write() (native rtc_init() - works good); also added stub for non-working on STM32F1xx rtc_read_subseconds().
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 149:156823d33999 | 1 | /* mbed Microcontroller Library |
<> | 149:156823d33999 | 2 | ******************************************************************************* |
<> | 149:156823d33999 | 3 | * Copyright (c) 2015, STMicroelectronics |
<> | 149:156823d33999 | 4 | * All rights reserved. |
<> | 149:156823d33999 | 5 | * |
<> | 149:156823d33999 | 6 | * Redistribution and use in source and binary forms, with or without |
<> | 149:156823d33999 | 7 | * modification, are permitted provided that the following conditions are met: |
<> | 149:156823d33999 | 8 | * |
<> | 149:156823d33999 | 9 | * 1. Redistributions of source code must retain the above copyright notice, |
<> | 149:156823d33999 | 10 | * this list of conditions and the following disclaimer. |
<> | 149:156823d33999 | 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
<> | 149:156823d33999 | 12 | * this list of conditions and the following disclaimer in the documentation |
<> | 149:156823d33999 | 13 | * and/or other materials provided with the distribution. |
<> | 149:156823d33999 | 14 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
<> | 149:156823d33999 | 15 | * may be used to endorse or promote products derived from this software |
<> | 149:156823d33999 | 16 | * without specific prior written permission. |
<> | 149:156823d33999 | 17 | * |
<> | 149:156823d33999 | 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
<> | 149:156823d33999 | 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
<> | 149:156823d33999 | 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
<> | 149:156823d33999 | 21 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
<> | 149:156823d33999 | 22 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
<> | 149:156823d33999 | 23 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
<> | 149:156823d33999 | 24 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
<> | 149:156823d33999 | 25 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
<> | 149:156823d33999 | 26 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
<> | 149:156823d33999 | 27 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
<> | 149:156823d33999 | 28 | ******************************************************************************* |
<> | 149:156823d33999 | 29 | */ |
<> | 149:156823d33999 | 30 | #include "mbed_assert.h" |
<> | 149:156823d33999 | 31 | #include "mbed_error.h" |
<> | 149:156823d33999 | 32 | #include "spi_api.h" |
<> | 149:156823d33999 | 33 | |
<> | 149:156823d33999 | 34 | #if DEVICE_SPI |
<> | 149:156823d33999 | 35 | #include <stdbool.h> |
<> | 149:156823d33999 | 36 | #include <math.h> |
<> | 149:156823d33999 | 37 | #include <string.h> |
<> | 149:156823d33999 | 38 | #include "cmsis.h" |
<> | 149:156823d33999 | 39 | #include "pinmap.h" |
<> | 149:156823d33999 | 40 | #include "PeripheralPins.h" |
AnnaBridge | 168:9672193075cf | 41 | #include "spi_device.h" |
<> | 149:156823d33999 | 42 | |
<> | 149:156823d33999 | 43 | #if DEVICE_SPI_ASYNCH |
<> | 149:156823d33999 | 44 | #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi.spi)) |
<> | 149:156823d33999 | 45 | #else |
<> | 149:156823d33999 | 46 | #define SPI_INST(obj) ((SPI_TypeDef *)(obj->spi)) |
<> | 149:156823d33999 | 47 | #endif |
<> | 149:156823d33999 | 48 | |
<> | 149:156823d33999 | 49 | #if DEVICE_SPI_ASYNCH |
<> | 149:156823d33999 | 50 | #define SPI_S(obj) (( struct spi_s *)(&(obj->spi))) |
<> | 149:156823d33999 | 51 | #else |
<> | 149:156823d33999 | 52 | #define SPI_S(obj) (( struct spi_s *)(obj)) |
<> | 149:156823d33999 | 53 | #endif |
<> | 149:156823d33999 | 54 | |
<> | 149:156823d33999 | 55 | #ifndef DEBUG_STDIO |
<> | 149:156823d33999 | 56 | # define DEBUG_STDIO 0 |
<> | 149:156823d33999 | 57 | #endif |
<> | 149:156823d33999 | 58 | |
<> | 149:156823d33999 | 59 | #if DEBUG_STDIO |
<> | 149:156823d33999 | 60 | # include <stdio.h> |
<> | 149:156823d33999 | 61 | # define DEBUG_PRINTF(...) do { printf(__VA_ARGS__); } while(0) |
<> | 149:156823d33999 | 62 | #else |
<> | 149:156823d33999 | 63 | # define DEBUG_PRINTF(...) {} |
<> | 149:156823d33999 | 64 | #endif |
<> | 149:156823d33999 | 65 | |
AnnaBridge | 173:e131a1973e81 | 66 | /* Consider 10ms as the default timeout for sending/receving 1 byte */ |
AnnaBridge | 173:e131a1973e81 | 67 | #define TIMEOUT_1_BYTE 10 |
AnnaBridge | 173:e131a1973e81 | 68 | |
<> | 149:156823d33999 | 69 | void init_spi(spi_t *obj) |
<> | 149:156823d33999 | 70 | { |
<> | 149:156823d33999 | 71 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 72 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 73 | |
<> | 149:156823d33999 | 74 | __HAL_SPI_DISABLE(handle); |
<> | 149:156823d33999 | 75 | |
<> | 149:156823d33999 | 76 | DEBUG_PRINTF("init_spi: instance=0x%8X\r\n", (int)handle->Instance); |
<> | 149:156823d33999 | 77 | if (HAL_SPI_Init(handle) != HAL_OK) { |
<> | 149:156823d33999 | 78 | error("Cannot initialize SPI"); |
<> | 149:156823d33999 | 79 | } |
<> | 149:156823d33999 | 80 | |
AnnaBridge | 173:e131a1973e81 | 81 | /* In case of standard 4 wires SPI,PI can be kept enabled all time |
AnnaBridge | 173:e131a1973e81 | 82 | * and SCK will only be generated during the write operations. But in case |
AnnaBridge | 173:e131a1973e81 | 83 | * of 3 wires, it should be only enabled during rd/wr unitary operations, |
AnnaBridge | 173:e131a1973e81 | 84 | * which is handled inside STM32 HAL layer. |
AnnaBridge | 173:e131a1973e81 | 85 | */ |
AnnaBridge | 173:e131a1973e81 | 86 | if (handle->Init.Direction == SPI_DIRECTION_2LINES) { |
AnnaBridge | 173:e131a1973e81 | 87 | __HAL_SPI_ENABLE(handle); |
AnnaBridge | 173:e131a1973e81 | 88 | } |
<> | 149:156823d33999 | 89 | } |
<> | 149:156823d33999 | 90 | |
<> | 149:156823d33999 | 91 | void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) |
<> | 149:156823d33999 | 92 | { |
<> | 149:156823d33999 | 93 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 94 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 95 | |
<> | 149:156823d33999 | 96 | // Determine the SPI to use |
<> | 149:156823d33999 | 97 | SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI); |
<> | 149:156823d33999 | 98 | SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO); |
<> | 149:156823d33999 | 99 | SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK); |
<> | 149:156823d33999 | 100 | SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL); |
<> | 149:156823d33999 | 101 | |
<> | 149:156823d33999 | 102 | SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso); |
<> | 149:156823d33999 | 103 | SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel); |
<> | 149:156823d33999 | 104 | |
<> | 149:156823d33999 | 105 | spiobj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl); |
<> | 149:156823d33999 | 106 | MBED_ASSERT(spiobj->spi != (SPIName)NC); |
<> | 149:156823d33999 | 107 | |
<> | 149:156823d33999 | 108 | #if defined SPI1_BASE |
<> | 149:156823d33999 | 109 | // Enable SPI clock |
<> | 149:156823d33999 | 110 | if (spiobj->spi == SPI_1) { |
<> | 149:156823d33999 | 111 | __HAL_RCC_SPI1_CLK_ENABLE(); |
<> | 149:156823d33999 | 112 | spiobj->spiIRQ = SPI1_IRQn; |
<> | 149:156823d33999 | 113 | } |
<> | 149:156823d33999 | 114 | #endif |
<> | 149:156823d33999 | 115 | |
<> | 149:156823d33999 | 116 | #if defined SPI2_BASE |
<> | 149:156823d33999 | 117 | if (spiobj->spi == SPI_2) { |
<> | 149:156823d33999 | 118 | __HAL_RCC_SPI2_CLK_ENABLE(); |
<> | 149:156823d33999 | 119 | spiobj->spiIRQ = SPI2_IRQn; |
<> | 149:156823d33999 | 120 | } |
<> | 149:156823d33999 | 121 | #endif |
<> | 149:156823d33999 | 122 | |
<> | 149:156823d33999 | 123 | #if defined SPI3_BASE |
<> | 149:156823d33999 | 124 | if (spiobj->spi == SPI_3) { |
<> | 149:156823d33999 | 125 | __HAL_RCC_SPI3_CLK_ENABLE(); |
<> | 149:156823d33999 | 126 | spiobj->spiIRQ = SPI3_IRQn; |
<> | 149:156823d33999 | 127 | } |
<> | 149:156823d33999 | 128 | #endif |
<> | 149:156823d33999 | 129 | |
<> | 149:156823d33999 | 130 | #if defined SPI4_BASE |
<> | 149:156823d33999 | 131 | if (spiobj->spi == SPI_4) { |
<> | 149:156823d33999 | 132 | __HAL_RCC_SPI4_CLK_ENABLE(); |
<> | 149:156823d33999 | 133 | spiobj->spiIRQ = SPI4_IRQn; |
<> | 149:156823d33999 | 134 | } |
<> | 149:156823d33999 | 135 | #endif |
<> | 149:156823d33999 | 136 | |
<> | 149:156823d33999 | 137 | #if defined SPI5_BASE |
<> | 149:156823d33999 | 138 | if (spiobj->spi == SPI_5) { |
<> | 149:156823d33999 | 139 | __HAL_RCC_SPI5_CLK_ENABLE(); |
<> | 149:156823d33999 | 140 | spiobj->spiIRQ = SPI5_IRQn; |
<> | 149:156823d33999 | 141 | } |
<> | 149:156823d33999 | 142 | #endif |
<> | 149:156823d33999 | 143 | |
<> | 149:156823d33999 | 144 | #if defined SPI6_BASE |
<> | 149:156823d33999 | 145 | if (spiobj->spi == SPI_6) { |
<> | 149:156823d33999 | 146 | __HAL_RCC_SPI6_CLK_ENABLE(); |
<> | 149:156823d33999 | 147 | spiobj->spiIRQ = SPI6_IRQn; |
<> | 149:156823d33999 | 148 | } |
<> | 149:156823d33999 | 149 | #endif |
<> | 149:156823d33999 | 150 | |
<> | 149:156823d33999 | 151 | // Configure the SPI pins |
<> | 149:156823d33999 | 152 | pinmap_pinout(mosi, PinMap_SPI_MOSI); |
<> | 149:156823d33999 | 153 | pinmap_pinout(miso, PinMap_SPI_MISO); |
<> | 149:156823d33999 | 154 | pinmap_pinout(sclk, PinMap_SPI_SCLK); |
<> | 149:156823d33999 | 155 | spiobj->pin_miso = miso; |
<> | 149:156823d33999 | 156 | spiobj->pin_mosi = mosi; |
<> | 149:156823d33999 | 157 | spiobj->pin_sclk = sclk; |
<> | 149:156823d33999 | 158 | spiobj->pin_ssel = ssel; |
<> | 149:156823d33999 | 159 | if (ssel != NC) { |
<> | 149:156823d33999 | 160 | pinmap_pinout(ssel, PinMap_SPI_SSEL); |
<> | 149:156823d33999 | 161 | } else { |
<> | 149:156823d33999 | 162 | handle->Init.NSS = SPI_NSS_SOFT; |
<> | 149:156823d33999 | 163 | } |
<> | 149:156823d33999 | 164 | |
<> | 149:156823d33999 | 165 | /* Fill default value */ |
<> | 149:156823d33999 | 166 | handle->Instance = SPI_INST(obj); |
<> | 149:156823d33999 | 167 | handle->Init.Mode = SPI_MODE_MASTER; |
<> | 149:156823d33999 | 168 | handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256; |
AnnaBridge | 173:e131a1973e81 | 169 | |
AnnaBridge | 173:e131a1973e81 | 170 | if (miso != NC) { |
AnnaBridge | 173:e131a1973e81 | 171 | handle->Init.Direction = SPI_DIRECTION_2LINES; |
AnnaBridge | 173:e131a1973e81 | 172 | } else { |
AnnaBridge | 173:e131a1973e81 | 173 | handle->Init.Direction = SPI_DIRECTION_1LINE; |
AnnaBridge | 173:e131a1973e81 | 174 | } |
AnnaBridge | 173:e131a1973e81 | 175 | |
<> | 149:156823d33999 | 176 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
<> | 149:156823d33999 | 177 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
AnnaBridge | 165:e614a9f1c9e2 | 178 | handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; |
<> | 149:156823d33999 | 179 | handle->Init.CRCPolynomial = 7; |
<> | 149:156823d33999 | 180 | handle->Init.DataSize = SPI_DATASIZE_8BIT; |
<> | 149:156823d33999 | 181 | handle->Init.FirstBit = SPI_FIRSTBIT_MSB; |
AnnaBridge | 165:e614a9f1c9e2 | 182 | handle->Init.TIMode = SPI_TIMODE_DISABLE; |
<> | 149:156823d33999 | 183 | |
<> | 149:156823d33999 | 184 | init_spi(obj); |
<> | 149:156823d33999 | 185 | } |
<> | 149:156823d33999 | 186 | |
<> | 149:156823d33999 | 187 | void spi_free(spi_t *obj) |
<> | 149:156823d33999 | 188 | { |
<> | 149:156823d33999 | 189 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 190 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 191 | |
<> | 149:156823d33999 | 192 | DEBUG_PRINTF("spi_free\r\n"); |
<> | 149:156823d33999 | 193 | |
<> | 149:156823d33999 | 194 | __HAL_SPI_DISABLE(handle); |
<> | 149:156823d33999 | 195 | HAL_SPI_DeInit(handle); |
<> | 149:156823d33999 | 196 | |
<> | 149:156823d33999 | 197 | #if defined SPI1_BASE |
<> | 149:156823d33999 | 198 | // Reset SPI and disable clock |
<> | 149:156823d33999 | 199 | if (spiobj->spi == SPI_1) { |
<> | 149:156823d33999 | 200 | __HAL_RCC_SPI1_FORCE_RESET(); |
<> | 149:156823d33999 | 201 | __HAL_RCC_SPI1_RELEASE_RESET(); |
<> | 149:156823d33999 | 202 | __HAL_RCC_SPI1_CLK_DISABLE(); |
<> | 149:156823d33999 | 203 | } |
<> | 149:156823d33999 | 204 | #endif |
<> | 149:156823d33999 | 205 | #if defined SPI2_BASE |
<> | 149:156823d33999 | 206 | if (spiobj->spi == SPI_2) { |
<> | 149:156823d33999 | 207 | __HAL_RCC_SPI2_FORCE_RESET(); |
<> | 149:156823d33999 | 208 | __HAL_RCC_SPI2_RELEASE_RESET(); |
<> | 149:156823d33999 | 209 | __HAL_RCC_SPI2_CLK_DISABLE(); |
<> | 149:156823d33999 | 210 | } |
<> | 149:156823d33999 | 211 | #endif |
<> | 149:156823d33999 | 212 | |
<> | 149:156823d33999 | 213 | #if defined SPI3_BASE |
<> | 149:156823d33999 | 214 | if (spiobj->spi == SPI_3) { |
<> | 149:156823d33999 | 215 | __HAL_RCC_SPI3_FORCE_RESET(); |
<> | 149:156823d33999 | 216 | __HAL_RCC_SPI3_RELEASE_RESET(); |
<> | 149:156823d33999 | 217 | __HAL_RCC_SPI3_CLK_DISABLE(); |
<> | 149:156823d33999 | 218 | } |
<> | 149:156823d33999 | 219 | #endif |
<> | 149:156823d33999 | 220 | |
<> | 149:156823d33999 | 221 | #if defined SPI4_BASE |
<> | 149:156823d33999 | 222 | if (spiobj->spi == SPI_4) { |
<> | 149:156823d33999 | 223 | __HAL_RCC_SPI4_FORCE_RESET(); |
<> | 149:156823d33999 | 224 | __HAL_RCC_SPI4_RELEASE_RESET(); |
<> | 149:156823d33999 | 225 | __HAL_RCC_SPI4_CLK_DISABLE(); |
<> | 149:156823d33999 | 226 | } |
<> | 149:156823d33999 | 227 | #endif |
<> | 149:156823d33999 | 228 | |
<> | 149:156823d33999 | 229 | #if defined SPI5_BASE |
<> | 149:156823d33999 | 230 | if (spiobj->spi == SPI_5) { |
<> | 149:156823d33999 | 231 | __HAL_RCC_SPI5_FORCE_RESET(); |
<> | 149:156823d33999 | 232 | __HAL_RCC_SPI5_RELEASE_RESET(); |
<> | 149:156823d33999 | 233 | __HAL_RCC_SPI5_CLK_DISABLE(); |
<> | 149:156823d33999 | 234 | } |
<> | 149:156823d33999 | 235 | #endif |
<> | 149:156823d33999 | 236 | |
<> | 149:156823d33999 | 237 | #if defined SPI6_BASE |
<> | 149:156823d33999 | 238 | if (spiobj->spi == SPI_6) { |
<> | 149:156823d33999 | 239 | __HAL_RCC_SPI6_FORCE_RESET(); |
<> | 149:156823d33999 | 240 | __HAL_RCC_SPI6_RELEASE_RESET(); |
<> | 149:156823d33999 | 241 | __HAL_RCC_SPI6_CLK_DISABLE(); |
<> | 149:156823d33999 | 242 | } |
<> | 149:156823d33999 | 243 | #endif |
<> | 149:156823d33999 | 244 | |
<> | 149:156823d33999 | 245 | // Configure GPIOs |
<> | 149:156823d33999 | 246 | pin_function(spiobj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
<> | 149:156823d33999 | 247 | pin_function(spiobj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
<> | 149:156823d33999 | 248 | pin_function(spiobj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
<> | 149:156823d33999 | 249 | if (handle->Init.NSS != SPI_NSS_SOFT) { |
<> | 149:156823d33999 | 250 | pin_function(spiobj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); |
<> | 149:156823d33999 | 251 | } |
<> | 149:156823d33999 | 252 | } |
<> | 149:156823d33999 | 253 | |
<> | 149:156823d33999 | 254 | void spi_format(spi_t *obj, int bits, int mode, int slave) |
<> | 149:156823d33999 | 255 | { |
<> | 149:156823d33999 | 256 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 257 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 258 | |
<> | 149:156823d33999 | 259 | DEBUG_PRINTF("spi_format, bits:%d, mode:%d, slave?:%d\r\n", bits, mode, slave); |
<> | 149:156823d33999 | 260 | |
<> | 149:156823d33999 | 261 | // Save new values |
<> | 149:156823d33999 | 262 | handle->Init.DataSize = (bits == 16) ? SPI_DATASIZE_16BIT : SPI_DATASIZE_8BIT; |
<> | 149:156823d33999 | 263 | |
<> | 149:156823d33999 | 264 | switch (mode) { |
<> | 149:156823d33999 | 265 | case 0: |
<> | 149:156823d33999 | 266 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
<> | 149:156823d33999 | 267 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
<> | 149:156823d33999 | 268 | break; |
<> | 149:156823d33999 | 269 | case 1: |
<> | 149:156823d33999 | 270 | handle->Init.CLKPolarity = SPI_POLARITY_LOW; |
<> | 149:156823d33999 | 271 | handle->Init.CLKPhase = SPI_PHASE_2EDGE; |
<> | 149:156823d33999 | 272 | break; |
<> | 149:156823d33999 | 273 | case 2: |
<> | 149:156823d33999 | 274 | handle->Init.CLKPolarity = SPI_POLARITY_HIGH; |
<> | 149:156823d33999 | 275 | handle->Init.CLKPhase = SPI_PHASE_1EDGE; |
<> | 149:156823d33999 | 276 | break; |
<> | 149:156823d33999 | 277 | default: |
<> | 149:156823d33999 | 278 | handle->Init.CLKPolarity = SPI_POLARITY_HIGH; |
<> | 149:156823d33999 | 279 | handle->Init.CLKPhase = SPI_PHASE_2EDGE; |
<> | 149:156823d33999 | 280 | break; |
<> | 149:156823d33999 | 281 | } |
<> | 149:156823d33999 | 282 | |
<> | 149:156823d33999 | 283 | if (handle->Init.NSS != SPI_NSS_SOFT) { |
<> | 149:156823d33999 | 284 | handle->Init.NSS = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT; |
<> | 149:156823d33999 | 285 | } |
<> | 149:156823d33999 | 286 | |
<> | 149:156823d33999 | 287 | handle->Init.Mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER; |
<> | 149:156823d33999 | 288 | |
<> | 149:156823d33999 | 289 | init_spi(obj); |
<> | 149:156823d33999 | 290 | } |
<> | 149:156823d33999 | 291 | |
<> | 149:156823d33999 | 292 | /* |
<> | 149:156823d33999 | 293 | * Only the IP clock input is family dependant so it computed |
<> | 149:156823d33999 | 294 | * separately in spi_get_clock_freq |
<> | 149:156823d33999 | 295 | */ |
<> | 149:156823d33999 | 296 | extern int spi_get_clock_freq(spi_t *obj); |
<> | 149:156823d33999 | 297 | |
<> | 149:156823d33999 | 298 | static const uint16_t baudrate_prescaler_table[] = {SPI_BAUDRATEPRESCALER_2, |
<> | 149:156823d33999 | 299 | SPI_BAUDRATEPRESCALER_4, |
<> | 149:156823d33999 | 300 | SPI_BAUDRATEPRESCALER_8, |
<> | 149:156823d33999 | 301 | SPI_BAUDRATEPRESCALER_16, |
<> | 149:156823d33999 | 302 | SPI_BAUDRATEPRESCALER_32, |
<> | 149:156823d33999 | 303 | SPI_BAUDRATEPRESCALER_64, |
<> | 149:156823d33999 | 304 | SPI_BAUDRATEPRESCALER_128, |
<> | 149:156823d33999 | 305 | SPI_BAUDRATEPRESCALER_256}; |
<> | 149:156823d33999 | 306 | |
<> | 149:156823d33999 | 307 | void spi_frequency(spi_t *obj, int hz) { |
<> | 149:156823d33999 | 308 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 309 | int spi_hz = 0; |
<> | 149:156823d33999 | 310 | uint8_t prescaler_rank = 0; |
<> | 159:612c381a210f | 311 | uint8_t last_index = (sizeof(baudrate_prescaler_table)/sizeof(baudrate_prescaler_table[0])) - 1; |
<> | 149:156823d33999 | 312 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 313 | |
<> | 159:612c381a210f | 314 | /* Calculate the spi clock for prescaler_rank 0: SPI_BAUDRATEPRESCALER_2 */ |
<> | 159:612c381a210f | 315 | spi_hz = spi_get_clock_freq(obj) / 2; |
<> | 149:156823d33999 | 316 | |
<> | 149:156823d33999 | 317 | /* Define pre-scaler in order to get highest available frequency below requested frequency */ |
<> | 159:612c381a210f | 318 | while ((spi_hz > hz) && (prescaler_rank < last_index)) { |
<> | 149:156823d33999 | 319 | spi_hz = spi_hz / 2; |
<> | 149:156823d33999 | 320 | prescaler_rank++; |
<> | 149:156823d33999 | 321 | } |
<> | 149:156823d33999 | 322 | |
<> | 159:612c381a210f | 323 | /* Use the best fit pre-scaler */ |
<> | 159:612c381a210f | 324 | handle->Init.BaudRatePrescaler = baudrate_prescaler_table[prescaler_rank]; |
<> | 159:612c381a210f | 325 | |
<> | 159:612c381a210f | 326 | /* In case maximum pre-scaler still gives too high freq, raise an error */ |
<> | 159:612c381a210f | 327 | if (spi_hz > hz) { |
<> | 160:d5399cc887bb | 328 | DEBUG_PRINTF("WARNING: lowest SPI freq (%d) higher than requested (%d)\r\n", spi_hz, hz); |
<> | 149:156823d33999 | 329 | } |
<> | 149:156823d33999 | 330 | |
<> | 159:612c381a210f | 331 | DEBUG_PRINTF("spi_frequency, request:%d, select:%d\r\n", hz, spi_hz); |
<> | 159:612c381a210f | 332 | |
<> | 149:156823d33999 | 333 | init_spi(obj); |
<> | 149:156823d33999 | 334 | } |
<> | 149:156823d33999 | 335 | |
<> | 149:156823d33999 | 336 | static inline int ssp_readable(spi_t *obj) |
<> | 149:156823d33999 | 337 | { |
<> | 149:156823d33999 | 338 | int status; |
<> | 149:156823d33999 | 339 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 340 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 341 | |
<> | 149:156823d33999 | 342 | // Check if data is received |
<> | 149:156823d33999 | 343 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_RXNE) != RESET) ? 1 : 0); |
<> | 149:156823d33999 | 344 | return status; |
<> | 149:156823d33999 | 345 | } |
<> | 149:156823d33999 | 346 | |
<> | 149:156823d33999 | 347 | static inline int ssp_writeable(spi_t *obj) |
<> | 149:156823d33999 | 348 | { |
<> | 149:156823d33999 | 349 | int status; |
<> | 149:156823d33999 | 350 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 351 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 352 | |
<> | 149:156823d33999 | 353 | // Check if data is transmitted |
<> | 149:156823d33999 | 354 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_TXE) != RESET) ? 1 : 0); |
<> | 149:156823d33999 | 355 | return status; |
<> | 149:156823d33999 | 356 | } |
<> | 149:156823d33999 | 357 | |
<> | 149:156823d33999 | 358 | static inline int ssp_busy(spi_t *obj) |
<> | 149:156823d33999 | 359 | { |
<> | 149:156823d33999 | 360 | int status; |
<> | 149:156823d33999 | 361 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 362 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 363 | status = ((__HAL_SPI_GET_FLAG(handle, SPI_FLAG_BSY) != RESET) ? 1 : 0); |
<> | 149:156823d33999 | 364 | return status; |
<> | 149:156823d33999 | 365 | } |
<> | 149:156823d33999 | 366 | |
<> | 149:156823d33999 | 367 | int spi_master_write(spi_t *obj, int value) |
<> | 149:156823d33999 | 368 | { |
<> | 149:156823d33999 | 369 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 370 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 371 | |
AnnaBridge | 173:e131a1973e81 | 372 | if (handle->Init.Direction == SPI_DIRECTION_1LINE) { |
AnnaBridge | 173:e131a1973e81 | 373 | return HAL_SPI_Transmit(handle, (uint8_t*)&value, 1, TIMEOUT_1_BYTE); |
AnnaBridge | 173:e131a1973e81 | 374 | } |
AnnaBridge | 173:e131a1973e81 | 375 | |
AnnaBridge | 168:9672193075cf | 376 | #if defined(LL_SPI_RX_FIFO_TH_HALF) |
AnnaBridge | 168:9672193075cf | 377 | /* Configure the default data size */ |
AnnaBridge | 168:9672193075cf | 378 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
AnnaBridge | 168:9672193075cf | 379 | LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_HALF); |
AnnaBridge | 168:9672193075cf | 380 | } else { |
AnnaBridge | 168:9672193075cf | 381 | LL_SPI_SetRxFIFOThreshold(SPI_INST(obj), LL_SPI_RX_FIFO_TH_QUARTER); |
AnnaBridge | 168:9672193075cf | 382 | } |
AnnaBridge | 168:9672193075cf | 383 | #endif |
<> | 149:156823d33999 | 384 | |
AnnaBridge | 168:9672193075cf | 385 | /* Here we're using LL which means direct registers access |
AnnaBridge | 168:9672193075cf | 386 | * There is no error management, so we may end up looping |
AnnaBridge | 168:9672193075cf | 387 | * infinitely here in case of faulty device for insatnce, |
AnnaBridge | 168:9672193075cf | 388 | * but this will increase performances significantly |
AnnaBridge | 168:9672193075cf | 389 | */ |
<> | 149:156823d33999 | 390 | |
AnnaBridge | 168:9672193075cf | 391 | /* Wait TXE flag to transmit data */ |
AnnaBridge | 168:9672193075cf | 392 | while (!LL_SPI_IsActiveFlag_TXE(SPI_INST(obj))); |
AnnaBridge | 168:9672193075cf | 393 | |
AnnaBridge | 168:9672193075cf | 394 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
AnnaBridge | 168:9672193075cf | 395 | LL_SPI_TransmitData16(SPI_INST(obj), value); |
<> | 149:156823d33999 | 396 | } else { |
AnnaBridge | 168:9672193075cf | 397 | LL_SPI_TransmitData8(SPI_INST(obj), (uint8_t) value); |
AnnaBridge | 168:9672193075cf | 398 | } |
AnnaBridge | 168:9672193075cf | 399 | |
AnnaBridge | 168:9672193075cf | 400 | /* Then wait RXE flag before reading */ |
AnnaBridge | 168:9672193075cf | 401 | while (!LL_SPI_IsActiveFlag_RXNE(SPI_INST(obj))); |
AnnaBridge | 168:9672193075cf | 402 | |
AnnaBridge | 168:9672193075cf | 403 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
AnnaBridge | 168:9672193075cf | 404 | return LL_SPI_ReceiveData16(SPI_INST(obj)); |
AnnaBridge | 168:9672193075cf | 405 | } else { |
AnnaBridge | 168:9672193075cf | 406 | return LL_SPI_ReceiveData8(SPI_INST(obj)); |
<> | 149:156823d33999 | 407 | } |
<> | 149:156823d33999 | 408 | } |
<> | 149:156823d33999 | 409 | |
Kojto | 170:19eb464bc2be | 410 | int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, |
Kojto | 170:19eb464bc2be | 411 | char *rx_buffer, int rx_length, char write_fill) |
AnnaBridge | 167:e84263d55307 | 412 | { |
AnnaBridge | 173:e131a1973e81 | 413 | struct spi_s *spiobj = SPI_S(obj); |
AnnaBridge | 173:e131a1973e81 | 414 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
AnnaBridge | 167:e84263d55307 | 415 | int total = (tx_length > rx_length) ? tx_length : rx_length; |
AnnaBridge | 173:e131a1973e81 | 416 | int i = 0; |
AnnaBridge | 173:e131a1973e81 | 417 | if (handle->Init.Direction == SPI_DIRECTION_2LINES) { |
AnnaBridge | 173:e131a1973e81 | 418 | for (i = 0; i < total; i++) { |
AnnaBridge | 173:e131a1973e81 | 419 | char out = (i < tx_length) ? tx_buffer[i] : write_fill; |
AnnaBridge | 173:e131a1973e81 | 420 | char in = spi_master_write(obj, out); |
AnnaBridge | 173:e131a1973e81 | 421 | if (i < rx_length) { |
AnnaBridge | 173:e131a1973e81 | 422 | rx_buffer[i] = in; |
AnnaBridge | 173:e131a1973e81 | 423 | } |
AnnaBridge | 173:e131a1973e81 | 424 | } |
AnnaBridge | 173:e131a1973e81 | 425 | } else { |
AnnaBridge | 173:e131a1973e81 | 426 | /* In case of 1 WIRE only, first handle TX, then Rx */ |
AnnaBridge | 173:e131a1973e81 | 427 | if (tx_length != 0) { |
AnnaBridge | 173:e131a1973e81 | 428 | if (HAL_OK != HAL_SPI_Transmit(handle, (uint8_t*)tx_buffer, tx_length, tx_length*TIMEOUT_1_BYTE)) { |
AnnaBridge | 173:e131a1973e81 | 429 | /* report an error */ |
AnnaBridge | 173:e131a1973e81 | 430 | total = 0; |
AnnaBridge | 173:e131a1973e81 | 431 | } |
AnnaBridge | 173:e131a1973e81 | 432 | } |
AnnaBridge | 173:e131a1973e81 | 433 | if (rx_length != 0) { |
AnnaBridge | 173:e131a1973e81 | 434 | if (HAL_OK != HAL_SPI_Receive(handle, (uint8_t*)rx_buffer, rx_length, rx_length*TIMEOUT_1_BYTE)) { |
AnnaBridge | 173:e131a1973e81 | 435 | /* report an error */ |
AnnaBridge | 173:e131a1973e81 | 436 | total = 0; |
AnnaBridge | 173:e131a1973e81 | 437 | } |
AnnaBridge | 167:e84263d55307 | 438 | } |
AnnaBridge | 167:e84263d55307 | 439 | } |
AnnaBridge | 167:e84263d55307 | 440 | |
AnnaBridge | 167:e84263d55307 | 441 | return total; |
AnnaBridge | 167:e84263d55307 | 442 | } |
AnnaBridge | 167:e84263d55307 | 443 | |
<> | 149:156823d33999 | 444 | int spi_slave_receive(spi_t *obj) |
<> | 149:156823d33999 | 445 | { |
<> | 149:156823d33999 | 446 | return ((ssp_readable(obj) && !ssp_busy(obj)) ? 1 : 0); |
<> | 149:156823d33999 | 447 | }; |
<> | 149:156823d33999 | 448 | |
<> | 149:156823d33999 | 449 | int spi_slave_read(spi_t *obj) |
<> | 149:156823d33999 | 450 | { |
<> | 149:156823d33999 | 451 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 452 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 453 | while (!ssp_readable(obj)); |
AnnaBridge | 173:e131a1973e81 | 454 | if (handle->Init.DataSize == SPI_DATASIZE_16BIT) { |
AnnaBridge | 173:e131a1973e81 | 455 | return LL_SPI_ReceiveData16(SPI_INST(obj)); |
<> | 149:156823d33999 | 456 | } else { |
AnnaBridge | 173:e131a1973e81 | 457 | return LL_SPI_ReceiveData8(SPI_INST(obj)); |
<> | 149:156823d33999 | 458 | } |
<> | 149:156823d33999 | 459 | } |
<> | 149:156823d33999 | 460 | |
<> | 149:156823d33999 | 461 | void spi_slave_write(spi_t *obj, int value) |
<> | 149:156823d33999 | 462 | { |
<> | 149:156823d33999 | 463 | SPI_TypeDef *spi = SPI_INST(obj); |
<> | 149:156823d33999 | 464 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 465 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 466 | while (!ssp_writeable(obj)); |
<> | 149:156823d33999 | 467 | if (handle->Init.DataSize == SPI_DATASIZE_8BIT) { |
<> | 149:156823d33999 | 468 | // Force 8-bit access to the data register |
<> | 149:156823d33999 | 469 | uint8_t *p_spi_dr = 0; |
<> | 149:156823d33999 | 470 | p_spi_dr = (uint8_t *) & (spi->DR); |
<> | 149:156823d33999 | 471 | *p_spi_dr = (uint8_t)value; |
<> | 149:156823d33999 | 472 | } else { // SPI_DATASIZE_16BIT |
<> | 149:156823d33999 | 473 | spi->DR = (uint16_t)value; |
<> | 149:156823d33999 | 474 | } |
<> | 149:156823d33999 | 475 | } |
<> | 149:156823d33999 | 476 | |
<> | 149:156823d33999 | 477 | int spi_busy(spi_t *obj) |
<> | 149:156823d33999 | 478 | { |
<> | 149:156823d33999 | 479 | return ssp_busy(obj); |
<> | 149:156823d33999 | 480 | } |
<> | 149:156823d33999 | 481 | |
<> | 149:156823d33999 | 482 | #ifdef DEVICE_SPI_ASYNCH |
<> | 149:156823d33999 | 483 | typedef enum { |
<> | 149:156823d33999 | 484 | SPI_TRANSFER_TYPE_NONE = 0, |
<> | 149:156823d33999 | 485 | SPI_TRANSFER_TYPE_TX = 1, |
<> | 149:156823d33999 | 486 | SPI_TRANSFER_TYPE_RX = 2, |
<> | 149:156823d33999 | 487 | SPI_TRANSFER_TYPE_TXRX = 3, |
<> | 149:156823d33999 | 488 | } transfer_type_t; |
<> | 149:156823d33999 | 489 | |
<> | 149:156823d33999 | 490 | |
<> | 149:156823d33999 | 491 | /// @returns the number of bytes transferred, or `0` if nothing transferred |
<> | 149:156823d33999 | 492 | static int spi_master_start_asynch_transfer(spi_t *obj, transfer_type_t transfer_type, const void *tx, void *rx, size_t length) |
<> | 149:156823d33999 | 493 | { |
<> | 149:156823d33999 | 494 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 495 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 496 | bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT); |
<> | 149:156823d33999 | 497 | // the HAL expects number of transfers instead of number of bytes |
<> | 149:156823d33999 | 498 | // so for 16 bit transfer width the count needs to be halved |
<> | 149:156823d33999 | 499 | size_t words; |
<> | 149:156823d33999 | 500 | |
<> | 149:156823d33999 | 501 | DEBUG_PRINTF("SPI inst=0x%8X Start: %u, %u\r\n", (int)handle->Instance, transfer_type, length); |
<> | 149:156823d33999 | 502 | |
<> | 149:156823d33999 | 503 | obj->spi.transfer_type = transfer_type; |
<> | 149:156823d33999 | 504 | |
<> | 149:156823d33999 | 505 | if (is16bit) { |
<> | 149:156823d33999 | 506 | words = length / 2; |
<> | 149:156823d33999 | 507 | } else { |
<> | 149:156823d33999 | 508 | words = length; |
<> | 149:156823d33999 | 509 | } |
<> | 149:156823d33999 | 510 | |
<> | 149:156823d33999 | 511 | // enable the interrupt |
<> | 149:156823d33999 | 512 | IRQn_Type irq_n = spiobj->spiIRQ; |
<> | 153:fa9ff456f731 | 513 | NVIC_DisableIRQ(irq_n); |
<> | 149:156823d33999 | 514 | NVIC_ClearPendingIRQ(irq_n); |
<> | 149:156823d33999 | 515 | NVIC_SetPriority(irq_n, 1); |
<> | 149:156823d33999 | 516 | NVIC_EnableIRQ(irq_n); |
<> | 149:156823d33999 | 517 | |
<> | 149:156823d33999 | 518 | // enable the right hal transfer |
<> | 149:156823d33999 | 519 | int rc = 0; |
<> | 149:156823d33999 | 520 | switch(transfer_type) { |
<> | 149:156823d33999 | 521 | case SPI_TRANSFER_TYPE_TXRX: |
<> | 149:156823d33999 | 522 | rc = HAL_SPI_TransmitReceive_IT(handle, (uint8_t*)tx, (uint8_t*)rx, words); |
<> | 149:156823d33999 | 523 | break; |
<> | 149:156823d33999 | 524 | case SPI_TRANSFER_TYPE_TX: |
<> | 149:156823d33999 | 525 | rc = HAL_SPI_Transmit_IT(handle, (uint8_t*)tx, words); |
<> | 149:156823d33999 | 526 | break; |
<> | 149:156823d33999 | 527 | case SPI_TRANSFER_TYPE_RX: |
<> | 149:156823d33999 | 528 | // the receive function also "transmits" the receive buffer so in order |
<> | 149:156823d33999 | 529 | // to guarantee that 0xff is on the line, we explicitly memset it here |
<> | 149:156823d33999 | 530 | memset(rx, SPI_FILL_WORD, length); |
<> | 149:156823d33999 | 531 | rc = HAL_SPI_Receive_IT(handle, (uint8_t*)rx, words); |
<> | 149:156823d33999 | 532 | break; |
<> | 149:156823d33999 | 533 | default: |
<> | 149:156823d33999 | 534 | length = 0; |
<> | 149:156823d33999 | 535 | } |
<> | 149:156823d33999 | 536 | |
<> | 149:156823d33999 | 537 | if (rc) { |
<> | 149:156823d33999 | 538 | DEBUG_PRINTF("SPI: RC=%u\n", rc); |
<> | 149:156823d33999 | 539 | length = 0; |
<> | 149:156823d33999 | 540 | } |
<> | 149:156823d33999 | 541 | |
<> | 149:156823d33999 | 542 | return length; |
<> | 149:156823d33999 | 543 | } |
<> | 149:156823d33999 | 544 | |
<> | 149:156823d33999 | 545 | // asynchronous API |
<> | 149:156823d33999 | 546 | void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint) |
<> | 149:156823d33999 | 547 | { |
<> | 149:156823d33999 | 548 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 549 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 550 | |
<> | 149:156823d33999 | 551 | // TODO: DMA usage is currently ignored |
<> | 149:156823d33999 | 552 | (void) hint; |
<> | 149:156823d33999 | 553 | |
<> | 149:156823d33999 | 554 | // check which use-case we have |
<> | 149:156823d33999 | 555 | bool use_tx = (tx != NULL && tx_length > 0); |
<> | 149:156823d33999 | 556 | bool use_rx = (rx != NULL && rx_length > 0); |
<> | 149:156823d33999 | 557 | bool is16bit = (handle->Init.DataSize == SPI_DATASIZE_16BIT); |
<> | 149:156823d33999 | 558 | |
<> | 149:156823d33999 | 559 | // don't do anything, if the buffers aren't valid |
<> | 149:156823d33999 | 560 | if (!use_tx && !use_rx) |
<> | 149:156823d33999 | 561 | return; |
<> | 149:156823d33999 | 562 | |
<> | 149:156823d33999 | 563 | // copy the buffers to the SPI object |
<> | 149:156823d33999 | 564 | obj->tx_buff.buffer = (void *) tx; |
<> | 149:156823d33999 | 565 | obj->tx_buff.length = tx_length; |
<> | 149:156823d33999 | 566 | obj->tx_buff.pos = 0; |
<> | 149:156823d33999 | 567 | obj->tx_buff.width = is16bit ? 16 : 8; |
<> | 149:156823d33999 | 568 | |
<> | 149:156823d33999 | 569 | obj->rx_buff.buffer = rx; |
<> | 149:156823d33999 | 570 | obj->rx_buff.length = rx_length; |
<> | 149:156823d33999 | 571 | obj->rx_buff.pos = 0; |
<> | 149:156823d33999 | 572 | obj->rx_buff.width = obj->tx_buff.width; |
<> | 149:156823d33999 | 573 | |
<> | 149:156823d33999 | 574 | obj->spi.event = event; |
<> | 149:156823d33999 | 575 | |
<> | 149:156823d33999 | 576 | DEBUG_PRINTF("SPI: Transfer: %u, %u\n", tx_length, rx_length); |
<> | 149:156823d33999 | 577 | |
<> | 149:156823d33999 | 578 | // register the thunking handler |
<> | 149:156823d33999 | 579 | IRQn_Type irq_n = spiobj->spiIRQ; |
<> | 149:156823d33999 | 580 | NVIC_SetVector(irq_n, (uint32_t)handler); |
<> | 149:156823d33999 | 581 | |
<> | 149:156823d33999 | 582 | // enable the right hal transfer |
<> | 149:156823d33999 | 583 | if (use_tx && use_rx) { |
<> | 149:156823d33999 | 584 | // we cannot manage different rx / tx sizes, let's use smaller one |
<> | 149:156823d33999 | 585 | size_t size = (tx_length < rx_length)? tx_length : rx_length; |
<> | 149:156823d33999 | 586 | if(tx_length != rx_length) { |
<> | 149:156823d33999 | 587 | DEBUG_PRINTF("SPI: Full duplex transfer only 1 size: %d\n", size); |
<> | 149:156823d33999 | 588 | obj->tx_buff.length = size; |
<> | 149:156823d33999 | 589 | obj->rx_buff.length = size; |
<> | 149:156823d33999 | 590 | } |
<> | 149:156823d33999 | 591 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TXRX, tx, rx, size); |
<> | 149:156823d33999 | 592 | } else if (use_tx) { |
<> | 149:156823d33999 | 593 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_TX, tx, NULL, tx_length); |
<> | 149:156823d33999 | 594 | } else if (use_rx) { |
<> | 149:156823d33999 | 595 | spi_master_start_asynch_transfer(obj, SPI_TRANSFER_TYPE_RX, NULL, rx, rx_length); |
<> | 149:156823d33999 | 596 | } |
<> | 149:156823d33999 | 597 | } |
<> | 149:156823d33999 | 598 | |
<> | 153:fa9ff456f731 | 599 | inline uint32_t spi_irq_handler_asynch(spi_t *obj) |
<> | 149:156823d33999 | 600 | { |
<> | 149:156823d33999 | 601 | int event = 0; |
<> | 149:156823d33999 | 602 | |
<> | 149:156823d33999 | 603 | // call the CubeF4 handler, this will update the handle |
<> | 153:fa9ff456f731 | 604 | HAL_SPI_IRQHandler(&obj->spi.handle); |
<> | 149:156823d33999 | 605 | |
<> | 153:fa9ff456f731 | 606 | if (obj->spi.handle.State == HAL_SPI_STATE_READY) { |
<> | 149:156823d33999 | 607 | // When HAL SPI is back to READY state, check if there was an error |
<> | 153:fa9ff456f731 | 608 | int error = obj->spi.handle.ErrorCode; |
<> | 149:156823d33999 | 609 | if(error != HAL_SPI_ERROR_NONE) { |
<> | 149:156823d33999 | 610 | // something went wrong and the transfer has definitely completed |
<> | 149:156823d33999 | 611 | event = SPI_EVENT_ERROR | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; |
<> | 149:156823d33999 | 612 | |
<> | 149:156823d33999 | 613 | if (error & HAL_SPI_ERROR_OVR) { |
<> | 149:156823d33999 | 614 | // buffer overrun |
<> | 149:156823d33999 | 615 | event |= SPI_EVENT_RX_OVERFLOW; |
<> | 149:156823d33999 | 616 | } |
<> | 149:156823d33999 | 617 | } else { |
<> | 149:156823d33999 | 618 | // else we're done |
<> | 149:156823d33999 | 619 | event = SPI_EVENT_COMPLETE | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE; |
<> | 149:156823d33999 | 620 | } |
<> | 153:fa9ff456f731 | 621 | // enable the interrupt |
<> | 153:fa9ff456f731 | 622 | NVIC_DisableIRQ(obj->spi.spiIRQ); |
<> | 153:fa9ff456f731 | 623 | NVIC_ClearPendingIRQ(obj->spi.spiIRQ); |
<> | 149:156823d33999 | 624 | } |
<> | 149:156823d33999 | 625 | |
<> | 149:156823d33999 | 626 | |
<> | 149:156823d33999 | 627 | return (event & (obj->spi.event | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)); |
<> | 149:156823d33999 | 628 | } |
<> | 149:156823d33999 | 629 | |
<> | 149:156823d33999 | 630 | uint8_t spi_active(spi_t *obj) |
<> | 149:156823d33999 | 631 | { |
<> | 149:156823d33999 | 632 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 633 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 634 | HAL_SPI_StateTypeDef state = HAL_SPI_GetState(handle); |
<> | 149:156823d33999 | 635 | |
<> | 149:156823d33999 | 636 | switch(state) { |
<> | 149:156823d33999 | 637 | case HAL_SPI_STATE_RESET: |
<> | 149:156823d33999 | 638 | case HAL_SPI_STATE_READY: |
<> | 149:156823d33999 | 639 | case HAL_SPI_STATE_ERROR: |
<> | 149:156823d33999 | 640 | return 0; |
<> | 149:156823d33999 | 641 | default: |
<> | 149:156823d33999 | 642 | return 1; |
<> | 149:156823d33999 | 643 | } |
<> | 149:156823d33999 | 644 | } |
<> | 149:156823d33999 | 645 | |
<> | 149:156823d33999 | 646 | void spi_abort_asynch(spi_t *obj) |
<> | 149:156823d33999 | 647 | { |
<> | 149:156823d33999 | 648 | struct spi_s *spiobj = SPI_S(obj); |
<> | 149:156823d33999 | 649 | SPI_HandleTypeDef *handle = &(spiobj->handle); |
<> | 149:156823d33999 | 650 | |
<> | 149:156823d33999 | 651 | // disable interrupt |
<> | 149:156823d33999 | 652 | IRQn_Type irq_n = spiobj->spiIRQ; |
<> | 149:156823d33999 | 653 | NVIC_ClearPendingIRQ(irq_n); |
<> | 149:156823d33999 | 654 | NVIC_DisableIRQ(irq_n); |
<> | 149:156823d33999 | 655 | |
<> | 149:156823d33999 | 656 | // clean-up |
<> | 149:156823d33999 | 657 | __HAL_SPI_DISABLE(handle); |
<> | 149:156823d33999 | 658 | HAL_SPI_DeInit(handle); |
<> | 149:156823d33999 | 659 | HAL_SPI_Init(handle); |
<> | 149:156823d33999 | 660 | __HAL_SPI_ENABLE(handle); |
<> | 149:156823d33999 | 661 | } |
<> | 149:156823d33999 | 662 | |
<> | 149:156823d33999 | 663 | #endif //DEVICE_SPI_ASYNCH |
<> | 149:156823d33999 | 664 | |
<> | 149:156823d33999 | 665 | #endif |