Simple sample that demonstrates reading the FXOS8700CQ accelerometer, convert the data to JSON and send to an Azure IoT Hub.
Dependencies: azure_umqtt_c iothub_mqtt_transport mbed-rtos mbed wolfSSL Socket lwip-eth lwip-sys lwip
FXOS8700CQ/FXOS8700CQ.h@7:2564d95cbf81, 2017-04-25 (annotated)
- Committer:
- markrad
- Date:
- Tue Apr 25 01:33:13 2017 +0000
- Revision:
- 7:2564d95cbf81
- Parent:
- 6:0bffe8529f60
Fix bug in NTP library. Clean up code some.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
markrad | 6:0bffe8529f60 | 1 | #ifndef FXOS8700CQ_H |
markrad | 6:0bffe8529f60 | 2 | #define FXOS8700CQ_H |
markrad | 6:0bffe8529f60 | 3 | |
markrad | 6:0bffe8529f60 | 4 | #include "mbed.h" // Building this for the mbed platform |
markrad | 6:0bffe8529f60 | 5 | |
markrad | 6:0bffe8529f60 | 6 | #define I2C_400K 400000 |
markrad | 6:0bffe8529f60 | 7 | |
markrad | 6:0bffe8529f60 | 8 | // FXOS8700CQ I2C address |
markrad | 6:0bffe8529f60 | 9 | #define FXOS8700CQ_SLAVE_ADDR0 (0x1E<<1) // with pins SA0=0, SA1=0 |
markrad | 6:0bffe8529f60 | 10 | #define FXOS8700CQ_SLAVE_ADDR1 (0x1D<<1) // with pins SA0=1, SA1=0 |
markrad | 6:0bffe8529f60 | 11 | #define FXOS8700CQ_SLAVE_ADDR2 (0x1C<<1) // with pins SA0=0, SA1=1 |
markrad | 6:0bffe8529f60 | 12 | #define FXOS8700CQ_SLAVE_ADDR3 (0x1F<<1) // with pins SA0=1, SA1=1 |
markrad | 6:0bffe8529f60 | 13 | |
markrad | 6:0bffe8529f60 | 14 | // FXOS8700CQ internal register addresses |
markrad | 6:0bffe8529f60 | 15 | #define FXOS8700CQ_STATUS 0x00 |
markrad | 6:0bffe8529f60 | 16 | #define FXOS8700CQ_OUT_X_MSB 0x01 |
markrad | 6:0bffe8529f60 | 17 | #define FXOS8700CQ_WHOAMI 0x0D |
markrad | 6:0bffe8529f60 | 18 | #define FXOS8700CQ_M_OUT_X_MSB 0x33 |
markrad | 6:0bffe8529f60 | 19 | |
markrad | 6:0bffe8529f60 | 20 | #define FXOS8700CQ_XYZ_DATA_CFG 0x0E |
markrad | 6:0bffe8529f60 | 21 | |
markrad | 6:0bffe8529f60 | 22 | #define FXOS8700CQ_CTRL_REG1 0x2A |
markrad | 6:0bffe8529f60 | 23 | #define FXOS8700CQ_CTRL_REG2 0x2B |
markrad | 6:0bffe8529f60 | 24 | #define FXOS8700CQ_CTRL_REG3 0x2C |
markrad | 6:0bffe8529f60 | 25 | #define FXOS8700CQ_CTRL_REG4 0x2D |
markrad | 6:0bffe8529f60 | 26 | #define FXOS8700CQ_CTRL_REG5 0x2E |
markrad | 6:0bffe8529f60 | 27 | |
markrad | 6:0bffe8529f60 | 28 | #define FXOS8700CQ_M_CTRL_REG1 0x5B |
markrad | 6:0bffe8529f60 | 29 | #define FXOS8700CQ_M_CTRL_REG2 0x5C |
markrad | 6:0bffe8529f60 | 30 | #define FXOS8700CQ_M_CTRL_REG3 0x5D |
markrad | 6:0bffe8529f60 | 31 | |
markrad | 6:0bffe8529f60 | 32 | // FXOS8700CQ configuration macros, per register |
markrad | 6:0bffe8529f60 | 33 | |
markrad | 6:0bffe8529f60 | 34 | #define FXOS8700CQ_CTRL_REG1_ASLP_RATE2(x) (x << 6) // x is 2-bit |
markrad | 6:0bffe8529f60 | 35 | #define FXOS8700CQ_CTRL_REG1_DR3(x) (x << 3) // x is 3-bit |
markrad | 6:0bffe8529f60 | 36 | #define FXOS8700CQ_CTRL_REG1_LNOISE (1 << 2) |
markrad | 6:0bffe8529f60 | 37 | #define FXOS8700CQ_CTRL_REG1_F_READ (1 << 1) |
markrad | 6:0bffe8529f60 | 38 | #define FXOS8700CQ_CTRL_REG1_ACTIVE (1 << 0) |
markrad | 6:0bffe8529f60 | 39 | |
markrad | 6:0bffe8529f60 | 40 | #define FXOS8700CQ_CTRL_REG2_ST (1 << 7) |
markrad | 6:0bffe8529f60 | 41 | #define FXOS8700CQ_CTRL_REG2_RST (1 << 6) |
markrad | 6:0bffe8529f60 | 42 | #define FXOS8700CQ_CTRL_REG2_SMODS2(x) (x << 3) // x is 2-bit |
markrad | 6:0bffe8529f60 | 43 | #define FXOS8700CQ_CTRL_REG2_SLPE (1 << 2) |
markrad | 6:0bffe8529f60 | 44 | #define FXOS8700CQ_CTRL_REG2_MODS2(x) (x << 0) // x is 2-bit |
markrad | 6:0bffe8529f60 | 45 | |
markrad | 6:0bffe8529f60 | 46 | #define FXOS8700CQ_CTRL_REG3_FIFO_GATE (1 << 7) |
markrad | 6:0bffe8529f60 | 47 | #define FXOS8700CQ_CTRL_REG3_WAKE_TRANS (1 << 6) |
markrad | 6:0bffe8529f60 | 48 | #define FXOS8700CQ_CTRL_REG3_WAKE_LNDPRT (1 << 5) |
markrad | 6:0bffe8529f60 | 49 | #define FXOS8700CQ_CTRL_REG3_WAKE_PULSE (1 << 4) |
markrad | 6:0bffe8529f60 | 50 | #define FXOS8700CQ_CTRL_REG3_WAKE_FFMT (1 << 3) |
markrad | 6:0bffe8529f60 | 51 | #define FXOS8700CQ_CTRL_REG3_WAKE_A_VECM (1 << 2) |
markrad | 6:0bffe8529f60 | 52 | #define FXOS8700CQ_CTRL_REG3_IPOL (1 << 1) |
markrad | 6:0bffe8529f60 | 53 | #define FXOS8700CQ_CTRL_REG3_PP_OD (1 << 0) |
markrad | 6:0bffe8529f60 | 54 | |
markrad | 6:0bffe8529f60 | 55 | #define FXOS8700CQ_CTRL_REG4_INT_EN_ASLP (1 << 7) |
markrad | 6:0bffe8529f60 | 56 | #define FXOS8700CQ_CTRL_REG4_INT_EN_FIFO (1 << 6) |
markrad | 6:0bffe8529f60 | 57 | #define FXOS8700CQ_CTRL_REG4_INT_EN_TRANS (1 << 5) |
markrad | 6:0bffe8529f60 | 58 | #define FXOS8700CQ_CTRL_REG4_INT_EN_LNDPRT (1 << 4) |
markrad | 6:0bffe8529f60 | 59 | #define FXOS8700CQ_CTRL_REG4_INT_EN_PULSE (1 << 3) |
markrad | 6:0bffe8529f60 | 60 | #define FXOS8700CQ_CTRL_REG4_INT_EN_FFMT (1 << 2) |
markrad | 6:0bffe8529f60 | 61 | #define FXOS8700CQ_CTRL_REG4_INT_EN_A_VECM (1 << 1) |
markrad | 6:0bffe8529f60 | 62 | #define FXOS8700CQ_CTRL_REG4_INT_EN_DRDY (1 << 0) |
markrad | 6:0bffe8529f60 | 63 | |
markrad | 6:0bffe8529f60 | 64 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_ASLP (1 << 7) |
markrad | 6:0bffe8529f60 | 65 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_FIFO (1 << 6) |
markrad | 6:0bffe8529f60 | 66 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_TRANS (1 << 5) |
markrad | 6:0bffe8529f60 | 67 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_LNDPRT (1 << 4) |
markrad | 6:0bffe8529f60 | 68 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_PULSE (1 << 3) |
markrad | 6:0bffe8529f60 | 69 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_FFMT (1 << 2) |
markrad | 6:0bffe8529f60 | 70 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_A_VECM (1 << 1) |
markrad | 6:0bffe8529f60 | 71 | #define FXOS8700CQ_CTRL_REG5_INT_CFG_DRDY (1 << 0) |
markrad | 6:0bffe8529f60 | 72 | |
markrad | 6:0bffe8529f60 | 73 | #define FXOS8700CQ_XYZ_DATA_CFG_HPF_OUT (1 << 4) |
markrad | 6:0bffe8529f60 | 74 | #define FXOS8700CQ_XYZ_DATA_CFG_FS2(x) (x << 0) // x is 2-bit |
markrad | 6:0bffe8529f60 | 75 | |
markrad | 6:0bffe8529f60 | 76 | #define FXOS8700CQ_M_CTRL_REG1_M_ACAL (1 << 7) |
markrad | 6:0bffe8529f60 | 77 | #define FXOS8700CQ_M_CTRL_REG1_M_RST (1 << 6) |
markrad | 6:0bffe8529f60 | 78 | #define FXOS8700CQ_M_CTRL_REG1_M_OST (1 << 5) |
markrad | 6:0bffe8529f60 | 79 | #define FXOS8700CQ_M_CTRL_REG1_MO_OS3(x) (x << 2) // x is 3-bit |
markrad | 6:0bffe8529f60 | 80 | #define FXOS8700CQ_M_CTRL_REG1_M_HMS2(x) (x << 0) // x is 2-bit |
markrad | 6:0bffe8529f60 | 81 | |
markrad | 6:0bffe8529f60 | 82 | #define FXOS8700CQ_M_CTRL_REG2_HYB_AUTOINC_MODE (1 << 5) |
markrad | 6:0bffe8529f60 | 83 | #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS (1 << 4) |
markrad | 6:0bffe8529f60 | 84 | #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_DIS_THS (1 << 3) |
markrad | 6:0bffe8529f60 | 85 | #define FXOS8700CQ_M_CTRL_REG2_M_MAXMIN_RST (1 << 2) |
markrad | 6:0bffe8529f60 | 86 | #define FXOS8700CQ_M_CTRL_REG2_M_RST_CNT2(x) (x << 0) // x is 2-bit |
markrad | 6:0bffe8529f60 | 87 | |
markrad | 6:0bffe8529f60 | 88 | #define FXOS8700CQ_M_CTRL_REG3_M_RAW (1 << 7) |
markrad | 6:0bffe8529f60 | 89 | #define FXOS8700CQ_M_CTRL_REG3_M_ASLP_OS3(x) (x << 4) // x is 3-bit |
markrad | 6:0bffe8529f60 | 90 | #define FXOS8700CQ_M_CTRL_REG3_M_THS_XYZ_UPDATE (1 << 3) |
markrad | 6:0bffe8529f60 | 91 | #define FXOS8700CQ_M_CTRL_REG3_M_ST_Z (1 << 2) |
markrad | 6:0bffe8529f60 | 92 | #define FXOS8700CQ_M_CTRL_REG3_M_ST_XY2(x) (x << 0) // x is 2-bit |
markrad | 6:0bffe8529f60 | 93 | |
markrad | 6:0bffe8529f60 | 94 | // FXOS8700CQ WHOAMI production register value |
markrad | 6:0bffe8529f60 | 95 | #define FXOS8700CQ_WHOAMI_VAL 0xC7 |
markrad | 6:0bffe8529f60 | 96 | |
markrad | 6:0bffe8529f60 | 97 | // 6 channels of two bytes = 12 bytes; read from FXOS8700CQ_OUT_X_MSB |
markrad | 6:0bffe8529f60 | 98 | #define FXOS8700CQ_READ_LEN 12 |
markrad | 6:0bffe8529f60 | 99 | |
markrad | 6:0bffe8529f60 | 100 | // For processing the accelerometer data to right-justified 2's complement |
markrad | 6:0bffe8529f60 | 101 | #define UINT14_MAX 16383 |
markrad | 6:0bffe8529f60 | 102 | |
markrad | 6:0bffe8529f60 | 103 | // TODO: struct to hold the data out of the sensor |
markrad | 6:0bffe8529f60 | 104 | typedef struct { |
markrad | 6:0bffe8529f60 | 105 | int16_t x; |
markrad | 6:0bffe8529f60 | 106 | int16_t y; |
markrad | 6:0bffe8529f60 | 107 | int16_t z; |
markrad | 6:0bffe8529f60 | 108 | } SRAWDATA; |
markrad | 6:0bffe8529f60 | 109 | |
markrad | 6:0bffe8529f60 | 110 | |
markrad | 6:0bffe8529f60 | 111 | /** |
markrad | 6:0bffe8529f60 | 112 | * A driver on top of mbed-I2C to operate the FXOS8700CQ accelerometer/magnetometer |
markrad | 6:0bffe8529f60 | 113 | * on the FRDM-K64F. |
markrad | 6:0bffe8529f60 | 114 | * |
markrad | 6:0bffe8529f60 | 115 | * Code has been completed, but likely not optimized and potentially buggy. |
markrad | 6:0bffe8529f60 | 116 | */ |
markrad | 6:0bffe8529f60 | 117 | class FXOS8700CQ |
markrad | 6:0bffe8529f60 | 118 | { |
markrad | 6:0bffe8529f60 | 119 | public: |
markrad | 6:0bffe8529f60 | 120 | /** |
markrad | 6:0bffe8529f60 | 121 | * FXOS8700CQ constructor |
markrad | 6:0bffe8529f60 | 122 | * |
markrad | 6:0bffe8529f60 | 123 | * @param sda SDA pin |
markrad | 6:0bffe8529f60 | 124 | * @param sdl SCL pin |
markrad | 6:0bffe8529f60 | 125 | * @param addr address of the I2C peripheral in (7-bit << 1) form |
markrad | 6:0bffe8529f60 | 126 | */ |
markrad | 6:0bffe8529f60 | 127 | FXOS8700CQ(PinName sda, PinName scl, int addr); |
markrad | 6:0bffe8529f60 | 128 | |
markrad | 6:0bffe8529f60 | 129 | /** |
markrad | 6:0bffe8529f60 | 130 | * FXOS8700CQ destructor |
markrad | 6:0bffe8529f60 | 131 | */ |
markrad | 6:0bffe8529f60 | 132 | ~FXOS8700CQ(void); |
markrad | 6:0bffe8529f60 | 133 | |
markrad | 6:0bffe8529f60 | 134 | void enable(void); |
markrad | 6:0bffe8529f60 | 135 | void disable(void); |
markrad | 6:0bffe8529f60 | 136 | |
markrad | 6:0bffe8529f60 | 137 | /** |
markrad | 6:0bffe8529f60 | 138 | * @return the contents of device register FXOS8700CQ_WHOAMI 0x0D, |
markrad | 6:0bffe8529f60 | 139 | * should be FXOS8700CQ_WHOAMI_VAL 0xC7 |
markrad | 6:0bffe8529f60 | 140 | */ |
markrad | 6:0bffe8529f60 | 141 | uint8_t get_whoami(void); |
markrad | 6:0bffe8529f60 | 142 | |
markrad | 6:0bffe8529f60 | 143 | /** |
markrad | 6:0bffe8529f60 | 144 | * @return the contents of device register FXOS8700CQ_STATUS 0x00 |
markrad | 6:0bffe8529f60 | 145 | */ |
markrad | 6:0bffe8529f60 | 146 | uint8_t status(void); |
markrad | 6:0bffe8529f60 | 147 | |
markrad | 6:0bffe8529f60 | 148 | /** |
markrad | 6:0bffe8529f60 | 149 | * Data retrieval from the FXOS8700CQ |
markrad | 6:0bffe8529f60 | 150 | * |
markrad | 6:0bffe8529f60 | 151 | * @param accel_data destination XYZ accelerometer data struct |
markrad | 6:0bffe8529f60 | 152 | * @param magn_data destination XYZ magnetometer data struct |
markrad | 6:0bffe8529f60 | 153 | * @return 0 on success, non-zero on failure |
markrad | 6:0bffe8529f60 | 154 | */ |
markrad | 6:0bffe8529f60 | 155 | uint8_t get_data(SRAWDATA *accel_data, SRAWDATA *magn_data); |
markrad | 6:0bffe8529f60 | 156 | |
markrad | 6:0bffe8529f60 | 157 | /** |
markrad | 6:0bffe8529f60 | 158 | * Retrieve the full-range scale value of the accelerometer |
markrad | 6:0bffe8529f60 | 159 | * |
markrad | 6:0bffe8529f60 | 160 | * @return 2, 4, or 8, depending on part configuration; 0 on error |
markrad | 6:0bffe8529f60 | 161 | */ |
markrad | 6:0bffe8529f60 | 162 | uint8_t get_accel_scale(void); |
markrad | 6:0bffe8529f60 | 163 | |
markrad | 6:0bffe8529f60 | 164 | |
markrad | 6:0bffe8529f60 | 165 | |
markrad | 6:0bffe8529f60 | 166 | private: |
markrad | 6:0bffe8529f60 | 167 | I2C dev_i2c; // instance of the mbed I2C class |
markrad | 6:0bffe8529f60 | 168 | uint8_t dev_addr; // Device I2C address, in (7-bit << 1) form |
markrad | 6:0bffe8529f60 | 169 | bool enabled; // keep track of enable bit of device |
markrad | 6:0bffe8529f60 | 170 | |
markrad | 6:0bffe8529f60 | 171 | // I2C helper methods |
markrad | 6:0bffe8529f60 | 172 | void read_regs(int reg_addr, uint8_t* data, int len); |
markrad | 6:0bffe8529f60 | 173 | void write_regs(uint8_t* data, int len); |
markrad | 6:0bffe8529f60 | 174 | |
markrad | 6:0bffe8529f60 | 175 | }; |
markrad | 6:0bffe8529f60 | 176 | |
markrad | 6:0bffe8529f60 | 177 | #endif |