Marek Trojan / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c@66:fdb3f9f9a72f, 2016-02-18 (annotated)

Committer:
mbed_official
Date:
Thu Feb 18 09:45:10 2016 +0000
Revision:
66:fdb3f9f9a72f
Parent:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Synchronized with git revision b57f7d56840134d072ca567460a86b77fb7adcf8



Full URL: https://github.com/mbedmicro/mbed/commit/b57f7d56840134d072ca567460a86b77fb7adcf8/



Support of export function to the IAR.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <string.h>
bogdanm 0:9b334a45a8ff 17 #include "ethernet_api.h"
bogdanm 0:9b334a45a8ff 18 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 19 #include "mbed_interface.h"
bogdanm 0:9b334a45a8ff 20 #include "toolchain.h"
bogdanm 0:9b334a45a8ff 21 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 22 #include "ether_iodefine.h"
bogdanm 0:9b334a45a8ff 23 #include "ethernetext_api.h"
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 /* Descriptor info */
bogdanm 0:9b334a45a8ff 26 #define NUM_OF_TX_DESCRIPTOR (16)
bogdanm 0:9b334a45a8ff 27 #define NUM_OF_RX_DESCRIPTOR (16)
bogdanm 0:9b334a45a8ff 28 #define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
bogdanm 0:9b334a45a8ff 29 #define MAX_SEND_SIZE (1514)
bogdanm 0:9b334a45a8ff 30 /* Ethernet Descriptor Value Define */
bogdanm 0:9b334a45a8ff 31 #define TD0_TFP_TOP_BOTTOM (0x30000000)
bogdanm 0:9b334a45a8ff 32 #define TD0_TACT (0x80000000)
bogdanm 0:9b334a45a8ff 33 #define TD0_TDLE (0x40000000)
bogdanm 0:9b334a45a8ff 34 #define RD0_RACT (0x80000000)
bogdanm 0:9b334a45a8ff 35 #define RD0_RDLE (0x40000000)
bogdanm 0:9b334a45a8ff 36 #define RD0_RFE (0x08000000)
bogdanm 0:9b334a45a8ff 37 #define RD0_RCSE (0x04000000)
bogdanm 0:9b334a45a8ff 38 #define RD0_RFS (0x03FF0000)
bogdanm 0:9b334a45a8ff 39 #define RD0_RCS (0x0000FFFF)
bogdanm 0:9b334a45a8ff 40 #define RD0_RFS_RFOF (0x02000000)
bogdanm 0:9b334a45a8ff 41 #define RD0_RFS_RUAF (0x00400000)
bogdanm 0:9b334a45a8ff 42 #define RD0_RFS_RRF (0x00100000)
bogdanm 0:9b334a45a8ff 43 #define RD0_RFS_RTLF (0x00080000)
bogdanm 0:9b334a45a8ff 44 #define RD0_RFS_RTSF (0x00040000)
bogdanm 0:9b334a45a8ff 45 #define RD0_RFS_PRE (0x00020000)
bogdanm 0:9b334a45a8ff 46 #define RD0_RFS_CERF (0x00010000)
bogdanm 0:9b334a45a8ff 47 #define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
bogdanm 0:9b334a45a8ff 48 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
bogdanm 0:9b334a45a8ff 49 #define RD1_RDL_MSK (0x0000FFFF)
bogdanm 0:9b334a45a8ff 50 /* PHY Register */
bogdanm 0:9b334a45a8ff 51 #define BASIC_MODE_CONTROL_REG (0)
bogdanm 0:9b334a45a8ff 52 #define BASIC_MODE_STATUS_REG (1)
bogdanm 0:9b334a45a8ff 53 #define PHY_IDENTIFIER1_REG (2)
bogdanm 0:9b334a45a8ff 54 #define PHY_IDENTIFIER2_REG (3)
bogdanm 0:9b334a45a8ff 55 #define PHY_SP_CTL_STS_REG (31)
bogdanm 0:9b334a45a8ff 56 /* MII management interface access */
bogdanm 0:9b334a45a8ff 57 #define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
bogdanm 0:9b334a45a8ff 58 #define PHY_ST (1)
bogdanm 0:9b334a45a8ff 59 #define PHY_WRITE (1)
bogdanm 0:9b334a45a8ff 60 #define PHY_READ (2)
bogdanm 0:9b334a45a8ff 61 #define MDC_WAIT (6) /* 400ns/4 */
bogdanm 0:9b334a45a8ff 62 #define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
mbed_official 66:fdb3f9f9a72f 63 #define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */
bogdanm 0:9b334a45a8ff 64 #define M_PHY_ID (0xFFFFFFF0)
bogdanm 0:9b334a45a8ff 65 #define PHY_ID_LAN8710A (0x0007C0F0)
bogdanm 0:9b334a45a8ff 66 /* ETHERPIR0 */
bogdanm 0:9b334a45a8ff 67 #define PIR0_MDI (0x00000008)
bogdanm 0:9b334a45a8ff 68 #define PIR0_MDO (0x00000004)
bogdanm 0:9b334a45a8ff 69 #define PIR0_MMD (0x00000002)
bogdanm 0:9b334a45a8ff 70 #define PIR0_MDC (0x00000001)
bogdanm 0:9b334a45a8ff 71 #define PIR0_MDC_HIGH (0x00000001)
bogdanm 0:9b334a45a8ff 72 #define PIR0_MDC_LOW (0x00000000)
bogdanm 0:9b334a45a8ff 73 /* ETHEREDRRR0 */
bogdanm 0:9b334a45a8ff 74 #define EDRRR0_RR (0x00000001)
bogdanm 0:9b334a45a8ff 75 /* ETHEREDTRR0 */
bogdanm 0:9b334a45a8ff 76 #define EDTRR0_TR (0x00000003)
bogdanm 0:9b334a45a8ff 77 /* software wait */
bogdanm 0:9b334a45a8ff 78 #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
bogdanm 0:9b334a45a8ff 81 /* 0x00040000 : Detect frame reception */
bogdanm 0:9b334a45a8ff 82 /* 0x00010000 : Receive FIFO overflow */
bogdanm 0:9b334a45a8ff 83 /* 0x00000010 : Residual bit frame reception */
bogdanm 0:9b334a45a8ff 84 /* 0x00000008 : Long frame reception */
bogdanm 0:9b334a45a8ff 85 /* 0x00000004 : Short frame reception */
bogdanm 0:9b334a45a8ff 86 /* 0x00000002 : PHY-LSI reception error */
bogdanm 0:9b334a45a8ff 87 /* 0x00000001 : Receive frame CRC error */
bogdanm 0:9b334a45a8ff 88 #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /* Send descriptor */
bogdanm 0:9b334a45a8ff 91 typedef struct tag_edmac_send_desc {
bogdanm 0:9b334a45a8ff 92 uint32_t td0;
bogdanm 0:9b334a45a8ff 93 uint32_t td1;
bogdanm 0:9b334a45a8ff 94 uint8_t *td2;
bogdanm 0:9b334a45a8ff 95 uint32_t padding4;
bogdanm 0:9b334a45a8ff 96 } edmac_send_desc_t;
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /* Receive descriptor */
bogdanm 0:9b334a45a8ff 99 typedef struct tag_edmac_recv_desc {
bogdanm 0:9b334a45a8ff 100 uint32_t rd0;
bogdanm 0:9b334a45a8ff 101 uint32_t rd1;
bogdanm 0:9b334a45a8ff 102 uint8_t *rd2;
bogdanm 0:9b334a45a8ff 103 uint32_t padding4;
bogdanm 0:9b334a45a8ff 104 } edmac_recv_desc_t;
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /* memory */
bogdanm 0:9b334a45a8ff 107 /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
bogdanm 0:9b334a45a8ff 108 /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
mbed_official 66:fdb3f9f9a72f 109 #if defined(__ICCARM__)
mbed_official 66:fdb3f9f9a72f 110 #pragma data_alignment=16
mbed_official 66:fdb3f9f9a72f 111 static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
mbed_official 66:fdb3f9f9a72f 112 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
mbed_official 66:fdb3f9f9a72f 113 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
mbed_official 66:fdb3f9f9a72f 114 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned!
mbed_official 66:fdb3f9f9a72f 115 @ ".mirrorram";
mbed_official 66:fdb3f9f9a72f 116 #else
mbed_official 66:fdb3f9f9a72f 117 static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
bogdanm 0:9b334a45a8ff 118 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
bogdanm 0:9b334a45a8ff 119 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
bogdanm 0:9b334a45a8ff 120 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
bogdanm 0:9b334a45a8ff 121 __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
mbed_official 66:fdb3f9f9a72f 122 #endif
bogdanm 0:9b334a45a8ff 123 static int32_t rx_read_offset; /* read offset */
bogdanm 0:9b334a45a8ff 124 static int32_t tx_wite_offset; /* write offset */
bogdanm 0:9b334a45a8ff 125 static uint32_t send_top_index;
bogdanm 0:9b334a45a8ff 126 static uint32_t recv_top_index;
bogdanm 0:9b334a45a8ff 127 static int32_t Interrupt_priority;
bogdanm 0:9b334a45a8ff 128 static edmac_send_desc_t *p_eth_desc_dsend = NULL;
bogdanm 0:9b334a45a8ff 129 static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
bogdanm 0:9b334a45a8ff 130 static edmac_recv_desc_t *p_recv_end_desc = NULL;
bogdanm 0:9b334a45a8ff 131 static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
bogdanm 0:9b334a45a8ff 132 static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
bogdanm 0:9b334a45a8ff 133 static uint32_t phy_id = 0;
bogdanm 0:9b334a45a8ff 134 static uint32_t start_stop = 1; /* 0:stop 1:start */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 /* function */
bogdanm 0:9b334a45a8ff 137 static void lan_reg_reset(void);
bogdanm 0:9b334a45a8ff 138 static void lan_desc_create(void);
bogdanm 0:9b334a45a8ff 139 static void lan_reg_set(int32_t link);
bogdanm 0:9b334a45a8ff 140 static uint16_t phy_reg_read(uint16_t reg_addr);
bogdanm 0:9b334a45a8ff 141 static void phy_reg_write(uint16_t reg_addr, uint16_t data);
bogdanm 0:9b334a45a8ff 142 static void mii_preamble(void);
bogdanm 0:9b334a45a8ff 143 static void mii_cmd(uint16_t reg_addr, uint32_t option);
bogdanm 0:9b334a45a8ff 144 static void mii_reg_read(uint16_t *data);
bogdanm 0:9b334a45a8ff 145 static void mii_reg_write(uint16_t data);
bogdanm 0:9b334a45a8ff 146 static void mii_z(void);
bogdanm 0:9b334a45a8ff 147 static void mii_write_1(void);
bogdanm 0:9b334a45a8ff 148 static void mii_write_0(void);
bogdanm 0:9b334a45a8ff 149 static void set_ether_pir(uint32_t set_data);
bogdanm 0:9b334a45a8ff 150 static void wait_100us(int32_t wait_cnt);
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152
bogdanm 0:9b334a45a8ff 153 int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
bogdanm 0:9b334a45a8ff 154 int32_t i;
bogdanm 0:9b334a45a8ff 155 uint16_t val;
bogdanm 0:9b334a45a8ff 156
bogdanm 0:9b334a45a8ff 157 CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
bogdanm 0:9b334a45a8ff 158
bogdanm 0:9b334a45a8ff 159 /* P4_2(PHY Reset) */
bogdanm 0:9b334a45a8ff 160 GPIOP4 &= ~0x0004; /* Outputs low level */
bogdanm 0:9b334a45a8ff 161 GPIOPMC4 &= ~0x0004; /* Port mode */
bogdanm 0:9b334a45a8ff 162 GPIOPM4 &= ~0x0004; /* Output mode */
bogdanm 0:9b334a45a8ff 163
bogdanm 0:9b334a45a8ff 164 /* GPIO P1 P1_14(ET_COL) */
bogdanm 0:9b334a45a8ff 165 GPIOPMC1 |= 0x4000;
bogdanm 0:9b334a45a8ff 166 GPIOPFCAE1 &= ~0x4000;
bogdanm 0:9b334a45a8ff 167 GPIOPFCE1 |= 0x4000;
bogdanm 0:9b334a45a8ff 168 GPIOPFC1 |= 0x4000;
bogdanm 0:9b334a45a8ff 169
bogdanm 0:9b334a45a8ff 170 /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
bogdanm 0:9b334a45a8ff 171 GPIOPMC3 |= 0x0079;
bogdanm 0:9b334a45a8ff 172 GPIOPFCAE3 &= ~0x0079;
bogdanm 0:9b334a45a8ff 173 GPIOPFCE3 &= ~0x0079;
bogdanm 0:9b334a45a8ff 174 GPIOPFC3 |= 0x0079;
bogdanm 0:9b334a45a8ff 175 GPIOPIPC3 |= 0x0079;
bogdanm 0:9b334a45a8ff 176
bogdanm 0:9b334a45a8ff 177 /* P5_9(ET_MDC) */
bogdanm 0:9b334a45a8ff 178 GPIOPMC5 |= 0x0200;
bogdanm 0:9b334a45a8ff 179 GPIOPFCAE5 &= ~0x0200;
bogdanm 0:9b334a45a8ff 180 GPIOPFCE5 &= ~0x0200;
bogdanm 0:9b334a45a8ff 181 GPIOPFC5 |= 0x0200;
bogdanm 0:9b334a45a8ff 182 GPIOPIPC5 |= 0x0200;
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
bogdanm 0:9b334a45a8ff 185 /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
bogdanm 0:9b334a45a8ff 186 GPIOPMC10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 187 GPIOPFCAE10 &= ~0x0FFE;
bogdanm 0:9b334a45a8ff 188 GPIOPFCE10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 189 GPIOPFC10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 190 GPIOPIPC10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /* Resets the E-MAC,E-DMAC */
bogdanm 0:9b334a45a8ff 193 lan_reg_reset();
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 /* PHY Reset */
bogdanm 0:9b334a45a8ff 196 GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */
bogdanm 0:9b334a45a8ff 197 wait_100us(250); /* 25msec */
bogdanm 0:9b334a45a8ff 198 GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
bogdanm 0:9b334a45a8ff 199 wait_100us(100); /* 10msec */
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 /* Resets the PHY-LSI */
bogdanm 0:9b334a45a8ff 202 phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
bogdanm 0:9b334a45a8ff 203 for (i = 10000; i > 0; i--) {
bogdanm 0:9b334a45a8ff 204 val = phy_reg_read(BASIC_MODE_CONTROL_REG);
bogdanm 0:9b334a45a8ff 205 if (((uint32_t)val & 0x8000uL) == 0) {
bogdanm 0:9b334a45a8ff 206 break; /* Reset complete */
bogdanm 0:9b334a45a8ff 207 }
bogdanm 0:9b334a45a8ff 208 }
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
bogdanm 0:9b334a45a8ff 211 | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
bogdanm 0:9b334a45a8ff 212
bogdanm 0:9b334a45a8ff 213 Interrupt_priority = p_ethcfg->int_priority;
bogdanm 0:9b334a45a8ff 214 p_recv_cb_fnc = p_ethcfg->recv_cb;
bogdanm 0:9b334a45a8ff 215 start_stop = 1;
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 if (p_ethcfg->ether_mac != NULL) {
bogdanm 0:9b334a45a8ff 218 (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
bogdanm 0:9b334a45a8ff 219 } else {
mbed_official 66:fdb3f9f9a72f 220 ethernet_address(mac_addr); /* Get MAC Address */
bogdanm 0:9b334a45a8ff 221 }
bogdanm 0:9b334a45a8ff 222
bogdanm 0:9b334a45a8ff 223 return 0;
bogdanm 0:9b334a45a8ff 224 }
bogdanm 0:9b334a45a8ff 225
bogdanm 0:9b334a45a8ff 226 void ethernetext_start_stop(int32_t mode) {
bogdanm 0:9b334a45a8ff 227 if (mode == 1) {
bogdanm 0:9b334a45a8ff 228 /* start */
bogdanm 0:9b334a45a8ff 229 ETHEREDTRR0 |= EDTRR0_TR;
bogdanm 0:9b334a45a8ff 230 ETHEREDRRR0 |= EDRRR0_RR;
bogdanm 0:9b334a45a8ff 231 start_stop = 1;
bogdanm 0:9b334a45a8ff 232 } else {
bogdanm 0:9b334a45a8ff 233 /* stop */
bogdanm 0:9b334a45a8ff 234 ETHEREDTRR0 &= ~EDTRR0_TR;
bogdanm 0:9b334a45a8ff 235 ETHEREDRRR0 &= ~EDRRR0_RR;
bogdanm 0:9b334a45a8ff 236 start_stop = 0;
bogdanm 0:9b334a45a8ff 237 }
bogdanm 0:9b334a45a8ff 238 }
bogdanm 0:9b334a45a8ff 239
bogdanm 0:9b334a45a8ff 240 int ethernetext_chk_link_mode(void) {
bogdanm 0:9b334a45a8ff 241 int32_t link;
bogdanm 0:9b334a45a8ff 242 uint16_t data;
bogdanm 0:9b334a45a8ff 243
bogdanm 0:9b334a45a8ff 244 if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
bogdanm 0:9b334a45a8ff 245 data = phy_reg_read(PHY_SP_CTL_STS_REG);
bogdanm 0:9b334a45a8ff 246 switch (((uint32_t)data >> 2) & 0x00000007) {
bogdanm 0:9b334a45a8ff 247 case 0x0001:
bogdanm 0:9b334a45a8ff 248 link = HALF_10M;
bogdanm 0:9b334a45a8ff 249 break;
bogdanm 0:9b334a45a8ff 250 case 0x0005:
bogdanm 0:9b334a45a8ff 251 link = FULL_10M;
bogdanm 0:9b334a45a8ff 252 break;
bogdanm 0:9b334a45a8ff 253 case 0x0002:
bogdanm 0:9b334a45a8ff 254 link = HALF_TX;
bogdanm 0:9b334a45a8ff 255 break;
bogdanm 0:9b334a45a8ff 256 case 0x0006:
bogdanm 0:9b334a45a8ff 257 link = FULL_TX;
bogdanm 0:9b334a45a8ff 258 break;
bogdanm 0:9b334a45a8ff 259 default:
bogdanm 0:9b334a45a8ff 260 link = NEGO_FAIL;
bogdanm 0:9b334a45a8ff 261 break;
bogdanm 0:9b334a45a8ff 262 }
bogdanm 0:9b334a45a8ff 263 } else {
bogdanm 0:9b334a45a8ff 264 link = NEGO_FAIL;
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 return link;
bogdanm 0:9b334a45a8ff 268 }
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 void ethernetext_set_link_mode(int32_t link) {
bogdanm 0:9b334a45a8ff 271 lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
bogdanm 0:9b334a45a8ff 272 lan_desc_create(); /* Initialize of buffer memory */
bogdanm 0:9b334a45a8ff 273 lan_reg_set(link); /* E-DMAC, E-MAC initialization */
bogdanm 0:9b334a45a8ff 274 }
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 int ethernet_init() {
bogdanm 0:9b334a45a8ff 277 ethernet_cfg_t ethcfg;
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 ethcfg.int_priority = 5;
bogdanm 0:9b334a45a8ff 280 ethcfg.recv_cb = NULL;
bogdanm 0:9b334a45a8ff 281 ethcfg.ether_mac = NULL;
bogdanm 0:9b334a45a8ff 282 ethernetext_init(&ethcfg);
bogdanm 0:9b334a45a8ff 283 ethernet_set_link(-1, 0); /* Auto-Negotiation */
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 return 0;
bogdanm 0:9b334a45a8ff 286 }
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 void ethernet_free() {
bogdanm 0:9b334a45a8ff 289 ETHERARSTR |= 0x00000001; /* ETHER software reset */
bogdanm 0:9b334a45a8ff 290 CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
bogdanm 0:9b334a45a8ff 291 }
bogdanm 0:9b334a45a8ff 292
bogdanm 0:9b334a45a8ff 293 int ethernet_write(const char *data, int slen) {
bogdanm 0:9b334a45a8ff 294 edmac_send_desc_t *p_send_desc;
bogdanm 0:9b334a45a8ff 295 int32_t copy_size;
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
bogdanm 0:9b334a45a8ff 298 || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
bogdanm 0:9b334a45a8ff 299 copy_size = 0;
bogdanm 0:9b334a45a8ff 300 } else {
bogdanm 0:9b334a45a8ff 301 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
bogdanm 0:9b334a45a8ff 302 if ((p_send_desc->td0 & TD0_TACT) != 0) {
bogdanm 0:9b334a45a8ff 303 copy_size = 0;
bogdanm 0:9b334a45a8ff 304 } else {
bogdanm 0:9b334a45a8ff 305 copy_size = MAX_SEND_SIZE - tx_wite_offset;
bogdanm 0:9b334a45a8ff 306 if (copy_size > slen) {
bogdanm 0:9b334a45a8ff 307 copy_size = slen;
bogdanm 0:9b334a45a8ff 308 }
bogdanm 0:9b334a45a8ff 309 (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
bogdanm 0:9b334a45a8ff 310 tx_wite_offset += copy_size;
bogdanm 0:9b334a45a8ff 311 }
bogdanm 0:9b334a45a8ff 312 }
bogdanm 0:9b334a45a8ff 313
bogdanm 0:9b334a45a8ff 314 return copy_size;
bogdanm 0:9b334a45a8ff 315 }
bogdanm 0:9b334a45a8ff 316
bogdanm 0:9b334a45a8ff 317 int ethernet_send() {
bogdanm 0:9b334a45a8ff 318 edmac_send_desc_t *p_send_desc;
bogdanm 0:9b334a45a8ff 319 int32_t ret;
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
bogdanm 0:9b334a45a8ff 322 ret = 0;
bogdanm 0:9b334a45a8ff 323 } else {
bogdanm 0:9b334a45a8ff 324 /* Transfer 1 frame */
bogdanm 0:9b334a45a8ff 325 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
bogdanm 0:9b334a45a8ff 326
bogdanm 0:9b334a45a8ff 327 /* Sets the frame length */
bogdanm 0:9b334a45a8ff 328 p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
bogdanm 0:9b334a45a8ff 329 tx_wite_offset = 0;
bogdanm 0:9b334a45a8ff 330
bogdanm 0:9b334a45a8ff 331 /* Sets the transmit descriptor to transmit again */
bogdanm 0:9b334a45a8ff 332 p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
bogdanm 0:9b334a45a8ff 333 p_send_desc->td0 |= TD0_TACT;
bogdanm 0:9b334a45a8ff 334 if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
bogdanm 0:9b334a45a8ff 335 ETHEREDTRR0 |= EDTRR0_TR;
bogdanm 0:9b334a45a8ff 336 }
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /* Update the current descriptor */
bogdanm 0:9b334a45a8ff 339 send_top_index++;
bogdanm 0:9b334a45a8ff 340 if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
bogdanm 0:9b334a45a8ff 341 send_top_index = 0;
bogdanm 0:9b334a45a8ff 342 }
bogdanm 0:9b334a45a8ff 343 ret = 1;
bogdanm 0:9b334a45a8ff 344 }
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 return ret;
bogdanm 0:9b334a45a8ff 347 }
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 int ethernet_receive() {
bogdanm 0:9b334a45a8ff 350 edmac_recv_desc_t *p_recv_desc;
bogdanm 0:9b334a45a8ff 351 int32_t receive_size = 0;
bogdanm 0:9b334a45a8ff 352
bogdanm 0:9b334a45a8ff 353 if (p_eth_desc_drecv != NULL) {
bogdanm 0:9b334a45a8ff 354 if (p_recv_end_desc != NULL) {
bogdanm 0:9b334a45a8ff 355 /* Sets the receive descriptor to receive again */
bogdanm 0:9b334a45a8ff 356 p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
bogdanm 0:9b334a45a8ff 357 p_recv_end_desc->rd0 |= RD0_RACT;
bogdanm 0:9b334a45a8ff 358 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
bogdanm 0:9b334a45a8ff 359 ETHEREDRRR0 |= EDRRR0_RR;
bogdanm 0:9b334a45a8ff 360 }
bogdanm 0:9b334a45a8ff 361 p_recv_end_desc = NULL;
bogdanm 0:9b334a45a8ff 362 }
bogdanm 0:9b334a45a8ff 363
bogdanm 0:9b334a45a8ff 364 p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
bogdanm 0:9b334a45a8ff 365 if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
bogdanm 0:9b334a45a8ff 366 /* Receives 1 frame */
bogdanm 0:9b334a45a8ff 367 if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
bogdanm 0:9b334a45a8ff 368 /* Receive frame error */
bogdanm 0:9b334a45a8ff 369 /* Sets the receive descriptor to receive again */
bogdanm 0:9b334a45a8ff 370 p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
bogdanm 0:9b334a45a8ff 371 p_recv_desc->rd0 |= RD0_RACT;
bogdanm 0:9b334a45a8ff 372 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
bogdanm 0:9b334a45a8ff 373 ETHEREDRRR0 |= EDRRR0_RR;
bogdanm 0:9b334a45a8ff 374 }
bogdanm 0:9b334a45a8ff 375 } else {
bogdanm 0:9b334a45a8ff 376 /* Copies the received frame */
bogdanm 0:9b334a45a8ff 377 rx_read_offset = 0;
bogdanm 0:9b334a45a8ff 378 p_recv_end_desc = p_recv_desc;
bogdanm 0:9b334a45a8ff 379 receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
bogdanm 0:9b334a45a8ff 380 }
bogdanm 0:9b334a45a8ff 381
bogdanm 0:9b334a45a8ff 382 /* Update the current descriptor */
bogdanm 0:9b334a45a8ff 383 recv_top_index++;
bogdanm 0:9b334a45a8ff 384 if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
bogdanm 0:9b334a45a8ff 385 recv_top_index = 0;
bogdanm 0:9b334a45a8ff 386 }
bogdanm 0:9b334a45a8ff 387 }
bogdanm 0:9b334a45a8ff 388 }
bogdanm 0:9b334a45a8ff 389
bogdanm 0:9b334a45a8ff 390 return receive_size;
bogdanm 0:9b334a45a8ff 391 }
bogdanm 0:9b334a45a8ff 392
bogdanm 0:9b334a45a8ff 393 int ethernet_read(char *data, int dlen) {
bogdanm 0:9b334a45a8ff 394 edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
bogdanm 0:9b334a45a8ff 395 int32_t copy_size;
bogdanm 0:9b334a45a8ff 396
bogdanm 0:9b334a45a8ff 397 if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
bogdanm 0:9b334a45a8ff 398 copy_size = 0;
bogdanm 0:9b334a45a8ff 399 } else {
bogdanm 0:9b334a45a8ff 400 copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
bogdanm 0:9b334a45a8ff 401 if (copy_size > dlen) {
bogdanm 0:9b334a45a8ff 402 copy_size = dlen;
bogdanm 0:9b334a45a8ff 403 }
bogdanm 0:9b334a45a8ff 404 (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
bogdanm 0:9b334a45a8ff 405 rx_read_offset += copy_size;
bogdanm 0:9b334a45a8ff 406 }
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 return copy_size;
bogdanm 0:9b334a45a8ff 409 }
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 void ethernet_address(char *mac) {
bogdanm 0:9b334a45a8ff 412 if (mac != NULL) {
mbed_official 66:fdb3f9f9a72f 413 mbed_mac_address(mac); /* Get MAC Address */
bogdanm 0:9b334a45a8ff 414 }
bogdanm 0:9b334a45a8ff 415 }
bogdanm 0:9b334a45a8ff 416
bogdanm 0:9b334a45a8ff 417 int ethernet_link(void) {
bogdanm 0:9b334a45a8ff 418 int32_t ret;
bogdanm 0:9b334a45a8ff 419 uint16_t data;
bogdanm 0:9b334a45a8ff 420
bogdanm 0:9b334a45a8ff 421 data = phy_reg_read(BASIC_MODE_STATUS_REG);
bogdanm 0:9b334a45a8ff 422 if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
bogdanm 0:9b334a45a8ff 423 ret = 1;
bogdanm 0:9b334a45a8ff 424 } else {
bogdanm 0:9b334a45a8ff 425 ret = 0;
bogdanm 0:9b334a45a8ff 426 }
bogdanm 0:9b334a45a8ff 427
bogdanm 0:9b334a45a8ff 428 return ret;
bogdanm 0:9b334a45a8ff 429 }
bogdanm 0:9b334a45a8ff 430
bogdanm 0:9b334a45a8ff 431 void ethernet_set_link(int speed, int duplex) {
bogdanm 0:9b334a45a8ff 432 uint16_t data;
bogdanm 0:9b334a45a8ff 433 int32_t i;
bogdanm 0:9b334a45a8ff 434 int32_t link;
bogdanm 0:9b334a45a8ff 435
bogdanm 0:9b334a45a8ff 436 if ((speed < 0) || (speed > 1)) {
bogdanm 0:9b334a45a8ff 437 data = 0x1000; /* Auto-Negotiation Enable */
bogdanm 0:9b334a45a8ff 438 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
bogdanm 0:9b334a45a8ff 439 for (i = 0; i < 1000; i++) {
mbed_official 66:fdb3f9f9a72f 440 data = phy_reg_read(BASIC_MODE_STATUS_REG);
bogdanm 0:9b334a45a8ff 441 if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
bogdanm 0:9b334a45a8ff 442 break;
bogdanm 0:9b334a45a8ff 443 }
bogdanm 0:9b334a45a8ff 444 wait_100us(10);
bogdanm 0:9b334a45a8ff 445 }
bogdanm 0:9b334a45a8ff 446 } else {
bogdanm 0:9b334a45a8ff 447 data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
bogdanm 0:9b334a45a8ff 448 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
bogdanm 0:9b334a45a8ff 449 wait_100us(1);
bogdanm 0:9b334a45a8ff 450 }
bogdanm 0:9b334a45a8ff 451
bogdanm 0:9b334a45a8ff 452 link = ethernetext_chk_link_mode();
bogdanm 0:9b334a45a8ff 453 ethernetext_set_link_mode(link);
bogdanm 0:9b334a45a8ff 454 }
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 void INT_Ether(void) {
bogdanm 0:9b334a45a8ff 457 uint32_t stat_edmac;
bogdanm 0:9b334a45a8ff 458 uint32_t stat_etherc;
bogdanm 0:9b334a45a8ff 459
bogdanm 0:9b334a45a8ff 460 /* Clear the interrupt request flag */
bogdanm 0:9b334a45a8ff 461 stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
bogdanm 0:9b334a45a8ff 462 ETHEREESR0 = stat_edmac;
bogdanm 0:9b334a45a8ff 463 /* Reception-related */
bogdanm 0:9b334a45a8ff 464 if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
bogdanm 0:9b334a45a8ff 465 if (p_recv_cb_fnc != NULL) {
bogdanm 0:9b334a45a8ff 466 p_recv_cb_fnc();
bogdanm 0:9b334a45a8ff 467 }
bogdanm 0:9b334a45a8ff 468 }
bogdanm 0:9b334a45a8ff 469 /* E-MAC-related */
bogdanm 0:9b334a45a8ff 470 if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
bogdanm 0:9b334a45a8ff 471 /* Clear the interrupt request flag */
bogdanm 0:9b334a45a8ff 472 stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
bogdanm 0:9b334a45a8ff 473 ETHERECSR0 = stat_etherc;
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475 }
bogdanm 0:9b334a45a8ff 476
bogdanm 0:9b334a45a8ff 477 static void lan_reg_reset(void) {
bogdanm 0:9b334a45a8ff 478 volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
bogdanm 0:9b334a45a8ff 479
bogdanm 0:9b334a45a8ff 480 ETHERARSTR |= 0x00000001; /* ETHER software reset */
bogdanm 0:9b334a45a8ff 481 while (j--) {
bogdanm 0:9b334a45a8ff 482 /* Do Nothing */
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
bogdanm 0:9b334a45a8ff 486 ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
bogdanm 0:9b334a45a8ff 487
bogdanm 0:9b334a45a8ff 488 /* Check clear software reset */
bogdanm 0:9b334a45a8ff 489 while ((ETHEREDMR0 & 0x00000003) != 0) {
bogdanm 0:9b334a45a8ff 490 /* Do Nothing */
bogdanm 0:9b334a45a8ff 491 }
bogdanm 0:9b334a45a8ff 492 }
bogdanm 0:9b334a45a8ff 493
bogdanm 0:9b334a45a8ff 494 static void lan_desc_create(void) {
bogdanm 0:9b334a45a8ff 495 int32_t i;
bogdanm 0:9b334a45a8ff 496 uint8_t *p_memory_top;
bogdanm 0:9b334a45a8ff 497
mbed_official 66:fdb3f9f9a72f 498 (void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
mbed_official 66:fdb3f9f9a72f 499 p_memory_top = ethernet_nc_memory;
bogdanm 0:9b334a45a8ff 500
bogdanm 0:9b334a45a8ff 501 /* Descriptor area configuration */
bogdanm 0:9b334a45a8ff 502 p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
bogdanm 0:9b334a45a8ff 503 p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
bogdanm 0:9b334a45a8ff 504 p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
bogdanm 0:9b334a45a8ff 505 p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 /* Transmit descriptor */
bogdanm 0:9b334a45a8ff 508 for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
bogdanm 0:9b334a45a8ff 509 p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
bogdanm 0:9b334a45a8ff 510 p_memory_top += SIZE_OF_BUFFER;
bogdanm 0:9b334a45a8ff 511 p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
bogdanm 0:9b334a45a8ff 512 p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
bogdanm 0:9b334a45a8ff 513 }
bogdanm 0:9b334a45a8ff 514 p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /* Receive descriptor */
bogdanm 0:9b334a45a8ff 517 for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
bogdanm 0:9b334a45a8ff 518 p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
bogdanm 0:9b334a45a8ff 519 p_memory_top += SIZE_OF_BUFFER;
bogdanm 0:9b334a45a8ff 520 p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
bogdanm 0:9b334a45a8ff 521 p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523 p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
bogdanm 0:9b334a45a8ff 524
bogdanm 0:9b334a45a8ff 525 /* Initialize descriptor management information */
bogdanm 0:9b334a45a8ff 526 send_top_index = 0;
bogdanm 0:9b334a45a8ff 527 recv_top_index = 0;
bogdanm 0:9b334a45a8ff 528 rx_read_offset = 0;
bogdanm 0:9b334a45a8ff 529 tx_wite_offset = 0;
bogdanm 0:9b334a45a8ff 530 p_recv_end_desc = NULL;
bogdanm 0:9b334a45a8ff 531 }
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 static void lan_reg_set(int32_t link) {
bogdanm 0:9b334a45a8ff 534 /* MAC address setting */
bogdanm 0:9b334a45a8ff 535 ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
bogdanm 0:9b334a45a8ff 536 | ((uint32_t)mac_addr[1] << 16)
bogdanm 0:9b334a45a8ff 537 | ((uint32_t)mac_addr[2] << 8)
bogdanm 0:9b334a45a8ff 538 | (uint32_t)mac_addr[3];
bogdanm 0:9b334a45a8ff 539 ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
bogdanm 0:9b334a45a8ff 540 | (uint32_t)mac_addr[5];
bogdanm 0:9b334a45a8ff 541
bogdanm 0:9b334a45a8ff 542 /* E-DMAC */
bogdanm 0:9b334a45a8ff 543 ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
bogdanm 0:9b334a45a8ff 544 ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
bogdanm 0:9b334a45a8ff 545 ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
bogdanm 0:9b334a45a8ff 546 ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
bogdanm 0:9b334a45a8ff 547 ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
bogdanm 0:9b334a45a8ff 548 ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
bogdanm 0:9b334a45a8ff 549 ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
bogdanm 0:9b334a45a8ff 550 ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
bogdanm 0:9b334a45a8ff 551 ETHEREDMR0 |= 0x00000040; /* Little endian */
bogdanm 0:9b334a45a8ff 552 ETHERTRSCER0 &= ~0x0003009F; /* All clear */
bogdanm 0:9b334a45a8ff 553 ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
bogdanm 0:9b334a45a8ff 554 ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
bogdanm 0:9b334a45a8ff 555 ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
bogdanm 0:9b334a45a8ff 556 ETHERFCFTR0 &= ~0x001F00FF;
bogdanm 0:9b334a45a8ff 557 ETHERFCFTR0 |= 0x00070007;
bogdanm 0:9b334a45a8ff 558 ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
bogdanm 0:9b334a45a8ff 559
bogdanm 0:9b334a45a8ff 560 /* E-MAC */
bogdanm 0:9b334a45a8ff 561 ETHERECMR0 &= ~0x04BF2063; /* All clear */
bogdanm 0:9b334a45a8ff 562 ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
bogdanm 0:9b334a45a8ff 563 ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
bogdanm 0:9b334a45a8ff 564 ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
bogdanm 0:9b334a45a8ff 565 ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
bogdanm 0:9b334a45a8ff 566 ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
bogdanm 0:9b334a45a8ff 567 if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
bogdanm 0:9b334a45a8ff 568 ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
bogdanm 0:9b334a45a8ff 569 } else {
bogdanm 0:9b334a45a8ff 570 ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
bogdanm 0:9b334a45a8ff 571 }
bogdanm 0:9b334a45a8ff 572
bogdanm 0:9b334a45a8ff 573 /* Interrupt-related */
bogdanm 0:9b334a45a8ff 574 if (p_recv_cb_fnc != NULL) {
bogdanm 0:9b334a45a8ff 575 ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
bogdanm 0:9b334a45a8ff 576 ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
bogdanm 0:9b334a45a8ff 577 ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
bogdanm 0:9b334a45a8ff 578 ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
bogdanm 0:9b334a45a8ff 579 InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
bogdanm 0:9b334a45a8ff 580 GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
bogdanm 0:9b334a45a8ff 581 GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
bogdanm 0:9b334a45a8ff 582 }
bogdanm 0:9b334a45a8ff 583
bogdanm 0:9b334a45a8ff 584 ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 /* Enable transmission/reception */
bogdanm 0:9b334a45a8ff 587 if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
bogdanm 0:9b334a45a8ff 588 ETHEREDRRR0 |= 0x00000001; /* RR */
bogdanm 0:9b334a45a8ff 589 }
bogdanm 0:9b334a45a8ff 590 }
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 static uint16_t phy_reg_read(uint16_t reg_addr) {
bogdanm 0:9b334a45a8ff 593 uint16_t data;
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 mii_preamble();
bogdanm 0:9b334a45a8ff 596 mii_cmd(reg_addr, PHY_READ);
bogdanm 0:9b334a45a8ff 597 mii_z();
bogdanm 0:9b334a45a8ff 598 mii_reg_read(&data);
bogdanm 0:9b334a45a8ff 599 mii_z();
bogdanm 0:9b334a45a8ff 600
bogdanm 0:9b334a45a8ff 601 return data;
bogdanm 0:9b334a45a8ff 602 }
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
bogdanm 0:9b334a45a8ff 605 mii_preamble();
bogdanm 0:9b334a45a8ff 606 mii_cmd(reg_addr, PHY_WRITE);
bogdanm 0:9b334a45a8ff 607 mii_write_1();
bogdanm 0:9b334a45a8ff 608 mii_write_0();
bogdanm 0:9b334a45a8ff 609 mii_reg_write(data);
bogdanm 0:9b334a45a8ff 610 mii_z();
bogdanm 0:9b334a45a8ff 611 }
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 static void mii_preamble(void) {
bogdanm 0:9b334a45a8ff 614 int32_t i = 32;
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 for (i = 32; i > 0; i--) {
bogdanm 0:9b334a45a8ff 617 /* 1 is output via the MII (Media Independent Interface) block. */
bogdanm 0:9b334a45a8ff 618 mii_write_1();
bogdanm 0:9b334a45a8ff 619 }
bogdanm 0:9b334a45a8ff 620 }
bogdanm 0:9b334a45a8ff 621
bogdanm 0:9b334a45a8ff 622 static void mii_cmd(uint16_t reg_addr, uint32_t option) {
bogdanm 0:9b334a45a8ff 623 int32_t i;
bogdanm 0:9b334a45a8ff 624 uint16_t data = 0;
bogdanm 0:9b334a45a8ff 625
bogdanm 0:9b334a45a8ff 626 data |= (PHY_ST << 14); /* ST code */
bogdanm 0:9b334a45a8ff 627 data |= (option << 12); /* OP code */
bogdanm 0:9b334a45a8ff 628 data |= (PHY_ADDR << 7); /* PHY Address */
bogdanm 0:9b334a45a8ff 629 data |= (uint16_t)(reg_addr << 2); /* Reg Address */
bogdanm 0:9b334a45a8ff 630 for (i = 14; i > 0; i--) {
bogdanm 0:9b334a45a8ff 631 if ((data & 0x8000) == 0) {
bogdanm 0:9b334a45a8ff 632 mii_write_0();
bogdanm 0:9b334a45a8ff 633 } else {
bogdanm 0:9b334a45a8ff 634 mii_write_1();
bogdanm 0:9b334a45a8ff 635 }
bogdanm 0:9b334a45a8ff 636 data <<= 1;
bogdanm 0:9b334a45a8ff 637 }
bogdanm 0:9b334a45a8ff 638 }
bogdanm 0:9b334a45a8ff 639
bogdanm 0:9b334a45a8ff 640 static void mii_reg_read(uint16_t *data) {
bogdanm 0:9b334a45a8ff 641 int32_t i;
bogdanm 0:9b334a45a8ff 642 uint16_t reg_data = 0;
bogdanm 0:9b334a45a8ff 643
bogdanm 0:9b334a45a8ff 644 /* Data are read in one bit at a time */
bogdanm 0:9b334a45a8ff 645 for (i = 16; i > 0; i--) {
bogdanm 0:9b334a45a8ff 646 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 647 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 648 reg_data <<= 1;
bogdanm 0:9b334a45a8ff 649 reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
bogdanm 0:9b334a45a8ff 650 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 651 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 652 }
bogdanm 0:9b334a45a8ff 653 *data = reg_data;
bogdanm 0:9b334a45a8ff 654 }
bogdanm 0:9b334a45a8ff 655
bogdanm 0:9b334a45a8ff 656 static void mii_reg_write(uint16_t data) {
bogdanm 0:9b334a45a8ff 657 int32_t i;
bogdanm 0:9b334a45a8ff 658
bogdanm 0:9b334a45a8ff 659 /* Data are written one bit at a time */
bogdanm 0:9b334a45a8ff 660 for (i = 16; i > 0; i--) {
bogdanm 0:9b334a45a8ff 661 if ((data & 0x8000) == 0) {
bogdanm 0:9b334a45a8ff 662 mii_write_0();
bogdanm 0:9b334a45a8ff 663 } else {
bogdanm 0:9b334a45a8ff 664 mii_write_1();
bogdanm 0:9b334a45a8ff 665 }
bogdanm 0:9b334a45a8ff 666 data <<= 1;
bogdanm 0:9b334a45a8ff 667 }
bogdanm 0:9b334a45a8ff 668 }
bogdanm 0:9b334a45a8ff 669
bogdanm 0:9b334a45a8ff 670 static void mii_z(void) {
bogdanm 0:9b334a45a8ff 671 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 672 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 673 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 674 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 675 }
bogdanm 0:9b334a45a8ff 676
bogdanm 0:9b334a45a8ff 677 static void mii_write_1(void) {
bogdanm 0:9b334a45a8ff 678 set_ether_pir(PIR0_MDO | PIR0_MMD);
bogdanm 0:9b334a45a8ff 679 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 680 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 681 set_ether_pir(PIR0_MDO | PIR0_MMD);
bogdanm 0:9b334a45a8ff 682 }
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684 static void mii_write_0(void) {
bogdanm 0:9b334a45a8ff 685 set_ether_pir(PIR0_MMD);
bogdanm 0:9b334a45a8ff 686 set_ether_pir(PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 687 set_ether_pir(PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 688 set_ether_pir(PIR0_MMD);
bogdanm 0:9b334a45a8ff 689 }
bogdanm 0:9b334a45a8ff 690
bogdanm 0:9b334a45a8ff 691 static void set_ether_pir(uint32_t set_data) {
bogdanm 0:9b334a45a8ff 692 int32_t i;
bogdanm 0:9b334a45a8ff 693
bogdanm 0:9b334a45a8ff 694 for (i = MDC_WAIT; i > 0; i--) {
bogdanm 0:9b334a45a8ff 695 ETHERPIR0 = set_data;
bogdanm 0:9b334a45a8ff 696 }
bogdanm 0:9b334a45a8ff 697 }
bogdanm 0:9b334a45a8ff 698
bogdanm 0:9b334a45a8ff 699 static void wait_100us(int32_t wait_cnt) {
bogdanm 0:9b334a45a8ff 700 volatile int32_t j = LOOP_100us * wait_cnt;
bogdanm 0:9b334a45a8ff 701
bogdanm 0:9b334a45a8ff 702 while (--j) {
bogdanm 0:9b334a45a8ff 703 /* Do Nothing */
bogdanm 0:9b334a45a8ff 704 }
bogdanm 0:9b334a45a8ff 705 }