Marek Trojan / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/ethernet_api.c@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
66:fdb3f9f9a72f
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /* mbed Microcontroller Library
bogdanm 0:9b334a45a8ff 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 0:9b334a45a8ff 3 *
bogdanm 0:9b334a45a8ff 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 0:9b334a45a8ff 5 * you may not use this file except in compliance with the License.
bogdanm 0:9b334a45a8ff 6 * You may obtain a copy of the License at
bogdanm 0:9b334a45a8ff 7 *
bogdanm 0:9b334a45a8ff 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 0:9b334a45a8ff 9 *
bogdanm 0:9b334a45a8ff 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 0:9b334a45a8ff 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 0:9b334a45a8ff 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 0:9b334a45a8ff 13 * See the License for the specific language governing permissions and
bogdanm 0:9b334a45a8ff 14 * limitations under the License.
bogdanm 0:9b334a45a8ff 15 */
bogdanm 0:9b334a45a8ff 16 #include <string.h>
bogdanm 0:9b334a45a8ff 17 #include "ethernet_api.h"
bogdanm 0:9b334a45a8ff 18 #include "cmsis.h"
bogdanm 0:9b334a45a8ff 19 #include "mbed_interface.h"
bogdanm 0:9b334a45a8ff 20 #include "toolchain.h"
bogdanm 0:9b334a45a8ff 21 #include "mbed_error.h"
bogdanm 0:9b334a45a8ff 22 #include "ether_iodefine.h"
bogdanm 0:9b334a45a8ff 23 #include "ethernetext_api.h"
bogdanm 0:9b334a45a8ff 24
bogdanm 0:9b334a45a8ff 25 /* Descriptor info */
bogdanm 0:9b334a45a8ff 26 #define NUM_OF_TX_DESCRIPTOR (16)
bogdanm 0:9b334a45a8ff 27 #define NUM_OF_RX_DESCRIPTOR (16)
bogdanm 0:9b334a45a8ff 28 #define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
bogdanm 0:9b334a45a8ff 29 #define MAX_SEND_SIZE (1514)
bogdanm 0:9b334a45a8ff 30 /* Ethernet Descriptor Value Define */
bogdanm 0:9b334a45a8ff 31 #define TD0_TFP_TOP_BOTTOM (0x30000000)
bogdanm 0:9b334a45a8ff 32 #define TD0_TACT (0x80000000)
bogdanm 0:9b334a45a8ff 33 #define TD0_TDLE (0x40000000)
bogdanm 0:9b334a45a8ff 34 #define RD0_RACT (0x80000000)
bogdanm 0:9b334a45a8ff 35 #define RD0_RDLE (0x40000000)
bogdanm 0:9b334a45a8ff 36 #define RD0_RFE (0x08000000)
bogdanm 0:9b334a45a8ff 37 #define RD0_RCSE (0x04000000)
bogdanm 0:9b334a45a8ff 38 #define RD0_RFS (0x03FF0000)
bogdanm 0:9b334a45a8ff 39 #define RD0_RCS (0x0000FFFF)
bogdanm 0:9b334a45a8ff 40 #define RD0_RFS_RFOF (0x02000000)
bogdanm 0:9b334a45a8ff 41 #define RD0_RFS_RUAF (0x00400000)
bogdanm 0:9b334a45a8ff 42 #define RD0_RFS_RRF (0x00100000)
bogdanm 0:9b334a45a8ff 43 #define RD0_RFS_RTLF (0x00080000)
bogdanm 0:9b334a45a8ff 44 #define RD0_RFS_RTSF (0x00040000)
bogdanm 0:9b334a45a8ff 45 #define RD0_RFS_PRE (0x00020000)
bogdanm 0:9b334a45a8ff 46 #define RD0_RFS_CERF (0x00010000)
bogdanm 0:9b334a45a8ff 47 #define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
bogdanm 0:9b334a45a8ff 48 RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
bogdanm 0:9b334a45a8ff 49 #define RD1_RDL_MSK (0x0000FFFF)
bogdanm 0:9b334a45a8ff 50 /* PHY Register */
bogdanm 0:9b334a45a8ff 51 #define BASIC_MODE_CONTROL_REG (0)
bogdanm 0:9b334a45a8ff 52 #define BASIC_MODE_STATUS_REG (1)
bogdanm 0:9b334a45a8ff 53 #define PHY_IDENTIFIER1_REG (2)
bogdanm 0:9b334a45a8ff 54 #define PHY_IDENTIFIER2_REG (3)
bogdanm 0:9b334a45a8ff 55 #define PHY_SP_CTL_STS_REG (31)
bogdanm 0:9b334a45a8ff 56 /* MII management interface access */
bogdanm 0:9b334a45a8ff 57 #define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
bogdanm 0:9b334a45a8ff 58 #define PHY_ST (1)
bogdanm 0:9b334a45a8ff 59 #define PHY_WRITE (1)
bogdanm 0:9b334a45a8ff 60 #define PHY_READ (2)
bogdanm 0:9b334a45a8ff 61 #define MDC_WAIT (6) /* 400ns/4 */
bogdanm 0:9b334a45a8ff 62 #define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
bogdanm 0:9b334a45a8ff 63 #define BASIC_STS_MSK_AUTO_CMP (0x0010) /* Auto-Negotiate Complete */
bogdanm 0:9b334a45a8ff 64 #define M_PHY_ID (0xFFFFFFF0)
bogdanm 0:9b334a45a8ff 65 #define PHY_ID_LAN8710A (0x0007C0F0)
bogdanm 0:9b334a45a8ff 66 /* ETHERPIR0 */
bogdanm 0:9b334a45a8ff 67 #define PIR0_MDI (0x00000008)
bogdanm 0:9b334a45a8ff 68 #define PIR0_MDO (0x00000004)
bogdanm 0:9b334a45a8ff 69 #define PIR0_MMD (0x00000002)
bogdanm 0:9b334a45a8ff 70 #define PIR0_MDC (0x00000001)
bogdanm 0:9b334a45a8ff 71 #define PIR0_MDC_HIGH (0x00000001)
bogdanm 0:9b334a45a8ff 72 #define PIR0_MDC_LOW (0x00000000)
bogdanm 0:9b334a45a8ff 73 /* ETHEREDRRR0 */
bogdanm 0:9b334a45a8ff 74 #define EDRRR0_RR (0x00000001)
bogdanm 0:9b334a45a8ff 75 /* ETHEREDTRR0 */
bogdanm 0:9b334a45a8ff 76 #define EDTRR0_TR (0x00000003)
bogdanm 0:9b334a45a8ff 77 /* software wait */
bogdanm 0:9b334a45a8ff 78 #define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80 #define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
bogdanm 0:9b334a45a8ff 81 /* 0x00040000 : Detect frame reception */
bogdanm 0:9b334a45a8ff 82 /* 0x00010000 : Receive FIFO overflow */
bogdanm 0:9b334a45a8ff 83 /* 0x00000010 : Residual bit frame reception */
bogdanm 0:9b334a45a8ff 84 /* 0x00000008 : Long frame reception */
bogdanm 0:9b334a45a8ff 85 /* 0x00000004 : Short frame reception */
bogdanm 0:9b334a45a8ff 86 /* 0x00000002 : PHY-LSI reception error */
bogdanm 0:9b334a45a8ff 87 /* 0x00000001 : Receive frame CRC error */
bogdanm 0:9b334a45a8ff 88 #define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
bogdanm 0:9b334a45a8ff 89
bogdanm 0:9b334a45a8ff 90 /* Send descriptor */
bogdanm 0:9b334a45a8ff 91 typedef struct tag_edmac_send_desc {
bogdanm 0:9b334a45a8ff 92 uint32_t td0;
bogdanm 0:9b334a45a8ff 93 uint32_t td1;
bogdanm 0:9b334a45a8ff 94 uint8_t *td2;
bogdanm 0:9b334a45a8ff 95 uint32_t padding4;
bogdanm 0:9b334a45a8ff 96 } edmac_send_desc_t;
bogdanm 0:9b334a45a8ff 97
bogdanm 0:9b334a45a8ff 98 /* Receive descriptor */
bogdanm 0:9b334a45a8ff 99 typedef struct tag_edmac_recv_desc {
bogdanm 0:9b334a45a8ff 100 uint32_t rd0;
bogdanm 0:9b334a45a8ff 101 uint32_t rd1;
bogdanm 0:9b334a45a8ff 102 uint8_t *rd2;
bogdanm 0:9b334a45a8ff 103 uint32_t padding4;
bogdanm 0:9b334a45a8ff 104 } edmac_recv_desc_t;
bogdanm 0:9b334a45a8ff 105
bogdanm 0:9b334a45a8ff 106 /* memory */
bogdanm 0:9b334a45a8ff 107 /* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
bogdanm 0:9b334a45a8ff 108 /* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
bogdanm 0:9b334a45a8ff 109 static uint8_t ehernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
bogdanm 0:9b334a45a8ff 110 (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
bogdanm 0:9b334a45a8ff 111 (NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
bogdanm 0:9b334a45a8ff 112 (NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
bogdanm 0:9b334a45a8ff 113 __attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
bogdanm 0:9b334a45a8ff 114 static int32_t rx_read_offset; /* read offset */
bogdanm 0:9b334a45a8ff 115 static int32_t tx_wite_offset; /* write offset */
bogdanm 0:9b334a45a8ff 116 static uint32_t send_top_index;
bogdanm 0:9b334a45a8ff 117 static uint32_t recv_top_index;
bogdanm 0:9b334a45a8ff 118 static int32_t Interrupt_priority;
bogdanm 0:9b334a45a8ff 119 static edmac_send_desc_t *p_eth_desc_dsend = NULL;
bogdanm 0:9b334a45a8ff 120 static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
bogdanm 0:9b334a45a8ff 121 static edmac_recv_desc_t *p_recv_end_desc = NULL;
bogdanm 0:9b334a45a8ff 122 static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
bogdanm 0:9b334a45a8ff 123 static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
bogdanm 0:9b334a45a8ff 124 static uint32_t phy_id = 0;
bogdanm 0:9b334a45a8ff 125 static uint32_t start_stop = 1; /* 0:stop 1:start */
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /* function */
bogdanm 0:9b334a45a8ff 128 static void lan_reg_reset(void);
bogdanm 0:9b334a45a8ff 129 static void lan_desc_create(void);
bogdanm 0:9b334a45a8ff 130 static void lan_reg_set(int32_t link);
bogdanm 0:9b334a45a8ff 131 static uint16_t phy_reg_read(uint16_t reg_addr);
bogdanm 0:9b334a45a8ff 132 static void phy_reg_write(uint16_t reg_addr, uint16_t data);
bogdanm 0:9b334a45a8ff 133 static void mii_preamble(void);
bogdanm 0:9b334a45a8ff 134 static void mii_cmd(uint16_t reg_addr, uint32_t option);
bogdanm 0:9b334a45a8ff 135 static void mii_reg_read(uint16_t *data);
bogdanm 0:9b334a45a8ff 136 static void mii_reg_write(uint16_t data);
bogdanm 0:9b334a45a8ff 137 static void mii_z(void);
bogdanm 0:9b334a45a8ff 138 static void mii_write_1(void);
bogdanm 0:9b334a45a8ff 139 static void mii_write_0(void);
bogdanm 0:9b334a45a8ff 140 static void set_ether_pir(uint32_t set_data);
bogdanm 0:9b334a45a8ff 141 static void wait_100us(int32_t wait_cnt);
bogdanm 0:9b334a45a8ff 142
bogdanm 0:9b334a45a8ff 143
bogdanm 0:9b334a45a8ff 144 int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
bogdanm 0:9b334a45a8ff 145 int32_t i;
bogdanm 0:9b334a45a8ff 146 uint16_t val;
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 /* P4_2(PHY Reset) */
bogdanm 0:9b334a45a8ff 151 GPIOP4 &= ~0x0004; /* Outputs low level */
bogdanm 0:9b334a45a8ff 152 GPIOPMC4 &= ~0x0004; /* Port mode */
bogdanm 0:9b334a45a8ff 153 GPIOPM4 &= ~0x0004; /* Output mode */
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 /* GPIO P1 P1_14(ET_COL) */
bogdanm 0:9b334a45a8ff 156 GPIOPMC1 |= 0x4000;
bogdanm 0:9b334a45a8ff 157 GPIOPFCAE1 &= ~0x4000;
bogdanm 0:9b334a45a8ff 158 GPIOPFCE1 |= 0x4000;
bogdanm 0:9b334a45a8ff 159 GPIOPFC1 |= 0x4000;
bogdanm 0:9b334a45a8ff 160
bogdanm 0:9b334a45a8ff 161 /* P3_0(ET_TXCLK), P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
bogdanm 0:9b334a45a8ff 162 GPIOPMC3 |= 0x0079;
bogdanm 0:9b334a45a8ff 163 GPIOPFCAE3 &= ~0x0079;
bogdanm 0:9b334a45a8ff 164 GPIOPFCE3 &= ~0x0079;
bogdanm 0:9b334a45a8ff 165 GPIOPFC3 |= 0x0079;
bogdanm 0:9b334a45a8ff 166 GPIOPIPC3 |= 0x0079;
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /* P5_9(ET_MDC) */
bogdanm 0:9b334a45a8ff 169 GPIOPMC5 |= 0x0200;
bogdanm 0:9b334a45a8ff 170 GPIOPFCAE5 &= ~0x0200;
bogdanm 0:9b334a45a8ff 171 GPIOPFCE5 &= ~0x0200;
bogdanm 0:9b334a45a8ff 172 GPIOPFC5 |= 0x0200;
bogdanm 0:9b334a45a8ff 173 GPIOPIPC5 |= 0x0200;
bogdanm 0:9b334a45a8ff 174
bogdanm 0:9b334a45a8ff 175 /* P10_1(ET_TXER), P10_2(ET_TXEN), P10_3(ET_CRS), P10_4(ET_TXD0), P10_5(ET_TXD1) */
bogdanm 0:9b334a45a8ff 176 /* P10_6(ET_TXD2), P10_7(ET_TXD3), P10_8(ET_RXD0), P10_9(ET_RXD1), P10_10(ET_RXD2), P10_11(ET_RXD3) */
bogdanm 0:9b334a45a8ff 177 GPIOPMC10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 178 GPIOPFCAE10 &= ~0x0FFE;
bogdanm 0:9b334a45a8ff 179 GPIOPFCE10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 180 GPIOPFC10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 181 GPIOPIPC10 |= 0x0FFE;
bogdanm 0:9b334a45a8ff 182
bogdanm 0:9b334a45a8ff 183 /* Resets the E-MAC,E-DMAC */
bogdanm 0:9b334a45a8ff 184 lan_reg_reset();
bogdanm 0:9b334a45a8ff 185
bogdanm 0:9b334a45a8ff 186 /* PHY Reset */
bogdanm 0:9b334a45a8ff 187 GPIOP4 &= ~0x0004; /* P4_2 Outputs low level */
bogdanm 0:9b334a45a8ff 188 wait_100us(250); /* 25msec */
bogdanm 0:9b334a45a8ff 189 GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
bogdanm 0:9b334a45a8ff 190 wait_100us(100); /* 10msec */
bogdanm 0:9b334a45a8ff 191
bogdanm 0:9b334a45a8ff 192 /* Resets the PHY-LSI */
bogdanm 0:9b334a45a8ff 193 phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
bogdanm 0:9b334a45a8ff 194 for (i = 10000; i > 0; i--) {
bogdanm 0:9b334a45a8ff 195 val = phy_reg_read(BASIC_MODE_CONTROL_REG);
bogdanm 0:9b334a45a8ff 196 if (((uint32_t)val & 0x8000uL) == 0) {
bogdanm 0:9b334a45a8ff 197 break; /* Reset complete */
bogdanm 0:9b334a45a8ff 198 }
bogdanm 0:9b334a45a8ff 199 }
bogdanm 0:9b334a45a8ff 200
bogdanm 0:9b334a45a8ff 201 phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
bogdanm 0:9b334a45a8ff 202 | (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
bogdanm 0:9b334a45a8ff 203
bogdanm 0:9b334a45a8ff 204 Interrupt_priority = p_ethcfg->int_priority;
bogdanm 0:9b334a45a8ff 205 p_recv_cb_fnc = p_ethcfg->recv_cb;
bogdanm 0:9b334a45a8ff 206 start_stop = 1;
bogdanm 0:9b334a45a8ff 207
bogdanm 0:9b334a45a8ff 208 if (p_ethcfg->ether_mac != NULL) {
bogdanm 0:9b334a45a8ff 209 (void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
bogdanm 0:9b334a45a8ff 210 } else {
bogdanm 0:9b334a45a8ff 211 ethernet_address(mac_addr); /* Get MAC Address */
bogdanm 0:9b334a45a8ff 212 }
bogdanm 0:9b334a45a8ff 213
bogdanm 0:9b334a45a8ff 214 return 0;
bogdanm 0:9b334a45a8ff 215 }
bogdanm 0:9b334a45a8ff 216
bogdanm 0:9b334a45a8ff 217 void ethernetext_start_stop(int32_t mode) {
bogdanm 0:9b334a45a8ff 218 if (mode == 1) {
bogdanm 0:9b334a45a8ff 219 /* start */
bogdanm 0:9b334a45a8ff 220 ETHEREDTRR0 |= EDTRR0_TR;
bogdanm 0:9b334a45a8ff 221 ETHEREDRRR0 |= EDRRR0_RR;
bogdanm 0:9b334a45a8ff 222 start_stop = 1;
bogdanm 0:9b334a45a8ff 223 } else {
bogdanm 0:9b334a45a8ff 224 /* stop */
bogdanm 0:9b334a45a8ff 225 ETHEREDTRR0 &= ~EDTRR0_TR;
bogdanm 0:9b334a45a8ff 226 ETHEREDRRR0 &= ~EDRRR0_RR;
bogdanm 0:9b334a45a8ff 227 start_stop = 0;
bogdanm 0:9b334a45a8ff 228 }
bogdanm 0:9b334a45a8ff 229 }
bogdanm 0:9b334a45a8ff 230
bogdanm 0:9b334a45a8ff 231 int ethernetext_chk_link_mode(void) {
bogdanm 0:9b334a45a8ff 232 int32_t link;
bogdanm 0:9b334a45a8ff 233 uint16_t data;
bogdanm 0:9b334a45a8ff 234
bogdanm 0:9b334a45a8ff 235 if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
bogdanm 0:9b334a45a8ff 236 data = phy_reg_read(PHY_SP_CTL_STS_REG);
bogdanm 0:9b334a45a8ff 237 switch (((uint32_t)data >> 2) & 0x00000007) {
bogdanm 0:9b334a45a8ff 238 case 0x0001:
bogdanm 0:9b334a45a8ff 239 link = HALF_10M;
bogdanm 0:9b334a45a8ff 240 break;
bogdanm 0:9b334a45a8ff 241 case 0x0005:
bogdanm 0:9b334a45a8ff 242 link = FULL_10M;
bogdanm 0:9b334a45a8ff 243 break;
bogdanm 0:9b334a45a8ff 244 case 0x0002:
bogdanm 0:9b334a45a8ff 245 link = HALF_TX;
bogdanm 0:9b334a45a8ff 246 break;
bogdanm 0:9b334a45a8ff 247 case 0x0006:
bogdanm 0:9b334a45a8ff 248 link = FULL_TX;
bogdanm 0:9b334a45a8ff 249 break;
bogdanm 0:9b334a45a8ff 250 default:
bogdanm 0:9b334a45a8ff 251 link = NEGO_FAIL;
bogdanm 0:9b334a45a8ff 252 break;
bogdanm 0:9b334a45a8ff 253 }
bogdanm 0:9b334a45a8ff 254 } else {
bogdanm 0:9b334a45a8ff 255 link = NEGO_FAIL;
bogdanm 0:9b334a45a8ff 256 }
bogdanm 0:9b334a45a8ff 257
bogdanm 0:9b334a45a8ff 258 return link;
bogdanm 0:9b334a45a8ff 259 }
bogdanm 0:9b334a45a8ff 260
bogdanm 0:9b334a45a8ff 261 void ethernetext_set_link_mode(int32_t link) {
bogdanm 0:9b334a45a8ff 262 lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
bogdanm 0:9b334a45a8ff 263 lan_desc_create(); /* Initialize of buffer memory */
bogdanm 0:9b334a45a8ff 264 lan_reg_set(link); /* E-DMAC, E-MAC initialization */
bogdanm 0:9b334a45a8ff 265 }
bogdanm 0:9b334a45a8ff 266
bogdanm 0:9b334a45a8ff 267 int ethernet_init() {
bogdanm 0:9b334a45a8ff 268 ethernet_cfg_t ethcfg;
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 ethcfg.int_priority = 5;
bogdanm 0:9b334a45a8ff 271 ethcfg.recv_cb = NULL;
bogdanm 0:9b334a45a8ff 272 ethcfg.ether_mac = NULL;
bogdanm 0:9b334a45a8ff 273 ethernetext_init(&ethcfg);
bogdanm 0:9b334a45a8ff 274 ethernet_set_link(-1, 0); /* Auto-Negotiation */
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 return 0;
bogdanm 0:9b334a45a8ff 277 }
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 void ethernet_free() {
bogdanm 0:9b334a45a8ff 280 ETHERARSTR |= 0x00000001; /* ETHER software reset */
bogdanm 0:9b334a45a8ff 281 CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
bogdanm 0:9b334a45a8ff 282 }
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284 int ethernet_write(const char *data, int slen) {
bogdanm 0:9b334a45a8ff 285 edmac_send_desc_t *p_send_desc;
bogdanm 0:9b334a45a8ff 286 int32_t copy_size;
bogdanm 0:9b334a45a8ff 287
bogdanm 0:9b334a45a8ff 288 if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
bogdanm 0:9b334a45a8ff 289 || (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
bogdanm 0:9b334a45a8ff 290 copy_size = 0;
bogdanm 0:9b334a45a8ff 291 } else {
bogdanm 0:9b334a45a8ff 292 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
bogdanm 0:9b334a45a8ff 293 if ((p_send_desc->td0 & TD0_TACT) != 0) {
bogdanm 0:9b334a45a8ff 294 copy_size = 0;
bogdanm 0:9b334a45a8ff 295 } else {
bogdanm 0:9b334a45a8ff 296 copy_size = MAX_SEND_SIZE - tx_wite_offset;
bogdanm 0:9b334a45a8ff 297 if (copy_size > slen) {
bogdanm 0:9b334a45a8ff 298 copy_size = slen;
bogdanm 0:9b334a45a8ff 299 }
bogdanm 0:9b334a45a8ff 300 (void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
bogdanm 0:9b334a45a8ff 301 tx_wite_offset += copy_size;
bogdanm 0:9b334a45a8ff 302 }
bogdanm 0:9b334a45a8ff 303 }
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 return copy_size;
bogdanm 0:9b334a45a8ff 306 }
bogdanm 0:9b334a45a8ff 307
bogdanm 0:9b334a45a8ff 308 int ethernet_send() {
bogdanm 0:9b334a45a8ff 309 edmac_send_desc_t *p_send_desc;
bogdanm 0:9b334a45a8ff 310 int32_t ret;
bogdanm 0:9b334a45a8ff 311
bogdanm 0:9b334a45a8ff 312 if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
bogdanm 0:9b334a45a8ff 313 ret = 0;
bogdanm 0:9b334a45a8ff 314 } else {
bogdanm 0:9b334a45a8ff 315 /* Transfer 1 frame */
bogdanm 0:9b334a45a8ff 316 p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
bogdanm 0:9b334a45a8ff 317
bogdanm 0:9b334a45a8ff 318 /* Sets the frame length */
bogdanm 0:9b334a45a8ff 319 p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
bogdanm 0:9b334a45a8ff 320 tx_wite_offset = 0;
bogdanm 0:9b334a45a8ff 321
bogdanm 0:9b334a45a8ff 322 /* Sets the transmit descriptor to transmit again */
bogdanm 0:9b334a45a8ff 323 p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
bogdanm 0:9b334a45a8ff 324 p_send_desc->td0 |= TD0_TACT;
bogdanm 0:9b334a45a8ff 325 if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
bogdanm 0:9b334a45a8ff 326 ETHEREDTRR0 |= EDTRR0_TR;
bogdanm 0:9b334a45a8ff 327 }
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329 /* Update the current descriptor */
bogdanm 0:9b334a45a8ff 330 send_top_index++;
bogdanm 0:9b334a45a8ff 331 if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
bogdanm 0:9b334a45a8ff 332 send_top_index = 0;
bogdanm 0:9b334a45a8ff 333 }
bogdanm 0:9b334a45a8ff 334 ret = 1;
bogdanm 0:9b334a45a8ff 335 }
bogdanm 0:9b334a45a8ff 336
bogdanm 0:9b334a45a8ff 337 return ret;
bogdanm 0:9b334a45a8ff 338 }
bogdanm 0:9b334a45a8ff 339
bogdanm 0:9b334a45a8ff 340 int ethernet_receive() {
bogdanm 0:9b334a45a8ff 341 edmac_recv_desc_t *p_recv_desc;
bogdanm 0:9b334a45a8ff 342 int32_t receive_size = 0;
bogdanm 0:9b334a45a8ff 343
bogdanm 0:9b334a45a8ff 344 if (p_eth_desc_drecv != NULL) {
bogdanm 0:9b334a45a8ff 345 if (p_recv_end_desc != NULL) {
bogdanm 0:9b334a45a8ff 346 /* Sets the receive descriptor to receive again */
bogdanm 0:9b334a45a8ff 347 p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
bogdanm 0:9b334a45a8ff 348 p_recv_end_desc->rd0 |= RD0_RACT;
bogdanm 0:9b334a45a8ff 349 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
bogdanm 0:9b334a45a8ff 350 ETHEREDRRR0 |= EDRRR0_RR;
bogdanm 0:9b334a45a8ff 351 }
bogdanm 0:9b334a45a8ff 352 p_recv_end_desc = NULL;
bogdanm 0:9b334a45a8ff 353 }
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
bogdanm 0:9b334a45a8ff 356 if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
bogdanm 0:9b334a45a8ff 357 /* Receives 1 frame */
bogdanm 0:9b334a45a8ff 358 if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
bogdanm 0:9b334a45a8ff 359 /* Receive frame error */
bogdanm 0:9b334a45a8ff 360 /* Sets the receive descriptor to receive again */
bogdanm 0:9b334a45a8ff 361 p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
bogdanm 0:9b334a45a8ff 362 p_recv_desc->rd0 |= RD0_RACT;
bogdanm 0:9b334a45a8ff 363 if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
bogdanm 0:9b334a45a8ff 364 ETHEREDRRR0 |= EDRRR0_RR;
bogdanm 0:9b334a45a8ff 365 }
bogdanm 0:9b334a45a8ff 366 } else {
bogdanm 0:9b334a45a8ff 367 /* Copies the received frame */
bogdanm 0:9b334a45a8ff 368 rx_read_offset = 0;
bogdanm 0:9b334a45a8ff 369 p_recv_end_desc = p_recv_desc;
bogdanm 0:9b334a45a8ff 370 receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
bogdanm 0:9b334a45a8ff 371 }
bogdanm 0:9b334a45a8ff 372
bogdanm 0:9b334a45a8ff 373 /* Update the current descriptor */
bogdanm 0:9b334a45a8ff 374 recv_top_index++;
bogdanm 0:9b334a45a8ff 375 if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
bogdanm 0:9b334a45a8ff 376 recv_top_index = 0;
bogdanm 0:9b334a45a8ff 377 }
bogdanm 0:9b334a45a8ff 378 }
bogdanm 0:9b334a45a8ff 379 }
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 return receive_size;
bogdanm 0:9b334a45a8ff 382 }
bogdanm 0:9b334a45a8ff 383
bogdanm 0:9b334a45a8ff 384 int ethernet_read(char *data, int dlen) {
bogdanm 0:9b334a45a8ff 385 edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
bogdanm 0:9b334a45a8ff 386 int32_t copy_size;
bogdanm 0:9b334a45a8ff 387
bogdanm 0:9b334a45a8ff 388 if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
bogdanm 0:9b334a45a8ff 389 copy_size = 0;
bogdanm 0:9b334a45a8ff 390 } else {
bogdanm 0:9b334a45a8ff 391 copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
bogdanm 0:9b334a45a8ff 392 if (copy_size > dlen) {
bogdanm 0:9b334a45a8ff 393 copy_size = dlen;
bogdanm 0:9b334a45a8ff 394 }
bogdanm 0:9b334a45a8ff 395 (void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
bogdanm 0:9b334a45a8ff 396 rx_read_offset += copy_size;
bogdanm 0:9b334a45a8ff 397 }
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 return copy_size;
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401
bogdanm 0:9b334a45a8ff 402 void ethernet_address(char *mac) {
bogdanm 0:9b334a45a8ff 403 if (mac != NULL) {
bogdanm 0:9b334a45a8ff 404 mbed_mac_address(mac); /* Get MAC Address */
bogdanm 0:9b334a45a8ff 405 }
bogdanm 0:9b334a45a8ff 406 }
bogdanm 0:9b334a45a8ff 407
bogdanm 0:9b334a45a8ff 408 int ethernet_link(void) {
bogdanm 0:9b334a45a8ff 409 int32_t ret;
bogdanm 0:9b334a45a8ff 410 uint16_t data;
bogdanm 0:9b334a45a8ff 411
bogdanm 0:9b334a45a8ff 412 data = phy_reg_read(BASIC_MODE_STATUS_REG);
bogdanm 0:9b334a45a8ff 413 if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
bogdanm 0:9b334a45a8ff 414 ret = 1;
bogdanm 0:9b334a45a8ff 415 } else {
bogdanm 0:9b334a45a8ff 416 ret = 0;
bogdanm 0:9b334a45a8ff 417 }
bogdanm 0:9b334a45a8ff 418
bogdanm 0:9b334a45a8ff 419 return ret;
bogdanm 0:9b334a45a8ff 420 }
bogdanm 0:9b334a45a8ff 421
bogdanm 0:9b334a45a8ff 422 void ethernet_set_link(int speed, int duplex) {
bogdanm 0:9b334a45a8ff 423 uint16_t data;
bogdanm 0:9b334a45a8ff 424 int32_t i;
bogdanm 0:9b334a45a8ff 425 int32_t link;
bogdanm 0:9b334a45a8ff 426
bogdanm 0:9b334a45a8ff 427 if ((speed < 0) || (speed > 1)) {
bogdanm 0:9b334a45a8ff 428 data = 0x1000; /* Auto-Negotiation Enable */
bogdanm 0:9b334a45a8ff 429 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
bogdanm 0:9b334a45a8ff 430 data = phy_reg_read(BASIC_MODE_STATUS_REG);
bogdanm 0:9b334a45a8ff 431 for (i = 0; i < 1000; i++) {
bogdanm 0:9b334a45a8ff 432 if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
bogdanm 0:9b334a45a8ff 433 break;
bogdanm 0:9b334a45a8ff 434 }
bogdanm 0:9b334a45a8ff 435 wait_100us(10);
bogdanm 0:9b334a45a8ff 436 }
bogdanm 0:9b334a45a8ff 437 } else {
bogdanm 0:9b334a45a8ff 438 data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
bogdanm 0:9b334a45a8ff 439 phy_reg_write(BASIC_MODE_CONTROL_REG, data);
bogdanm 0:9b334a45a8ff 440 wait_100us(1);
bogdanm 0:9b334a45a8ff 441 }
bogdanm 0:9b334a45a8ff 442
bogdanm 0:9b334a45a8ff 443 link = ethernetext_chk_link_mode();
bogdanm 0:9b334a45a8ff 444 ethernetext_set_link_mode(link);
bogdanm 0:9b334a45a8ff 445 }
bogdanm 0:9b334a45a8ff 446
bogdanm 0:9b334a45a8ff 447 void INT_Ether(void) {
bogdanm 0:9b334a45a8ff 448 uint32_t stat_edmac;
bogdanm 0:9b334a45a8ff 449 uint32_t stat_etherc;
bogdanm 0:9b334a45a8ff 450
bogdanm 0:9b334a45a8ff 451 /* Clear the interrupt request flag */
bogdanm 0:9b334a45a8ff 452 stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
bogdanm 0:9b334a45a8ff 453 ETHEREESR0 = stat_edmac;
bogdanm 0:9b334a45a8ff 454 /* Reception-related */
bogdanm 0:9b334a45a8ff 455 if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
bogdanm 0:9b334a45a8ff 456 if (p_recv_cb_fnc != NULL) {
bogdanm 0:9b334a45a8ff 457 p_recv_cb_fnc();
bogdanm 0:9b334a45a8ff 458 }
bogdanm 0:9b334a45a8ff 459 }
bogdanm 0:9b334a45a8ff 460 /* E-MAC-related */
bogdanm 0:9b334a45a8ff 461 if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
bogdanm 0:9b334a45a8ff 462 /* Clear the interrupt request flag */
bogdanm 0:9b334a45a8ff 463 stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
bogdanm 0:9b334a45a8ff 464 ETHERECSR0 = stat_etherc;
bogdanm 0:9b334a45a8ff 465 }
bogdanm 0:9b334a45a8ff 466 }
bogdanm 0:9b334a45a8ff 467
bogdanm 0:9b334a45a8ff 468 static void lan_reg_reset(void) {
bogdanm 0:9b334a45a8ff 469 volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
bogdanm 0:9b334a45a8ff 470
bogdanm 0:9b334a45a8ff 471 ETHERARSTR |= 0x00000001; /* ETHER software reset */
bogdanm 0:9b334a45a8ff 472 while (j--) {
bogdanm 0:9b334a45a8ff 473 /* Do Nothing */
bogdanm 0:9b334a45a8ff 474 }
bogdanm 0:9b334a45a8ff 475
bogdanm 0:9b334a45a8ff 476 ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
bogdanm 0:9b334a45a8ff 477 ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
bogdanm 0:9b334a45a8ff 478
bogdanm 0:9b334a45a8ff 479 /* Check clear software reset */
bogdanm 0:9b334a45a8ff 480 while ((ETHEREDMR0 & 0x00000003) != 0) {
bogdanm 0:9b334a45a8ff 481 /* Do Nothing */
bogdanm 0:9b334a45a8ff 482 }
bogdanm 0:9b334a45a8ff 483 }
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 static void lan_desc_create(void) {
bogdanm 0:9b334a45a8ff 486 int32_t i;
bogdanm 0:9b334a45a8ff 487 uint8_t *p_memory_top;
bogdanm 0:9b334a45a8ff 488
bogdanm 0:9b334a45a8ff 489 (void)memset((void *)ehernet_nc_memory, 0, sizeof(ehernet_nc_memory));
bogdanm 0:9b334a45a8ff 490 p_memory_top = ehernet_nc_memory;
bogdanm 0:9b334a45a8ff 491
bogdanm 0:9b334a45a8ff 492 /* Descriptor area configuration */
bogdanm 0:9b334a45a8ff 493 p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
bogdanm 0:9b334a45a8ff 494 p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
bogdanm 0:9b334a45a8ff 495 p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
bogdanm 0:9b334a45a8ff 496 p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
bogdanm 0:9b334a45a8ff 497
bogdanm 0:9b334a45a8ff 498 /* Transmit descriptor */
bogdanm 0:9b334a45a8ff 499 for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
bogdanm 0:9b334a45a8ff 500 p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
bogdanm 0:9b334a45a8ff 501 p_memory_top += SIZE_OF_BUFFER;
bogdanm 0:9b334a45a8ff 502 p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
bogdanm 0:9b334a45a8ff 503 p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
bogdanm 0:9b334a45a8ff 504 }
bogdanm 0:9b334a45a8ff 505 p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
bogdanm 0:9b334a45a8ff 506
bogdanm 0:9b334a45a8ff 507 /* Receive descriptor */
bogdanm 0:9b334a45a8ff 508 for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
bogdanm 0:9b334a45a8ff 509 p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
bogdanm 0:9b334a45a8ff 510 p_memory_top += SIZE_OF_BUFFER;
bogdanm 0:9b334a45a8ff 511 p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
bogdanm 0:9b334a45a8ff 512 p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
bogdanm 0:9b334a45a8ff 513 }
bogdanm 0:9b334a45a8ff 514 p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
bogdanm 0:9b334a45a8ff 515
bogdanm 0:9b334a45a8ff 516 /* Initialize descriptor management information */
bogdanm 0:9b334a45a8ff 517 send_top_index = 0;
bogdanm 0:9b334a45a8ff 518 recv_top_index = 0;
bogdanm 0:9b334a45a8ff 519 rx_read_offset = 0;
bogdanm 0:9b334a45a8ff 520 tx_wite_offset = 0;
bogdanm 0:9b334a45a8ff 521 p_recv_end_desc = NULL;
bogdanm 0:9b334a45a8ff 522 }
bogdanm 0:9b334a45a8ff 523
bogdanm 0:9b334a45a8ff 524 static void lan_reg_set(int32_t link) {
bogdanm 0:9b334a45a8ff 525 /* MAC address setting */
bogdanm 0:9b334a45a8ff 526 ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
bogdanm 0:9b334a45a8ff 527 | ((uint32_t)mac_addr[1] << 16)
bogdanm 0:9b334a45a8ff 528 | ((uint32_t)mac_addr[2] << 8)
bogdanm 0:9b334a45a8ff 529 | (uint32_t)mac_addr[3];
bogdanm 0:9b334a45a8ff 530 ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
bogdanm 0:9b334a45a8ff 531 | (uint32_t)mac_addr[5];
bogdanm 0:9b334a45a8ff 532
bogdanm 0:9b334a45a8ff 533 /* E-DMAC */
bogdanm 0:9b334a45a8ff 534 ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
bogdanm 0:9b334a45a8ff 535 ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
bogdanm 0:9b334a45a8ff 536 ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
bogdanm 0:9b334a45a8ff 537 ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
bogdanm 0:9b334a45a8ff 538 ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
bogdanm 0:9b334a45a8ff 539 ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
bogdanm 0:9b334a45a8ff 540 ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
bogdanm 0:9b334a45a8ff 541 ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
bogdanm 0:9b334a45a8ff 542 ETHEREDMR0 |= 0x00000040; /* Little endian */
bogdanm 0:9b334a45a8ff 543 ETHERTRSCER0 &= ~0x0003009F; /* All clear */
bogdanm 0:9b334a45a8ff 544 ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
bogdanm 0:9b334a45a8ff 545 ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
bogdanm 0:9b334a45a8ff 546 ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
bogdanm 0:9b334a45a8ff 547 ETHERFCFTR0 &= ~0x001F00FF;
bogdanm 0:9b334a45a8ff 548 ETHERFCFTR0 |= 0x00070007;
bogdanm 0:9b334a45a8ff 549 ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
bogdanm 0:9b334a45a8ff 550
bogdanm 0:9b334a45a8ff 551 /* E-MAC */
bogdanm 0:9b334a45a8ff 552 ETHERECMR0 &= ~0x04BF2063; /* All clear */
bogdanm 0:9b334a45a8ff 553 ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
bogdanm 0:9b334a45a8ff 554 ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
bogdanm 0:9b334a45a8ff 555 ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
bogdanm 0:9b334a45a8ff 556 ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
bogdanm 0:9b334a45a8ff 557 ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
bogdanm 0:9b334a45a8ff 558 if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
bogdanm 0:9b334a45a8ff 559 ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
bogdanm 0:9b334a45a8ff 560 } else {
bogdanm 0:9b334a45a8ff 561 ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
bogdanm 0:9b334a45a8ff 562 }
bogdanm 0:9b334a45a8ff 563
bogdanm 0:9b334a45a8ff 564 /* Interrupt-related */
bogdanm 0:9b334a45a8ff 565 if (p_recv_cb_fnc != NULL) {
bogdanm 0:9b334a45a8ff 566 ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
bogdanm 0:9b334a45a8ff 567 ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
bogdanm 0:9b334a45a8ff 568 ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
bogdanm 0:9b334a45a8ff 569 ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
bogdanm 0:9b334a45a8ff 570 InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
bogdanm 0:9b334a45a8ff 571 GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
bogdanm 0:9b334a45a8ff 572 GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
bogdanm 0:9b334a45a8ff 573 }
bogdanm 0:9b334a45a8ff 574
bogdanm 0:9b334a45a8ff 575 ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
bogdanm 0:9b334a45a8ff 576
bogdanm 0:9b334a45a8ff 577 /* Enable transmission/reception */
bogdanm 0:9b334a45a8ff 578 if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
bogdanm 0:9b334a45a8ff 579 ETHEREDRRR0 |= 0x00000001; /* RR */
bogdanm 0:9b334a45a8ff 580 }
bogdanm 0:9b334a45a8ff 581 }
bogdanm 0:9b334a45a8ff 582
bogdanm 0:9b334a45a8ff 583 static uint16_t phy_reg_read(uint16_t reg_addr) {
bogdanm 0:9b334a45a8ff 584 uint16_t data;
bogdanm 0:9b334a45a8ff 585
bogdanm 0:9b334a45a8ff 586 mii_preamble();
bogdanm 0:9b334a45a8ff 587 mii_cmd(reg_addr, PHY_READ);
bogdanm 0:9b334a45a8ff 588 mii_z();
bogdanm 0:9b334a45a8ff 589 mii_reg_read(&data);
bogdanm 0:9b334a45a8ff 590 mii_z();
bogdanm 0:9b334a45a8ff 591
bogdanm 0:9b334a45a8ff 592 return data;
bogdanm 0:9b334a45a8ff 593 }
bogdanm 0:9b334a45a8ff 594
bogdanm 0:9b334a45a8ff 595 static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
bogdanm 0:9b334a45a8ff 596 mii_preamble();
bogdanm 0:9b334a45a8ff 597 mii_cmd(reg_addr, PHY_WRITE);
bogdanm 0:9b334a45a8ff 598 mii_write_1();
bogdanm 0:9b334a45a8ff 599 mii_write_0();
bogdanm 0:9b334a45a8ff 600 mii_reg_write(data);
bogdanm 0:9b334a45a8ff 601 mii_z();
bogdanm 0:9b334a45a8ff 602 }
bogdanm 0:9b334a45a8ff 603
bogdanm 0:9b334a45a8ff 604 static void mii_preamble(void) {
bogdanm 0:9b334a45a8ff 605 int32_t i = 32;
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 for (i = 32; i > 0; i--) {
bogdanm 0:9b334a45a8ff 608 /* 1 is output via the MII (Media Independent Interface) block. */
bogdanm 0:9b334a45a8ff 609 mii_write_1();
bogdanm 0:9b334a45a8ff 610 }
bogdanm 0:9b334a45a8ff 611 }
bogdanm 0:9b334a45a8ff 612
bogdanm 0:9b334a45a8ff 613 static void mii_cmd(uint16_t reg_addr, uint32_t option) {
bogdanm 0:9b334a45a8ff 614 int32_t i;
bogdanm 0:9b334a45a8ff 615 uint16_t data = 0;
bogdanm 0:9b334a45a8ff 616
bogdanm 0:9b334a45a8ff 617 data |= (PHY_ST << 14); /* ST code */
bogdanm 0:9b334a45a8ff 618 data |= (option << 12); /* OP code */
bogdanm 0:9b334a45a8ff 619 data |= (PHY_ADDR << 7); /* PHY Address */
bogdanm 0:9b334a45a8ff 620 data |= (uint16_t)(reg_addr << 2); /* Reg Address */
bogdanm 0:9b334a45a8ff 621 for (i = 14; i > 0; i--) {
bogdanm 0:9b334a45a8ff 622 if ((data & 0x8000) == 0) {
bogdanm 0:9b334a45a8ff 623 mii_write_0();
bogdanm 0:9b334a45a8ff 624 } else {
bogdanm 0:9b334a45a8ff 625 mii_write_1();
bogdanm 0:9b334a45a8ff 626 }
bogdanm 0:9b334a45a8ff 627 data <<= 1;
bogdanm 0:9b334a45a8ff 628 }
bogdanm 0:9b334a45a8ff 629 }
bogdanm 0:9b334a45a8ff 630
bogdanm 0:9b334a45a8ff 631 static void mii_reg_read(uint16_t *data) {
bogdanm 0:9b334a45a8ff 632 int32_t i;
bogdanm 0:9b334a45a8ff 633 uint16_t reg_data = 0;
bogdanm 0:9b334a45a8ff 634
bogdanm 0:9b334a45a8ff 635 /* Data are read in one bit at a time */
bogdanm 0:9b334a45a8ff 636 for (i = 16; i > 0; i--) {
bogdanm 0:9b334a45a8ff 637 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 638 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 639 reg_data <<= 1;
bogdanm 0:9b334a45a8ff 640 reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
bogdanm 0:9b334a45a8ff 641 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 642 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 643 }
bogdanm 0:9b334a45a8ff 644 *data = reg_data;
bogdanm 0:9b334a45a8ff 645 }
bogdanm 0:9b334a45a8ff 646
bogdanm 0:9b334a45a8ff 647 static void mii_reg_write(uint16_t data) {
bogdanm 0:9b334a45a8ff 648 int32_t i;
bogdanm 0:9b334a45a8ff 649
bogdanm 0:9b334a45a8ff 650 /* Data are written one bit at a time */
bogdanm 0:9b334a45a8ff 651 for (i = 16; i > 0; i--) {
bogdanm 0:9b334a45a8ff 652 if ((data & 0x8000) == 0) {
bogdanm 0:9b334a45a8ff 653 mii_write_0();
bogdanm 0:9b334a45a8ff 654 } else {
bogdanm 0:9b334a45a8ff 655 mii_write_1();
bogdanm 0:9b334a45a8ff 656 }
bogdanm 0:9b334a45a8ff 657 data <<= 1;
bogdanm 0:9b334a45a8ff 658 }
bogdanm 0:9b334a45a8ff 659 }
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 static void mii_z(void) {
bogdanm 0:9b334a45a8ff 662 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 663 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 664 set_ether_pir(PIR0_MDC_HIGH);
bogdanm 0:9b334a45a8ff 665 set_ether_pir(PIR0_MDC_LOW);
bogdanm 0:9b334a45a8ff 666 }
bogdanm 0:9b334a45a8ff 667
bogdanm 0:9b334a45a8ff 668 static void mii_write_1(void) {
bogdanm 0:9b334a45a8ff 669 set_ether_pir(PIR0_MDO | PIR0_MMD);
bogdanm 0:9b334a45a8ff 670 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 671 set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 672 set_ether_pir(PIR0_MDO | PIR0_MMD);
bogdanm 0:9b334a45a8ff 673 }
bogdanm 0:9b334a45a8ff 674
bogdanm 0:9b334a45a8ff 675 static void mii_write_0(void) {
bogdanm 0:9b334a45a8ff 676 set_ether_pir(PIR0_MMD);
bogdanm 0:9b334a45a8ff 677 set_ether_pir(PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 678 set_ether_pir(PIR0_MMD | PIR0_MDC);
bogdanm 0:9b334a45a8ff 679 set_ether_pir(PIR0_MMD);
bogdanm 0:9b334a45a8ff 680 }
bogdanm 0:9b334a45a8ff 681
bogdanm 0:9b334a45a8ff 682 static void set_ether_pir(uint32_t set_data) {
bogdanm 0:9b334a45a8ff 683 int32_t i;
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 for (i = MDC_WAIT; i > 0; i--) {
bogdanm 0:9b334a45a8ff 686 ETHERPIR0 = set_data;
bogdanm 0:9b334a45a8ff 687 }
bogdanm 0:9b334a45a8ff 688 }
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 static void wait_100us(int32_t wait_cnt) {
bogdanm 0:9b334a45a8ff 691 volatile int32_t j = LOOP_100us * wait_cnt;
bogdanm 0:9b334a45a8ff 692
bogdanm 0:9b334a45a8ff 693 while (--j) {
bogdanm 0:9b334a45a8ff 694 /* Do Nothing */
bogdanm 0:9b334a45a8ff 695 }
bogdanm 0:9b334a45a8ff 696 }