SX1276Lib updated in order to be RTOS aware
Fork of SX1276Lib by
sx1276/sx1276-hal.cpp@31:a9575b07944d, 2018-03-03 (annotated)
- Committer:
- Lorenzo Maiorfi
- Date:
- Sat Mar 03 18:08:11 2018 +0100
- Revision:
- 31:a9575b07944d
- Parent:
- 30:3b83eee4e72a
Fix debug
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
GregCr | 0:e6ceb13d2d05 | 1 | /* |
GregCr | 0:e6ceb13d2d05 | 2 | / _____) _ | | |
GregCr | 0:e6ceb13d2d05 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
GregCr | 0:e6ceb13d2d05 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
GregCr | 0:e6ceb13d2d05 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
GregCr | 0:e6ceb13d2d05 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
mluis | 22:7f3aab69cca9 | 7 | (C) 2014 Semtech |
GregCr | 0:e6ceb13d2d05 | 8 | |
GregCr | 0:e6ceb13d2d05 | 9 | Description: - |
GregCr | 0:e6ceb13d2d05 | 10 | |
GregCr | 0:e6ceb13d2d05 | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
GregCr | 0:e6ceb13d2d05 | 12 | |
GregCr | 0:e6ceb13d2d05 | 13 | Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin |
GregCr | 0:e6ceb13d2d05 | 14 | */ |
GregCr | 0:e6ceb13d2d05 | 15 | #include "sx1276-hal.h" |
GregCr | 0:e6ceb13d2d05 | 16 | |
mluis | 22:7f3aab69cca9 | 17 | const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE; |
GregCr | 0:e6ceb13d2d05 | 18 | |
Lorenzo Maiorfi |
30:3b83eee4e72a | 19 | SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events, BoardType_t board, |
GregCr | 0:e6ceb13d2d05 | 20 | PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, |
GregCr | 0:e6ceb13d2d05 | 21 | PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5, |
GregCr | 0:e6ceb13d2d05 | 22 | PinName antSwitch ) |
mluis | 21:2e496deb7858 | 23 | : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ), |
mluis | 26:d09a8ef807e2 | 24 | AntSwitch( antSwitch ), |
GregCr | 12:aa5b3bf7fdf4 | 25 | #if( defined ( TARGET_NUCLEO_L152RE ) ) |
mluis | 26:d09a8ef807e2 | 26 | Fake( D8 ) |
GregCr | 12:aa5b3bf7fdf4 | 27 | #else |
mluis | 26:d09a8ef807e2 | 28 | Fake( A3 ) |
GregCr | 0:e6ceb13d2d05 | 29 | #endif |
GregCr | 0:e6ceb13d2d05 | 30 | { |
mluis | 21:2e496deb7858 | 31 | this->RadioEvents = events; |
mluis | 21:2e496deb7858 | 32 | |
Lorenzo Maiorfi |
30:3b83eee4e72a | 33 | boardConnected = board; |
Lorenzo Maiorfi |
30:3b83eee4e72a | 34 | |
GregCr | 0:e6ceb13d2d05 | 35 | Reset( ); |
mluis | 26:d09a8ef807e2 | 36 | |
GregCr | 0:e6ceb13d2d05 | 37 | RxChainCalibration( ); |
mluis | 26:d09a8ef807e2 | 38 | |
GregCr | 0:e6ceb13d2d05 | 39 | IoInit( ); |
mluis | 26:d09a8ef807e2 | 40 | |
GregCr | 0:e6ceb13d2d05 | 41 | SetOpMode( RF_OPMODE_SLEEP ); |
mluis | 26:d09a8ef807e2 | 42 | |
GregCr | 0:e6ceb13d2d05 | 43 | IoIrqInit( dioIrq ); |
mluis | 26:d09a8ef807e2 | 44 | |
GregCr | 0:e6ceb13d2d05 | 45 | RadioRegistersInit( ); |
GregCr | 0:e6ceb13d2d05 | 46 | |
GregCr | 0:e6ceb13d2d05 | 47 | SetModem( MODEM_FSK ); |
GregCr | 0:e6ceb13d2d05 | 48 | |
mluis | 21:2e496deb7858 | 49 | this->settings.State = RF_IDLE ; |
GregCr | 0:e6ceb13d2d05 | 50 | } |
GregCr | 0:e6ceb13d2d05 | 51 | |
mluis | 26:d09a8ef807e2 | 52 | SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events ) |
Lorenzo Maiorfi |
30:3b83eee4e72a | 53 | #if defined ( TARGET_NUCLEO_L152RE ) || defined (TARGET_NUCLEO_L476RG) || defined (TARGET_NUCLEO_F401RE) |
mluis | 21:2e496deb7858 | 54 | : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3 |
mluis | 26:d09a8ef807e2 | 55 | AntSwitch( A4 ), |
mluis | 26:d09a8ef807e2 | 56 | Fake( D8 ) |
Lorenzo Maiorfi |
30:3b83eee4e72a | 57 | #elif defined( TARGET_NUCLEO_L073RZ ) |
Lorenzo Maiorfi |
30:3b83eee4e72a | 58 | : SX1276( events, PB_15, PB_14, PB_13, PB_12, PC_6, PC_8, D3, D4, D5, D8, D9 ), |
Lorenzo Maiorfi |
30:3b83eee4e72a | 59 | AntSwitch( A4 ), |
Lorenzo Maiorfi |
30:3b83eee4e72a | 60 | Fake( A3 ) |
mluis | 20:e05596ba4166 | 61 | #elif defined( TARGET_LPC11U6X ) |
mluis | 21:2e496deb7858 | 62 | : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ), |
mluis | 26:d09a8ef807e2 | 63 | AntSwitch( P0_23 ), |
mluis | 26:d09a8ef807e2 | 64 | Fake( A3 ) |
GregCr | 0:e6ceb13d2d05 | 65 | #else |
mluis | 21:2e496deb7858 | 66 | : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ), |
mluis | 26:d09a8ef807e2 | 67 | AntSwitch( A4 ), |
mluis | 26:d09a8ef807e2 | 68 | Fake( A3 ) |
GregCr | 0:e6ceb13d2d05 | 69 | #endif |
GregCr | 0:e6ceb13d2d05 | 70 | { |
mluis | 21:2e496deb7858 | 71 | this->RadioEvents = events; |
mluis | 21:2e496deb7858 | 72 | |
GregCr | 0:e6ceb13d2d05 | 73 | Reset( ); |
mluis | 26:d09a8ef807e2 | 74 | |
Lorenzo Maiorfi |
30:3b83eee4e72a | 75 | boardConnected = RFM95_SX1276; |
mluis | 26:d09a8ef807e2 | 76 | |
GregCr | 1:f979673946c0 | 77 | DetectBoardType( ); |
mluis | 26:d09a8ef807e2 | 78 | |
GregCr | 0:e6ceb13d2d05 | 79 | RxChainCalibration( ); |
mluis | 26:d09a8ef807e2 | 80 | |
GregCr | 0:e6ceb13d2d05 | 81 | IoInit( ); |
mluis | 26:d09a8ef807e2 | 82 | |
GregCr | 0:e6ceb13d2d05 | 83 | SetOpMode( RF_OPMODE_SLEEP ); |
GregCr | 0:e6ceb13d2d05 | 84 | IoIrqInit( dioIrq ); |
mluis | 26:d09a8ef807e2 | 85 | |
GregCr | 0:e6ceb13d2d05 | 86 | RadioRegistersInit( ); |
GregCr | 0:e6ceb13d2d05 | 87 | |
GregCr | 0:e6ceb13d2d05 | 88 | SetModem( MODEM_FSK ); |
GregCr | 0:e6ceb13d2d05 | 89 | |
mluis | 21:2e496deb7858 | 90 | this->settings.State = RF_IDLE ; |
GregCr | 0:e6ceb13d2d05 | 91 | } |
GregCr | 0:e6ceb13d2d05 | 92 | |
GregCr | 0:e6ceb13d2d05 | 93 | //------------------------------------------------------------------------- |
GregCr | 0:e6ceb13d2d05 | 94 | // Board relative functions |
GregCr | 0:e6ceb13d2d05 | 95 | //------------------------------------------------------------------------- |
GregCr | 2:5eb3066446dd | 96 | uint8_t SX1276MB1xAS::DetectBoardType( void ) |
GregCr | 1:f979673946c0 | 97 | { |
Lorenzo Maiorfi |
30:3b83eee4e72a | 98 | return boardConnected; |
GregCr | 1:f979673946c0 | 99 | } |
GregCr | 0:e6ceb13d2d05 | 100 | |
GregCr | 0:e6ceb13d2d05 | 101 | void SX1276MB1xAS::IoInit( void ) |
GregCr | 0:e6ceb13d2d05 | 102 | { |
GregCr | 0:e6ceb13d2d05 | 103 | AntSwInit( ); |
GregCr | 0:e6ceb13d2d05 | 104 | SpiInit( ); |
GregCr | 0:e6ceb13d2d05 | 105 | } |
GregCr | 0:e6ceb13d2d05 | 106 | |
mluis | 22:7f3aab69cca9 | 107 | void SX1276MB1xAS::RadioRegistersInit( ) |
mluis | 22:7f3aab69cca9 | 108 | { |
GregCr | 0:e6ceb13d2d05 | 109 | uint8_t i = 0; |
GregCr | 0:e6ceb13d2d05 | 110 | for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ ) |
GregCr | 0:e6ceb13d2d05 | 111 | { |
GregCr | 0:e6ceb13d2d05 | 112 | SetModem( RadioRegsInit[i].Modem ); |
GregCr | 0:e6ceb13d2d05 | 113 | Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value ); |
GregCr | 0:e6ceb13d2d05 | 114 | } |
GregCr | 0:e6ceb13d2d05 | 115 | } |
GregCr | 0:e6ceb13d2d05 | 116 | |
GregCr | 0:e6ceb13d2d05 | 117 | void SX1276MB1xAS::SpiInit( void ) |
GregCr | 0:e6ceb13d2d05 | 118 | { |
GregCr | 0:e6ceb13d2d05 | 119 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 120 | spi.format( 8,0 ); |
GregCr | 0:e6ceb13d2d05 | 121 | uint32_t frequencyToSet = 8000000; |
Lorenzo Maiorfi |
30:3b83eee4e72a | 122 | #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_MOTE_L152RC ) || defined ( TARGET_NUCLEO_L476RG ) || defined ( TARGET_LPC11U6X ) || defined ( TARGET_MTS_MDOT_F411RE ) || defined ( TARGET_NUCLEO_L073RZ )) |
GregCr | 0:e6ceb13d2d05 | 123 | spi.frequency( frequencyToSet ); |
GregCr | 0:e6ceb13d2d05 | 124 | #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate |
GregCr | 0:e6ceb13d2d05 | 125 | spi.frequency( frequencyToSet * 2 ); |
GregCr | 0:e6ceb13d2d05 | 126 | #else |
GregCr | 0:e6ceb13d2d05 | 127 | #warning "Check the board's SPI frequency" |
GregCr | 0:e6ceb13d2d05 | 128 | #endif |
GregCr | 0:e6ceb13d2d05 | 129 | wait(0.1); |
GregCr | 0:e6ceb13d2d05 | 130 | } |
GregCr | 0:e6ceb13d2d05 | 131 | |
GregCr | 0:e6ceb13d2d05 | 132 | void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers ) |
GregCr | 0:e6ceb13d2d05 | 133 | { |
mluis | 26:d09a8ef807e2 | 134 | #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) ) |
mluis | 26:d09a8ef807e2 | 135 | dio0.mode( PullDown ); |
mluis | 26:d09a8ef807e2 | 136 | dio1.mode( PullDown ); |
mluis | 26:d09a8ef807e2 | 137 | dio2.mode( PullDown ); |
mluis | 26:d09a8ef807e2 | 138 | dio3.mode( PullDown ); |
mluis | 26:d09a8ef807e2 | 139 | dio4.mode( PullDown ); |
mluis | 22:7f3aab69cca9 | 140 | #endif |
mluis | 26:d09a8ef807e2 | 141 | dio0.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) ) ); |
mluis | 26:d09a8ef807e2 | 142 | dio1.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) ) ); |
mluis | 26:d09a8ef807e2 | 143 | dio2.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) ) ); |
mluis | 26:d09a8ef807e2 | 144 | dio3.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) ) ); |
mluis | 26:d09a8ef807e2 | 145 | dio4.rise( mbed::callback( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) ) ); |
GregCr | 0:e6ceb13d2d05 | 146 | } |
GregCr | 0:e6ceb13d2d05 | 147 | |
GregCr | 0:e6ceb13d2d05 | 148 | void SX1276MB1xAS::IoDeInit( void ) |
GregCr | 0:e6ceb13d2d05 | 149 | { |
GregCr | 0:e6ceb13d2d05 | 150 | //nothing |
GregCr | 0:e6ceb13d2d05 | 151 | } |
GregCr | 0:e6ceb13d2d05 | 152 | |
mluis | 26:d09a8ef807e2 | 153 | void SX1276MB1xAS::SetRfTxPower( int8_t power ) |
mluis | 26:d09a8ef807e2 | 154 | { |
mluis | 26:d09a8ef807e2 | 155 | uint8_t paConfig = 0; |
mluis | 26:d09a8ef807e2 | 156 | uint8_t paDac = 0; |
mluis | 26:d09a8ef807e2 | 157 | |
mluis | 26:d09a8ef807e2 | 158 | paConfig = Read( REG_PACONFIG ); |
mluis | 26:d09a8ef807e2 | 159 | paDac = Read( REG_PADAC ); |
mluis | 26:d09a8ef807e2 | 160 | |
mluis | 26:d09a8ef807e2 | 161 | paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel ); |
mluis | 26:d09a8ef807e2 | 162 | paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70; |
mluis | 26:d09a8ef807e2 | 163 | |
mluis | 26:d09a8ef807e2 | 164 | if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST ) |
mluis | 26:d09a8ef807e2 | 165 | { |
mluis | 26:d09a8ef807e2 | 166 | if( power > 17 ) |
mluis | 26:d09a8ef807e2 | 167 | { |
mluis | 26:d09a8ef807e2 | 168 | paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON; |
mluis | 26:d09a8ef807e2 | 169 | } |
mluis | 26:d09a8ef807e2 | 170 | else |
mluis | 26:d09a8ef807e2 | 171 | { |
mluis | 26:d09a8ef807e2 | 172 | paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF; |
mluis | 26:d09a8ef807e2 | 173 | } |
mluis | 26:d09a8ef807e2 | 174 | if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON ) |
mluis | 26:d09a8ef807e2 | 175 | { |
mluis | 26:d09a8ef807e2 | 176 | if( power < 5 ) |
mluis | 26:d09a8ef807e2 | 177 | { |
mluis | 26:d09a8ef807e2 | 178 | power = 5; |
mluis | 26:d09a8ef807e2 | 179 | } |
mluis | 26:d09a8ef807e2 | 180 | if( power > 20 ) |
mluis | 26:d09a8ef807e2 | 181 | { |
mluis | 26:d09a8ef807e2 | 182 | power = 20; |
mluis | 26:d09a8ef807e2 | 183 | } |
mluis | 26:d09a8ef807e2 | 184 | paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F ); |
mluis | 26:d09a8ef807e2 | 185 | } |
mluis | 26:d09a8ef807e2 | 186 | else |
mluis | 26:d09a8ef807e2 | 187 | { |
mluis | 26:d09a8ef807e2 | 188 | if( power < 2 ) |
mluis | 26:d09a8ef807e2 | 189 | { |
mluis | 26:d09a8ef807e2 | 190 | power = 2; |
mluis | 26:d09a8ef807e2 | 191 | } |
mluis | 26:d09a8ef807e2 | 192 | if( power > 17 ) |
mluis | 26:d09a8ef807e2 | 193 | { |
mluis | 26:d09a8ef807e2 | 194 | power = 17; |
mluis | 26:d09a8ef807e2 | 195 | } |
mluis | 26:d09a8ef807e2 | 196 | paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F ); |
mluis | 26:d09a8ef807e2 | 197 | } |
mluis | 26:d09a8ef807e2 | 198 | } |
mluis | 26:d09a8ef807e2 | 199 | else |
mluis | 26:d09a8ef807e2 | 200 | { |
mluis | 26:d09a8ef807e2 | 201 | if( power < -1 ) |
mluis | 26:d09a8ef807e2 | 202 | { |
mluis | 26:d09a8ef807e2 | 203 | power = -1; |
mluis | 26:d09a8ef807e2 | 204 | } |
mluis | 26:d09a8ef807e2 | 205 | if( power > 14 ) |
mluis | 26:d09a8ef807e2 | 206 | { |
mluis | 26:d09a8ef807e2 | 207 | power = 14; |
mluis | 26:d09a8ef807e2 | 208 | } |
mluis | 26:d09a8ef807e2 | 209 | paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F ); |
mluis | 26:d09a8ef807e2 | 210 | } |
mluis | 26:d09a8ef807e2 | 211 | Write( REG_PACONFIG, paConfig ); |
mluis | 26:d09a8ef807e2 | 212 | Write( REG_PADAC, paDac ); |
mluis | 26:d09a8ef807e2 | 213 | } |
mluis | 26:d09a8ef807e2 | 214 | |
GregCr | 0:e6ceb13d2d05 | 215 | uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel ) |
GregCr | 0:e6ceb13d2d05 | 216 | { |
GregCr | 0:e6ceb13d2d05 | 217 | if( channel > RF_MID_BAND_THRESH ) |
GregCr | 0:e6ceb13d2d05 | 218 | { |
Lorenzo Maiorfi |
30:3b83eee4e72a | 219 | if( boardConnected == SX1276MB1LAS || boardConnected == RFM95_SX1276 || boardConnected == MURATA_SX1276) |
GregCr | 1:f979673946c0 | 220 | { |
GregCr | 1:f979673946c0 | 221 | return RF_PACONFIG_PASELECT_PABOOST; |
GregCr | 1:f979673946c0 | 222 | } |
GregCr | 1:f979673946c0 | 223 | else |
GregCr | 1:f979673946c0 | 224 | { |
GregCr | 1:f979673946c0 | 225 | return RF_PACONFIG_PASELECT_RFO; |
GregCr | 1:f979673946c0 | 226 | } |
GregCr | 0:e6ceb13d2d05 | 227 | } |
GregCr | 0:e6ceb13d2d05 | 228 | else |
GregCr | 0:e6ceb13d2d05 | 229 | { |
GregCr | 0:e6ceb13d2d05 | 230 | return RF_PACONFIG_PASELECT_RFO; |
GregCr | 0:e6ceb13d2d05 | 231 | } |
GregCr | 0:e6ceb13d2d05 | 232 | } |
GregCr | 0:e6ceb13d2d05 | 233 | |
GregCr | 0:e6ceb13d2d05 | 234 | void SX1276MB1xAS::SetAntSwLowPower( bool status ) |
GregCr | 0:e6ceb13d2d05 | 235 | { |
GregCr | 0:e6ceb13d2d05 | 236 | if( isRadioActive != status ) |
GregCr | 0:e6ceb13d2d05 | 237 | { |
GregCr | 0:e6ceb13d2d05 | 238 | isRadioActive = status; |
GregCr | 0:e6ceb13d2d05 | 239 | |
GregCr | 0:e6ceb13d2d05 | 240 | if( status == false ) |
GregCr | 0:e6ceb13d2d05 | 241 | { |
GregCr | 0:e6ceb13d2d05 | 242 | AntSwInit( ); |
GregCr | 0:e6ceb13d2d05 | 243 | } |
GregCr | 0:e6ceb13d2d05 | 244 | else |
GregCr | 0:e6ceb13d2d05 | 245 | { |
GregCr | 0:e6ceb13d2d05 | 246 | AntSwDeInit( ); |
GregCr | 0:e6ceb13d2d05 | 247 | } |
GregCr | 0:e6ceb13d2d05 | 248 | } |
GregCr | 0:e6ceb13d2d05 | 249 | } |
GregCr | 0:e6ceb13d2d05 | 250 | |
GregCr | 0:e6ceb13d2d05 | 251 | void SX1276MB1xAS::AntSwInit( void ) |
GregCr | 0:e6ceb13d2d05 | 252 | { |
mluis | 26:d09a8ef807e2 | 253 | this->AntSwitch = 0; |
GregCr | 0:e6ceb13d2d05 | 254 | } |
GregCr | 0:e6ceb13d2d05 | 255 | |
GregCr | 0:e6ceb13d2d05 | 256 | void SX1276MB1xAS::AntSwDeInit( void ) |
GregCr | 0:e6ceb13d2d05 | 257 | { |
mluis | 26:d09a8ef807e2 | 258 | this->AntSwitch = 0; |
GregCr | 0:e6ceb13d2d05 | 259 | } |
GregCr | 0:e6ceb13d2d05 | 260 | |
mluis | 26:d09a8ef807e2 | 261 | void SX1276MB1xAS::SetAntSw( uint8_t opMode ) |
GregCr | 0:e6ceb13d2d05 | 262 | { |
mluis | 26:d09a8ef807e2 | 263 | switch( opMode ) |
GregCr | 0:e6ceb13d2d05 | 264 | { |
mluis | 26:d09a8ef807e2 | 265 | case RFLR_OPMODE_TRANSMITTER: |
mluis | 26:d09a8ef807e2 | 266 | this->AntSwitch = 1; |
mluis | 26:d09a8ef807e2 | 267 | break; |
mluis | 26:d09a8ef807e2 | 268 | case RFLR_OPMODE_RECEIVER: |
mluis | 26:d09a8ef807e2 | 269 | case RFLR_OPMODE_RECEIVER_SINGLE: |
mluis | 26:d09a8ef807e2 | 270 | case RFLR_OPMODE_CAD: |
mluis | 26:d09a8ef807e2 | 271 | this->AntSwitch = 0; |
mluis | 26:d09a8ef807e2 | 272 | break; |
mluis | 26:d09a8ef807e2 | 273 | default: |
mluis | 26:d09a8ef807e2 | 274 | this->AntSwitch = 0; |
mluis | 26:d09a8ef807e2 | 275 | break; |
GregCr | 0:e6ceb13d2d05 | 276 | } |
GregCr | 0:e6ceb13d2d05 | 277 | } |
GregCr | 0:e6ceb13d2d05 | 278 | |
GregCr | 0:e6ceb13d2d05 | 279 | bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency ) |
GregCr | 0:e6ceb13d2d05 | 280 | { |
mluis | 26:d09a8ef807e2 | 281 | // Implement check. Currently all frequencies are supported |
GregCr | 0:e6ceb13d2d05 | 282 | return true; |
GregCr | 0:e6ceb13d2d05 | 283 | } |
GregCr | 0:e6ceb13d2d05 | 284 | |
GregCr | 0:e6ceb13d2d05 | 285 | void SX1276MB1xAS::Reset( void ) |
GregCr | 0:e6ceb13d2d05 | 286 | { |
mluis | 26:d09a8ef807e2 | 287 | reset.output( ); |
GregCr | 0:e6ceb13d2d05 | 288 | reset = 0; |
GregCr | 0:e6ceb13d2d05 | 289 | wait_ms( 1 ); |
mluis | 26:d09a8ef807e2 | 290 | reset.input( ); |
GregCr | 0:e6ceb13d2d05 | 291 | wait_ms( 6 ); |
GregCr | 0:e6ceb13d2d05 | 292 | } |
mluis | 26:d09a8ef807e2 | 293 | |
GregCr | 0:e6ceb13d2d05 | 294 | void SX1276MB1xAS::Write( uint8_t addr, uint8_t data ) |
GregCr | 0:e6ceb13d2d05 | 295 | { |
GregCr | 0:e6ceb13d2d05 | 296 | Write( addr, &data, 1 ); |
GregCr | 0:e6ceb13d2d05 | 297 | } |
GregCr | 0:e6ceb13d2d05 | 298 | |
GregCr | 0:e6ceb13d2d05 | 299 | uint8_t SX1276MB1xAS::Read( uint8_t addr ) |
GregCr | 0:e6ceb13d2d05 | 300 | { |
GregCr | 0:e6ceb13d2d05 | 301 | uint8_t data; |
GregCr | 0:e6ceb13d2d05 | 302 | Read( addr, &data, 1 ); |
GregCr | 0:e6ceb13d2d05 | 303 | return data; |
GregCr | 0:e6ceb13d2d05 | 304 | } |
GregCr | 0:e6ceb13d2d05 | 305 | |
GregCr | 0:e6ceb13d2d05 | 306 | void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 307 | { |
GregCr | 0:e6ceb13d2d05 | 308 | uint8_t i; |
GregCr | 0:e6ceb13d2d05 | 309 | |
GregCr | 0:e6ceb13d2d05 | 310 | nss = 0; |
GregCr | 0:e6ceb13d2d05 | 311 | spi.write( addr | 0x80 ); |
GregCr | 0:e6ceb13d2d05 | 312 | for( i = 0; i < size; i++ ) |
GregCr | 0:e6ceb13d2d05 | 313 | { |
GregCr | 0:e6ceb13d2d05 | 314 | spi.write( buffer[i] ); |
GregCr | 0:e6ceb13d2d05 | 315 | } |
GregCr | 0:e6ceb13d2d05 | 316 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 317 | } |
GregCr | 0:e6ceb13d2d05 | 318 | |
GregCr | 0:e6ceb13d2d05 | 319 | void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 320 | { |
GregCr | 0:e6ceb13d2d05 | 321 | uint8_t i; |
GregCr | 0:e6ceb13d2d05 | 322 | |
GregCr | 0:e6ceb13d2d05 | 323 | nss = 0; |
GregCr | 0:e6ceb13d2d05 | 324 | spi.write( addr & 0x7F ); |
GregCr | 0:e6ceb13d2d05 | 325 | for( i = 0; i < size; i++ ) |
GregCr | 0:e6ceb13d2d05 | 326 | { |
GregCr | 0:e6ceb13d2d05 | 327 | buffer[i] = spi.write( 0 ); |
GregCr | 0:e6ceb13d2d05 | 328 | } |
GregCr | 0:e6ceb13d2d05 | 329 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 330 | } |
GregCr | 0:e6ceb13d2d05 | 331 | |
GregCr | 0:e6ceb13d2d05 | 332 | void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 333 | { |
GregCr | 0:e6ceb13d2d05 | 334 | Write( 0, buffer, size ); |
GregCr | 0:e6ceb13d2d05 | 335 | } |
GregCr | 0:e6ceb13d2d05 | 336 | |
GregCr | 0:e6ceb13d2d05 | 337 | void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 338 | { |
GregCr | 0:e6ceb13d2d05 | 339 | Read( 0, buffer, size ); |
GregCr | 0:e6ceb13d2d05 | 340 | } |