lzbp li / SX1276Lib-test

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Fork of SX1276Lib by lzbp li

sx1276/sx1276.cpp@25:ff4574f6f1a6, 2016-07-11 (annotated)

Committer:
lzbpli
Date:
Mon Jul 11 07:47:29 2016 +0000
Revision:
25:ff4574f6f1a6
Parent:
24:3d058e9d6129
Child:
26:ba9dda357a36
tiao shi

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
lzbpli 25:ff4574f6f1a6 16 #include "board.h"
GregCr 0:e6ceb13d2d05 17
GregCr 0:e6ceb13d2d05 18 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 19 {
GregCr 0:e6ceb13d2d05 20 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 21 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 22 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 23 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 24 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 25 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 26 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 27 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 28 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 29 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 30 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 31 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 32 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 33 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 34 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 35 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 36 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 37 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 38 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 39 { 200000, 0x09 },
mluis 15:04374b1c33fa 40 { 250000, 0x01 },
mluis 16:d447f8d2d2d6 41 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 42 };
GregCr 0:e6ceb13d2d05 43
GregCr 0:e6ceb13d2d05 44
mluis 21:2e496deb7858 45 SX1276::SX1276( RadioEvents_t *events,
mluis 13:618826a997e2 46 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 47 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 21:2e496deb7858 48 : Radio( events ),
mluis 13:618826a997e2 49 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 50 nss( nss ),
mluis 13:618826a997e2 51 reset( reset ),
mluis 13:618826a997e2 52 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 53 isRadioActive( false )
GregCr 0:e6ceb13d2d05 54 {
mluis 13:618826a997e2 55 wait_ms( 10 );
mluis 13:618826a997e2 56 this->rxTx = 0;
mluis 13:618826a997e2 57 this->rxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 58 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 59
mluis 21:2e496deb7858 60 this->RadioEvents = events;
mluis 21:2e496deb7858 61
mluis 13:618826a997e2 62 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 63
mluis 13:618826a997e2 64 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 65 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 66 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 67 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 68 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 69 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 70
mluis 21:2e496deb7858 71 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 72 }
GregCr 0:e6ceb13d2d05 73
GregCr 0:e6ceb13d2d05 74 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 75 {
mluis 13:618826a997e2 76 delete this->rxBuffer;
mluis 13:618826a997e2 77 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 78 }
GregCr 0:e6ceb13d2d05 79
mluis 21:2e496deb7858 80 void SX1276::Init( RadioEvents_t *events )
mluis 21:2e496deb7858 81 {
mluis 21:2e496deb7858 82 this->RadioEvents = events;
mluis 21:2e496deb7858 83 }
mluis 21:2e496deb7858 84
GregCr 19:71a47bb03fbb 85 RadioState SX1276::GetStatus( void )
GregCr 0:e6ceb13d2d05 86 {
GregCr 0:e6ceb13d2d05 87 return this->settings.State;
GregCr 0:e6ceb13d2d05 88 }
GregCr 0:e6ceb13d2d05 89
GregCr 0:e6ceb13d2d05 90 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 91 {
GregCr 0:e6ceb13d2d05 92 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 93 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 94 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 95 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 96 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 97 }
GregCr 0:e6ceb13d2d05 98
mluis 22:7f3aab69cca9 99 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
GregCr 0:e6ceb13d2d05 100 {
GregCr 7:2b555111463f 101 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 102
GregCr 0:e6ceb13d2d05 103 SetModem( modem );
GregCr 0:e6ceb13d2d05 104
GregCr 0:e6ceb13d2d05 105 SetChannel( freq );
GregCr 0:e6ceb13d2d05 106
GregCr 0:e6ceb13d2d05 107 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 108
GregCr 4:f0ce52e94d3f 109 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 110
GregCr 0:e6ceb13d2d05 111 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 112
GregCr 0:e6ceb13d2d05 113 Sleep( );
GregCr 0:e6ceb13d2d05 114
mluis 22:7f3aab69cca9 115 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 116 {
GregCr 0:e6ceb13d2d05 117 return false;
GregCr 0:e6ceb13d2d05 118 }
GregCr 0:e6ceb13d2d05 119 return true;
GregCr 0:e6ceb13d2d05 120 }
GregCr 0:e6ceb13d2d05 121
GregCr 0:e6ceb13d2d05 122 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 123 {
GregCr 0:e6ceb13d2d05 124 uint8_t i;
GregCr 0:e6ceb13d2d05 125 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 126
GregCr 0:e6ceb13d2d05 127 /*
GregCr 0:e6ceb13d2d05 128 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 129 */
GregCr 0:e6ceb13d2d05 130 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 131 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 132
GregCr 0:e6ceb13d2d05 133 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 134 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 135 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 136 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 137 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 138 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 139 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 140 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 141 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 142
GregCr 0:e6ceb13d2d05 143 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 144 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 145
GregCr 0:e6ceb13d2d05 146 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 147 {
GregCr 4:f0ce52e94d3f 148 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 149 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 150 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 151 }
GregCr 0:e6ceb13d2d05 152
GregCr 0:e6ceb13d2d05 153 Sleep( );
GregCr 0:e6ceb13d2d05 154
GregCr 0:e6ceb13d2d05 155 return rnd;
GregCr 0:e6ceb13d2d05 156 }
GregCr 0:e6ceb13d2d05 157
GregCr 0:e6ceb13d2d05 158 /*!
mluis 22:7f3aab69cca9 159 * Performs the Rx chain calibration for LF and HF bands
mluis 22:7f3aab69cca9 160 * \remark Must be called just after the reset so all registers are at their
mluis 22:7f3aab69cca9 161 * default values
mluis 22:7f3aab69cca9 162 */
mluis 22:7f3aab69cca9 163 void SX1276::RxChainCalibration( void )
mluis 22:7f3aab69cca9 164 {
mluis 22:7f3aab69cca9 165 uint8_t regPaConfigInitVal;
mluis 22:7f3aab69cca9 166 uint32_t initialFreq;
mluis 22:7f3aab69cca9 167
mluis 22:7f3aab69cca9 168 // Save context
mluis 22:7f3aab69cca9 169 regPaConfigInitVal = this->Read( REG_PACONFIG );
mluis 22:7f3aab69cca9 170 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
mluis 22:7f3aab69cca9 171 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
mluis 22:7f3aab69cca9 172 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
mluis 22:7f3aab69cca9 173
mluis 22:7f3aab69cca9 174 // Cut the PA just in case, RFO output, power = -1 dBm
mluis 22:7f3aab69cca9 175 this->Write( REG_PACONFIG, 0x00 );
mluis 22:7f3aab69cca9 176
mluis 22:7f3aab69cca9 177 // Launch Rx chain calibration for LF band
mluis 22:7f3aab69cca9 178 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 179 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 180 {
mluis 22:7f3aab69cca9 181 }
mluis 22:7f3aab69cca9 182
mluis 22:7f3aab69cca9 183 // Sets a Frequency in HF band
mluis 22:7f3aab69cca9 184 SetChannel( 868000000 );
mluis 22:7f3aab69cca9 185
mluis 22:7f3aab69cca9 186 // Launch Rx chain calibration for HF band
mluis 22:7f3aab69cca9 187 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 188 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 189 {
mluis 22:7f3aab69cca9 190 }
mluis 22:7f3aab69cca9 191
mluis 22:7f3aab69cca9 192 // Restore context
mluis 22:7f3aab69cca9 193 this->Write( REG_PACONFIG, regPaConfigInitVal );
mluis 22:7f3aab69cca9 194 SetChannel( initialFreq );
mluis 22:7f3aab69cca9 195 }
mluis 22:7f3aab69cca9 196
mluis 22:7f3aab69cca9 197 /*!
GregCr 0:e6ceb13d2d05 198 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 199 *
GregCr 0:e6ceb13d2d05 200 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 201 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 202 */
GregCr 0:e6ceb13d2d05 203 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 204 {
GregCr 0:e6ceb13d2d05 205 uint8_t i;
GregCr 0:e6ceb13d2d05 206
GregCr 0:e6ceb13d2d05 207 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 208 {
GregCr 0:e6ceb13d2d05 209 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 210 {
GregCr 0:e6ceb13d2d05 211 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213 }
GregCr 0:e6ceb13d2d05 214 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 215 while( 1 );
GregCr 0:e6ceb13d2d05 216 }
GregCr 0:e6ceb13d2d05 217
mluis 22:7f3aab69cca9 218 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 219 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 220 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 221 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 222 uint8_t payloadLen,
mluis 13:618826a997e2 223 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 224 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 225 {
GregCr 0:e6ceb13d2d05 226 SetModem( modem );
GregCr 0:e6ceb13d2d05 227
GregCr 0:e6ceb13d2d05 228 switch( modem )
GregCr 0:e6ceb13d2d05 229 {
GregCr 0:e6ceb13d2d05 230 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 231 {
GregCr 0:e6ceb13d2d05 232 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 233 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 234 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 235 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 236 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 237 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 238 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 239 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 240 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 241
GregCr 0:e6ceb13d2d05 242 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 243 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 244 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 245
GregCr 0:e6ceb13d2d05 246 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 247 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 248
mluis 14:8552d0b840be 249 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 250 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 22:7f3aab69cca9 251
mluis 22:7f3aab69cca9 252 if( fixLen == 1 )
mluis 22:7f3aab69cca9 253 {
mluis 22:7f3aab69cca9 254 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 22:7f3aab69cca9 255 }
GregCr 0:e6ceb13d2d05 256
GregCr 0:e6ceb13d2d05 257 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 258 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 259 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 260 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 261 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 262 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 263 }
GregCr 0:e6ceb13d2d05 264 break;
GregCr 0:e6ceb13d2d05 265 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 266 {
GregCr 0:e6ceb13d2d05 267 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 268 {
GregCr 0:e6ceb13d2d05 269 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 270 while( 1 );
GregCr 0:e6ceb13d2d05 271 }
GregCr 0:e6ceb13d2d05 272 bandwidth += 7;
GregCr 0:e6ceb13d2d05 273 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 274 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 275 this->settings.LoRa.Coderate = coderate;
mluis 22:7f3aab69cca9 276 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 277 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 278 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 279 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 280 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 281 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 283 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 22:7f3aab69cca9 284
GregCr 0:e6ceb13d2d05 285 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 286 {
GregCr 0:e6ceb13d2d05 287 datarate = 12;
GregCr 0:e6ceb13d2d05 288 }
GregCr 0:e6ceb13d2d05 289 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 290 {
GregCr 0:e6ceb13d2d05 291 datarate = 6;
GregCr 0:e6ceb13d2d05 292 }
GregCr 0:e6ceb13d2d05 293
GregCr 0:e6ceb13d2d05 294 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 295 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 296 {
GregCr 0:e6ceb13d2d05 297 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 298 }
GregCr 0:e6ceb13d2d05 299 else
GregCr 0:e6ceb13d2d05 300 {
GregCr 0:e6ceb13d2d05 301 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 302 }
GregCr 0:e6ceb13d2d05 303
GregCr 0:e6ceb13d2d05 304 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 305 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 306 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 307 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 308 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 309 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 310 fixLen );
GregCr 0:e6ceb13d2d05 311
GregCr 0:e6ceb13d2d05 312 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 313 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 314 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 315 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 316 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 317 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 318 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 319
GregCr 0:e6ceb13d2d05 320 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 321 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 322 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 323 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 324
GregCr 0:e6ceb13d2d05 325 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 326
GregCr 0:e6ceb13d2d05 327 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 328 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 329
mluis 13:618826a997e2 330 if( fixLen == 1 )
mluis 13:618826a997e2 331 {
mluis 13:618826a997e2 332 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 333 }
mluis 13:618826a997e2 334
GregCr 6:e7f02929cd3d 335 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 336 {
GregCr 6:e7f02929cd3d 337 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 338 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 339 }
GregCr 6:e7f02929cd3d 340
mluis 22:7f3aab69cca9 341 if( ( bandwidth == 9 ) && ( RF_MID_BAND_THRESH ) )
mluis 22:7f3aab69cca9 342 {
mluis 22:7f3aab69cca9 343 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 344 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 345 Write( REG_LR_TEST3A, 0x64 );
mluis 22:7f3aab69cca9 346 }
mluis 22:7f3aab69cca9 347 else if( bandwidth == 9 )
mluis 22:7f3aab69cca9 348 {
mluis 22:7f3aab69cca9 349 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 350 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 351 Write( REG_LR_TEST3A, 0x7F );
mluis 22:7f3aab69cca9 352 }
mluis 22:7f3aab69cca9 353 else
mluis 22:7f3aab69cca9 354 {
mluis 22:7f3aab69cca9 355 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 356 Write( REG_LR_TEST36, 0x03 );
mluis 22:7f3aab69cca9 357 }
mluis 22:7f3aab69cca9 358
GregCr 0:e6ceb13d2d05 359 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 360 {
GregCr 0:e6ceb13d2d05 361 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 362 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 363 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 364 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 365 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 366 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 367 }
GregCr 0:e6ceb13d2d05 368 else
GregCr 0:e6ceb13d2d05 369 {
GregCr 0:e6ceb13d2d05 370 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 371 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 372 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 373 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 374 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 375 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 376 }
GregCr 0:e6ceb13d2d05 377 }
GregCr 0:e6ceb13d2d05 378 break;
GregCr 0:e6ceb13d2d05 379 }
GregCr 0:e6ceb13d2d05 380 }
GregCr 0:e6ceb13d2d05 381
mluis 22:7f3aab69cca9 382 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 383 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 384 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 385 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 386 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 387 {
GregCr 0:e6ceb13d2d05 388 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 389 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 390
GregCr 0:e6ceb13d2d05 391 SetModem( modem );
GregCr 0:e6ceb13d2d05 392
GregCr 0:e6ceb13d2d05 393 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 394 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 395
GregCr 0:e6ceb13d2d05 396 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
lzbpli 24:3d058e9d6129 397 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x80;
GregCr 0:e6ceb13d2d05 398
GregCr 0:e6ceb13d2d05 399 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 400 {
GregCr 0:e6ceb13d2d05 401 if( power > 17 )
GregCr 0:e6ceb13d2d05 402 {
GregCr 0:e6ceb13d2d05 403 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 404 }
GregCr 0:e6ceb13d2d05 405 else
GregCr 0:e6ceb13d2d05 406 {
GregCr 0:e6ceb13d2d05 407 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 408 }
GregCr 0:e6ceb13d2d05 409 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 410 {
GregCr 0:e6ceb13d2d05 411 if( power < 5 )
GregCr 0:e6ceb13d2d05 412 {
GregCr 0:e6ceb13d2d05 413 power = 5;
GregCr 0:e6ceb13d2d05 414 }
GregCr 0:e6ceb13d2d05 415 if( power > 20 )
GregCr 0:e6ceb13d2d05 416 {
GregCr 0:e6ceb13d2d05 417 power = 20;
GregCr 0:e6ceb13d2d05 418 }
GregCr 0:e6ceb13d2d05 419 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 420 }
GregCr 0:e6ceb13d2d05 421 else
GregCr 0:e6ceb13d2d05 422 {
GregCr 0:e6ceb13d2d05 423 if( power < 2 )
GregCr 0:e6ceb13d2d05 424 {
GregCr 0:e6ceb13d2d05 425 power = 2;
GregCr 0:e6ceb13d2d05 426 }
GregCr 0:e6ceb13d2d05 427 if( power > 17 )
GregCr 0:e6ceb13d2d05 428 {
GregCr 0:e6ceb13d2d05 429 power = 17;
GregCr 0:e6ceb13d2d05 430 }
GregCr 0:e6ceb13d2d05 431 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 432 }
GregCr 0:e6ceb13d2d05 433 }
GregCr 0:e6ceb13d2d05 434 else
GregCr 0:e6ceb13d2d05 435 {
GregCr 0:e6ceb13d2d05 436 if( power < -1 )
GregCr 0:e6ceb13d2d05 437 {
GregCr 0:e6ceb13d2d05 438 power = -1;
GregCr 0:e6ceb13d2d05 439 }
GregCr 0:e6ceb13d2d05 440 if( power > 14 )
GregCr 0:e6ceb13d2d05 441 {
GregCr 0:e6ceb13d2d05 442 power = 14;
GregCr 0:e6ceb13d2d05 443 }
GregCr 0:e6ceb13d2d05 444 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 445 }
GregCr 0:e6ceb13d2d05 446 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 447 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 448
GregCr 0:e6ceb13d2d05 449 switch( modem )
GregCr 0:e6ceb13d2d05 450 {
GregCr 0:e6ceb13d2d05 451 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 452 {
GregCr 0:e6ceb13d2d05 453 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 454 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 455 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 456 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 457 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 458 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 459 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 460 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 461 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 462
GregCr 0:e6ceb13d2d05 463 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 464 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 465 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 466
GregCr 0:e6ceb13d2d05 467 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 468 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 469 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 470
GregCr 0:e6ceb13d2d05 471 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 472 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 473
GregCr 0:e6ceb13d2d05 474 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 475 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 476 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 477 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 478 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 479 ( crcOn << 4 ) );
mluis 22:7f3aab69cca9 480
GregCr 0:e6ceb13d2d05 481 }
GregCr 0:e6ceb13d2d05 482 break;
GregCr 0:e6ceb13d2d05 483 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 484 {
GregCr 0:e6ceb13d2d05 485 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 486 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 487 {
GregCr 0:e6ceb13d2d05 488 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 489 while( 1 );
GregCr 0:e6ceb13d2d05 490 }
GregCr 0:e6ceb13d2d05 491 bandwidth += 7;
GregCr 0:e6ceb13d2d05 492 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 493 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 494 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 495 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 496 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 497 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 498 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 22:7f3aab69cca9 499 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 500 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 501 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 502
GregCr 0:e6ceb13d2d05 503 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 504 {
GregCr 0:e6ceb13d2d05 505 datarate = 12;
GregCr 0:e6ceb13d2d05 506 }
GregCr 0:e6ceb13d2d05 507 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 508 {
GregCr 0:e6ceb13d2d05 509 datarate = 6;
GregCr 0:e6ceb13d2d05 510 }
GregCr 0:e6ceb13d2d05 511 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 512 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 513 {
GregCr 0:e6ceb13d2d05 514 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 515 }
GregCr 0:e6ceb13d2d05 516 else
GregCr 0:e6ceb13d2d05 517 {
GregCr 0:e6ceb13d2d05 518 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 519 }
mluis 22:7f3aab69cca9 520
GregCr 6:e7f02929cd3d 521 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 522 {
GregCr 6:e7f02929cd3d 523 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 524 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 525 }
mluis 22:7f3aab69cca9 526
GregCr 0:e6ceb13d2d05 527 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 528 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 529 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 530 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 531 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 532 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 533 fixLen );
GregCr 0:e6ceb13d2d05 534
GregCr 0:e6ceb13d2d05 535 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 536 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 537 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 538 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 539 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 540
GregCr 0:e6ceb13d2d05 541 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 542 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 543 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 544 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 545
GregCr 0:e6ceb13d2d05 546 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 547 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 548
GregCr 0:e6ceb13d2d05 549 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 550 {
GregCr 0:e6ceb13d2d05 551 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 552 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 553 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 554 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 555 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 556 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 557 }
GregCr 0:e6ceb13d2d05 558 else
GregCr 0:e6ceb13d2d05 559 {
GregCr 0:e6ceb13d2d05 560 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 561 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 562 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 563 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 564 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 565 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 566 }
GregCr 0:e6ceb13d2d05 567 }
GregCr 0:e6ceb13d2d05 568 break;
GregCr 0:e6ceb13d2d05 569 }
GregCr 0:e6ceb13d2d05 570 }
GregCr 0:e6ceb13d2d05 571
mluis 22:7f3aab69cca9 572 double SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 573 {
mluis 22:7f3aab69cca9 574 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 575
GregCr 0:e6ceb13d2d05 576 switch( modem )
GregCr 0:e6ceb13d2d05 577 {
GregCr 0:e6ceb13d2d05 578 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 579 {
mluis 22:7f3aab69cca9 580 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 581 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 582 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 583 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 584 pktLen +
GregCr 0:e6ceb13d2d05 585 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 586 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 587 }
GregCr 0:e6ceb13d2d05 588 break;
GregCr 0:e6ceb13d2d05 589 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 590 {
GregCr 0:e6ceb13d2d05 591 double bw = 0.0;
GregCr 0:e6ceb13d2d05 592 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 593 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 594 {
GregCr 0:e6ceb13d2d05 595 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 596 // bw = 78e2;
GregCr 0:e6ceb13d2d05 597 // break;
GregCr 0:e6ceb13d2d05 598 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 599 // bw = 104e2;
GregCr 0:e6ceb13d2d05 600 // break;
GregCr 0:e6ceb13d2d05 601 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 602 // bw = 156e2;
GregCr 0:e6ceb13d2d05 603 // break;
GregCr 0:e6ceb13d2d05 604 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 605 // bw = 208e2;
GregCr 0:e6ceb13d2d05 606 // break;
GregCr 0:e6ceb13d2d05 607 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 608 // bw = 312e2;
GregCr 0:e6ceb13d2d05 609 // break;
GregCr 0:e6ceb13d2d05 610 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 611 // bw = 414e2;
GregCr 0:e6ceb13d2d05 612 // break;
GregCr 0:e6ceb13d2d05 613 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 614 // bw = 625e2;
GregCr 0:e6ceb13d2d05 615 // break;
GregCr 0:e6ceb13d2d05 616 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 617 bw = 125e3;
GregCr 0:e6ceb13d2d05 618 break;
GregCr 0:e6ceb13d2d05 619 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 620 bw = 250e3;
GregCr 0:e6ceb13d2d05 621 break;
GregCr 0:e6ceb13d2d05 622 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 623 bw = 500e3;
GregCr 0:e6ceb13d2d05 624 break;
GregCr 0:e6ceb13d2d05 625 }
GregCr 0:e6ceb13d2d05 626
GregCr 0:e6ceb13d2d05 627 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 628 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 629 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 630 // time of preamble
GregCr 0:e6ceb13d2d05 631 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 632 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 633 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 634 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 635 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 636 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 22:7f3aab69cca9 637 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 638 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 639 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 640 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 641 // Time on air
GregCr 0:e6ceb13d2d05 642 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 643 // return us secs
GregCr 0:e6ceb13d2d05 644 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 645 }
GregCr 0:e6ceb13d2d05 646 break;
GregCr 0:e6ceb13d2d05 647 }
GregCr 0:e6ceb13d2d05 648 return airTime;
GregCr 0:e6ceb13d2d05 649 }
GregCr 0:e6ceb13d2d05 650
GregCr 0:e6ceb13d2d05 651 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 652 {
GregCr 0:e6ceb13d2d05 653 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 654
GregCr 0:e6ceb13d2d05 655 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 656 {
GregCr 0:e6ceb13d2d05 657 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 658 {
GregCr 0:e6ceb13d2d05 659 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 660 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 661
GregCr 0:e6ceb13d2d05 662 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 663 {
GregCr 0:e6ceb13d2d05 664 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 665 }
GregCr 0:e6ceb13d2d05 666 else
GregCr 0:e6ceb13d2d05 667 {
GregCr 0:e6ceb13d2d05 668 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 669 }
GregCr 0:e6ceb13d2d05 670
GregCr 0:e6ceb13d2d05 671 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 672 {
GregCr 0:e6ceb13d2d05 673 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 674 }
GregCr 0:e6ceb13d2d05 675 else
GregCr 0:e6ceb13d2d05 676 {
GregCr 0:e6ceb13d2d05 677 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 678 }
GregCr 0:e6ceb13d2d05 679
GregCr 0:e6ceb13d2d05 680 // Write payload buffer
GregCr 0:e6ceb13d2d05 681 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 682 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 683 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 684 }
GregCr 0:e6ceb13d2d05 685 break;
GregCr 0:e6ceb13d2d05 686 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 687 {
GregCr 0:e6ceb13d2d05 688 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 689 {
GregCr 0:e6ceb13d2d05 690 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 22:7f3aab69cca9 691 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 692 }
GregCr 0:e6ceb13d2d05 693 else
GregCr 0:e6ceb13d2d05 694 {
GregCr 0:e6ceb13d2d05 695 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 696 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
GregCr 0:e6ceb13d2d05 697 }
GregCr 0:e6ceb13d2d05 698
GregCr 0:e6ceb13d2d05 699 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 700
GregCr 0:e6ceb13d2d05 701 // Initializes the payload size
GregCr 0:e6ceb13d2d05 702 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 703
GregCr 0:e6ceb13d2d05 704 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 705 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 706 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 707
GregCr 0:e6ceb13d2d05 708 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 709 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 710 {
GregCr 0:e6ceb13d2d05 711 Standby( );
GregCr 4:f0ce52e94d3f 712 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 713 }
GregCr 0:e6ceb13d2d05 714 // Write payload buffer
GregCr 0:e6ceb13d2d05 715 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 716 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 717 }
GregCr 0:e6ceb13d2d05 718 break;
GregCr 0:e6ceb13d2d05 719 }
GregCr 0:e6ceb13d2d05 720
GregCr 0:e6ceb13d2d05 721 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 722 }
GregCr 0:e6ceb13d2d05 723
GregCr 0:e6ceb13d2d05 724 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 725 {
mluis 13:618826a997e2 726 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 727 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 728
GregCr 0:e6ceb13d2d05 729 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 730 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 731 }
GregCr 0:e6ceb13d2d05 732
GregCr 0:e6ceb13d2d05 733 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 734 {
GregCr 0:e6ceb13d2d05 735 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 736 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 737
GregCr 0:e6ceb13d2d05 738 SetOpMode( RF_OPMODE_STANDBY );
mluis 22:7f3aab69cca9 739 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 740 }
GregCr 0:e6ceb13d2d05 741
GregCr 0:e6ceb13d2d05 742 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 743 {
GregCr 0:e6ceb13d2d05 744 bool rxContinuous = false;
mluis 22:7f3aab69cca9 745
GregCr 0:e6ceb13d2d05 746 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 747 {
GregCr 0:e6ceb13d2d05 748 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 749 {
GregCr 0:e6ceb13d2d05 750 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 751
GregCr 0:e6ceb13d2d05 752 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 753 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 754 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 755 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 756 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 757 // DIO5=ModeReady
mluis 22:7f3aab69cca9 758 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 0:e6ceb13d2d05 759 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 760 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 761 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 762
GregCr 0:e6ceb13d2d05 763 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 764 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 765 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 766 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 767
GregCr 0:e6ceb13d2d05 768 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 769
GregCr 0:e6ceb13d2d05 770 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 771 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 772 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 773 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 774 }
GregCr 0:e6ceb13d2d05 775 break;
GregCr 0:e6ceb13d2d05 776 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 777 {
GregCr 0:e6ceb13d2d05 778 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 779 {
GregCr 0:e6ceb13d2d05 780 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 781 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 782 }
GregCr 0:e6ceb13d2d05 783 else
GregCr 0:e6ceb13d2d05 784 {
GregCr 0:e6ceb13d2d05 785 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 786 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
GregCr 0:e6ceb13d2d05 787 }
GregCr 0:e6ceb13d2d05 788
mluis 22:7f3aab69cca9 789
mluis 22:7f3aab69cca9 790 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
mluis 22:7f3aab69cca9 791 if( this->settings.LoRa.Bandwidth < 9 )
mluis 22:7f3aab69cca9 792 {
mluis 22:7f3aab69cca9 793 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
mluis 22:7f3aab69cca9 794 Write( REG_LR_TEST30, 0x00 );
mluis 22:7f3aab69cca9 795 switch( this->settings.LoRa.Bandwidth )
mluis 22:7f3aab69cca9 796 {
mluis 22:7f3aab69cca9 797 case 0: // 7.8 kHz
mluis 22:7f3aab69cca9 798 Write( REG_LR_TEST2F, 0x48 );
mluis 22:7f3aab69cca9 799 SetChannel(this->settings.Channel + 7.81e3 );
mluis 22:7f3aab69cca9 800 break;
mluis 22:7f3aab69cca9 801 case 1: // 10.4 kHz
mluis 22:7f3aab69cca9 802 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 803 SetChannel(this->settings.Channel + 10.42e3 );
mluis 22:7f3aab69cca9 804 break;
mluis 22:7f3aab69cca9 805 case 2: // 15.6 kHz
mluis 22:7f3aab69cca9 806 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 807 SetChannel(this->settings.Channel + 15.62e3 );
mluis 22:7f3aab69cca9 808 break;
mluis 22:7f3aab69cca9 809 case 3: // 20.8 kHz
mluis 22:7f3aab69cca9 810 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 811 SetChannel(this->settings.Channel + 20.83e3 );
mluis 22:7f3aab69cca9 812 break;
mluis 22:7f3aab69cca9 813 case 4: // 31.2 kHz
mluis 22:7f3aab69cca9 814 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 815 SetChannel(this->settings.Channel + 31.25e3 );
mluis 22:7f3aab69cca9 816 break;
mluis 22:7f3aab69cca9 817 case 5: // 41.4 kHz
mluis 22:7f3aab69cca9 818 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 819 SetChannel(this->settings.Channel + 41.67e3 );
mluis 22:7f3aab69cca9 820 break;
mluis 22:7f3aab69cca9 821 case 6: // 62.5 kHz
mluis 22:7f3aab69cca9 822 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 823 break;
mluis 22:7f3aab69cca9 824 case 7: // 125 kHz
mluis 22:7f3aab69cca9 825 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 826 break;
mluis 22:7f3aab69cca9 827 case 8: // 250 kHz
mluis 22:7f3aab69cca9 828 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 829 break;
mluis 22:7f3aab69cca9 830 }
mluis 22:7f3aab69cca9 831 }
mluis 22:7f3aab69cca9 832 else
mluis 22:7f3aab69cca9 833 {
mluis 22:7f3aab69cca9 834 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
mluis 22:7f3aab69cca9 835 }
mluis 22:7f3aab69cca9 836
GregCr 0:e6ceb13d2d05 837 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 838
GregCr 6:e7f02929cd3d 839 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 840 {
GregCr 6:e7f02929cd3d 841 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 842 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 843 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 844 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 845 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 846 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 847 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 848 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 849
mluis 13:618826a997e2 850 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 851 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 852 }
GregCr 6:e7f02929cd3d 853 else
GregCr 6:e7f02929cd3d 854 {
GregCr 6:e7f02929cd3d 855 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 856 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 857 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 858 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 859 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 860 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 861 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 862 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 863
GregCr 6:e7f02929cd3d 864 // DIO0=RxDone
GregCr 6:e7f02929cd3d 865 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 866 }
GregCr 0:e6ceb13d2d05 867 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 868 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 869 }
GregCr 0:e6ceb13d2d05 870 break;
GregCr 0:e6ceb13d2d05 871 }
GregCr 0:e6ceb13d2d05 872
GregCr 0:e6ceb13d2d05 873 memset( rxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 874
mluis 21:2e496deb7858 875 this->settings.State = RF_RX_RUNNING;
GregCr 0:e6ceb13d2d05 876 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 877 {
GregCr 0:e6ceb13d2d05 878 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 879 }
GregCr 0:e6ceb13d2d05 880
GregCr 0:e6ceb13d2d05 881 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 882 {
GregCr 0:e6ceb13d2d05 883 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 884
GregCr 0:e6ceb13d2d05 885 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 886 {
GregCr 0:e6ceb13d2d05 887 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 888 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 889 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 890 1.0 ) + 10.0 ) /
mluis 22:7f3aab69cca9 891 ( double )this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 892 }
GregCr 0:e6ceb13d2d05 893 }
GregCr 0:e6ceb13d2d05 894 else
GregCr 0:e6ceb13d2d05 895 {
GregCr 0:e6ceb13d2d05 896 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 897 {
GregCr 0:e6ceb13d2d05 898 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 899 }
GregCr 0:e6ceb13d2d05 900 else
GregCr 0:e6ceb13d2d05 901 {
GregCr 0:e6ceb13d2d05 902 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 903 }
GregCr 0:e6ceb13d2d05 904 }
GregCr 0:e6ceb13d2d05 905 }
GregCr 0:e6ceb13d2d05 906
GregCr 0:e6ceb13d2d05 907 void SX1276::Tx( uint32_t timeout )
mluis 22:7f3aab69cca9 908 {
mluis 22:7f3aab69cca9 909
GregCr 0:e6ceb13d2d05 910 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 911 {
GregCr 0:e6ceb13d2d05 912 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 913 {
GregCr 0:e6ceb13d2d05 914 // DIO0=PacketSent
GregCr 0:e6ceb13d2d05 915 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 916 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 917 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 918 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 919 // DIO5=ModeReady
mluis 22:7f3aab69cca9 920 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 0:e6ceb13d2d05 921 RF_DIOMAPPING1_DIO2_MASK ) );
GregCr 0:e6ceb13d2d05 922
GregCr 0:e6ceb13d2d05 923 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 924 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 925 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 926 }
GregCr 0:e6ceb13d2d05 927 break;
GregCr 0:e6ceb13d2d05 928 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 929 {
GregCr 6:e7f02929cd3d 930 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 931 {
GregCr 6:e7f02929cd3d 932 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 933 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 934 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 935 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 936 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 937 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 938 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 939 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 940
mluis 22:7f3aab69cca9 941 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 22:7f3aab69cca9 942 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 943 }
GregCr 6:e7f02929cd3d 944 else
GregCr 6:e7f02929cd3d 945 {
GregCr 6:e7f02929cd3d 946 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 947 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 948 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 949 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 950 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 951 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 952 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 953 RFLR_IRQFLAGS_CADDETECTED );
mluis 22:7f3aab69cca9 954
GregCr 6:e7f02929cd3d 955 // DIO0=TxDone
mluis 22:7f3aab69cca9 956 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 957 }
GregCr 0:e6ceb13d2d05 958 }
GregCr 0:e6ceb13d2d05 959 break;
GregCr 0:e6ceb13d2d05 960 }
GregCr 0:e6ceb13d2d05 961
mluis 21:2e496deb7858 962 this->settings.State = RF_TX_RUNNING;
mluis 13:618826a997e2 963 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 964 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 965 }
GregCr 0:e6ceb13d2d05 966
GregCr 7:2b555111463f 967 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 968 {
GregCr 7:2b555111463f 969 switch( this->settings.Modem )
GregCr 7:2b555111463f 970 {
GregCr 7:2b555111463f 971 case MODEM_FSK:
GregCr 7:2b555111463f 972 {
GregCr 7:2b555111463f 973
GregCr 7:2b555111463f 974 }
GregCr 7:2b555111463f 975 break;
GregCr 7:2b555111463f 976 case MODEM_LORA:
GregCr 7:2b555111463f 977 {
GregCr 7:2b555111463f 978 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 979 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 980 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 981 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 982 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 983 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 984 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 985 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 986 );
GregCr 7:2b555111463f 987
GregCr 7:2b555111463f 988 // DIO3=CADDone
GregCr 7:2b555111463f 989 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 990
mluis 21:2e496deb7858 991 this->settings.State = RF_CAD;
GregCr 7:2b555111463f 992 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 993 }
GregCr 7:2b555111463f 994 break;
GregCr 7:2b555111463f 995 default:
GregCr 7:2b555111463f 996 break;
GregCr 7:2b555111463f 997 }
GregCr 7:2b555111463f 998 }
GregCr 7:2b555111463f 999
mluis 22:7f3aab69cca9 1000 int16_t SX1276::GetRssi( RadioModems_t modem )
GregCr 7:2b555111463f 1001 {
GregCr 7:2b555111463f 1002 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 1003
GregCr 0:e6ceb13d2d05 1004 switch( modem )
GregCr 0:e6ceb13d2d05 1005 {
GregCr 0:e6ceb13d2d05 1006 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1007 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1008 break;
GregCr 0:e6ceb13d2d05 1009 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1010 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1011 {
GregCr 0:e6ceb13d2d05 1012 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1013 }
GregCr 0:e6ceb13d2d05 1014 else
GregCr 0:e6ceb13d2d05 1015 {
GregCr 0:e6ceb13d2d05 1016 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1017 }
GregCr 0:e6ceb13d2d05 1018 break;
GregCr 0:e6ceb13d2d05 1019 default:
GregCr 0:e6ceb13d2d05 1020 rssi = -1;
GregCr 0:e6ceb13d2d05 1021 break;
GregCr 0:e6ceb13d2d05 1022 }
GregCr 0:e6ceb13d2d05 1023 return rssi;
GregCr 0:e6ceb13d2d05 1024 }
GregCr 0:e6ceb13d2d05 1025
GregCr 0:e6ceb13d2d05 1026 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 1027 {
GregCr 0:e6ceb13d2d05 1028 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 1029 {
GregCr 0:e6ceb13d2d05 1030 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 1031 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1032 {
GregCr 0:e6ceb13d2d05 1033 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 1034 }
GregCr 0:e6ceb13d2d05 1035 else
GregCr 0:e6ceb13d2d05 1036 {
GregCr 0:e6ceb13d2d05 1037 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 1038 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 1039 {
GregCr 0:e6ceb13d2d05 1040 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 1041 }
GregCr 0:e6ceb13d2d05 1042 else
GregCr 0:e6ceb13d2d05 1043 {
GregCr 0:e6ceb13d2d05 1044 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 1045 }
GregCr 0:e6ceb13d2d05 1046 }
GregCr 0:e6ceb13d2d05 1047 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1048 }
GregCr 0:e6ceb13d2d05 1049 }
GregCr 0:e6ceb13d2d05 1050
mluis 22:7f3aab69cca9 1051 void SX1276::SetModem( RadioModems_t modem )
GregCr 0:e6ceb13d2d05 1052 {
mluis 22:7f3aab69cca9 1053 if( this->settings.Modem == modem )
mluis 22:7f3aab69cca9 1054 {
mluis 22:7f3aab69cca9 1055 return;
mluis 22:7f3aab69cca9 1056 }
mluis 22:7f3aab69cca9 1057
mluis 22:7f3aab69cca9 1058 this->settings.Modem = modem;
mluis 22:7f3aab69cca9 1059 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1060 {
mluis 22:7f3aab69cca9 1061 default:
mluis 22:7f3aab69cca9 1062 case MODEM_FSK:
mluis 22:7f3aab69cca9 1063 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1064 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 22:7f3aab69cca9 1065
mluis 22:7f3aab69cca9 1066 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1067 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 22:7f3aab69cca9 1068 break;
mluis 22:7f3aab69cca9 1069 case MODEM_LORA:
mluis 22:7f3aab69cca9 1070 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1071 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 22:7f3aab69cca9 1072
mluis 22:7f3aab69cca9 1073 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1074 Write( REG_DIOMAPPING2, 0x00 );
mluis 22:7f3aab69cca9 1075 break;
GregCr 0:e6ceb13d2d05 1076 }
GregCr 0:e6ceb13d2d05 1077 }
GregCr 0:e6ceb13d2d05 1078
mluis 22:7f3aab69cca9 1079 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 20:e05596ba4166 1080 {
mluis 20:e05596ba4166 1081 this->SetModem( modem );
mluis 20:e05596ba4166 1082
mluis 20:e05596ba4166 1083 switch( modem )
mluis 20:e05596ba4166 1084 {
mluis 20:e05596ba4166 1085 case MODEM_FSK:
mluis 20:e05596ba4166 1086 if( this->settings.Fsk.FixLen == false )
mluis 20:e05596ba4166 1087 {
mluis 20:e05596ba4166 1088 this->Write( REG_PAYLOADLENGTH, max );
mluis 20:e05596ba4166 1089 }
mluis 20:e05596ba4166 1090 break;
mluis 20:e05596ba4166 1091 case MODEM_LORA:
mluis 20:e05596ba4166 1092 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 20:e05596ba4166 1093 break;
mluis 20:e05596ba4166 1094 }
mluis 20:e05596ba4166 1095 }
mluis 20:e05596ba4166 1096
GregCr 0:e6ceb13d2d05 1097 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1098 {
GregCr 0:e6ceb13d2d05 1099 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1100 {
mluis 21:2e496deb7858 1101 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1102 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1103 {
GregCr 0:e6ceb13d2d05 1104 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1105 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1106 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1107 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1108
GregCr 0:e6ceb13d2d05 1109 // Clear Irqs
GregCr 0:e6ceb13d2d05 1110 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1111 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1112 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1113 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1114
GregCr 0:e6ceb13d2d05 1115 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1116 {
GregCr 0:e6ceb13d2d05 1117 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1118 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1119 }
GregCr 0:e6ceb13d2d05 1120 else
GregCr 0:e6ceb13d2d05 1121 {
mluis 21:2e496deb7858 1122 this->settings.State = RF_IDLE;
GregCr 5:11ec8a6ba4f0 1123 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1124 }
GregCr 0:e6ceb13d2d05 1125 }
mluis 22:7f3aab69cca9 1126 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1127 {
mluis 21:2e496deb7858 1128 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1129 }
GregCr 0:e6ceb13d2d05 1130 break;
mluis 21:2e496deb7858 1131 case RF_TX_RUNNING:
mluis 21:2e496deb7858 1132 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1133 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1134 {
mluis 21:2e496deb7858 1135 this->RadioEvents->TxTimeout( );
GregCr 0:e6ceb13d2d05 1136 }
GregCr 0:e6ceb13d2d05 1137 break;
GregCr 0:e6ceb13d2d05 1138 default:
GregCr 0:e6ceb13d2d05 1139 break;
GregCr 0:e6ceb13d2d05 1140 }
GregCr 0:e6ceb13d2d05 1141 }
GregCr 0:e6ceb13d2d05 1142
GregCr 0:e6ceb13d2d05 1143 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1144 {
mluis 20:e05596ba4166 1145 volatile uint8_t irqFlags = 0;
lzbpli 25:ff4574f6f1a6 1146 pc.printf("OnDio0Irq:%d\r\n",this->settings.State);
GregCr 0:e6ceb13d2d05 1147 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1148 {
mluis 21:2e496deb7858 1149 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1150 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1151 // RxDone interrupt
lzbpli 25:ff4574f6f1a6 1152
GregCr 0:e6ceb13d2d05 1153 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1154 {
GregCr 0:e6ceb13d2d05 1155 case MODEM_FSK:
GregCr 18:99c6e44c1672 1156 if( this->settings.Fsk.CrcOn == true )
GregCr 0:e6ceb13d2d05 1157 {
GregCr 18:99c6e44c1672 1158 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 18:99c6e44c1672 1159 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1160 {
GregCr 18:99c6e44c1672 1161 // Clear Irqs
GregCr 18:99c6e44c1672 1162 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 18:99c6e44c1672 1163 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 18:99c6e44c1672 1164 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 18:99c6e44c1672 1165 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 18:99c6e44c1672 1166
GregCr 18:99c6e44c1672 1167 if( this->settings.Fsk.RxContinuous == false )
GregCr 18:99c6e44c1672 1168 {
mluis 21:2e496deb7858 1169 this->settings.State = RF_IDLE;
GregCr 18:99c6e44c1672 1170 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 18:99c6e44c1672 1171 ( ( Read( REG_SYNCCONFIG ) &
GregCr 18:99c6e44c1672 1172 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 1173 1.0 ) + 10.0 ) /
GregCr 18:99c6e44c1672 1174 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 18:99c6e44c1672 1175 }
GregCr 18:99c6e44c1672 1176 else
GregCr 18:99c6e44c1672 1177 {
GregCr 18:99c6e44c1672 1178 // Continuous mode restart Rx chain
GregCr 18:99c6e44c1672 1179 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 18:99c6e44c1672 1180 }
GregCr 18:99c6e44c1672 1181 rxTimeoutTimer.detach( );
GregCr 18:99c6e44c1672 1182
mluis 22:7f3aab69cca9 1183 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 18:99c6e44c1672 1184 {
mluis 22:7f3aab69cca9 1185 this->RadioEvents->RxError( );
GregCr 18:99c6e44c1672 1186 }
GregCr 18:99c6e44c1672 1187 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 18:99c6e44c1672 1188 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 18:99c6e44c1672 1189 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 18:99c6e44c1672 1190 this->settings.FskPacketHandler.Size = 0;
GregCr 18:99c6e44c1672 1191 break;
GregCr 0:e6ceb13d2d05 1192 }
GregCr 0:e6ceb13d2d05 1193 }
GregCr 18:99c6e44c1672 1194
GregCr 0:e6ceb13d2d05 1195 // Read received packet size
GregCr 0:e6ceb13d2d05 1196 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1197 {
GregCr 0:e6ceb13d2d05 1198 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1199 {
GregCr 0:e6ceb13d2d05 1200 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1201 }
GregCr 0:e6ceb13d2d05 1202 else
GregCr 0:e6ceb13d2d05 1203 {
GregCr 0:e6ceb13d2d05 1204 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1205 }
GregCr 0:e6ceb13d2d05 1206 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1207 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1208 }
GregCr 0:e6ceb13d2d05 1209 else
GregCr 0:e6ceb13d2d05 1210 {
GregCr 0:e6ceb13d2d05 1211 ReadFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1212 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1213 }
GregCr 0:e6ceb13d2d05 1214
GregCr 0:e6ceb13d2d05 1215 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1216 {
mluis 21:2e496deb7858 1217 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1218 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1219 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1220 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 1221 1.0 ) + 10.0 ) /
GregCr 0:e6ceb13d2d05 1222 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1223 }
GregCr 0:e6ceb13d2d05 1224 else
GregCr 0:e6ceb13d2d05 1225 {
GregCr 0:e6ceb13d2d05 1226 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1227 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1228 }
GregCr 0:e6ceb13d2d05 1229 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1230
mluis 22:7f3aab69cca9 1231 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1232 {
mluis 21:2e496deb7858 1233 this->RadioEvents->RxDone( rxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1234 }
GregCr 0:e6ceb13d2d05 1235 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1236 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1237 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1238 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1239 break;
GregCr 0:e6ceb13d2d05 1240 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1241 {
mluis 22:7f3aab69cca9 1242 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1243
GregCr 0:e6ceb13d2d05 1244 // Clear Irq
GregCr 0:e6ceb13d2d05 1245 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1246
GregCr 0:e6ceb13d2d05 1247 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1248 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1249 {
GregCr 0:e6ceb13d2d05 1250 // Clear Irq
GregCr 0:e6ceb13d2d05 1251 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1252
GregCr 0:e6ceb13d2d05 1253 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1254 {
mluis 21:2e496deb7858 1255 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1256 }
GregCr 0:e6ceb13d2d05 1257 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1258
mluis 22:7f3aab69cca9 1259 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 0:e6ceb13d2d05 1260 {
mluis 22:7f3aab69cca9 1261 this->RadioEvents->RxError( );
GregCr 0:e6ceb13d2d05 1262 }
GregCr 0:e6ceb13d2d05 1263 break;
GregCr 0:e6ceb13d2d05 1264 }
GregCr 0:e6ceb13d2d05 1265
GregCr 0:e6ceb13d2d05 1266 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1267 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1268 {
GregCr 0:e6ceb13d2d05 1269 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1270 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1271 snr = -snr;
GregCr 0:e6ceb13d2d05 1272 }
GregCr 0:e6ceb13d2d05 1273 else
GregCr 0:e6ceb13d2d05 1274 {
GregCr 0:e6ceb13d2d05 1275 // Divide by 4
GregCr 0:e6ceb13d2d05 1276 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1277 }
GregCr 0:e6ceb13d2d05 1278
GregCr 7:2b555111463f 1279 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 22:7f3aab69cca9 1280 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1281 {
GregCr 0:e6ceb13d2d05 1282 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1283 {
GregCr 0:e6ceb13d2d05 1284 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1285 snr;
GregCr 0:e6ceb13d2d05 1286 }
GregCr 0:e6ceb13d2d05 1287 else
GregCr 0:e6ceb13d2d05 1288 {
GregCr 0:e6ceb13d2d05 1289 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1290 snr;
GregCr 0:e6ceb13d2d05 1291 }
GregCr 0:e6ceb13d2d05 1292 }
GregCr 0:e6ceb13d2d05 1293 else
GregCr 0:e6ceb13d2d05 1294 {
GregCr 0:e6ceb13d2d05 1295 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1296 {
GregCr 0:e6ceb13d2d05 1297 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1298 }
GregCr 0:e6ceb13d2d05 1299 else
GregCr 0:e6ceb13d2d05 1300 {
GregCr 0:e6ceb13d2d05 1301 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1302 }
GregCr 0:e6ceb13d2d05 1303 }
GregCr 0:e6ceb13d2d05 1304
GregCr 0:e6ceb13d2d05 1305 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 0:e6ceb13d2d05 1306 ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1307
GregCr 0:e6ceb13d2d05 1308 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1309 {
mluis 21:2e496deb7858 1310 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1311 }
GregCr 0:e6ceb13d2d05 1312 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1313
mluis 22:7f3aab69cca9 1314 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1315 {
mluis 21:2e496deb7858 1316 this->RadioEvents->RxDone( rxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1317 }
GregCr 0:e6ceb13d2d05 1318 }
GregCr 0:e6ceb13d2d05 1319 break;
GregCr 0:e6ceb13d2d05 1320 default:
GregCr 0:e6ceb13d2d05 1321 break;
GregCr 0:e6ceb13d2d05 1322 }
GregCr 0:e6ceb13d2d05 1323 break;
mluis 21:2e496deb7858 1324 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1325 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1326 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1327 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1328 {
GregCr 0:e6ceb13d2d05 1329 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1330 // Clear Irq
GregCr 0:e6ceb13d2d05 1331 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1332 // Intentional fall through
GregCr 0:e6ceb13d2d05 1333 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1334 default:
mluis 21:2e496deb7858 1335 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1336 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1337 {
mluis 22:7f3aab69cca9 1338 this->RadioEvents->TxDone( );
GregCr 0:e6ceb13d2d05 1339 }
GregCr 0:e6ceb13d2d05 1340 break;
GregCr 0:e6ceb13d2d05 1341 }
GregCr 0:e6ceb13d2d05 1342 break;
GregCr 0:e6ceb13d2d05 1343 default:
GregCr 0:e6ceb13d2d05 1344 break;
GregCr 0:e6ceb13d2d05 1345 }
GregCr 0:e6ceb13d2d05 1346 }
GregCr 0:e6ceb13d2d05 1347
GregCr 0:e6ceb13d2d05 1348 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1349 {
GregCr 0:e6ceb13d2d05 1350 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1351 {
mluis 21:2e496deb7858 1352 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1353 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1354 {
GregCr 0:e6ceb13d2d05 1355 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1356 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1357 // Read received packet size
GregCr 0:e6ceb13d2d05 1358 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1359 {
GregCr 0:e6ceb13d2d05 1360 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1361 {
GregCr 0:e6ceb13d2d05 1362 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1363 }
GregCr 0:e6ceb13d2d05 1364 else
GregCr 0:e6ceb13d2d05 1365 {
GregCr 0:e6ceb13d2d05 1366 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1367 }
GregCr 0:e6ceb13d2d05 1368 }
GregCr 0:e6ceb13d2d05 1369
GregCr 0:e6ceb13d2d05 1370 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1371 {
GregCr 0:e6ceb13d2d05 1372 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1373 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1374 }
GregCr 0:e6ceb13d2d05 1375 else
GregCr 0:e6ceb13d2d05 1376 {
GregCr 0:e6ceb13d2d05 1377 ReadFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1378 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1379 }
GregCr 0:e6ceb13d2d05 1380 break;
GregCr 0:e6ceb13d2d05 1381 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1382 // Sync time out
GregCr 0:e6ceb13d2d05 1383 rxTimeoutTimer.detach( );
mluis 21:2e496deb7858 1384 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1385 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1386 {
mluis 21:2e496deb7858 1387 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1388 }
GregCr 0:e6ceb13d2d05 1389 break;
GregCr 0:e6ceb13d2d05 1390 default:
GregCr 0:e6ceb13d2d05 1391 break;
GregCr 0:e6ceb13d2d05 1392 }
GregCr 0:e6ceb13d2d05 1393 break;
mluis 21:2e496deb7858 1394 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1395 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1396 {
GregCr 0:e6ceb13d2d05 1397 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1398 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1399 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1400 {
GregCr 0:e6ceb13d2d05 1401 WriteFifo( ( rxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1402 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1403 }
GregCr 0:e6ceb13d2d05 1404 else
GregCr 0:e6ceb13d2d05 1405 {
GregCr 0:e6ceb13d2d05 1406 // Write the last chunk of data
GregCr 0:e6ceb13d2d05 1407 WriteFifo( rxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1408 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1409 }
GregCr 0:e6ceb13d2d05 1410 break;
GregCr 0:e6ceb13d2d05 1411 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1412 break;
GregCr 0:e6ceb13d2d05 1413 default:
GregCr 0:e6ceb13d2d05 1414 break;
GregCr 0:e6ceb13d2d05 1415 }
mluis 22:7f3aab69cca9 1416 break;
GregCr 0:e6ceb13d2d05 1417 default:
GregCr 0:e6ceb13d2d05 1418 break;
GregCr 0:e6ceb13d2d05 1419 }
GregCr 0:e6ceb13d2d05 1420 }
GregCr 0:e6ceb13d2d05 1421
GregCr 0:e6ceb13d2d05 1422 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1423 {
GregCr 0:e6ceb13d2d05 1424 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1425 {
mluis 21:2e496deb7858 1426 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1427 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1428 {
GregCr 0:e6ceb13d2d05 1429 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1430 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1431 {
GregCr 0:e6ceb13d2d05 1432 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1433
GregCr 0:e6ceb13d2d05 1434 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1435
GregCr 0:e6ceb13d2d05 1436 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1437
GregCr 0:e6ceb13d2d05 1438 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1439 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1440 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1441 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1442 }
GregCr 0:e6ceb13d2d05 1443 break;
GregCr 0:e6ceb13d2d05 1444 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1445 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1446 {
GregCr 6:e7f02929cd3d 1447 // Clear Irq
GregCr 6:e7f02929cd3d 1448 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1449
mluis 22:7f3aab69cca9 1450 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1451 {
mluis 21:2e496deb7858 1452 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1453 }
mluis 22:7f3aab69cca9 1454 }
GregCr 0:e6ceb13d2d05 1455 break;
GregCr 0:e6ceb13d2d05 1456 default:
GregCr 0:e6ceb13d2d05 1457 break;
GregCr 0:e6ceb13d2d05 1458 }
GregCr 0:e6ceb13d2d05 1459 break;
mluis 21:2e496deb7858 1460 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1461 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1462 {
GregCr 0:e6ceb13d2d05 1463 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1464 break;
GregCr 0:e6ceb13d2d05 1465 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1466 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1467 {
GregCr 6:e7f02929cd3d 1468 // Clear Irq
GregCr 6:e7f02929cd3d 1469 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1470
mluis 22:7f3aab69cca9 1471 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1472 {
mluis 21:2e496deb7858 1473 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1474 }
mluis 22:7f3aab69cca9 1475 }
GregCr 0:e6ceb13d2d05 1476 break;
GregCr 0:e6ceb13d2d05 1477 default:
GregCr 0:e6ceb13d2d05 1478 break;
GregCr 0:e6ceb13d2d05 1479 }
mluis 22:7f3aab69cca9 1480 break;
GregCr 0:e6ceb13d2d05 1481 default:
GregCr 0:e6ceb13d2d05 1482 break;
GregCr 0:e6ceb13d2d05 1483 }
GregCr 0:e6ceb13d2d05 1484 }
GregCr 0:e6ceb13d2d05 1485
GregCr 0:e6ceb13d2d05 1486 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1487 {
GregCr 0:e6ceb13d2d05 1488 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1489 {
GregCr 0:e6ceb13d2d05 1490 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1491 break;
GregCr 0:e6ceb13d2d05 1492 case MODEM_LORA:
mluis 22:7f3aab69cca9 1493 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 13:618826a997e2 1494 {
mluis 13:618826a997e2 1495 // Clear Irq
mluis 22:7f3aab69cca9 1496 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1497 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1498 {
mluis 21:2e496deb7858 1499 this->RadioEvents->CadDone( true );
mluis 13:618826a997e2 1500 }
GregCr 12:aa5b3bf7fdf4 1501 }
GregCr 12:aa5b3bf7fdf4 1502 else
mluis 13:618826a997e2 1503 {
mluis 13:618826a997e2 1504 // Clear Irq
mluis 13:618826a997e2 1505 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1506 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1507 {
mluis 21:2e496deb7858 1508 this->RadioEvents->CadDone( false );
mluis 13:618826a997e2 1509 }
GregCr 7:2b555111463f 1510 }
GregCr 0:e6ceb13d2d05 1511 break;
GregCr 0:e6ceb13d2d05 1512 default:
GregCr 0:e6ceb13d2d05 1513 break;
GregCr 0:e6ceb13d2d05 1514 }
GregCr 0:e6ceb13d2d05 1515 }
GregCr 0:e6ceb13d2d05 1516
GregCr 0:e6ceb13d2d05 1517 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1518 {
GregCr 0:e6ceb13d2d05 1519 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1520 {
GregCr 0:e6ceb13d2d05 1521 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1522 {
GregCr 0:e6ceb13d2d05 1523 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1524 {
GregCr 0:e6ceb13d2d05 1525 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1526 }
GregCr 0:e6ceb13d2d05 1527 }
GregCr 0:e6ceb13d2d05 1528 break;
GregCr 0:e6ceb13d2d05 1529 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1530 break;
GregCr 0:e6ceb13d2d05 1531 default:
GregCr 0:e6ceb13d2d05 1532 break;
GregCr 0:e6ceb13d2d05 1533 }
GregCr 0:e6ceb13d2d05 1534 }
GregCr 0:e6ceb13d2d05 1535
GregCr 0:e6ceb13d2d05 1536 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1537 {
GregCr 0:e6ceb13d2d05 1538 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1539 {
GregCr 0:e6ceb13d2d05 1540 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1541 break;
GregCr 0:e6ceb13d2d05 1542 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1543 break;
GregCr 0:e6ceb13d2d05 1544 default:
GregCr 0:e6ceb13d2d05 1545 break;
GregCr 0:e6ceb13d2d05 1546 }
mluis 13:618826a997e2 1547 }