lzbp li / SX1276Lib-test

sanfan-lora

Fork of SX1276Lib by lzbp li

sx1276/sx1276.cpp@26:ba9dda357a36, 2016-09-22 (annotated)

Committer:
lzbpli
Date:
Thu Sep 22 06:30:08 2016 +0000
Revision:
26:ba9dda357a36
Parent:
25:ff4574f6f1a6 
gengxinxinbanben;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
mluis 15:04374b1c33fa 39 { 250000, 0x01 },
mluis 16:d447f8d2d2d6 40 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 41 };
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43
mluis 21:2e496deb7858 44 SX1276::SX1276( RadioEvents_t *events,
mluis 13:618826a997e2 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 21:2e496deb7858 47 : Radio( events ),
mluis 13:618826a997e2 48 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 49 nss( nss ),
mluis 13:618826a997e2 50 reset( reset ),
mluis 13:618826a997e2 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 52 isRadioActive( false )
GregCr 0:e6ceb13d2d05 53 {
mluis 13:618826a997e2 54 wait_ms( 10 );
mluis 13:618826a997e2 55 this->rxTx = 0;
lzbpli 26:ba9dda357a36 56 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
lzbpli 26:ba9dda357a36 57 currentOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 58
mluis 21:2e496deb7858 59 this->RadioEvents = events;
mluis 21:2e496deb7858 60
mluis 13:618826a997e2 61 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 62
mluis 13:618826a997e2 63 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 64 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 65 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 66 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 67 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 68 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 69
mluis 21:2e496deb7858 70 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 71 }
GregCr 0:e6ceb13d2d05 72
GregCr 0:e6ceb13d2d05 73 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 74 {
lzbpli 26:ba9dda357a36 75 delete this->rxtxBuffer;
mluis 13:618826a997e2 76 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 77 }
GregCr 0:e6ceb13d2d05 78
mluis 21:2e496deb7858 79 void SX1276::Init( RadioEvents_t *events )
mluis 21:2e496deb7858 80 {
mluis 21:2e496deb7858 81 this->RadioEvents = events;
mluis 21:2e496deb7858 82 }
mluis 21:2e496deb7858 83
GregCr 19:71a47bb03fbb 84 RadioState SX1276::GetStatus( void )
GregCr 0:e6ceb13d2d05 85 {
GregCr 0:e6ceb13d2d05 86 return this->settings.State;
GregCr 0:e6ceb13d2d05 87 }
GregCr 0:e6ceb13d2d05 88
GregCr 0:e6ceb13d2d05 89 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 90 {
GregCr 0:e6ceb13d2d05 91 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 92 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 93 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 94 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 95 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 96 }
GregCr 0:e6ceb13d2d05 97
mluis 22:7f3aab69cca9 98 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
GregCr 0:e6ceb13d2d05 99 {
GregCr 7:2b555111463f 100 int16_t rssi = 0;
lzbpli 26:ba9dda357a36 101
GregCr 0:e6ceb13d2d05 102 SetModem( modem );
GregCr 0:e6ceb13d2d05 103
GregCr 0:e6ceb13d2d05 104 SetChannel( freq );
lzbpli 26:ba9dda357a36 105
GregCr 0:e6ceb13d2d05 106 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 107
GregCr 4:f0ce52e94d3f 108 wait_ms( 1 );
lzbpli 26:ba9dda357a36 109
GregCr 0:e6ceb13d2d05 110 rssi = GetRssi( modem );
lzbpli 26:ba9dda357a36 111
GregCr 0:e6ceb13d2d05 112 Sleep( );
lzbpli 26:ba9dda357a36 113
mluis 22:7f3aab69cca9 114 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 115 {
GregCr 0:e6ceb13d2d05 116 return false;
GregCr 0:e6ceb13d2d05 117 }
GregCr 0:e6ceb13d2d05 118 return true;
GregCr 0:e6ceb13d2d05 119 }
GregCr 0:e6ceb13d2d05 120
GregCr 0:e6ceb13d2d05 121 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 122 {
GregCr 0:e6ceb13d2d05 123 uint8_t i;
GregCr 0:e6ceb13d2d05 124 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 125
GregCr 0:e6ceb13d2d05 126 /*
lzbpli 26:ba9dda357a36 127 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 128 */
GregCr 0:e6ceb13d2d05 129 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 130 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 131
GregCr 0:e6ceb13d2d05 132 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 133 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 134 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 135 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 136 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 137 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 138 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 139 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 140 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 141
GregCr 0:e6ceb13d2d05 142 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 143 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 144
GregCr 0:e6ceb13d2d05 145 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 146 {
GregCr 4:f0ce52e94d3f 147 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 148 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 149 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 150 }
GregCr 0:e6ceb13d2d05 151
GregCr 0:e6ceb13d2d05 152 Sleep( );
GregCr 0:e6ceb13d2d05 153
GregCr 0:e6ceb13d2d05 154 return rnd;
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 /*!
mluis 22:7f3aab69cca9 158 * Performs the Rx chain calibration for LF and HF bands
mluis 22:7f3aab69cca9 159 * \remark Must be called just after the reset so all registers are at their
mluis 22:7f3aab69cca9 160 * default values
mluis 22:7f3aab69cca9 161 */
mluis 22:7f3aab69cca9 162 void SX1276::RxChainCalibration( void )
mluis 22:7f3aab69cca9 163 {
mluis 22:7f3aab69cca9 164 uint8_t regPaConfigInitVal;
mluis 22:7f3aab69cca9 165 uint32_t initialFreq;
mluis 22:7f3aab69cca9 166
mluis 22:7f3aab69cca9 167 // Save context
mluis 22:7f3aab69cca9 168 regPaConfigInitVal = this->Read( REG_PACONFIG );
mluis 22:7f3aab69cca9 169 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
mluis 22:7f3aab69cca9 170 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
mluis 22:7f3aab69cca9 171 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
mluis 22:7f3aab69cca9 172
mluis 22:7f3aab69cca9 173 // Cut the PA just in case, RFO output, power = -1 dBm
mluis 22:7f3aab69cca9 174 this->Write( REG_PACONFIG, 0x00 );
mluis 22:7f3aab69cca9 175
mluis 22:7f3aab69cca9 176 // Launch Rx chain calibration for LF band
mluis 22:7f3aab69cca9 177 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 178 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 179 {
mluis 22:7f3aab69cca9 180 }
mluis 22:7f3aab69cca9 181
mluis 22:7f3aab69cca9 182 // Sets a Frequency in HF band
mluis 22:7f3aab69cca9 183 SetChannel( 868000000 );
mluis 22:7f3aab69cca9 184
lzbpli 26:ba9dda357a36 185 // Launch Rx chain calibration for HF band
mluis 22:7f3aab69cca9 186 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 187 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 188 {
mluis 22:7f3aab69cca9 189 }
mluis 22:7f3aab69cca9 190
mluis 22:7f3aab69cca9 191 // Restore context
mluis 22:7f3aab69cca9 192 this->Write( REG_PACONFIG, regPaConfigInitVal );
mluis 22:7f3aab69cca9 193 SetChannel( initialFreq );
mluis 22:7f3aab69cca9 194 }
mluis 22:7f3aab69cca9 195
mluis 22:7f3aab69cca9 196 /*!
GregCr 0:e6ceb13d2d05 197 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 198 *
GregCr 0:e6ceb13d2d05 199 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 200 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 201 */
GregCr 0:e6ceb13d2d05 202 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 203 {
GregCr 0:e6ceb13d2d05 204 uint8_t i;
GregCr 0:e6ceb13d2d05 205
GregCr 0:e6ceb13d2d05 206 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 207 {
GregCr 0:e6ceb13d2d05 208 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 209 {
GregCr 0:e6ceb13d2d05 210 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 211 }
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 214 while( 1 );
GregCr 0:e6ceb13d2d05 215 }
GregCr 0:e6ceb13d2d05 216
mluis 22:7f3aab69cca9 217 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 218 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 219 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 220 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 221 uint8_t payloadLen,
mluis 13:618826a997e2 222 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 223 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 SetModem( modem );
GregCr 0:e6ceb13d2d05 226
GregCr 0:e6ceb13d2d05 227 switch( modem )
GregCr 0:e6ceb13d2d05 228 {
GregCr 0:e6ceb13d2d05 229 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 230 {
GregCr 0:e6ceb13d2d05 231 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 232 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 233 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 234 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 235 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 236 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 237 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 238 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 239 this->settings.Fsk.PreambleLen = preambleLen;
lzbpli 26:ba9dda357a36 240
GregCr 0:e6ceb13d2d05 241 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 242 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 243 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 246 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 247
mluis 14:8552d0b840be 248 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 249 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
lzbpli 26:ba9dda357a36 250
mluis 22:7f3aab69cca9 251 if( fixLen == 1 )
mluis 22:7f3aab69cca9 252 {
mluis 22:7f3aab69cca9 253 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 22:7f3aab69cca9 254 }
lzbpli 26:ba9dda357a36 255 else
lzbpli 26:ba9dda357a36 256 {
lzbpli 26:ba9dda357a36 257 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
lzbpli 26:ba9dda357a36 258 }
lzbpli 26:ba9dda357a36 259
GregCr 0:e6ceb13d2d05 260 Write( REG_PACKETCONFIG1,
lzbpli 26:ba9dda357a36 261 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 262 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 263 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 264 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 265 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 266 }
GregCr 0:e6ceb13d2d05 267 break;
GregCr 0:e6ceb13d2d05 268 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 269 {
GregCr 0:e6ceb13d2d05 270 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 271 {
GregCr 0:e6ceb13d2d05 272 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 273 while( 1 );
GregCr 0:e6ceb13d2d05 274 }
GregCr 0:e6ceb13d2d05 275 bandwidth += 7;
GregCr 0:e6ceb13d2d05 276 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 277 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 278 this->settings.LoRa.Coderate = coderate;
mluis 22:7f3aab69cca9 279 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 280 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 281 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 283 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 284 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 285 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 286 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 22:7f3aab69cca9 287
GregCr 0:e6ceb13d2d05 288 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 289 {
GregCr 0:e6ceb13d2d05 290 datarate = 12;
GregCr 0:e6ceb13d2d05 291 }
GregCr 0:e6ceb13d2d05 292 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 293 {
GregCr 0:e6ceb13d2d05 294 datarate = 6;
GregCr 0:e6ceb13d2d05 295 }
lzbpli 26:ba9dda357a36 296
GregCr 0:e6ceb13d2d05 297 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 298 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 299 {
GregCr 0:e6ceb13d2d05 300 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 301 }
GregCr 0:e6ceb13d2d05 302 else
GregCr 0:e6ceb13d2d05 303 {
GregCr 0:e6ceb13d2d05 304 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 305 }
GregCr 0:e6ceb13d2d05 306
lzbpli 26:ba9dda357a36 307 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 308 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 309 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 310 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 311 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
lzbpli 26:ba9dda357a36 312 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 313 fixLen );
lzbpli 26:ba9dda357a36 314
GregCr 0:e6ceb13d2d05 315 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 316 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 317 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 318 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 319 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 320 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 321 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 322
lzbpli 26:ba9dda357a36 323 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 324 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 325 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 326 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 327
GregCr 0:e6ceb13d2d05 328 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
lzbpli 26:ba9dda357a36 329
GregCr 0:e6ceb13d2d05 330 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 331 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 332
mluis 13:618826a997e2 333 if( fixLen == 1 )
mluis 13:618826a997e2 334 {
mluis 13:618826a997e2 335 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 336 }
mluis 13:618826a997e2 337
GregCr 6:e7f02929cd3d 338 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 339 {
GregCr 6:e7f02929cd3d 340 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 341 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 342 }
GregCr 6:e7f02929cd3d 343
lzbpli 26:ba9dda357a36 344 if( ( bandwidth == 9 ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
mluis 22:7f3aab69cca9 345 {
lzbpli 26:ba9dda357a36 346 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 347 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 348 Write( REG_LR_TEST3A, 0x64 );
mluis 22:7f3aab69cca9 349 }
mluis 22:7f3aab69cca9 350 else if( bandwidth == 9 )
mluis 22:7f3aab69cca9 351 {
mluis 22:7f3aab69cca9 352 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 353 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 354 Write( REG_LR_TEST3A, 0x7F );
mluis 22:7f3aab69cca9 355 }
mluis 22:7f3aab69cca9 356 else
mluis 22:7f3aab69cca9 357 {
mluis 22:7f3aab69cca9 358 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 359 Write( REG_LR_TEST36, 0x03 );
mluis 22:7f3aab69cca9 360 }
lzbpli 26:ba9dda357a36 361
GregCr 0:e6ceb13d2d05 362 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 363 {
lzbpli 26:ba9dda357a36 364 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 365 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 366 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 367 RFLR_DETECTIONOPTIMIZE_SF6 );
lzbpli 26:ba9dda357a36 368 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 369 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 370 }
GregCr 0:e6ceb13d2d05 371 else
GregCr 0:e6ceb13d2d05 372 {
GregCr 0:e6ceb13d2d05 373 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 374 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 375 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 376 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
lzbpli 26:ba9dda357a36 377 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 378 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 379 }
GregCr 0:e6ceb13d2d05 380 }
GregCr 0:e6ceb13d2d05 381 break;
GregCr 0:e6ceb13d2d05 382 }
GregCr 0:e6ceb13d2d05 383 }
GregCr 0:e6ceb13d2d05 384
lzbpli 26:ba9dda357a36 385 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 386 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 387 uint8_t coderate, uint16_t preambleLen,
lzbpli 26:ba9dda357a36 388 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 389 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 390 {
GregCr 0:e6ceb13d2d05 391 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 392 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 393
GregCr 0:e6ceb13d2d05 394 SetModem( modem );
lzbpli 26:ba9dda357a36 395
GregCr 0:e6ceb13d2d05 396 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 397 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 398
GregCr 0:e6ceb13d2d05 399 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
lzbpli 24:3d058e9d6129 400 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x80;
GregCr 0:e6ceb13d2d05 401
GregCr 0:e6ceb13d2d05 402 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 403 {
GregCr 0:e6ceb13d2d05 404 if( power > 17 )
GregCr 0:e6ceb13d2d05 405 {
GregCr 0:e6ceb13d2d05 406 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 407 }
GregCr 0:e6ceb13d2d05 408 else
GregCr 0:e6ceb13d2d05 409 {
GregCr 0:e6ceb13d2d05 410 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 411 }
GregCr 0:e6ceb13d2d05 412 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 413 {
GregCr 0:e6ceb13d2d05 414 if( power < 5 )
GregCr 0:e6ceb13d2d05 415 {
GregCr 0:e6ceb13d2d05 416 power = 5;
GregCr 0:e6ceb13d2d05 417 }
GregCr 0:e6ceb13d2d05 418 if( power > 20 )
GregCr 0:e6ceb13d2d05 419 {
GregCr 0:e6ceb13d2d05 420 power = 20;
GregCr 0:e6ceb13d2d05 421 }
GregCr 0:e6ceb13d2d05 422 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 423 }
GregCr 0:e6ceb13d2d05 424 else
GregCr 0:e6ceb13d2d05 425 {
GregCr 0:e6ceb13d2d05 426 if( power < 2 )
GregCr 0:e6ceb13d2d05 427 {
GregCr 0:e6ceb13d2d05 428 power = 2;
GregCr 0:e6ceb13d2d05 429 }
GregCr 0:e6ceb13d2d05 430 if( power > 17 )
GregCr 0:e6ceb13d2d05 431 {
GregCr 0:e6ceb13d2d05 432 power = 17;
GregCr 0:e6ceb13d2d05 433 }
GregCr 0:e6ceb13d2d05 434 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 435 }
GregCr 0:e6ceb13d2d05 436 }
GregCr 0:e6ceb13d2d05 437 else
GregCr 0:e6ceb13d2d05 438 {
GregCr 0:e6ceb13d2d05 439 if( power < -1 )
GregCr 0:e6ceb13d2d05 440 {
GregCr 0:e6ceb13d2d05 441 power = -1;
GregCr 0:e6ceb13d2d05 442 }
GregCr 0:e6ceb13d2d05 443 if( power > 14 )
GregCr 0:e6ceb13d2d05 444 {
GregCr 0:e6ceb13d2d05 445 power = 14;
GregCr 0:e6ceb13d2d05 446 }
GregCr 0:e6ceb13d2d05 447 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 448 }
GregCr 0:e6ceb13d2d05 449 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 450 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 451
GregCr 0:e6ceb13d2d05 452 switch( modem )
GregCr 0:e6ceb13d2d05 453 {
GregCr 0:e6ceb13d2d05 454 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 455 {
GregCr 0:e6ceb13d2d05 456 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 457 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 458 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 459 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 460 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 461 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 462 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 463 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 464 this->settings.Fsk.TxTimeout = timeout;
lzbpli 26:ba9dda357a36 465
GregCr 0:e6ceb13d2d05 466 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 467 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 468 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 469
GregCr 0:e6ceb13d2d05 470 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 471 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 472 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 473
GregCr 0:e6ceb13d2d05 474 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 475 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 476
GregCr 0:e6ceb13d2d05 477 Write( REG_PACKETCONFIG1,
lzbpli 26:ba9dda357a36 478 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 479 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 480 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 481 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 482 ( crcOn << 4 ) );
lzbpli 26:ba9dda357a36 483
GregCr 0:e6ceb13d2d05 484 }
GregCr 0:e6ceb13d2d05 485 break;
GregCr 0:e6ceb13d2d05 486 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 487 {
GregCr 0:e6ceb13d2d05 488 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 489 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 490 {
GregCr 0:e6ceb13d2d05 491 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 492 while( 1 );
GregCr 0:e6ceb13d2d05 493 }
GregCr 0:e6ceb13d2d05 494 bandwidth += 7;
GregCr 0:e6ceb13d2d05 495 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 496 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 497 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 498 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 499 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 500 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 501 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 22:7f3aab69cca9 502 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 503 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 504 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 505
GregCr 0:e6ceb13d2d05 506 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 507 {
GregCr 0:e6ceb13d2d05 508 datarate = 12;
GregCr 0:e6ceb13d2d05 509 }
GregCr 0:e6ceb13d2d05 510 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 511 {
GregCr 0:e6ceb13d2d05 512 datarate = 6;
GregCr 0:e6ceb13d2d05 513 }
GregCr 0:e6ceb13d2d05 514 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 515 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 516 {
GregCr 0:e6ceb13d2d05 517 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 518 }
GregCr 0:e6ceb13d2d05 519 else
GregCr 0:e6ceb13d2d05 520 {
GregCr 0:e6ceb13d2d05 521 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 522 }
mluis 22:7f3aab69cca9 523
GregCr 6:e7f02929cd3d 524 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 525 {
GregCr 6:e7f02929cd3d 526 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 527 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 528 }
mluis 22:7f3aab69cca9 529
lzbpli 26:ba9dda357a36 530 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 531 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 532 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 533 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 534 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
lzbpli 26:ba9dda357a36 535 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 536 fixLen );
GregCr 0:e6ceb13d2d05 537
GregCr 0:e6ceb13d2d05 538 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 539 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 540 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 541 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 542 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 543
lzbpli 26:ba9dda357a36 544 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 545 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 546 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 547 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
lzbpli 26:ba9dda357a36 548
GregCr 0:e6ceb13d2d05 549 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 550 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
lzbpli 26:ba9dda357a36 551
GregCr 0:e6ceb13d2d05 552 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 553 {
lzbpli 26:ba9dda357a36 554 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 555 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 556 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 557 RFLR_DETECTIONOPTIMIZE_SF6 );
lzbpli 26:ba9dda357a36 558 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 559 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 560 }
GregCr 0:e6ceb13d2d05 561 else
GregCr 0:e6ceb13d2d05 562 {
GregCr 0:e6ceb13d2d05 563 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 564 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 565 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 566 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
lzbpli 26:ba9dda357a36 567 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 568 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 569 }
GregCr 0:e6ceb13d2d05 570 }
GregCr 0:e6ceb13d2d05 571 break;
GregCr 0:e6ceb13d2d05 572 }
GregCr 0:e6ceb13d2d05 573 }
GregCr 0:e6ceb13d2d05 574
mluis 22:7f3aab69cca9 575 double SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 576 {
mluis 22:7f3aab69cca9 577 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 578
GregCr 0:e6ceb13d2d05 579 switch( modem )
GregCr 0:e6ceb13d2d05 580 {
GregCr 0:e6ceb13d2d05 581 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 582 {
mluis 22:7f3aab69cca9 583 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 584 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 585 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 586 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 587 pktLen +
GregCr 0:e6ceb13d2d05 588 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 589 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 590 }
GregCr 0:e6ceb13d2d05 591 break;
GregCr 0:e6ceb13d2d05 592 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 593 {
GregCr 0:e6ceb13d2d05 594 double bw = 0.0;
GregCr 0:e6ceb13d2d05 595 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 596 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 597 {
GregCr 0:e6ceb13d2d05 598 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 599 // bw = 78e2;
GregCr 0:e6ceb13d2d05 600 // break;
GregCr 0:e6ceb13d2d05 601 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 602 // bw = 104e2;
GregCr 0:e6ceb13d2d05 603 // break;
GregCr 0:e6ceb13d2d05 604 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 605 // bw = 156e2;
GregCr 0:e6ceb13d2d05 606 // break;
GregCr 0:e6ceb13d2d05 607 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 608 // bw = 208e2;
GregCr 0:e6ceb13d2d05 609 // break;
GregCr 0:e6ceb13d2d05 610 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 611 // bw = 312e2;
GregCr 0:e6ceb13d2d05 612 // break;
GregCr 0:e6ceb13d2d05 613 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 614 // bw = 414e2;
GregCr 0:e6ceb13d2d05 615 // break;
GregCr 0:e6ceb13d2d05 616 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 617 // bw = 625e2;
GregCr 0:e6ceb13d2d05 618 // break;
GregCr 0:e6ceb13d2d05 619 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 620 bw = 125e3;
GregCr 0:e6ceb13d2d05 621 break;
GregCr 0:e6ceb13d2d05 622 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 623 bw = 250e3;
GregCr 0:e6ceb13d2d05 624 break;
GregCr 0:e6ceb13d2d05 625 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 626 bw = 500e3;
GregCr 0:e6ceb13d2d05 627 break;
GregCr 0:e6ceb13d2d05 628 }
GregCr 0:e6ceb13d2d05 629
GregCr 0:e6ceb13d2d05 630 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 631 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 632 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 633 // time of preamble
GregCr 0:e6ceb13d2d05 634 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 635 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 636 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 637 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 638 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 639 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 22:7f3aab69cca9 640 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 641 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 642 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 643 double tPayload = nPayload * ts;
lzbpli 26:ba9dda357a36 644 // Time on air
GregCr 0:e6ceb13d2d05 645 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 646 // return us secs
GregCr 0:e6ceb13d2d05 647 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 648 }
GregCr 0:e6ceb13d2d05 649 break;
GregCr 0:e6ceb13d2d05 650 }
GregCr 0:e6ceb13d2d05 651 return airTime;
GregCr 0:e6ceb13d2d05 652 }
GregCr 0:e6ceb13d2d05 653
GregCr 0:e6ceb13d2d05 654 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 655 {
GregCr 0:e6ceb13d2d05 656 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 657
GregCr 0:e6ceb13d2d05 658 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 659 {
GregCr 0:e6ceb13d2d05 660 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 661 {
GregCr 0:e6ceb13d2d05 662 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 663 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 664
GregCr 0:e6ceb13d2d05 665 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 666 {
GregCr 0:e6ceb13d2d05 667 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 668 }
GregCr 0:e6ceb13d2d05 669 else
GregCr 0:e6ceb13d2d05 670 {
GregCr 0:e6ceb13d2d05 671 Write( REG_PAYLOADLENGTH, size );
lzbpli 26:ba9dda357a36 672 }
lzbpli 26:ba9dda357a36 673
GregCr 0:e6ceb13d2d05 674 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 675 {
GregCr 0:e6ceb13d2d05 676 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 677 }
GregCr 0:e6ceb13d2d05 678 else
GregCr 0:e6ceb13d2d05 679 {
lzbpli 26:ba9dda357a36 680 memcpy( rxtxBuffer, buffer, size );
GregCr 0:e6ceb13d2d05 681 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 682 }
GregCr 0:e6ceb13d2d05 683
GregCr 0:e6ceb13d2d05 684 // Write payload buffer
GregCr 0:e6ceb13d2d05 685 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 686 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 687 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 688 }
GregCr 0:e6ceb13d2d05 689 break;
GregCr 0:e6ceb13d2d05 690 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 691 {
GregCr 0:e6ceb13d2d05 692 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 693 {
GregCr 0:e6ceb13d2d05 694 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 22:7f3aab69cca9 695 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 696 }
GregCr 0:e6ceb13d2d05 697 else
GregCr 0:e6ceb13d2d05 698 {
GregCr 0:e6ceb13d2d05 699 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 700 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
lzbpli 26:ba9dda357a36 701 }
lzbpli 26:ba9dda357a36 702
GregCr 0:e6ceb13d2d05 703 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 704
GregCr 0:e6ceb13d2d05 705 // Initializes the payload size
GregCr 0:e6ceb13d2d05 706 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 707
lzbpli 26:ba9dda357a36 708 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 709 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 710 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 711
GregCr 0:e6ceb13d2d05 712 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 713 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 714 {
GregCr 0:e6ceb13d2d05 715 Standby( );
GregCr 4:f0ce52e94d3f 716 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 717 }
GregCr 0:e6ceb13d2d05 718 // Write payload buffer
GregCr 0:e6ceb13d2d05 719 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 720 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 721 }
GregCr 0:e6ceb13d2d05 722 break;
GregCr 0:e6ceb13d2d05 723 }
GregCr 0:e6ceb13d2d05 724
GregCr 0:e6ceb13d2d05 725 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 726 }
GregCr 0:e6ceb13d2d05 727
GregCr 0:e6ceb13d2d05 728 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 729 {
mluis 13:618826a997e2 730 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 731 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 732
GregCr 0:e6ceb13d2d05 733 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 734 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 735 }
GregCr 0:e6ceb13d2d05 736
GregCr 0:e6ceb13d2d05 737 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 738 {
GregCr 0:e6ceb13d2d05 739 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 740 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 741
GregCr 0:e6ceb13d2d05 742 SetOpMode( RF_OPMODE_STANDBY );
mluis 22:7f3aab69cca9 743 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 744 }
GregCr 0:e6ceb13d2d05 745
GregCr 0:e6ceb13d2d05 746 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 747 {
GregCr 0:e6ceb13d2d05 748 bool rxContinuous = false;
mluis 22:7f3aab69cca9 749
GregCr 0:e6ceb13d2d05 750 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 751 {
GregCr 0:e6ceb13d2d05 752 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 753 {
GregCr 0:e6ceb13d2d05 754 rxContinuous = this->settings.Fsk.RxContinuous;
lzbpli 26:ba9dda357a36 755
GregCr 0:e6ceb13d2d05 756 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 757 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 758 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 759 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 760 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 761 // DIO5=ModeReady
mluis 22:7f3aab69cca9 762 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
lzbpli 26:ba9dda357a36 763 RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 764 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 765 RF_DIOMAPPING1_DIO0_00 |
lzbpli 26:ba9dda357a36 766 RF_DIOMAPPING1_DIO1_00 |
GregCr 0:e6ceb13d2d05 767 RF_DIOMAPPING1_DIO2_11 );
lzbpli 26:ba9dda357a36 768
GregCr 0:e6ceb13d2d05 769 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
lzbpli 26:ba9dda357a36 770 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 771 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 772 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
lzbpli 26:ba9dda357a36 773
GregCr 0:e6ceb13d2d05 774 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
lzbpli 26:ba9dda357a36 775
lzbpli 26:ba9dda357a36 776 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
lzbpli 26:ba9dda357a36 777
GregCr 0:e6ceb13d2d05 778 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 779 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 780 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 781 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 782 }
GregCr 0:e6ceb13d2d05 783 break;
GregCr 0:e6ceb13d2d05 784 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 785 {
GregCr 0:e6ceb13d2d05 786 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 787 {
GregCr 0:e6ceb13d2d05 788 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 789 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 790 }
GregCr 0:e6ceb13d2d05 791 else
GregCr 0:e6ceb13d2d05 792 {
GregCr 0:e6ceb13d2d05 793 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 794 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
lzbpli 26:ba9dda357a36 795 }
mluis 22:7f3aab69cca9 796
mluis 22:7f3aab69cca9 797 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
mluis 22:7f3aab69cca9 798 if( this->settings.LoRa.Bandwidth < 9 )
mluis 22:7f3aab69cca9 799 {
mluis 22:7f3aab69cca9 800 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
mluis 22:7f3aab69cca9 801 Write( REG_LR_TEST30, 0x00 );
mluis 22:7f3aab69cca9 802 switch( this->settings.LoRa.Bandwidth )
mluis 22:7f3aab69cca9 803 {
mluis 22:7f3aab69cca9 804 case 0: // 7.8 kHz
mluis 22:7f3aab69cca9 805 Write( REG_LR_TEST2F, 0x48 );
mluis 22:7f3aab69cca9 806 SetChannel(this->settings.Channel + 7.81e3 );
mluis 22:7f3aab69cca9 807 break;
mluis 22:7f3aab69cca9 808 case 1: // 10.4 kHz
mluis 22:7f3aab69cca9 809 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 810 SetChannel(this->settings.Channel + 10.42e3 );
mluis 22:7f3aab69cca9 811 break;
mluis 22:7f3aab69cca9 812 case 2: // 15.6 kHz
mluis 22:7f3aab69cca9 813 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 814 SetChannel(this->settings.Channel + 15.62e3 );
mluis 22:7f3aab69cca9 815 break;
mluis 22:7f3aab69cca9 816 case 3: // 20.8 kHz
mluis 22:7f3aab69cca9 817 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 818 SetChannel(this->settings.Channel + 20.83e3 );
mluis 22:7f3aab69cca9 819 break;
mluis 22:7f3aab69cca9 820 case 4: // 31.2 kHz
mluis 22:7f3aab69cca9 821 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 822 SetChannel(this->settings.Channel + 31.25e3 );
mluis 22:7f3aab69cca9 823 break;
mluis 22:7f3aab69cca9 824 case 5: // 41.4 kHz
mluis 22:7f3aab69cca9 825 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 826 SetChannel(this->settings.Channel + 41.67e3 );
mluis 22:7f3aab69cca9 827 break;
mluis 22:7f3aab69cca9 828 case 6: // 62.5 kHz
mluis 22:7f3aab69cca9 829 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 830 break;
mluis 22:7f3aab69cca9 831 case 7: // 125 kHz
mluis 22:7f3aab69cca9 832 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 833 break;
mluis 22:7f3aab69cca9 834 case 8: // 250 kHz
mluis 22:7f3aab69cca9 835 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 836 break;
mluis 22:7f3aab69cca9 837 }
mluis 22:7f3aab69cca9 838 }
mluis 22:7f3aab69cca9 839 else
mluis 22:7f3aab69cca9 840 {
mluis 22:7f3aab69cca9 841 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
mluis 22:7f3aab69cca9 842 }
mluis 22:7f3aab69cca9 843
GregCr 0:e6ceb13d2d05 844 rxContinuous = this->settings.LoRa.RxContinuous;
lzbpli 26:ba9dda357a36 845
GregCr 6:e7f02929cd3d 846 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 847 {
GregCr 6:e7f02929cd3d 848 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 849 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 850 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 851 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 852 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 853 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 854 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 855 RFLR_IRQFLAGS_CADDETECTED );
lzbpli 26:ba9dda357a36 856
mluis 13:618826a997e2 857 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 858 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 859 }
GregCr 6:e7f02929cd3d 860 else
GregCr 6:e7f02929cd3d 861 {
GregCr 6:e7f02929cd3d 862 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 863 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 864 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 865 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 866 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 867 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 868 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 869 RFLR_IRQFLAGS_CADDETECTED );
lzbpli 26:ba9dda357a36 870
GregCr 6:e7f02929cd3d 871 // DIO0=RxDone
GregCr 6:e7f02929cd3d 872 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 873 }
GregCr 0:e6ceb13d2d05 874 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 875 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 876 }
GregCr 0:e6ceb13d2d05 877 break;
GregCr 0:e6ceb13d2d05 878 }
GregCr 0:e6ceb13d2d05 879
lzbpli 26:ba9dda357a36 880 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 881
mluis 21:2e496deb7858 882 this->settings.State = RF_RX_RUNNING;
GregCr 0:e6ceb13d2d05 883 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 884 {
GregCr 0:e6ceb13d2d05 885 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 886 }
GregCr 0:e6ceb13d2d05 887
GregCr 0:e6ceb13d2d05 888 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 889 {
GregCr 0:e6ceb13d2d05 890 SetOpMode( RF_OPMODE_RECEIVER );
lzbpli 26:ba9dda357a36 891
GregCr 0:e6ceb13d2d05 892 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 893 {
lzbpli 26:ba9dda357a36 894 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
lzbpli 26:ba9dda357a36 895 ( ( Read( REG_SYNCCONFIG ) &
lzbpli 26:ba9dda357a36 896 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
lzbpli 26:ba9dda357a36 897 1.0 ) + 10.0 ) /
lzbpli 26:ba9dda357a36 898 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 0:e6ceb13d2d05 899 }
GregCr 0:e6ceb13d2d05 900 }
GregCr 0:e6ceb13d2d05 901 else
GregCr 0:e6ceb13d2d05 902 {
GregCr 0:e6ceb13d2d05 903 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 904 {
GregCr 0:e6ceb13d2d05 905 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 906 }
GregCr 0:e6ceb13d2d05 907 else
GregCr 0:e6ceb13d2d05 908 {
GregCr 0:e6ceb13d2d05 909 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 910 }
GregCr 0:e6ceb13d2d05 911 }
GregCr 0:e6ceb13d2d05 912 }
GregCr 0:e6ceb13d2d05 913
GregCr 0:e6ceb13d2d05 914 void SX1276::Tx( uint32_t timeout )
mluis 22:7f3aab69cca9 915 {
mluis 22:7f3aab69cca9 916
GregCr 0:e6ceb13d2d05 917 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 918 {
GregCr 0:e6ceb13d2d05 919 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 920 {
GregCr 0:e6ceb13d2d05 921 // DIO0=PacketSent
lzbpli 26:ba9dda357a36 922 // DIO1=FifoEmpty
GregCr 0:e6ceb13d2d05 923 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 924 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 925 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 926 // DIO5=ModeReady
mluis 22:7f3aab69cca9 927 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
lzbpli 26:ba9dda357a36 928 RF_DIOMAPPING1_DIO1_MASK &
lzbpli 26:ba9dda357a36 929 RF_DIOMAPPING1_DIO2_MASK ) |
lzbpli 26:ba9dda357a36 930 RF_DIOMAPPING1_DIO1_01 );
GregCr 0:e6ceb13d2d05 931
GregCr 0:e6ceb13d2d05 932 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 933 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 934 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 935 }
GregCr 0:e6ceb13d2d05 936 break;
GregCr 0:e6ceb13d2d05 937 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 938 {
GregCr 6:e7f02929cd3d 939 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 940 {
GregCr 6:e7f02929cd3d 941 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 942 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 943 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 944 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 945 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 946 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 947 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 948 RFLR_IRQFLAGS_CADDETECTED );
lzbpli 26:ba9dda357a36 949
mluis 22:7f3aab69cca9 950 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 22:7f3aab69cca9 951 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 952 }
GregCr 6:e7f02929cd3d 953 else
GregCr 6:e7f02929cd3d 954 {
GregCr 6:e7f02929cd3d 955 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 956 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 957 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 958 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 959 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 960 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 961 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 962 RFLR_IRQFLAGS_CADDETECTED );
mluis 22:7f3aab69cca9 963
GregCr 6:e7f02929cd3d 964 // DIO0=TxDone
mluis 22:7f3aab69cca9 965 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 966 }
GregCr 0:e6ceb13d2d05 967 }
GregCr 0:e6ceb13d2d05 968 break;
GregCr 0:e6ceb13d2d05 969 }
GregCr 0:e6ceb13d2d05 970
mluis 21:2e496deb7858 971 this->settings.State = RF_TX_RUNNING;
mluis 13:618826a997e2 972 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 973 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 974 }
GregCr 0:e6ceb13d2d05 975
GregCr 7:2b555111463f 976 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 977 {
GregCr 7:2b555111463f 978 switch( this->settings.Modem )
GregCr 7:2b555111463f 979 {
GregCr 7:2b555111463f 980 case MODEM_FSK:
GregCr 7:2b555111463f 981 {
lzbpli 26:ba9dda357a36 982
GregCr 7:2b555111463f 983 }
GregCr 7:2b555111463f 984 break;
GregCr 7:2b555111463f 985 case MODEM_LORA:
GregCr 7:2b555111463f 986 {
GregCr 7:2b555111463f 987 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 988 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 989 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 990 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 991 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 992 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 993 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
lzbpli 26:ba9dda357a36 994 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 995 );
lzbpli 26:ba9dda357a36 996
GregCr 7:2b555111463f 997 // DIO3=CADDone
GregCr 7:2b555111463f 998 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
lzbpli 26:ba9dda357a36 999
mluis 21:2e496deb7858 1000 this->settings.State = RF_CAD;
GregCr 7:2b555111463f 1001 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 1002 }
GregCr 7:2b555111463f 1003 break;
GregCr 7:2b555111463f 1004 default:
GregCr 7:2b555111463f 1005 break;
GregCr 7:2b555111463f 1006 }
GregCr 7:2b555111463f 1007 }
GregCr 7:2b555111463f 1008
mluis 22:7f3aab69cca9 1009 int16_t SX1276::GetRssi( RadioModems_t modem )
GregCr 7:2b555111463f 1010 {
GregCr 7:2b555111463f 1011 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 1012
GregCr 0:e6ceb13d2d05 1013 switch( modem )
GregCr 0:e6ceb13d2d05 1014 {
GregCr 0:e6ceb13d2d05 1015 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1016 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1017 break;
GregCr 0:e6ceb13d2d05 1018 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1019 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1020 {
GregCr 0:e6ceb13d2d05 1021 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1022 }
GregCr 0:e6ceb13d2d05 1023 else
GregCr 0:e6ceb13d2d05 1024 {
GregCr 0:e6ceb13d2d05 1025 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1026 }
GregCr 0:e6ceb13d2d05 1027 break;
GregCr 0:e6ceb13d2d05 1028 default:
GregCr 0:e6ceb13d2d05 1029 rssi = -1;
GregCr 0:e6ceb13d2d05 1030 break;
GregCr 0:e6ceb13d2d05 1031 }
GregCr 0:e6ceb13d2d05 1032 return rssi;
GregCr 0:e6ceb13d2d05 1033 }
GregCr 0:e6ceb13d2d05 1034
GregCr 0:e6ceb13d2d05 1035 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 1036 {
lzbpli 26:ba9dda357a36 1037 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1038 {
lzbpli 26:ba9dda357a36 1039 SetAntSwLowPower( true );
lzbpli 26:ba9dda357a36 1040 }
lzbpli 26:ba9dda357a36 1041 else
lzbpli 26:ba9dda357a36 1042 {
lzbpli 26:ba9dda357a36 1043 SetAntSwLowPower( false );
lzbpli 26:ba9dda357a36 1044 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 1045 {
lzbpli 26:ba9dda357a36 1046 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 1047 }
GregCr 0:e6ceb13d2d05 1048 else
GregCr 0:e6ceb13d2d05 1049 {
lzbpli 26:ba9dda357a36 1050 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 1051 }
GregCr 0:e6ceb13d2d05 1052 }
lzbpli 26:ba9dda357a36 1053 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1054 }
GregCr 0:e6ceb13d2d05 1055
mluis 22:7f3aab69cca9 1056 void SX1276::SetModem( RadioModems_t modem )
GregCr 0:e6ceb13d2d05 1057 {
mluis 22:7f3aab69cca9 1058 if( this->settings.Modem == modem )
mluis 22:7f3aab69cca9 1059 {
mluis 22:7f3aab69cca9 1060 return;
mluis 22:7f3aab69cca9 1061 }
mluis 22:7f3aab69cca9 1062
mluis 22:7f3aab69cca9 1063 this->settings.Modem = modem;
mluis 22:7f3aab69cca9 1064 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1065 {
mluis 22:7f3aab69cca9 1066 default:
mluis 22:7f3aab69cca9 1067 case MODEM_FSK:
mluis 22:7f3aab69cca9 1068 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1069 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 22:7f3aab69cca9 1070
mluis 22:7f3aab69cca9 1071 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1072 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 22:7f3aab69cca9 1073 break;
mluis 22:7f3aab69cca9 1074 case MODEM_LORA:
mluis 22:7f3aab69cca9 1075 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1076 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 22:7f3aab69cca9 1077
mluis 22:7f3aab69cca9 1078 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1079 Write( REG_DIOMAPPING2, 0x00 );
mluis 22:7f3aab69cca9 1080 break;
GregCr 0:e6ceb13d2d05 1081 }
GregCr 0:e6ceb13d2d05 1082 }
GregCr 0:e6ceb13d2d05 1083
mluis 22:7f3aab69cca9 1084 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 20:e05596ba4166 1085 {
mluis 20:e05596ba4166 1086 this->SetModem( modem );
mluis 20:e05596ba4166 1087
mluis 20:e05596ba4166 1088 switch( modem )
mluis 20:e05596ba4166 1089 {
mluis 20:e05596ba4166 1090 case MODEM_FSK:
mluis 20:e05596ba4166 1091 if( this->settings.Fsk.FixLen == false )
mluis 20:e05596ba4166 1092 {
mluis 20:e05596ba4166 1093 this->Write( REG_PAYLOADLENGTH, max );
mluis 20:e05596ba4166 1094 }
mluis 20:e05596ba4166 1095 break;
mluis 20:e05596ba4166 1096 case MODEM_LORA:
mluis 20:e05596ba4166 1097 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 20:e05596ba4166 1098 break;
mluis 20:e05596ba4166 1099 }
mluis 20:e05596ba4166 1100 }
mluis 20:e05596ba4166 1101
GregCr 0:e6ceb13d2d05 1102 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1103 {
GregCr 0:e6ceb13d2d05 1104 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1105 {
mluis 21:2e496deb7858 1106 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1107 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1108 {
GregCr 0:e6ceb13d2d05 1109 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1110 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1111 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1112 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1113
GregCr 0:e6ceb13d2d05 1114 // Clear Irqs
lzbpli 26:ba9dda357a36 1115 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1116 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1117 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1118 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1119
GregCr 0:e6ceb13d2d05 1120 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1121 {
GregCr 0:e6ceb13d2d05 1122 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1123 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
lzbpli 26:ba9dda357a36 1124 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
lzbpli 26:ba9dda357a36 1125 ( ( Read( REG_SYNCCONFIG ) &
lzbpli 26:ba9dda357a36 1126 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
lzbpli 26:ba9dda357a36 1127 1.0 ) + 10.0 ) /
lzbpli 26:ba9dda357a36 1128 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 0:e6ceb13d2d05 1129 }
GregCr 0:e6ceb13d2d05 1130 else
GregCr 0:e6ceb13d2d05 1131 {
mluis 21:2e496deb7858 1132 this->settings.State = RF_IDLE;
GregCr 5:11ec8a6ba4f0 1133 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1134 }
GregCr 0:e6ceb13d2d05 1135 }
mluis 22:7f3aab69cca9 1136 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1137 {
mluis 21:2e496deb7858 1138 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1139 }
GregCr 0:e6ceb13d2d05 1140 break;
mluis 21:2e496deb7858 1141 case RF_TX_RUNNING:
mluis 21:2e496deb7858 1142 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1143 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1144 {
mluis 21:2e496deb7858 1145 this->RadioEvents->TxTimeout( );
GregCr 0:e6ceb13d2d05 1146 }
GregCr 0:e6ceb13d2d05 1147 break;
GregCr 0:e6ceb13d2d05 1148 default:
GregCr 0:e6ceb13d2d05 1149 break;
GregCr 0:e6ceb13d2d05 1150 }
GregCr 0:e6ceb13d2d05 1151 }
GregCr 0:e6ceb13d2d05 1152
GregCr 0:e6ceb13d2d05 1153 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1154 {
mluis 20:e05596ba4166 1155 volatile uint8_t irqFlags = 0;
lzbpli 26:ba9dda357a36 1156
GregCr 0:e6ceb13d2d05 1157 switch( this->settings.State )
lzbpli 26:ba9dda357a36 1158 {
mluis 21:2e496deb7858 1159 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1160 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1161 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1162 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1163 {
GregCr 0:e6ceb13d2d05 1164 case MODEM_FSK:
GregCr 18:99c6e44c1672 1165 if( this->settings.Fsk.CrcOn == true )
GregCr 0:e6ceb13d2d05 1166 {
GregCr 18:99c6e44c1672 1167 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 18:99c6e44c1672 1168 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1169 {
GregCr 18:99c6e44c1672 1170 // Clear Irqs
lzbpli 26:ba9dda357a36 1171 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 18:99c6e44c1672 1172 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 18:99c6e44c1672 1173 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 18:99c6e44c1672 1174 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
lzbpli 26:ba9dda357a36 1175
lzbpli 26:ba9dda357a36 1176 rxTimeoutTimer.detach( );
lzbpli 26:ba9dda357a36 1177
GregCr 18:99c6e44c1672 1178 if( this->settings.Fsk.RxContinuous == false )
GregCr 18:99c6e44c1672 1179 {
lzbpli 26:ba9dda357a36 1180 rxTimeoutSyncWord.detach( );
mluis 21:2e496deb7858 1181 this->settings.State = RF_IDLE;
GregCr 18:99c6e44c1672 1182 }
GregCr 18:99c6e44c1672 1183 else
GregCr 18:99c6e44c1672 1184 {
GregCr 18:99c6e44c1672 1185 // Continuous mode restart Rx chain
GregCr 18:99c6e44c1672 1186 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
lzbpli 26:ba9dda357a36 1187 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
lzbpli 26:ba9dda357a36 1188 ( ( Read( REG_SYNCCONFIG ) &
lzbpli 26:ba9dda357a36 1189 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
lzbpli 26:ba9dda357a36 1190 1.0 ) + 10.0 ) /
lzbpli 26:ba9dda357a36 1191 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 18:99c6e44c1672 1192 }
lzbpli 26:ba9dda357a36 1193
lzbpli 26:ba9dda357a36 1194
mluis 22:7f3aab69cca9 1195 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 18:99c6e44c1672 1196 {
mluis 22:7f3aab69cca9 1197 this->RadioEvents->RxError( );
GregCr 18:99c6e44c1672 1198 }
GregCr 18:99c6e44c1672 1199 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 18:99c6e44c1672 1200 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 18:99c6e44c1672 1201 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 18:99c6e44c1672 1202 this->settings.FskPacketHandler.Size = 0;
GregCr 18:99c6e44c1672 1203 break;
GregCr 0:e6ceb13d2d05 1204 }
GregCr 0:e6ceb13d2d05 1205 }
lzbpli 26:ba9dda357a36 1206
GregCr 0:e6ceb13d2d05 1207 // Read received packet size
GregCr 0:e6ceb13d2d05 1208 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1209 {
GregCr 0:e6ceb13d2d05 1210 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1211 {
GregCr 0:e6ceb13d2d05 1212 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1213 }
GregCr 0:e6ceb13d2d05 1214 else
GregCr 0:e6ceb13d2d05 1215 {
GregCr 0:e6ceb13d2d05 1216 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1217 }
lzbpli 26:ba9dda357a36 1218 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1219 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1220 }
GregCr 0:e6ceb13d2d05 1221 else
GregCr 0:e6ceb13d2d05 1222 {
lzbpli 26:ba9dda357a36 1223 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1224 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1225 }
GregCr 0:e6ceb13d2d05 1226
lzbpli 26:ba9dda357a36 1227 rxTimeoutTimer.detach( );
lzbpli 26:ba9dda357a36 1228
GregCr 0:e6ceb13d2d05 1229 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1230 {
mluis 21:2e496deb7858 1231 this->settings.State = RF_IDLE;
lzbpli 26:ba9dda357a36 1232 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1233 }
GregCr 0:e6ceb13d2d05 1234 else
GregCr 0:e6ceb13d2d05 1235 {
GregCr 0:e6ceb13d2d05 1236 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1237 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
lzbpli 26:ba9dda357a36 1238 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
lzbpli 26:ba9dda357a36 1239 ( ( Read( REG_SYNCCONFIG ) &
lzbpli 26:ba9dda357a36 1240 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
lzbpli 26:ba9dda357a36 1241 1.0 ) + 10.0 ) /
lzbpli 26:ba9dda357a36 1242 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
GregCr 0:e6ceb13d2d05 1243 }
GregCr 0:e6ceb13d2d05 1244
mluis 22:7f3aab69cca9 1245 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1246 {
lzbpli 26:ba9dda357a36 1247 this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
lzbpli 26:ba9dda357a36 1248 }
GregCr 0:e6ceb13d2d05 1249 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1250 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1251 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1252 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1253 break;
GregCr 0:e6ceb13d2d05 1254 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1255 {
mluis 22:7f3aab69cca9 1256 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1257
GregCr 0:e6ceb13d2d05 1258 // Clear Irq
GregCr 0:e6ceb13d2d05 1259 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1260
GregCr 0:e6ceb13d2d05 1261 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1262 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1263 {
GregCr 0:e6ceb13d2d05 1264 // Clear Irq
GregCr 0:e6ceb13d2d05 1265 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1266
GregCr 0:e6ceb13d2d05 1267 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1268 {
mluis 21:2e496deb7858 1269 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1270 }
GregCr 0:e6ceb13d2d05 1271 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1272
mluis 22:7f3aab69cca9 1273 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 0:e6ceb13d2d05 1274 {
mluis 22:7f3aab69cca9 1275 this->RadioEvents->RxError( );
GregCr 0:e6ceb13d2d05 1276 }
GregCr 0:e6ceb13d2d05 1277 break;
GregCr 0:e6ceb13d2d05 1278 }
GregCr 0:e6ceb13d2d05 1279
GregCr 0:e6ceb13d2d05 1280 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1281 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1282 {
GregCr 0:e6ceb13d2d05 1283 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1284 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1285 snr = -snr;
GregCr 0:e6ceb13d2d05 1286 }
GregCr 0:e6ceb13d2d05 1287 else
GregCr 0:e6ceb13d2d05 1288 {
GregCr 0:e6ceb13d2d05 1289 // Divide by 4
GregCr 0:e6ceb13d2d05 1290 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1291 }
GregCr 0:e6ceb13d2d05 1292
GregCr 7:2b555111463f 1293 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 22:7f3aab69cca9 1294 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1295 {
GregCr 0:e6ceb13d2d05 1296 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1297 {
GregCr 0:e6ceb13d2d05 1298 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1299 snr;
GregCr 0:e6ceb13d2d05 1300 }
GregCr 0:e6ceb13d2d05 1301 else
GregCr 0:e6ceb13d2d05 1302 {
GregCr 0:e6ceb13d2d05 1303 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1304 snr;
GregCr 0:e6ceb13d2d05 1305 }
GregCr 0:e6ceb13d2d05 1306 }
GregCr 0:e6ceb13d2d05 1307 else
lzbpli 26:ba9dda357a36 1308 {
GregCr 0:e6ceb13d2d05 1309 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1310 {
GregCr 0:e6ceb13d2d05 1311 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1312 }
GregCr 0:e6ceb13d2d05 1313 else
GregCr 0:e6ceb13d2d05 1314 {
GregCr 0:e6ceb13d2d05 1315 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1316 }
GregCr 0:e6ceb13d2d05 1317 }
GregCr 0:e6ceb13d2d05 1318
GregCr 0:e6ceb13d2d05 1319 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
lzbpli 26:ba9dda357a36 1320 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
lzbpli 26:ba9dda357a36 1321
GregCr 0:e6ceb13d2d05 1322 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1323 {
mluis 21:2e496deb7858 1324 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1325 }
GregCr 0:e6ceb13d2d05 1326 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1327
mluis 22:7f3aab69cca9 1328 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1329 {
lzbpli 26:ba9dda357a36 1330 this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1331 }
GregCr 0:e6ceb13d2d05 1332 }
GregCr 0:e6ceb13d2d05 1333 break;
GregCr 0:e6ceb13d2d05 1334 default:
GregCr 0:e6ceb13d2d05 1335 break;
GregCr 0:e6ceb13d2d05 1336 }
GregCr 0:e6ceb13d2d05 1337 break;
mluis 21:2e496deb7858 1338 case RF_TX_RUNNING:
lzbpli 26:ba9dda357a36 1339 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1340 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1341 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1342 {
GregCr 0:e6ceb13d2d05 1343 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1344 // Clear Irq
GregCr 0:e6ceb13d2d05 1345 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1346 // Intentional fall through
GregCr 0:e6ceb13d2d05 1347 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1348 default:
mluis 21:2e496deb7858 1349 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1350 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1351 {
mluis 22:7f3aab69cca9 1352 this->RadioEvents->TxDone( );
lzbpli 26:ba9dda357a36 1353 }
GregCr 0:e6ceb13d2d05 1354 break;
GregCr 0:e6ceb13d2d05 1355 }
GregCr 0:e6ceb13d2d05 1356 break;
GregCr 0:e6ceb13d2d05 1357 default:
GregCr 0:e6ceb13d2d05 1358 break;
GregCr 0:e6ceb13d2d05 1359 }
GregCr 0:e6ceb13d2d05 1360 }
GregCr 0:e6ceb13d2d05 1361
GregCr 0:e6ceb13d2d05 1362 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1363 {
GregCr 0:e6ceb13d2d05 1364 switch( this->settings.State )
lzbpli 26:ba9dda357a36 1365 {
mluis 21:2e496deb7858 1366 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1367 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1368 {
GregCr 0:e6ceb13d2d05 1369 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1370 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1371 // Read received packet size
GregCr 0:e6ceb13d2d05 1372 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1373 {
GregCr 0:e6ceb13d2d05 1374 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1375 {
GregCr 0:e6ceb13d2d05 1376 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1377 }
GregCr 0:e6ceb13d2d05 1378 else
GregCr 0:e6ceb13d2d05 1379 {
GregCr 0:e6ceb13d2d05 1380 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1381 }
GregCr 0:e6ceb13d2d05 1382 }
GregCr 0:e6ceb13d2d05 1383
GregCr 0:e6ceb13d2d05 1384 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1385 {
lzbpli 26:ba9dda357a36 1386 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1387 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1388 }
GregCr 0:e6ceb13d2d05 1389 else
GregCr 0:e6ceb13d2d05 1390 {
lzbpli 26:ba9dda357a36 1391 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1392 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1393 }
GregCr 0:e6ceb13d2d05 1394 break;
GregCr 0:e6ceb13d2d05 1395 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1396 // Sync time out
GregCr 0:e6ceb13d2d05 1397 rxTimeoutTimer.detach( );
mluis 21:2e496deb7858 1398 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1399 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1400 {
mluis 21:2e496deb7858 1401 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1402 }
GregCr 0:e6ceb13d2d05 1403 break;
GregCr 0:e6ceb13d2d05 1404 default:
GregCr 0:e6ceb13d2d05 1405 break;
GregCr 0:e6ceb13d2d05 1406 }
GregCr 0:e6ceb13d2d05 1407 break;
mluis 21:2e496deb7858 1408 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1409 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1410 {
GregCr 0:e6ceb13d2d05 1411 case MODEM_FSK:
lzbpli 26:ba9dda357a36 1412 // FifoEmpty interrupt
GregCr 0:e6ceb13d2d05 1413 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1414 {
lzbpli 26:ba9dda357a36 1415 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1416 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1417 }
lzbpli 26:ba9dda357a36 1418 else
GregCr 0:e6ceb13d2d05 1419 {
GregCr 0:e6ceb13d2d05 1420 // Write the last chunk of data
lzbpli 26:ba9dda357a36 1421 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1422 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1423 }
GregCr 0:e6ceb13d2d05 1424 break;
GregCr 0:e6ceb13d2d05 1425 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1426 break;
GregCr 0:e6ceb13d2d05 1427 default:
GregCr 0:e6ceb13d2d05 1428 break;
GregCr 0:e6ceb13d2d05 1429 }
mluis 22:7f3aab69cca9 1430 break;
GregCr 0:e6ceb13d2d05 1431 default:
GregCr 0:e6ceb13d2d05 1432 break;
GregCr 0:e6ceb13d2d05 1433 }
GregCr 0:e6ceb13d2d05 1434 }
GregCr 0:e6ceb13d2d05 1435
GregCr 0:e6ceb13d2d05 1436 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1437 {
GregCr 0:e6ceb13d2d05 1438 switch( this->settings.State )
lzbpli 26:ba9dda357a36 1439 {
mluis 21:2e496deb7858 1440 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1441 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1442 {
GregCr 0:e6ceb13d2d05 1443 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1444 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1445 {
GregCr 0:e6ceb13d2d05 1446 rxTimeoutSyncWord.detach( );
lzbpli 26:ba9dda357a36 1447
GregCr 0:e6ceb13d2d05 1448 this->settings.FskPacketHandler.SyncWordDetected = true;
lzbpli 26:ba9dda357a36 1449
GregCr 0:e6ceb13d2d05 1450 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1451
GregCr 0:e6ceb13d2d05 1452 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1453 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1454 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1455 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1456 }
GregCr 0:e6ceb13d2d05 1457 break;
GregCr 0:e6ceb13d2d05 1458 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1459 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1460 {
GregCr 6:e7f02929cd3d 1461 // Clear Irq
GregCr 6:e7f02929cd3d 1462 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
lzbpli 26:ba9dda357a36 1463
mluis 22:7f3aab69cca9 1464 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1465 {
mluis 21:2e496deb7858 1466 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1467 }
mluis 22:7f3aab69cca9 1468 }
GregCr 0:e6ceb13d2d05 1469 break;
GregCr 0:e6ceb13d2d05 1470 default:
GregCr 0:e6ceb13d2d05 1471 break;
GregCr 0:e6ceb13d2d05 1472 }
GregCr 0:e6ceb13d2d05 1473 break;
mluis 21:2e496deb7858 1474 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1475 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1476 {
GregCr 0:e6ceb13d2d05 1477 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1478 break;
GregCr 0:e6ceb13d2d05 1479 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1480 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1481 {
GregCr 6:e7f02929cd3d 1482 // Clear Irq
GregCr 6:e7f02929cd3d 1483 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
lzbpli 26:ba9dda357a36 1484
mluis 22:7f3aab69cca9 1485 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1486 {
mluis 21:2e496deb7858 1487 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1488 }
mluis 22:7f3aab69cca9 1489 }
GregCr 0:e6ceb13d2d05 1490 break;
GregCr 0:e6ceb13d2d05 1491 default:
GregCr 0:e6ceb13d2d05 1492 break;
GregCr 0:e6ceb13d2d05 1493 }
mluis 22:7f3aab69cca9 1494 break;
GregCr 0:e6ceb13d2d05 1495 default:
GregCr 0:e6ceb13d2d05 1496 break;
GregCr 0:e6ceb13d2d05 1497 }
GregCr 0:e6ceb13d2d05 1498 }
GregCr 0:e6ceb13d2d05 1499
GregCr 0:e6ceb13d2d05 1500 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1501 {
GregCr 0:e6ceb13d2d05 1502 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1503 {
GregCr 0:e6ceb13d2d05 1504 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1505 break;
GregCr 0:e6ceb13d2d05 1506 case MODEM_LORA:
mluis 22:7f3aab69cca9 1507 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 13:618826a997e2 1508 {
mluis 13:618826a997e2 1509 // Clear Irq
mluis 22:7f3aab69cca9 1510 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1511 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1512 {
mluis 21:2e496deb7858 1513 this->RadioEvents->CadDone( true );
mluis 13:618826a997e2 1514 }
GregCr 12:aa5b3bf7fdf4 1515 }
GregCr 12:aa5b3bf7fdf4 1516 else
lzbpli 26:ba9dda357a36 1517 {
mluis 13:618826a997e2 1518 // Clear Irq
mluis 13:618826a997e2 1519 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1520 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1521 {
mluis 21:2e496deb7858 1522 this->RadioEvents->CadDone( false );
mluis 13:618826a997e2 1523 }
GregCr 7:2b555111463f 1524 }
GregCr 0:e6ceb13d2d05 1525 break;
GregCr 0:e6ceb13d2d05 1526 default:
GregCr 0:e6ceb13d2d05 1527 break;
GregCr 0:e6ceb13d2d05 1528 }
GregCr 0:e6ceb13d2d05 1529 }
GregCr 0:e6ceb13d2d05 1530
GregCr 0:e6ceb13d2d05 1531 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1532 {
GregCr 0:e6ceb13d2d05 1533 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1534 {
GregCr 0:e6ceb13d2d05 1535 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1536 {
GregCr 0:e6ceb13d2d05 1537 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1538 {
GregCr 0:e6ceb13d2d05 1539 this->settings.FskPacketHandler.PreambleDetected = true;
lzbpli 26:ba9dda357a36 1540 }
GregCr 0:e6ceb13d2d05 1541 }
GregCr 0:e6ceb13d2d05 1542 break;
GregCr 0:e6ceb13d2d05 1543 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1544 break;
GregCr 0:e6ceb13d2d05 1545 default:
GregCr 0:e6ceb13d2d05 1546 break;
GregCr 0:e6ceb13d2d05 1547 }
GregCr 0:e6ceb13d2d05 1548 }
GregCr 0:e6ceb13d2d05 1549
GregCr 0:e6ceb13d2d05 1550 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1551 {
GregCr 0:e6ceb13d2d05 1552 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1553 {
GregCr 0:e6ceb13d2d05 1554 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1555 break;
GregCr 0:e6ceb13d2d05 1556 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1557 break;
GregCr 0:e6ceb13d2d05 1558 default:
GregCr 0:e6ceb13d2d05 1559 break;
GregCr 0:e6ceb13d2d05 1560 }
mluis 13:618826a997e2 1561 }