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/***********************************************************************//**
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* @file lpc17xx_clkpwr.c
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* @brief Contains all functions support for Clock and Power Control
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* firmware library on LPC17xx
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* @version 3.0
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* @date 18. June. 2010
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* @author NXP MCU SW Application Team
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @addtogroup CLKPWR
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* @{
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*/
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/* Includes ------------------------------------------------------------------- */
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#include "lpc17xx_clkpwr.h"
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/* Public Functions ----------------------------------------------------------- */
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/** @addtogroup CLKPWR_Public_Functions
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* @{
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*/
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/*********************************************************************//**
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* @brief Set value of each Peripheral Clock Selection
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* @param[in] ClkType Peripheral Clock Selection of each type,
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* should be one of the following:
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* - CLKPWR_PCLKSEL_WDT : WDT
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- CLKPWR_PCLKSEL_TIMER0 : Timer 0
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- CLKPWR_PCLKSEL_TIMER1 : Timer 1
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- CLKPWR_PCLKSEL_UART0 : UART 0
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- CLKPWR_PCLKSEL_UART1 : UART 1
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- CLKPWR_PCLKSEL_PWM1 : PWM 1
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- CLKPWR_PCLKSEL_I2C0 : I2C 0
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- CLKPWR_PCLKSEL_SPI : SPI
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- CLKPWR_PCLKSEL_SSP1 : SSP 1
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- CLKPWR_PCLKSEL_DAC : DAC
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- CLKPWR_PCLKSEL_ADC : ADC
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- CLKPWR_PCLKSEL_CAN1 : CAN 1
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- CLKPWR_PCLKSEL_CAN2 : CAN 2
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- CLKPWR_PCLKSEL_ACF : ACF
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- CLKPWR_PCLKSEL_QEI : QEI
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- CLKPWR_PCLKSEL_PCB : PCB
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- CLKPWR_PCLKSEL_I2C1 : I2C 1
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- CLKPWR_PCLKSEL_SSP0 : SSP 0
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- CLKPWR_PCLKSEL_TIMER2 : Timer 2
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- CLKPWR_PCLKSEL_TIMER3 : Timer 3
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- CLKPWR_PCLKSEL_UART2 : UART 2
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- CLKPWR_PCLKSEL_UART3 : UART 3
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- CLKPWR_PCLKSEL_I2C2 : I2C 2
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- CLKPWR_PCLKSEL_I2S : I2S
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- CLKPWR_PCLKSEL_RIT : RIT
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- CLKPWR_PCLKSEL_SYSCON : SYSCON
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- CLKPWR_PCLKSEL_MC : MC
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* @param[in] DivVal Value of divider, should be:
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* - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
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* - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
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* - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
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*
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* @return none
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**********************************************************************/
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void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
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{
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uint32_t bitpos;
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bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
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/* PCLKSEL0 selected */
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if (ClkType < 32)
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{
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/* Clear two bit at bit position */
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LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
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/* Set two selected bit */
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LPC_SC->PCLKSEL0 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
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}
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/* PCLKSEL1 selected */
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else
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{
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/* Clear two bit at bit position */
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LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
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/* Set two selected bit */
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LPC_SC->PCLKSEL1 |= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
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}
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}
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/*********************************************************************//**
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* @brief Get current value of each Peripheral Clock Selection
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* @param[in] ClkType Peripheral Clock Selection of each type,
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* should be one of the following:
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* - CLKPWR_PCLKSEL_WDT : WDT
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- CLKPWR_PCLKSEL_TIMER0 : Timer 0
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107
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- CLKPWR_PCLKSEL_TIMER1 : Timer 1
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- CLKPWR_PCLKSEL_UART0 : UART 0
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- CLKPWR_PCLKSEL_UART1 : UART 1
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110
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- CLKPWR_PCLKSEL_PWM1 : PWM 1
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111
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- CLKPWR_PCLKSEL_I2C0 : I2C 0
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112
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- CLKPWR_PCLKSEL_SPI : SPI
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- CLKPWR_PCLKSEL_SSP1 : SSP 1
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- CLKPWR_PCLKSEL_DAC : DAC
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- CLKPWR_PCLKSEL_ADC : ADC
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- CLKPWR_PCLKSEL_CAN1 : CAN 1
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- CLKPWR_PCLKSEL_CAN2 : CAN 2
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- CLKPWR_PCLKSEL_ACF : ACF
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- CLKPWR_PCLKSEL_QEI : QEI
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- CLKPWR_PCLKSEL_PCB : PCB
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- CLKPWR_PCLKSEL_I2C1 : I2C 1
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122
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- CLKPWR_PCLKSEL_SSP0 : SSP 0
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123
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- CLKPWR_PCLKSEL_TIMER2 : Timer 2
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124
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- CLKPWR_PCLKSEL_TIMER3 : Timer 3
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- CLKPWR_PCLKSEL_UART2 : UART 2
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- CLKPWR_PCLKSEL_UART3 : UART 3
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127
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- CLKPWR_PCLKSEL_I2C2 : I2C 2
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128
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- CLKPWR_PCLKSEL_I2S : I2S
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129
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- CLKPWR_PCLKSEL_RIT : RIT
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130
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- CLKPWR_PCLKSEL_SYSCON : SYSCON
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131
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- CLKPWR_PCLKSEL_MC : MC
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132
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* @return Value of Selected Peripheral Clock Selection
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134
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**********************************************************************/
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135
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uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
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136
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{
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uint32_t bitpos, retval;
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138
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139
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if (ClkType < 32)
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140
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{
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141
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bitpos = ClkType;
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142
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retval = LPC_SC->PCLKSEL0;
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143
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}
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144
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else
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145
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{
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146
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bitpos = ClkType - 32;
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147
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retval = LPC_SC->PCLKSEL1;
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148
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}
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149
|
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150
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retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
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151
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return retval;
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152
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}
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|
153
|
|
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|
154
|
|
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|
155
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156
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/*********************************************************************//**
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lynxeyed_atsu |
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|
157
|
* @brief Get current value of each Peripheral Clock
|
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0:63ed631d8c3a
|
158
|
* @param[in] ClkType Peripheral Clock Selection of each type,
|
lynxeyed_atsu |
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|
159
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* should be one of the following:
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|
160
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* - CLKPWR_PCLKSEL_WDT : WDT
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|
161
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- CLKPWR_PCLKSEL_TIMER0 : Timer 0
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0:63ed631d8c3a
|
162
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- CLKPWR_PCLKSEL_TIMER1 : Timer 1
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0:63ed631d8c3a
|
163
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- CLKPWR_PCLKSEL_UART0 : UART 0
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0:63ed631d8c3a
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164
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- CLKPWR_PCLKSEL_UART1 : UART 1
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0:63ed631d8c3a
|
165
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- CLKPWR_PCLKSEL_PWM1 : PWM 1
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0:63ed631d8c3a
|
166
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- CLKPWR_PCLKSEL_I2C0 : I2C 0
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0:63ed631d8c3a
|
167
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- CLKPWR_PCLKSEL_SPI : SPI
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0:63ed631d8c3a
|
168
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- CLKPWR_PCLKSEL_SSP1 : SSP 1
|
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0:63ed631d8c3a
|
169
|
- CLKPWR_PCLKSEL_DAC : DAC
|
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0:63ed631d8c3a
|
170
|
- CLKPWR_PCLKSEL_ADC : ADC
|
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0:63ed631d8c3a
|
171
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- CLKPWR_PCLKSEL_CAN1 : CAN 1
|
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0:63ed631d8c3a
|
172
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- CLKPWR_PCLKSEL_CAN2 : CAN 2
|
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|
173
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- CLKPWR_PCLKSEL_ACF : ACF
|
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|
174
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- CLKPWR_PCLKSEL_QEI : QEI
|
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|
175
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- CLKPWR_PCLKSEL_PCB : PCB
|
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|
176
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- CLKPWR_PCLKSEL_I2C1 : I2C 1
|
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|
177
|
- CLKPWR_PCLKSEL_SSP0 : SSP 0
|
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0:63ed631d8c3a
|
178
|
- CLKPWR_PCLKSEL_TIMER2 : Timer 2
|
lynxeyed_atsu |
0:63ed631d8c3a
|
179
|
- CLKPWR_PCLKSEL_TIMER3 : Timer 3
|
lynxeyed_atsu |
0:63ed631d8c3a
|
180
|
- CLKPWR_PCLKSEL_UART2 : UART 2
|
lynxeyed_atsu |
0:63ed631d8c3a
|
181
|
- CLKPWR_PCLKSEL_UART3 : UART 3
|
lynxeyed_atsu |
0:63ed631d8c3a
|
182
|
- CLKPWR_PCLKSEL_I2C2 : I2C 2
|
lynxeyed_atsu |
0:63ed631d8c3a
|
183
|
- CLKPWR_PCLKSEL_I2S : I2S
|
lynxeyed_atsu |
0:63ed631d8c3a
|
184
|
- CLKPWR_PCLKSEL_RIT : RIT
|
lynxeyed_atsu |
0:63ed631d8c3a
|
185
|
- CLKPWR_PCLKSEL_SYSCON : SYSCON
|
lynxeyed_atsu |
0:63ed631d8c3a
|
186
|
- CLKPWR_PCLKSEL_MC : MC
|
lynxeyed_atsu |
0:63ed631d8c3a
|
187
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
188
|
* @return Value of Selected Peripheral Clock
|
lynxeyed_atsu |
0:63ed631d8c3a
|
189
|
**********************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
190
|
uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
191
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
192
|
uint32_t retval, div;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
193
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
194
|
retval = SystemCoreClock;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
195
|
div = CLKPWR_GetPCLKSEL(ClkType);
|
lynxeyed_atsu |
0:63ed631d8c3a
|
196
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
197
|
switch (div)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
198
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
199
|
case 0:
|
lynxeyed_atsu |
0:63ed631d8c3a
|
200
|
div = 4;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
201
|
break;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
202
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
203
|
case 1:
|
lynxeyed_atsu |
0:63ed631d8c3a
|
204
|
div = 1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
205
|
break;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
206
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
207
|
case 2:
|
lynxeyed_atsu |
0:63ed631d8c3a
|
208
|
div = 2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
209
|
break;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
210
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
211
|
case 3:
|
lynxeyed_atsu |
0:63ed631d8c3a
|
212
|
div = 8;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
213
|
break;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
214
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
215
|
retval /= div;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
216
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
217
|
return retval;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
218
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
219
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
220
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
221
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
222
|
/*********************************************************************//**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
223
|
* @brief Configure power supply for each peripheral according to NewState
|
lynxeyed_atsu |
0:63ed631d8c3a
|
224
|
* @param[in] PPType Type of peripheral used to enable power,
|
lynxeyed_atsu |
0:63ed631d8c3a
|
225
|
* should be one of the following:
|
lynxeyed_atsu |
0:63ed631d8c3a
|
226
|
* - CLKPWR_PCONP_PCTIM0 : Timer 0
|
lynxeyed_atsu |
0:63ed631d8c3a
|
227
|
- CLKPWR_PCONP_PCTIM1 : Timer 1
|
lynxeyed_atsu |
0:63ed631d8c3a
|
228
|
- CLKPWR_PCONP_PCUART0 : UART 0
|
lynxeyed_atsu |
0:63ed631d8c3a
|
229
|
- CLKPWR_PCONP_PCUART1 : UART 1
|
lynxeyed_atsu |
0:63ed631d8c3a
|
230
|
- CLKPWR_PCONP_PCPWM1 : PWM 1
|
lynxeyed_atsu |
0:63ed631d8c3a
|
231
|
- CLKPWR_PCONP_PCI2C0 : I2C 0
|
lynxeyed_atsu |
0:63ed631d8c3a
|
232
|
- CLKPWR_PCONP_PCSPI : SPI
|
lynxeyed_atsu |
0:63ed631d8c3a
|
233
|
- CLKPWR_PCONP_PCRTC : RTC
|
lynxeyed_atsu |
0:63ed631d8c3a
|
234
|
- CLKPWR_PCONP_PCSSP1 : SSP 1
|
lynxeyed_atsu |
0:63ed631d8c3a
|
235
|
- CLKPWR_PCONP_PCAD : ADC
|
lynxeyed_atsu |
0:63ed631d8c3a
|
236
|
- CLKPWR_PCONP_PCAN1 : CAN 1
|
lynxeyed_atsu |
0:63ed631d8c3a
|
237
|
- CLKPWR_PCONP_PCAN2 : CAN 2
|
lynxeyed_atsu |
0:63ed631d8c3a
|
238
|
- CLKPWR_PCONP_PCGPIO : GPIO
|
lynxeyed_atsu |
0:63ed631d8c3a
|
239
|
- CLKPWR_PCONP_PCRIT : RIT
|
lynxeyed_atsu |
0:63ed631d8c3a
|
240
|
- CLKPWR_PCONP_PCMC : MC
|
lynxeyed_atsu |
0:63ed631d8c3a
|
241
|
- CLKPWR_PCONP_PCQEI : QEI
|
lynxeyed_atsu |
0:63ed631d8c3a
|
242
|
- CLKPWR_PCONP_PCI2C1 : I2C 1
|
lynxeyed_atsu |
0:63ed631d8c3a
|
243
|
- CLKPWR_PCONP_PCSSP0 : SSP 0
|
lynxeyed_atsu |
0:63ed631d8c3a
|
244
|
- CLKPWR_PCONP_PCTIM2 : Timer 2
|
lynxeyed_atsu |
0:63ed631d8c3a
|
245
|
- CLKPWR_PCONP_PCTIM3 : Timer 3
|
lynxeyed_atsu |
0:63ed631d8c3a
|
246
|
- CLKPWR_PCONP_PCUART2 : UART 2
|
lynxeyed_atsu |
0:63ed631d8c3a
|
247
|
- CLKPWR_PCONP_PCUART3 : UART 3
|
lynxeyed_atsu |
0:63ed631d8c3a
|
248
|
- CLKPWR_PCONP_PCI2C2 : I2C 2
|
lynxeyed_atsu |
0:63ed631d8c3a
|
249
|
- CLKPWR_PCONP_PCI2S : I2S
|
lynxeyed_atsu |
0:63ed631d8c3a
|
250
|
- CLKPWR_PCONP_PCGPDMA : GPDMA
|
lynxeyed_atsu |
0:63ed631d8c3a
|
251
|
- CLKPWR_PCONP_PCENET : Ethernet
|
lynxeyed_atsu |
0:63ed631d8c3a
|
252
|
- CLKPWR_PCONP_PCUSB : USB
|
lynxeyed_atsu |
0:63ed631d8c3a
|
253
|
*
|
lynxeyed_atsu |
0:63ed631d8c3a
|
254
|
* @param[in] NewState New state of Peripheral Power, should be:
|
lynxeyed_atsu |
0:63ed631d8c3a
|
255
|
* - ENABLE : Enable power for this peripheral
|
lynxeyed_atsu |
0:63ed631d8c3a
|
256
|
* - DISABLE : Disable power for this peripheral
|
lynxeyed_atsu |
0:63ed631d8c3a
|
257
|
*
|
lynxeyed_atsu |
0:63ed631d8c3a
|
258
|
* @return none
|
lynxeyed_atsu |
0:63ed631d8c3a
|
259
|
**********************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
260
|
void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
261
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
262
|
if (NewState == ENABLE)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
263
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
264
|
LPC_SC->PCONP |= PPType & CLKPWR_PCONP_BITMASK;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
265
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
266
|
else if (NewState == DISABLE)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
267
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
268
|
LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
269
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
270
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
271
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
272
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
273
|
/*********************************************************************//**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
274
|
* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
|
lynxeyed_atsu |
0:63ed631d8c3a
|
275
|
* @param[in] None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
276
|
* @return None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
277
|
**********************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
278
|
void CLKPWR_Sleep(void)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
279
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
280
|
LPC_SC->PCON = 0x00;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
281
|
/* Sleep Mode*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
282
|
__WFI();
|
lynxeyed_atsu |
0:63ed631d8c3a
|
283
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
284
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
285
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
286
|
/*********************************************************************//**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
287
|
* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
|
lynxeyed_atsu |
0:63ed631d8c3a
|
288
|
* @param[in] None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
289
|
* @return None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
290
|
**********************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
291
|
void CLKPWR_DeepSleep(void)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
292
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
293
|
/* Deep-Sleep Mode, set SLEEPDEEP bit */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
294
|
SCB->SCR = 0x4;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
295
|
LPC_SC->PCON = 0x8;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
296
|
/* Deep Sleep Mode*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
297
|
__WFI();
|
lynxeyed_atsu |
0:63ed631d8c3a
|
298
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
299
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
300
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
301
|
/*********************************************************************//**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
302
|
* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
|
lynxeyed_atsu |
0:63ed631d8c3a
|
303
|
* @param[in] None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
304
|
* @return None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
305
|
**********************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
306
|
void CLKPWR_PowerDown(void)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
307
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
308
|
/* Deep-Sleep Mode, set SLEEPDEEP bit */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
309
|
SCB->SCR = 0x4;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
310
|
LPC_SC->PCON = 0x09;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
311
|
/* Power Down Mode*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
312
|
__WFI();
|
lynxeyed_atsu |
0:63ed631d8c3a
|
313
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
314
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
315
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
316
|
/*********************************************************************//**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
317
|
* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
|
lynxeyed_atsu |
0:63ed631d8c3a
|
318
|
* @param[in] None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
319
|
* @return None
|
lynxeyed_atsu |
0:63ed631d8c3a
|
320
|
**********************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
321
|
void CLKPWR_DeepPowerDown(void)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
322
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
323
|
/* Deep-Sleep Mode, set SLEEPDEEP bit */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
324
|
SCB->SCR = 0x4;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
325
|
LPC_SC->PCON = 0x03;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
326
|
/* Deep Power Down Mode*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
327
|
__WFI();
|
lynxeyed_atsu |
0:63ed631d8c3a
|
328
|
}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
329
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
330
|
/**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
331
|
* @}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
332
|
*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
333
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
334
|
/**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
335
|
* @}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
336
|
*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
337
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
338
|
/* --------------------------------- End Of File ------------------------------ */
|