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I2S_Example/lpc17xx_clkpwr.c@0:63ed631d8c3a, 2011-01-21 (annotated)

Committer:: lynxeyed_atsu
Date:: Fri Jan 21 08:39:48 2011 +0000
Revision:: 0:63ed631d8c3a

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:63ed631d8c3a	1	/*********************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	2	* @file lpc17xx_clkpwr.c
lynxeyed_atsu	0:63ed631d8c3a	3	* @brief Contains all functions support for Clock and Power Control
lynxeyed_atsu	0:63ed631d8c3a	4	* firmware library on LPC17xx
lynxeyed_atsu	0:63ed631d8c3a	5	* @version 3.0
lynxeyed_atsu	0:63ed631d8c3a	6	* @date 18. June. 2010
lynxeyed_atsu	0:63ed631d8c3a	7	* @author NXP MCU SW Application Team
lynxeyed_atsu	0:63ed631d8c3a	8	**************************************************************************
lynxeyed_atsu	0:63ed631d8c3a	9	* Software that is described herein is for illustrative purposes only
lynxeyed_atsu	0:63ed631d8c3a	10	* which provides customers with programming information regarding the
lynxeyed_atsu	0:63ed631d8c3a	11	* products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu	0:63ed631d8c3a	12	* NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu	0:63ed631d8c3a	13	* use of the software, conveys no license or title under any patent,
lynxeyed_atsu	0:63ed631d8c3a	14	* copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu	0:63ed631d8c3a	15	* reserves the right to make changes in the software without
lynxeyed_atsu	0:63ed631d8c3a	16	* notification. NXP Semiconductors also make no representation or
lynxeyed_atsu	0:63ed631d8c3a	17	* warranty that such application will be suitable for the specified
lynxeyed_atsu	0:63ed631d8c3a	18	* use without further testing or modification.
lynxeyed_atsu	0:63ed631d8c3a	19	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	20
lynxeyed_atsu	0:63ed631d8c3a	21	/* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	22	/** @addtogroup CLKPWR
lynxeyed_atsu	0:63ed631d8c3a	23	* @{
lynxeyed_atsu	0:63ed631d8c3a	24	*/
lynxeyed_atsu	0:63ed631d8c3a	25
lynxeyed_atsu	0:63ed631d8c3a	26	/* Includes ------------------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	27	#include "lpc17xx_clkpwr.h"
lynxeyed_atsu	0:63ed631d8c3a	28
lynxeyed_atsu	0:63ed631d8c3a	29
lynxeyed_atsu	0:63ed631d8c3a	30	/* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu	0:63ed631d8c3a	31	/** @addtogroup CLKPWR_Public_Functions
lynxeyed_atsu	0:63ed631d8c3a	32	* @{
lynxeyed_atsu	0:63ed631d8c3a	33	*/
lynxeyed_atsu	0:63ed631d8c3a	34
lynxeyed_atsu	0:63ed631d8c3a	35	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	36	* @brief Set value of each Peripheral Clock Selection
lynxeyed_atsu	0:63ed631d8c3a	37	* @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu	0:63ed631d8c3a	38	* should be one of the following:
lynxeyed_atsu	0:63ed631d8c3a	39	* - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu	0:63ed631d8c3a	40	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu	0:63ed631d8c3a	41	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu	0:63ed631d8c3a	42	- CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu	0:63ed631d8c3a	43	- CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu	0:63ed631d8c3a	44	- CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu	0:63ed631d8c3a	45	- CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu	0:63ed631d8c3a	46	- CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu	0:63ed631d8c3a	47	- CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu	0:63ed631d8c3a	48	- CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu	0:63ed631d8c3a	49	- CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu	0:63ed631d8c3a	50	- CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu	0:63ed631d8c3a	51	- CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu	0:63ed631d8c3a	52	- CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu	0:63ed631d8c3a	53	- CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu	0:63ed631d8c3a	54	- CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu	0:63ed631d8c3a	55	- CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu	0:63ed631d8c3a	56	- CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu	0:63ed631d8c3a	57	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu	0:63ed631d8c3a	58	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu	0:63ed631d8c3a	59	- CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu	0:63ed631d8c3a	60	- CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu	0:63ed631d8c3a	61	- CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu	0:63ed631d8c3a	62	- CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu	0:63ed631d8c3a	63	- CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu	0:63ed631d8c3a	64	- CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu	0:63ed631d8c3a	65	- CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu	0:63ed631d8c3a	66
lynxeyed_atsu	0:63ed631d8c3a	67	* @param[in] DivVal Value of divider, should be:
lynxeyed_atsu	0:63ed631d8c3a	68	* - CLKPWR_PCLKSEL_CCLK_DIV_4 : PCLK_peripheral = CCLK/4
lynxeyed_atsu	0:63ed631d8c3a	69	* - CLKPWR_PCLKSEL_CCLK_DIV_1 : PCLK_peripheral = CCLK/1
lynxeyed_atsu	0:63ed631d8c3a	70	* - CLKPWR_PCLKSEL_CCLK_DIV_2 : PCLK_peripheral = CCLK/2
lynxeyed_atsu	0:63ed631d8c3a	71	*
lynxeyed_atsu	0:63ed631d8c3a	72	* @return none
lynxeyed_atsu	0:63ed631d8c3a	73	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	74	void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal)
lynxeyed_atsu	0:63ed631d8c3a	75	{
lynxeyed_atsu	0:63ed631d8c3a	76	uint32_t bitpos;
lynxeyed_atsu	0:63ed631d8c3a	77
lynxeyed_atsu	0:63ed631d8c3a	78	bitpos = (ClkType < 32) ? (ClkType) : (ClkType - 32);
lynxeyed_atsu	0:63ed631d8c3a	79
lynxeyed_atsu	0:63ed631d8c3a	80	/* PCLKSEL0 selected */
lynxeyed_atsu	0:63ed631d8c3a	81	if (ClkType < 32)
lynxeyed_atsu	0:63ed631d8c3a	82	{
lynxeyed_atsu	0:63ed631d8c3a	83	/* Clear two bit at bit position */
lynxeyed_atsu	0:63ed631d8c3a	84	LPC_SC->PCLKSEL0 &= (~(CLKPWR_PCLKSEL_BITMASK(bitpos)));
lynxeyed_atsu	0:63ed631d8c3a	85
lynxeyed_atsu	0:63ed631d8c3a	86	/* Set two selected bit */
lynxeyed_atsu	0:63ed631d8c3a	87	LPC_SC->PCLKSEL0 \|= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
lynxeyed_atsu	0:63ed631d8c3a	88	}
lynxeyed_atsu	0:63ed631d8c3a	89	/* PCLKSEL1 selected */
lynxeyed_atsu	0:63ed631d8c3a	90	else
lynxeyed_atsu	0:63ed631d8c3a	91	{
lynxeyed_atsu	0:63ed631d8c3a	92	/* Clear two bit at bit position */
lynxeyed_atsu	0:63ed631d8c3a	93	LPC_SC->PCLKSEL1 &= ~(CLKPWR_PCLKSEL_BITMASK(bitpos));
lynxeyed_atsu	0:63ed631d8c3a	94
lynxeyed_atsu	0:63ed631d8c3a	95	/* Set two selected bit */
lynxeyed_atsu	0:63ed631d8c3a	96	LPC_SC->PCLKSEL1 \|= (CLKPWR_PCLKSEL_SET(bitpos, DivVal));
lynxeyed_atsu	0:63ed631d8c3a	97	}
lynxeyed_atsu	0:63ed631d8c3a	98	}
lynxeyed_atsu	0:63ed631d8c3a	99
lynxeyed_atsu	0:63ed631d8c3a	100
lynxeyed_atsu	0:63ed631d8c3a	101	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	102	* @brief Get current value of each Peripheral Clock Selection
lynxeyed_atsu	0:63ed631d8c3a	103	* @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu	0:63ed631d8c3a	104	* should be one of the following:
lynxeyed_atsu	0:63ed631d8c3a	105	* - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu	0:63ed631d8c3a	106	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu	0:63ed631d8c3a	107	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu	0:63ed631d8c3a	108	- CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu	0:63ed631d8c3a	109	- CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu	0:63ed631d8c3a	110	- CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu	0:63ed631d8c3a	111	- CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu	0:63ed631d8c3a	112	- CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu	0:63ed631d8c3a	113	- CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu	0:63ed631d8c3a	114	- CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu	0:63ed631d8c3a	115	- CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu	0:63ed631d8c3a	116	- CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu	0:63ed631d8c3a	117	- CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu	0:63ed631d8c3a	118	- CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu	0:63ed631d8c3a	119	- CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu	0:63ed631d8c3a	120	- CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu	0:63ed631d8c3a	121	- CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu	0:63ed631d8c3a	122	- CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu	0:63ed631d8c3a	123	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu	0:63ed631d8c3a	124	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu	0:63ed631d8c3a	125	- CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu	0:63ed631d8c3a	126	- CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu	0:63ed631d8c3a	127	- CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu	0:63ed631d8c3a	128	- CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu	0:63ed631d8c3a	129	- CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu	0:63ed631d8c3a	130	- CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu	0:63ed631d8c3a	131	- CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu	0:63ed631d8c3a	132
lynxeyed_atsu	0:63ed631d8c3a	133	* @return Value of Selected Peripheral Clock Selection
lynxeyed_atsu	0:63ed631d8c3a	134	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	135	uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType)
lynxeyed_atsu	0:63ed631d8c3a	136	{
lynxeyed_atsu	0:63ed631d8c3a	137	uint32_t bitpos, retval;
lynxeyed_atsu	0:63ed631d8c3a	138
lynxeyed_atsu	0:63ed631d8c3a	139	if (ClkType < 32)
lynxeyed_atsu	0:63ed631d8c3a	140	{
lynxeyed_atsu	0:63ed631d8c3a	141	bitpos = ClkType;
lynxeyed_atsu	0:63ed631d8c3a	142	retval = LPC_SC->PCLKSEL0;
lynxeyed_atsu	0:63ed631d8c3a	143	}
lynxeyed_atsu	0:63ed631d8c3a	144	else
lynxeyed_atsu	0:63ed631d8c3a	145	{
lynxeyed_atsu	0:63ed631d8c3a	146	bitpos = ClkType - 32;
lynxeyed_atsu	0:63ed631d8c3a	147	retval = LPC_SC->PCLKSEL1;
lynxeyed_atsu	0:63ed631d8c3a	148	}
lynxeyed_atsu	0:63ed631d8c3a	149
lynxeyed_atsu	0:63ed631d8c3a	150	retval = CLKPWR_PCLKSEL_GET(bitpos, retval);
lynxeyed_atsu	0:63ed631d8c3a	151	return retval;
lynxeyed_atsu	0:63ed631d8c3a	152	}
lynxeyed_atsu	0:63ed631d8c3a	153
lynxeyed_atsu	0:63ed631d8c3a	154
lynxeyed_atsu	0:63ed631d8c3a	155
lynxeyed_atsu	0:63ed631d8c3a	156	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	157	* @brief Get current value of each Peripheral Clock
lynxeyed_atsu	0:63ed631d8c3a	158	* @param[in] ClkType Peripheral Clock Selection of each type,
lynxeyed_atsu	0:63ed631d8c3a	159	* should be one of the following:
lynxeyed_atsu	0:63ed631d8c3a	160	* - CLKPWR_PCLKSEL_WDT : WDT
lynxeyed_atsu	0:63ed631d8c3a	161	- CLKPWR_PCLKSEL_TIMER0 : Timer 0
lynxeyed_atsu	0:63ed631d8c3a	162	- CLKPWR_PCLKSEL_TIMER1 : Timer 1
lynxeyed_atsu	0:63ed631d8c3a	163	- CLKPWR_PCLKSEL_UART0 : UART 0
lynxeyed_atsu	0:63ed631d8c3a	164	- CLKPWR_PCLKSEL_UART1 : UART 1
lynxeyed_atsu	0:63ed631d8c3a	165	- CLKPWR_PCLKSEL_PWM1 : PWM 1
lynxeyed_atsu	0:63ed631d8c3a	166	- CLKPWR_PCLKSEL_I2C0 : I2C 0
lynxeyed_atsu	0:63ed631d8c3a	167	- CLKPWR_PCLKSEL_SPI : SPI
lynxeyed_atsu	0:63ed631d8c3a	168	- CLKPWR_PCLKSEL_SSP1 : SSP 1
lynxeyed_atsu	0:63ed631d8c3a	169	- CLKPWR_PCLKSEL_DAC : DAC
lynxeyed_atsu	0:63ed631d8c3a	170	- CLKPWR_PCLKSEL_ADC : ADC
lynxeyed_atsu	0:63ed631d8c3a	171	- CLKPWR_PCLKSEL_CAN1 : CAN 1
lynxeyed_atsu	0:63ed631d8c3a	172	- CLKPWR_PCLKSEL_CAN2 : CAN 2
lynxeyed_atsu	0:63ed631d8c3a	173	- CLKPWR_PCLKSEL_ACF : ACF
lynxeyed_atsu	0:63ed631d8c3a	174	- CLKPWR_PCLKSEL_QEI : QEI
lynxeyed_atsu	0:63ed631d8c3a	175	- CLKPWR_PCLKSEL_PCB : PCB
lynxeyed_atsu	0:63ed631d8c3a	176	- CLKPWR_PCLKSEL_I2C1 : I2C 1
lynxeyed_atsu	0:63ed631d8c3a	177	- CLKPWR_PCLKSEL_SSP0 : SSP 0
lynxeyed_atsu	0:63ed631d8c3a	178	- CLKPWR_PCLKSEL_TIMER2 : Timer 2
lynxeyed_atsu	0:63ed631d8c3a	179	- CLKPWR_PCLKSEL_TIMER3 : Timer 3
lynxeyed_atsu	0:63ed631d8c3a	180	- CLKPWR_PCLKSEL_UART2 : UART 2
lynxeyed_atsu	0:63ed631d8c3a	181	- CLKPWR_PCLKSEL_UART3 : UART 3
lynxeyed_atsu	0:63ed631d8c3a	182	- CLKPWR_PCLKSEL_I2C2 : I2C 2
lynxeyed_atsu	0:63ed631d8c3a	183	- CLKPWR_PCLKSEL_I2S : I2S
lynxeyed_atsu	0:63ed631d8c3a	184	- CLKPWR_PCLKSEL_RIT : RIT
lynxeyed_atsu	0:63ed631d8c3a	185	- CLKPWR_PCLKSEL_SYSCON : SYSCON
lynxeyed_atsu	0:63ed631d8c3a	186	- CLKPWR_PCLKSEL_MC : MC
lynxeyed_atsu	0:63ed631d8c3a	187
lynxeyed_atsu	0:63ed631d8c3a	188	* @return Value of Selected Peripheral Clock
lynxeyed_atsu	0:63ed631d8c3a	189	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	190	uint32_t CLKPWR_GetPCLK (uint32_t ClkType)
lynxeyed_atsu	0:63ed631d8c3a	191	{
lynxeyed_atsu	0:63ed631d8c3a	192	uint32_t retval, div;
lynxeyed_atsu	0:63ed631d8c3a	193
lynxeyed_atsu	0:63ed631d8c3a	194	retval = SystemCoreClock;
lynxeyed_atsu	0:63ed631d8c3a	195	div = CLKPWR_GetPCLKSEL(ClkType);
lynxeyed_atsu	0:63ed631d8c3a	196
lynxeyed_atsu	0:63ed631d8c3a	197	switch (div)
lynxeyed_atsu	0:63ed631d8c3a	198	{
lynxeyed_atsu	0:63ed631d8c3a	199	case 0:
lynxeyed_atsu	0:63ed631d8c3a	200	div = 4;
lynxeyed_atsu	0:63ed631d8c3a	201	break;
lynxeyed_atsu	0:63ed631d8c3a	202
lynxeyed_atsu	0:63ed631d8c3a	203	case 1:
lynxeyed_atsu	0:63ed631d8c3a	204	div = 1;
lynxeyed_atsu	0:63ed631d8c3a	205	break;
lynxeyed_atsu	0:63ed631d8c3a	206
lynxeyed_atsu	0:63ed631d8c3a	207	case 2:
lynxeyed_atsu	0:63ed631d8c3a	208	div = 2;
lynxeyed_atsu	0:63ed631d8c3a	209	break;
lynxeyed_atsu	0:63ed631d8c3a	210
lynxeyed_atsu	0:63ed631d8c3a	211	case 3:
lynxeyed_atsu	0:63ed631d8c3a	212	div = 8;
lynxeyed_atsu	0:63ed631d8c3a	213	break;
lynxeyed_atsu	0:63ed631d8c3a	214	}
lynxeyed_atsu	0:63ed631d8c3a	215	retval /= div;
lynxeyed_atsu	0:63ed631d8c3a	216
lynxeyed_atsu	0:63ed631d8c3a	217	return retval;
lynxeyed_atsu	0:63ed631d8c3a	218	}
lynxeyed_atsu	0:63ed631d8c3a	219
lynxeyed_atsu	0:63ed631d8c3a	220
lynxeyed_atsu	0:63ed631d8c3a	221
lynxeyed_atsu	0:63ed631d8c3a	222	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	223	* @brief Configure power supply for each peripheral according to NewState
lynxeyed_atsu	0:63ed631d8c3a	224	* @param[in] PPType Type of peripheral used to enable power,
lynxeyed_atsu	0:63ed631d8c3a	225	* should be one of the following:
lynxeyed_atsu	0:63ed631d8c3a	226	* - CLKPWR_PCONP_PCTIM0 : Timer 0
lynxeyed_atsu	0:63ed631d8c3a	227	- CLKPWR_PCONP_PCTIM1 : Timer 1
lynxeyed_atsu	0:63ed631d8c3a	228	- CLKPWR_PCONP_PCUART0 : UART 0
lynxeyed_atsu	0:63ed631d8c3a	229	- CLKPWR_PCONP_PCUART1 : UART 1
lynxeyed_atsu	0:63ed631d8c3a	230	- CLKPWR_PCONP_PCPWM1 : PWM 1
lynxeyed_atsu	0:63ed631d8c3a	231	- CLKPWR_PCONP_PCI2C0 : I2C 0
lynxeyed_atsu	0:63ed631d8c3a	232	- CLKPWR_PCONP_PCSPI : SPI
lynxeyed_atsu	0:63ed631d8c3a	233	- CLKPWR_PCONP_PCRTC : RTC
lynxeyed_atsu	0:63ed631d8c3a	234	- CLKPWR_PCONP_PCSSP1 : SSP 1
lynxeyed_atsu	0:63ed631d8c3a	235	- CLKPWR_PCONP_PCAD : ADC
lynxeyed_atsu	0:63ed631d8c3a	236	- CLKPWR_PCONP_PCAN1 : CAN 1
lynxeyed_atsu	0:63ed631d8c3a	237	- CLKPWR_PCONP_PCAN2 : CAN 2
lynxeyed_atsu	0:63ed631d8c3a	238	- CLKPWR_PCONP_PCGPIO : GPIO
lynxeyed_atsu	0:63ed631d8c3a	239	- CLKPWR_PCONP_PCRIT : RIT
lynxeyed_atsu	0:63ed631d8c3a	240	- CLKPWR_PCONP_PCMC : MC
lynxeyed_atsu	0:63ed631d8c3a	241	- CLKPWR_PCONP_PCQEI : QEI
lynxeyed_atsu	0:63ed631d8c3a	242	- CLKPWR_PCONP_PCI2C1 : I2C 1
lynxeyed_atsu	0:63ed631d8c3a	243	- CLKPWR_PCONP_PCSSP0 : SSP 0
lynxeyed_atsu	0:63ed631d8c3a	244	- CLKPWR_PCONP_PCTIM2 : Timer 2
lynxeyed_atsu	0:63ed631d8c3a	245	- CLKPWR_PCONP_PCTIM3 : Timer 3
lynxeyed_atsu	0:63ed631d8c3a	246	- CLKPWR_PCONP_PCUART2 : UART 2
lynxeyed_atsu	0:63ed631d8c3a	247	- CLKPWR_PCONP_PCUART3 : UART 3
lynxeyed_atsu	0:63ed631d8c3a	248	- CLKPWR_PCONP_PCI2C2 : I2C 2
lynxeyed_atsu	0:63ed631d8c3a	249	- CLKPWR_PCONP_PCI2S : I2S
lynxeyed_atsu	0:63ed631d8c3a	250	- CLKPWR_PCONP_PCGPDMA : GPDMA
lynxeyed_atsu	0:63ed631d8c3a	251	- CLKPWR_PCONP_PCENET : Ethernet
lynxeyed_atsu	0:63ed631d8c3a	252	- CLKPWR_PCONP_PCUSB : USB
lynxeyed_atsu	0:63ed631d8c3a	253	*
lynxeyed_atsu	0:63ed631d8c3a	254	* @param[in] NewState New state of Peripheral Power, should be:
lynxeyed_atsu	0:63ed631d8c3a	255	* - ENABLE : Enable power for this peripheral
lynxeyed_atsu	0:63ed631d8c3a	256	* - DISABLE : Disable power for this peripheral
lynxeyed_atsu	0:63ed631d8c3a	257	*
lynxeyed_atsu	0:63ed631d8c3a	258	* @return none
lynxeyed_atsu	0:63ed631d8c3a	259	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	260	void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState)
lynxeyed_atsu	0:63ed631d8c3a	261	{
lynxeyed_atsu	0:63ed631d8c3a	262	if (NewState == ENABLE)
lynxeyed_atsu	0:63ed631d8c3a	263	{
lynxeyed_atsu	0:63ed631d8c3a	264	LPC_SC->PCONP \|= PPType & CLKPWR_PCONP_BITMASK;
lynxeyed_atsu	0:63ed631d8c3a	265	}
lynxeyed_atsu	0:63ed631d8c3a	266	else if (NewState == DISABLE)
lynxeyed_atsu	0:63ed631d8c3a	267	{
lynxeyed_atsu	0:63ed631d8c3a	268	LPC_SC->PCONP &= (~PPType) & CLKPWR_PCONP_BITMASK;
lynxeyed_atsu	0:63ed631d8c3a	269	}
lynxeyed_atsu	0:63ed631d8c3a	270	}
lynxeyed_atsu	0:63ed631d8c3a	271
lynxeyed_atsu	0:63ed631d8c3a	272
lynxeyed_atsu	0:63ed631d8c3a	273	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	274	* @brief Enter Sleep mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:63ed631d8c3a	275	* @param[in] None
lynxeyed_atsu	0:63ed631d8c3a	276	* @return None
lynxeyed_atsu	0:63ed631d8c3a	277	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	278	void CLKPWR_Sleep(void)
lynxeyed_atsu	0:63ed631d8c3a	279	{
lynxeyed_atsu	0:63ed631d8c3a	280	LPC_SC->PCON = 0x00;
lynxeyed_atsu	0:63ed631d8c3a	281	/* Sleep Mode*/
lynxeyed_atsu	0:63ed631d8c3a	282	__WFI();
lynxeyed_atsu	0:63ed631d8c3a	283	}
lynxeyed_atsu	0:63ed631d8c3a	284
lynxeyed_atsu	0:63ed631d8c3a	285
lynxeyed_atsu	0:63ed631d8c3a	286	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	287	* @brief Enter Deep Sleep mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:63ed631d8c3a	288	* @param[in] None
lynxeyed_atsu	0:63ed631d8c3a	289	* @return None
lynxeyed_atsu	0:63ed631d8c3a	290	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	291	void CLKPWR_DeepSleep(void)
lynxeyed_atsu	0:63ed631d8c3a	292	{
lynxeyed_atsu	0:63ed631d8c3a	293	/* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu	0:63ed631d8c3a	294	SCB->SCR = 0x4;
lynxeyed_atsu	0:63ed631d8c3a	295	LPC_SC->PCON = 0x8;
lynxeyed_atsu	0:63ed631d8c3a	296	/* Deep Sleep Mode*/
lynxeyed_atsu	0:63ed631d8c3a	297	__WFI();
lynxeyed_atsu	0:63ed631d8c3a	298	}
lynxeyed_atsu	0:63ed631d8c3a	299
lynxeyed_atsu	0:63ed631d8c3a	300
lynxeyed_atsu	0:63ed631d8c3a	301	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	302	* @brief Enter Power Down mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:63ed631d8c3a	303	* @param[in] None
lynxeyed_atsu	0:63ed631d8c3a	304	* @return None
lynxeyed_atsu	0:63ed631d8c3a	305	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	306	void CLKPWR_PowerDown(void)
lynxeyed_atsu	0:63ed631d8c3a	307	{
lynxeyed_atsu	0:63ed631d8c3a	308	/* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu	0:63ed631d8c3a	309	SCB->SCR = 0x4;
lynxeyed_atsu	0:63ed631d8c3a	310	LPC_SC->PCON = 0x09;
lynxeyed_atsu	0:63ed631d8c3a	311	/* Power Down Mode*/
lynxeyed_atsu	0:63ed631d8c3a	312	__WFI();
lynxeyed_atsu	0:63ed631d8c3a	313	}
lynxeyed_atsu	0:63ed631d8c3a	314
lynxeyed_atsu	0:63ed631d8c3a	315
lynxeyed_atsu	0:63ed631d8c3a	316	/*******************************************************************//
lynxeyed_atsu	0:63ed631d8c3a	317	* @brief Enter Deep Power Down mode with co-operated instruction by the Cortex-M3.
lynxeyed_atsu	0:63ed631d8c3a	318	* @param[in] None
lynxeyed_atsu	0:63ed631d8c3a	319	* @return None
lynxeyed_atsu	0:63ed631d8c3a	320	**********************************************************************/
lynxeyed_atsu	0:63ed631d8c3a	321	void CLKPWR_DeepPowerDown(void)
lynxeyed_atsu	0:63ed631d8c3a	322	{
lynxeyed_atsu	0:63ed631d8c3a	323	/* Deep-Sleep Mode, set SLEEPDEEP bit */
lynxeyed_atsu	0:63ed631d8c3a	324	SCB->SCR = 0x4;
lynxeyed_atsu	0:63ed631d8c3a	325	LPC_SC->PCON = 0x03;
lynxeyed_atsu	0:63ed631d8c3a	326	/* Deep Power Down Mode*/
lynxeyed_atsu	0:63ed631d8c3a	327	__WFI();
lynxeyed_atsu	0:63ed631d8c3a	328	}
lynxeyed_atsu	0:63ed631d8c3a	329
lynxeyed_atsu	0:63ed631d8c3a	330	/**
lynxeyed_atsu	0:63ed631d8c3a	331	* @}
lynxeyed_atsu	0:63ed631d8c3a	332	*/
lynxeyed_atsu	0:63ed631d8c3a	333
lynxeyed_atsu	0:63ed631d8c3a	334	/**
lynxeyed_atsu	0:63ed631d8c3a	335	* @}
lynxeyed_atsu	0:63ed631d8c3a	336	*/
lynxeyed_atsu	0:63ed631d8c3a	337
lynxeyed_atsu	0:63ed631d8c3a	338	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	21 Jan 2011
Imports:	2
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	2

I2S_Example/lpc17xx_clkpwr.c@0:63ed631d8c3a, 2011-01-21 (annotated)

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