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/**************************************************************************//**
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* @file LPC17xx.h
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* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
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* NXP LPC17xx Device Series
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* @version: V1.08
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* @date: 21. December 2009
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*
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* @note
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* Copyright (C) 2009 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __LPC17xx_H__
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#define __LPC17xx_H__
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/*
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* ==========================================================================
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* ---------- Interrupt Number Definition -----------------------------------
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* ==========================================================================
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*/
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/** @addtogroup LPC17xx_System
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* @{
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*/
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/** @brief IRQ interrupt source definition */
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typedef enum IRQn
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{
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/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
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/****** LPC17xx Specific Interrupt Numbers *******************************************************/
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WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
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TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
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TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
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TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
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TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
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UART0_IRQn = 5, /*!< UART0 Interrupt */
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UART1_IRQn = 6, /*!< UART1 Interrupt */
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UART2_IRQn = 7, /*!< UART2 Interrupt */
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UART3_IRQn = 8, /*!< UART3 Interrupt */
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PWM1_IRQn = 9, /*!< PWM1 Interrupt */
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I2C0_IRQn = 10, /*!< I2C0 Interrupt */
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I2C1_IRQn = 11, /*!< I2C1 Interrupt */
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I2C2_IRQn = 12, /*!< I2C2 Interrupt */
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SPI_IRQn = 13, /*!< SPI Interrupt */
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SSP0_IRQn = 14, /*!< SSP0 Interrupt */
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SSP1_IRQn = 15, /*!< SSP1 Interrupt */
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PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
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RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
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EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
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EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
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EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
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EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
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ADC_IRQn = 22, /*!< A/D Converter Interrupt */
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BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
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USB_IRQn = 24, /*!< USB Interrupt */
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CAN_IRQn = 25, /*!< CAN Interrupt */
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DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
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I2S_IRQn = 27, /*!< I2S Interrupt */
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ENET_IRQn = 28, /*!< Ethernet Interrupt */
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RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
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MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
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QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
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PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
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USBActivity_IRQn = 33, /*!< USB Activity Interrupt */
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CANActivity_IRQn = 34, /*!< CAN Activity Interrupt */
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} IRQn_Type;
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/*
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* ==========================================================================
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* ----------- Processor and Core Peripheral Section ------------------------
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* ==========================================================================
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*/
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/* Configuration of the Cortex-M3 Processor and Core Peripherals */
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#define __MPU_PRESENT 1 /*!< MPU present or not */
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#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
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#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
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#include "system_LPC17xx.h" /* System Header */
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/******************************************************************************/
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/* Device Specific Peripheral registers structures */
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/******************************************************************************/
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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/*------------- System Control (SC) ------------------------------------------*/
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/** @brief System Control (SC) register structure definition */
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typedef struct
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{
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__IO uint32_t FLASHCFG; /* Flash Accelerator Module */
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uint32_t RESERVED0[31];
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__IO uint32_t PLL0CON; /* Clocking and Power Control */
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__IO uint32_t PLL0CFG;
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__I uint32_t PLL0STAT;
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__O uint32_t PLL0FEED;
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uint32_t RESERVED1[4];
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__IO uint32_t PLL1CON;
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__IO uint32_t PLL1CFG;
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__I uint32_t PLL1STAT;
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__O uint32_t PLL1FEED;
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uint32_t RESERVED2[4];
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__IO uint32_t PCON;
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__IO uint32_t PCONP;
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uint32_t RESERVED3[15];
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__IO uint32_t CCLKCFG;
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__IO uint32_t USBCLKCFG;
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__IO uint32_t CLKSRCSEL;
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__IO uint32_t CANSLEEPCLR;
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__IO uint32_t CANWAKEFLAGS;
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uint32_t RESERVED4[10];
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__IO uint32_t EXTINT; /* External Interrupts */
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uint32_t RESERVED5;
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__IO uint32_t EXTMODE;
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__IO uint32_t EXTPOLAR;
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uint32_t RESERVED6[12];
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__IO uint32_t RSID; /* Reset */
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uint32_t RESERVED7[7];
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147
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__IO uint32_t SCS; /* Syscon Miscellaneous Registers */
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148
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__IO uint32_t IRCTRIM; /* Clock Dividers */
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149
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__IO uint32_t PCLKSEL0;
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150
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__IO uint32_t PCLKSEL1;
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151
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uint32_t RESERVED8[4];
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152
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__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
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153
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__IO uint32_t DMAREQSEL;
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__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
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} LPC_SC_TypeDef;
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157
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/*------------- Pin Connect Block (PINCON) -----------------------------------*/
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/** @brief Pin Connect Block (PINCON) register structure definition */
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typedef struct
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{
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__IO uint32_t PINSEL0;
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__IO uint32_t PINSEL1;
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__IO uint32_t PINSEL2;
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__IO uint32_t PINSEL3;
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__IO uint32_t PINSEL4;
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__IO uint32_t PINSEL5;
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__IO uint32_t PINSEL6;
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__IO uint32_t PINSEL7;
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__IO uint32_t PINSEL8;
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170
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__IO uint32_t PINSEL9;
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171
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__IO uint32_t PINSEL10;
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uint32_t RESERVED0[5];
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173
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__IO uint32_t PINMODE0;
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174
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__IO uint32_t PINMODE1;
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175
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__IO uint32_t PINMODE2;
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__IO uint32_t PINMODE3;
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__IO uint32_t PINMODE4;
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__IO uint32_t PINMODE5;
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179
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__IO uint32_t PINMODE6;
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180
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__IO uint32_t PINMODE7;
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181
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__IO uint32_t PINMODE8;
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182
|
__IO uint32_t PINMODE9;
|
lynxeyed_atsu |
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|
183
|
__IO uint32_t PINMODE_OD0;
|
lynxeyed_atsu |
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|
184
|
__IO uint32_t PINMODE_OD1;
|
lynxeyed_atsu |
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|
185
|
__IO uint32_t PINMODE_OD2;
|
lynxeyed_atsu |
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|
186
|
__IO uint32_t PINMODE_OD3;
|
lynxeyed_atsu |
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|
187
|
__IO uint32_t PINMODE_OD4;
|
lynxeyed_atsu |
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|
188
|
__IO uint32_t I2CPADCFG;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
189
|
} LPC_PINCON_TypeDef;
|
lynxeyed_atsu |
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|
190
|
|
lynxeyed_atsu |
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|
191
|
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
|
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|
192
|
/** @brief General Purpose Input/Output (GPIO) register structure definition */
|
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193
|
typedef struct
|
lynxeyed_atsu |
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|
194
|
{
|
lynxeyed_atsu |
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|
195
|
union {
|
lynxeyed_atsu |
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|
196
|
__IO uint32_t FIODIR;
|
lynxeyed_atsu |
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|
197
|
struct {
|
lynxeyed_atsu |
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|
198
|
__IO uint16_t FIODIRL;
|
lynxeyed_atsu |
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|
199
|
__IO uint16_t FIODIRH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
200
|
};
|
lynxeyed_atsu |
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|
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|
struct {
|
lynxeyed_atsu |
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|
202
|
__IO uint8_t FIODIR0;
|
lynxeyed_atsu |
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|
203
|
__IO uint8_t FIODIR1;
|
lynxeyed_atsu |
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|
204
|
__IO uint8_t FIODIR2;
|
lynxeyed_atsu |
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|
205
|
__IO uint8_t FIODIR3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
206
|
};
|
lynxeyed_atsu |
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|
207
|
};
|
lynxeyed_atsu |
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|
208
|
uint32_t RESERVED0[3];
|
lynxeyed_atsu |
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|
209
|
union {
|
lynxeyed_atsu |
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|
210
|
__IO uint32_t FIOMASK;
|
lynxeyed_atsu |
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|
211
|
struct {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
212
|
__IO uint16_t FIOMASKL;
|
lynxeyed_atsu |
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|
213
|
__IO uint16_t FIOMASKH;
|
lynxeyed_atsu |
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|
214
|
};
|
lynxeyed_atsu |
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|
215
|
struct {
|
lynxeyed_atsu |
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|
216
|
__IO uint8_t FIOMASK0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
217
|
__IO uint8_t FIOMASK1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
218
|
__IO uint8_t FIOMASK2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
219
|
__IO uint8_t FIOMASK3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
220
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
221
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
222
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
223
|
__IO uint32_t FIOPIN;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
224
|
struct {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
225
|
__IO uint16_t FIOPINL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
226
|
__IO uint16_t FIOPINH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
227
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
228
|
struct {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
229
|
__IO uint8_t FIOPIN0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
230
|
__IO uint8_t FIOPIN1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
231
|
__IO uint8_t FIOPIN2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
232
|
__IO uint8_t FIOPIN3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
233
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
234
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
235
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
236
|
__IO uint32_t FIOSET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
237
|
struct {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
238
|
__IO uint16_t FIOSETL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
239
|
__IO uint16_t FIOSETH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
240
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
241
|
struct {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
242
|
__IO uint8_t FIOSET0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
243
|
__IO uint8_t FIOSET1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
244
|
__IO uint8_t FIOSET2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
245
|
__IO uint8_t FIOSET3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
246
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
247
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
248
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
249
|
__O uint32_t FIOCLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
250
|
struct {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
251
|
__O uint16_t FIOCLRL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
252
|
__O uint16_t FIOCLRH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
253
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
254
|
struct {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
255
|
__O uint8_t FIOCLR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
256
|
__O uint8_t FIOCLR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
257
|
__O uint8_t FIOCLR2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
258
|
__O uint8_t FIOCLR3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
259
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
260
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
261
|
} LPC_GPIO_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
262
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
263
|
/** @brief General Purpose Input/Output interrupt (GPIOINT) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
264
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
265
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
266
|
__I uint32_t IntStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
267
|
__I uint32_t IO0IntStatR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
268
|
__I uint32_t IO0IntStatF;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
269
|
__O uint32_t IO0IntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
270
|
__IO uint32_t IO0IntEnR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
271
|
__IO uint32_t IO0IntEnF;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
272
|
uint32_t RESERVED0[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
273
|
__I uint32_t IO2IntStatR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
274
|
__I uint32_t IO2IntStatF;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
275
|
__O uint32_t IO2IntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
276
|
__IO uint32_t IO2IntEnR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
277
|
__IO uint32_t IO2IntEnF;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
278
|
} LPC_GPIOINT_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
279
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
280
|
/*------------- Timer (TIM) --------------------------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
281
|
/** @brief Timer (TIM) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
282
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
283
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
284
|
__IO uint32_t IR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
285
|
__IO uint32_t TCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
286
|
__IO uint32_t TC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
287
|
__IO uint32_t PR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
288
|
__IO uint32_t PC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
289
|
__IO uint32_t MCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
290
|
__IO uint32_t MR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
291
|
__IO uint32_t MR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
292
|
__IO uint32_t MR2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
293
|
__IO uint32_t MR3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
294
|
__IO uint32_t CCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
295
|
__I uint32_t CR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
296
|
__I uint32_t CR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
297
|
uint32_t RESERVED0[2];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
298
|
__IO uint32_t EMR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
299
|
uint32_t RESERVED1[12];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
300
|
__IO uint32_t CTCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
301
|
} LPC_TIM_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
302
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
303
|
/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
304
|
/** @brief Pulse-Width Modulation (PWM) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
305
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
306
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
307
|
__IO uint32_t IR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
308
|
__IO uint32_t TCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
309
|
__IO uint32_t TC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
310
|
__IO uint32_t PR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
311
|
__IO uint32_t PC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
312
|
__IO uint32_t MCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
313
|
__IO uint32_t MR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
314
|
__IO uint32_t MR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
315
|
__IO uint32_t MR2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
316
|
__IO uint32_t MR3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
317
|
__IO uint32_t CCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
318
|
__I uint32_t CR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
319
|
__I uint32_t CR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
320
|
__I uint32_t CR2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
321
|
__I uint32_t CR3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
322
|
uint32_t RESERVED0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
323
|
__IO uint32_t MR4;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
324
|
__IO uint32_t MR5;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
325
|
__IO uint32_t MR6;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
326
|
__IO uint32_t PCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
327
|
__IO uint32_t LER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
328
|
uint32_t RESERVED1[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
329
|
__IO uint32_t CTCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
330
|
} LPC_PWM_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
331
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
332
|
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
333
|
/** @brief Universal Asynchronous Receiver Transmitter (UART) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
334
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
335
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
336
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
337
|
__I uint8_t RBR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
338
|
__O uint8_t THR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
339
|
__IO uint8_t DLL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
340
|
uint32_t RESERVED0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
341
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
342
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
343
|
__IO uint8_t DLM;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
344
|
__IO uint32_t IER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
345
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
346
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
347
|
__I uint32_t IIR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
348
|
__O uint8_t FCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
349
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
350
|
__IO uint8_t LCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
351
|
uint8_t RESERVED1[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
352
|
__I uint8_t LSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
353
|
uint8_t RESERVED2[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
354
|
__IO uint8_t SCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
355
|
uint8_t RESERVED3[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
356
|
__IO uint32_t ACR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
357
|
__IO uint8_t ICR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
358
|
uint8_t RESERVED4[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
359
|
__IO uint8_t FDR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
360
|
uint8_t RESERVED5[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
361
|
__IO uint8_t TER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
362
|
uint8_t RESERVED6[39];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
363
|
__I uint8_t FIFOLVL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
364
|
} LPC_UART_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
365
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
366
|
/** @brief Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
367
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
368
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
369
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
370
|
__I uint8_t RBR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
371
|
__O uint8_t THR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
372
|
__IO uint8_t DLL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
373
|
uint32_t RESERVED0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
374
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
375
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
376
|
__IO uint8_t DLM;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
377
|
__IO uint32_t IER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
378
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
379
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
380
|
__I uint32_t IIR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
381
|
__O uint8_t FCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
382
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
383
|
__IO uint8_t LCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
384
|
uint8_t RESERVED1[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
385
|
__I uint8_t LSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
386
|
uint8_t RESERVED2[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
387
|
__IO uint8_t SCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
388
|
uint8_t RESERVED3[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
389
|
__IO uint32_t ACR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
390
|
__IO uint8_t ICR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
391
|
uint8_t RESERVED4[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
392
|
__IO uint8_t FDR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
393
|
uint8_t RESERVED5[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
394
|
__IO uint8_t TER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
395
|
uint8_t RESERVED6[39];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
396
|
__I uint8_t FIFOLVL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
397
|
} LPC_UART0_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
398
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
399
|
/** @brief Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
400
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
401
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
402
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
403
|
__I uint8_t RBR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
404
|
__O uint8_t THR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
405
|
__IO uint8_t DLL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
406
|
uint32_t RESERVED0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
407
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
408
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
409
|
__IO uint8_t DLM;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
410
|
__IO uint32_t IER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
411
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
412
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
413
|
__I uint32_t IIR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
414
|
__O uint8_t FCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
415
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
416
|
__IO uint8_t LCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
417
|
uint8_t RESERVED1[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
418
|
__IO uint8_t MCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
419
|
uint8_t RESERVED2[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
420
|
__I uint8_t LSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
421
|
uint8_t RESERVED3[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
422
|
__I uint8_t MSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
423
|
uint8_t RESERVED4[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
424
|
__IO uint8_t SCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
425
|
uint8_t RESERVED5[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
426
|
__IO uint32_t ACR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
427
|
uint32_t RESERVED6;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
428
|
__IO uint32_t FDR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
429
|
uint32_t RESERVED7;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
430
|
__IO uint8_t TER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
431
|
uint8_t RESERVED8[27];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
432
|
__IO uint8_t RS485CTRL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
433
|
uint8_t RESERVED9[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
434
|
__IO uint8_t ADRMATCH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
435
|
uint8_t RESERVED10[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
436
|
__IO uint8_t RS485DLY;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
437
|
uint8_t RESERVED11[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
438
|
__I uint8_t FIFOLVL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
439
|
} LPC_UART1_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
440
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
441
|
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
442
|
/** @brief Serial Peripheral Interface (SPI) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
443
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
444
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
445
|
__IO uint32_t SPCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
446
|
__I uint32_t SPSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
447
|
__IO uint32_t SPDR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
448
|
__IO uint32_t SPCCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
449
|
uint32_t RESERVED0[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
450
|
__IO uint32_t SPINT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
451
|
} LPC_SPI_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
452
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
453
|
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
454
|
/** @brief Synchronous Serial Communication (SSP) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
455
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
456
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
457
|
__IO uint32_t CR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
458
|
__IO uint32_t CR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
459
|
__IO uint32_t DR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
460
|
__I uint32_t SR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
461
|
__IO uint32_t CPSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
462
|
__IO uint32_t IMSC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
463
|
__IO uint32_t RIS;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
464
|
__IO uint32_t MIS;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
465
|
__IO uint32_t ICR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
466
|
__IO uint32_t DMACR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
467
|
} LPC_SSP_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
468
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
469
|
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
470
|
/** @brief Inter-Integrated Circuit (I2C) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
471
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
472
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
473
|
__IO uint32_t I2CONSET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
474
|
__I uint32_t I2STAT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
475
|
__IO uint32_t I2DAT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
476
|
__IO uint32_t I2ADR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
477
|
__IO uint32_t I2SCLH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
478
|
__IO uint32_t I2SCLL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
479
|
__O uint32_t I2CONCLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
480
|
__IO uint32_t MMCTRL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
481
|
__IO uint32_t I2ADR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
482
|
__IO uint32_t I2ADR2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
483
|
__IO uint32_t I2ADR3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
484
|
__I uint32_t I2DATA_BUFFER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
485
|
__IO uint32_t I2MASK0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
486
|
__IO uint32_t I2MASK1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
487
|
__IO uint32_t I2MASK2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
488
|
__IO uint32_t I2MASK3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
489
|
} LPC_I2C_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
490
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
491
|
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
492
|
/** @brief Inter IC Sound (I2S) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
493
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
494
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
495
|
__IO uint32_t I2SDAO;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
496
|
__IO uint32_t I2SDAI;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
497
|
__O uint32_t I2STXFIFO;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
498
|
__I uint32_t I2SRXFIFO;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
499
|
__I uint32_t I2SSTATE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
500
|
__IO uint32_t I2SDMA1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
501
|
__IO uint32_t I2SDMA2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
502
|
__IO uint32_t I2SIRQ;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
503
|
__IO uint32_t I2STXRATE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
504
|
__IO uint32_t I2SRXRATE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
505
|
__IO uint32_t I2STXBITRATE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
506
|
__IO uint32_t I2SRXBITRATE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
507
|
__IO uint32_t I2STXMODE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
508
|
__IO uint32_t I2SRXMODE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
509
|
} LPC_I2S_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
510
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
511
|
/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
512
|
/** @brief Repetitive Interrupt Timer (RIT) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
513
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
514
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
515
|
__IO uint32_t RICOMPVAL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
516
|
__IO uint32_t RIMASK;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
517
|
__IO uint8_t RICTRL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
518
|
uint8_t RESERVED0[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
519
|
__IO uint32_t RICOUNTER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
520
|
} LPC_RIT_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
521
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
522
|
/*------------- Real-Time Clock (RTC) ----------------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
523
|
/** @brief Real-Time Clock (RTC) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
524
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
525
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
526
|
__IO uint8_t ILR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
527
|
uint8_t RESERVED0[7];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
528
|
__IO uint8_t CCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
529
|
uint8_t RESERVED1[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
530
|
__IO uint8_t CIIR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
531
|
uint8_t RESERVED2[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
532
|
__IO uint8_t AMR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
533
|
uint8_t RESERVED3[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
534
|
__I uint32_t CTIME0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
535
|
__I uint32_t CTIME1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
536
|
__I uint32_t CTIME2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
537
|
__IO uint8_t SEC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
538
|
uint8_t RESERVED4[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
539
|
__IO uint8_t MIN;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
540
|
uint8_t RESERVED5[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
541
|
__IO uint8_t HOUR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
542
|
uint8_t RESERVED6[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
543
|
__IO uint8_t DOM;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
544
|
uint8_t RESERVED7[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
545
|
__IO uint8_t DOW;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
546
|
uint8_t RESERVED8[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
547
|
__IO uint16_t DOY;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
548
|
uint16_t RESERVED9;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
549
|
__IO uint8_t MONTH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
550
|
uint8_t RESERVED10[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
551
|
__IO uint16_t YEAR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
552
|
uint16_t RESERVED11;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
553
|
__IO uint32_t CALIBRATION;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
554
|
__IO uint32_t GPREG0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
555
|
__IO uint32_t GPREG1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
556
|
__IO uint32_t GPREG2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
557
|
__IO uint32_t GPREG3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
558
|
__IO uint32_t GPREG4;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
559
|
__IO uint8_t RTC_AUXEN;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
560
|
uint8_t RESERVED12[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
561
|
__IO uint8_t RTC_AUX;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
562
|
uint8_t RESERVED13[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
563
|
__IO uint8_t ALSEC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
564
|
uint8_t RESERVED14[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
565
|
__IO uint8_t ALMIN;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
566
|
uint8_t RESERVED15[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
567
|
__IO uint8_t ALHOUR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
568
|
uint8_t RESERVED16[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
569
|
__IO uint8_t ALDOM;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
570
|
uint8_t RESERVED17[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
571
|
__IO uint8_t ALDOW;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
572
|
uint8_t RESERVED18[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
573
|
__IO uint16_t ALDOY;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
574
|
uint16_t RESERVED19;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
575
|
__IO uint8_t ALMON;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
576
|
uint8_t RESERVED20[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
577
|
__IO uint16_t ALYEAR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
578
|
uint16_t RESERVED21;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
579
|
} LPC_RTC_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
580
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
581
|
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
582
|
/** @brief Watchdog Timer (WDT) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
583
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
584
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
585
|
__IO uint8_t WDMOD;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
586
|
uint8_t RESERVED0[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
587
|
__IO uint32_t WDTC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
588
|
__O uint8_t WDFEED;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
589
|
uint8_t RESERVED1[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
590
|
__I uint32_t WDTV;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
591
|
__IO uint32_t WDCLKSEL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
592
|
} LPC_WDT_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
593
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
594
|
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
595
|
/** @brief Analog-to-Digital Converter (ADC) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
596
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
597
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
598
|
__IO uint32_t ADCR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
599
|
__IO uint32_t ADGDR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
600
|
uint32_t RESERVED0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
601
|
__IO uint32_t ADINTEN;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
602
|
__I uint32_t ADDR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
603
|
__I uint32_t ADDR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
604
|
__I uint32_t ADDR2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
605
|
__I uint32_t ADDR3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
606
|
__I uint32_t ADDR4;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
607
|
__I uint32_t ADDR5;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
608
|
__I uint32_t ADDR6;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
609
|
__I uint32_t ADDR7;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
610
|
__I uint32_t ADSTAT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
611
|
__IO uint32_t ADTRM;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
612
|
} LPC_ADC_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
613
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
614
|
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
615
|
/** @brief Digital-to-Analog Converter (DAC) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
616
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
617
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
618
|
__IO uint32_t DACR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
619
|
__IO uint32_t DACCTRL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
620
|
__IO uint16_t DACCNTVAL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
621
|
} LPC_DAC_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
622
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
623
|
/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
624
|
/** @brief Motor Control Pulse-Width Modulation (MCPWM) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
625
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
626
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
627
|
__I uint32_t MCCON;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
628
|
__O uint32_t MCCON_SET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
629
|
__O uint32_t MCCON_CLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
630
|
__I uint32_t MCCAPCON;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
631
|
__O uint32_t MCCAPCON_SET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
632
|
__O uint32_t MCCAPCON_CLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
633
|
__IO uint32_t MCTIM0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
634
|
__IO uint32_t MCTIM1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
635
|
__IO uint32_t MCTIM2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
636
|
__IO uint32_t MCPER0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
637
|
__IO uint32_t MCPER1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
638
|
__IO uint32_t MCPER2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
639
|
__IO uint32_t MCPW0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
640
|
__IO uint32_t MCPW1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
641
|
__IO uint32_t MCPW2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
642
|
__IO uint32_t MCDEADTIME;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
643
|
__IO uint32_t MCCCP;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
644
|
__IO uint32_t MCCR0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
645
|
__IO uint32_t MCCR1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
646
|
__IO uint32_t MCCR2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
647
|
__I uint32_t MCINTEN;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
648
|
__O uint32_t MCINTEN_SET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
649
|
__O uint32_t MCINTEN_CLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
650
|
__I uint32_t MCCNTCON;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
651
|
__O uint32_t MCCNTCON_SET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
652
|
__O uint32_t MCCNTCON_CLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
653
|
__I uint32_t MCINTFLAG;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
654
|
__O uint32_t MCINTFLAG_SET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
655
|
__O uint32_t MCINTFLAG_CLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
656
|
__O uint32_t MCCAP_CLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
657
|
} LPC_MCPWM_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
658
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
659
|
/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
660
|
/** @brief Quadrature Encoder Interface (QEI) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
661
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
662
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
663
|
__O uint32_t QEICON;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
664
|
__I uint32_t QEISTAT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
665
|
__IO uint32_t QEICONF;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
666
|
__I uint32_t QEIPOS;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
667
|
__IO uint32_t QEIMAXPOS;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
668
|
__IO uint32_t CMPOS0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
669
|
__IO uint32_t CMPOS1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
670
|
__IO uint32_t CMPOS2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
671
|
__I uint32_t INXCNT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
672
|
__IO uint32_t INXCMP;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
673
|
__IO uint32_t QEILOAD;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
674
|
__I uint32_t QEITIME;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
675
|
__I uint32_t QEIVEL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
676
|
__I uint32_t QEICAP;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
677
|
__IO uint32_t VELCOMP;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
678
|
__IO uint32_t FILTER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
679
|
uint32_t RESERVED0[998];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
680
|
__O uint32_t QEIIEC;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
681
|
__O uint32_t QEIIES;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
682
|
__I uint32_t QEIINTSTAT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
683
|
__I uint32_t QEIIE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
684
|
__O uint32_t QEICLR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
685
|
__O uint32_t QEISET;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
686
|
} LPC_QEI_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
687
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
688
|
/*------------- Controller Area Network (CAN) --------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
689
|
/** @brief Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
690
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
691
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
692
|
__IO uint32_t mask[512]; /* ID Masks */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
693
|
} LPC_CANAF_RAM_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
694
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
695
|
/** @brief Controller Area Network Acceptance Filter(CANAF) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
696
|
typedef struct /* Acceptance Filter Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
697
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
698
|
__IO uint32_t AFMR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
699
|
__IO uint32_t SFF_sa;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
700
|
__IO uint32_t SFF_GRP_sa;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
701
|
__IO uint32_t EFF_sa;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
702
|
__IO uint32_t EFF_GRP_sa;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
703
|
__IO uint32_t ENDofTable;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
704
|
__I uint32_t LUTerrAd;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
705
|
__I uint32_t LUTerr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
706
|
__IO uint32_t FCANIE;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
707
|
__IO uint32_t FCANIC0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
708
|
__IO uint32_t FCANIC1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
709
|
} LPC_CANAF_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
710
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
711
|
/** @brief Controller Area Network Central (CANCR) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
712
|
typedef struct /* Central Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
713
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
714
|
__I uint32_t CANTxSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
715
|
__I uint32_t CANRxSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
716
|
__I uint32_t CANMSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
717
|
} LPC_CANCR_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
718
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
719
|
/** @brief Controller Area Network Controller (CAN) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
720
|
typedef struct /* Controller Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
721
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
722
|
__IO uint32_t MOD;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
723
|
__O uint32_t CMR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
724
|
__IO uint32_t GSR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
725
|
__I uint32_t ICR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
726
|
__IO uint32_t IER;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
727
|
__IO uint32_t BTR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
728
|
__IO uint32_t EWL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
729
|
__I uint32_t SR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
730
|
__IO uint32_t RFS;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
731
|
__IO uint32_t RID;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
732
|
__IO uint32_t RDA;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
733
|
__IO uint32_t RDB;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
734
|
__IO uint32_t TFI1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
735
|
__IO uint32_t TID1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
736
|
__IO uint32_t TDA1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
737
|
__IO uint32_t TDB1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
738
|
__IO uint32_t TFI2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
739
|
__IO uint32_t TID2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
740
|
__IO uint32_t TDA2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
741
|
__IO uint32_t TDB2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
742
|
__IO uint32_t TFI3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
743
|
__IO uint32_t TID3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
744
|
__IO uint32_t TDA3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
745
|
__IO uint32_t TDB3;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
746
|
} LPC_CAN_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
747
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
748
|
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
749
|
/** @brief General Purpose Direct Memory Access (GPDMA) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
750
|
typedef struct /* Common Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
751
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
752
|
__I uint32_t DMACIntStat;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
753
|
__I uint32_t DMACIntTCStat;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
754
|
__O uint32_t DMACIntTCClear;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
755
|
__I uint32_t DMACIntErrStat;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
756
|
__O uint32_t DMACIntErrClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
757
|
__I uint32_t DMACRawIntTCStat;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
758
|
__I uint32_t DMACRawIntErrStat;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
759
|
__I uint32_t DMACEnbldChns;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
760
|
__IO uint32_t DMACSoftBReq;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
761
|
__IO uint32_t DMACSoftSReq;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
762
|
__IO uint32_t DMACSoftLBReq;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
763
|
__IO uint32_t DMACSoftLSReq;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
764
|
__IO uint32_t DMACConfig;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
765
|
__IO uint32_t DMACSync;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
766
|
} LPC_GPDMA_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
767
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
768
|
/** @brief General Purpose Direct Memory Access Channel (GPDMACH) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
769
|
typedef struct /* Channel Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
770
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
771
|
__IO uint32_t DMACCSrcAddr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
772
|
__IO uint32_t DMACCDestAddr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
773
|
__IO uint32_t DMACCLLI;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
774
|
__IO uint32_t DMACCControl;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
775
|
__IO uint32_t DMACCConfig;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
776
|
} LPC_GPDMACH_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
777
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
778
|
/*------------- Universal Serial Bus (USB) -----------------------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
779
|
/** @brief Universal Serial Bus (USB) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
780
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
781
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
782
|
__I uint32_t HcRevision; /* USB Host Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
783
|
__IO uint32_t HcControl;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
784
|
__IO uint32_t HcCommandStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
785
|
__IO uint32_t HcInterruptStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
786
|
__IO uint32_t HcInterruptEnable;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
787
|
__IO uint32_t HcInterruptDisable;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
788
|
__IO uint32_t HcHCCA;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
789
|
__I uint32_t HcPeriodCurrentED;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
790
|
__IO uint32_t HcControlHeadED;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
791
|
__IO uint32_t HcControlCurrentED;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
792
|
__IO uint32_t HcBulkHeadED;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
793
|
__IO uint32_t HcBulkCurrentED;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
794
|
__I uint32_t HcDoneHead;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
795
|
__IO uint32_t HcFmInterval;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
796
|
__I uint32_t HcFmRemaining;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
797
|
__I uint32_t HcFmNumber;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
798
|
__IO uint32_t HcPeriodicStart;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
799
|
__IO uint32_t HcLSTreshold;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
800
|
__IO uint32_t HcRhDescriptorA;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
801
|
__IO uint32_t HcRhDescriptorB;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
802
|
__IO uint32_t HcRhStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
803
|
__IO uint32_t HcRhPortStatus1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
804
|
__IO uint32_t HcRhPortStatus2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
805
|
uint32_t RESERVED0[40];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
806
|
__I uint32_t Module_ID;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
807
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
808
|
__I uint32_t OTGIntSt; /* USB On-The-Go Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
809
|
__IO uint32_t OTGIntEn;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
810
|
__O uint32_t OTGIntSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
811
|
__O uint32_t OTGIntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
812
|
__IO uint32_t OTGStCtrl;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
813
|
__IO uint32_t OTGTmr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
814
|
uint32_t RESERVED1[58];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
815
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
816
|
__I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
817
|
__IO uint32_t USBDevIntEn;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
818
|
__O uint32_t USBDevIntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
819
|
__O uint32_t USBDevIntSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
820
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
821
|
__O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
822
|
__I uint32_t USBCmdData;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
823
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
824
|
__I uint32_t USBRxData; /* USB Device Transfer Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
825
|
__O uint32_t USBTxData;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
826
|
__I uint32_t USBRxPLen;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
827
|
__O uint32_t USBTxPLen;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
828
|
__IO uint32_t USBCtrl;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
829
|
__O uint32_t USBDevIntPri;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
830
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
831
|
__I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
832
|
__IO uint32_t USBEpIntEn;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
833
|
__O uint32_t USBEpIntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
834
|
__O uint32_t USBEpIntSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
835
|
__O uint32_t USBEpIntPri;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
836
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
837
|
__IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
838
|
__O uint32_t USBEpInd;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
839
|
__IO uint32_t USBMaxPSize;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
840
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
841
|
__I uint32_t USBDMARSt; /* USB Device DMA Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
842
|
__O uint32_t USBDMARClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
843
|
__O uint32_t USBDMARSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
844
|
uint32_t RESERVED2[9];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
845
|
__IO uint32_t USBUDCAH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
846
|
__I uint32_t USBEpDMASt;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
847
|
__O uint32_t USBEpDMAEn;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
848
|
__O uint32_t USBEpDMADis;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
849
|
__I uint32_t USBDMAIntSt;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
850
|
__IO uint32_t USBDMAIntEn;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
851
|
uint32_t RESERVED3[2];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
852
|
__I uint32_t USBEoTIntSt;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
853
|
__O uint32_t USBEoTIntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
854
|
__O uint32_t USBEoTIntSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
855
|
__I uint32_t USBNDDRIntSt;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
856
|
__O uint32_t USBNDDRIntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
857
|
__O uint32_t USBNDDRIntSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
858
|
__I uint32_t USBSysErrIntSt;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
859
|
__O uint32_t USBSysErrIntClr;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
860
|
__O uint32_t USBSysErrIntSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
861
|
uint32_t RESERVED4[15];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
862
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
863
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
864
|
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
865
|
__O uint32_t I2C_TX;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
866
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
867
|
__I uint32_t I2C_STS;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
868
|
__IO uint32_t I2C_CTL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
869
|
__IO uint32_t I2C_CLKHI;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
870
|
__O uint32_t I2C_CLKLO;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
871
|
uint32_t RESERVED5[824];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
872
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
873
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
874
|
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
875
|
__IO uint32_t OTGClkCtrl;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
876
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
877
|
union {
|
lynxeyed_atsu |
0:63ed631d8c3a
|
878
|
__I uint32_t USBClkSt;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
879
|
__I uint32_t OTGClkSt;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
880
|
};
|
lynxeyed_atsu |
0:63ed631d8c3a
|
881
|
} LPC_USB_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
882
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
883
|
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
884
|
/** @brief Ethernet Media Access Controller (EMAC) register structure definition */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
885
|
typedef struct
|
lynxeyed_atsu |
0:63ed631d8c3a
|
886
|
{
|
lynxeyed_atsu |
0:63ed631d8c3a
|
887
|
__IO uint32_t MAC1; /* MAC Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
888
|
__IO uint32_t MAC2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
889
|
__IO uint32_t IPGT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
890
|
__IO uint32_t IPGR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
891
|
__IO uint32_t CLRT;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
892
|
__IO uint32_t MAXF;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
893
|
__IO uint32_t SUPP;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
894
|
__IO uint32_t TEST;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
895
|
__IO uint32_t MCFG;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
896
|
__IO uint32_t MCMD;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
897
|
__IO uint32_t MADR;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
898
|
__O uint32_t MWTD;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
899
|
__I uint32_t MRDD;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
900
|
__I uint32_t MIND;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
901
|
uint32_t RESERVED0[2];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
902
|
__IO uint32_t SA0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
903
|
__IO uint32_t SA1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
904
|
__IO uint32_t SA2;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
905
|
uint32_t RESERVED1[45];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
906
|
__IO uint32_t Command; /* Control Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
907
|
__I uint32_t Status;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
908
|
__IO uint32_t RxDescriptor;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
909
|
__IO uint32_t RxStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
910
|
__IO uint32_t RxDescriptorNumber;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
911
|
__I uint32_t RxProduceIndex;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
912
|
__IO uint32_t RxConsumeIndex;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
913
|
__IO uint32_t TxDescriptor;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
914
|
__IO uint32_t TxStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
915
|
__IO uint32_t TxDescriptorNumber;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
916
|
__IO uint32_t TxProduceIndex;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
917
|
__I uint32_t TxConsumeIndex;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
918
|
uint32_t RESERVED2[10];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
919
|
__I uint32_t TSV0;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
920
|
__I uint32_t TSV1;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
921
|
__I uint32_t RSV;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
922
|
uint32_t RESERVED3[3];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
923
|
__IO uint32_t FlowControlCounter;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
924
|
__I uint32_t FlowControlStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
925
|
uint32_t RESERVED4[34];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
926
|
__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
927
|
__IO uint32_t RxFilterWoLStatus;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
928
|
__IO uint32_t RxFilterWoLClear;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
929
|
uint32_t RESERVED5;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
930
|
__IO uint32_t HashFilterL;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
931
|
__IO uint32_t HashFilterH;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
932
|
uint32_t RESERVED6[882];
|
lynxeyed_atsu |
0:63ed631d8c3a
|
933
|
__I uint32_t IntStatus; /* Module Control Registers */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
934
|
__IO uint32_t IntEnable;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
935
|
__O uint32_t IntClear;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
936
|
__O uint32_t IntSet;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
937
|
uint32_t RESERVED7;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
938
|
__IO uint32_t PowerDown;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
939
|
uint32_t RESERVED8;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
940
|
__IO uint32_t Module_ID;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
941
|
} LPC_EMAC_TypeDef;
|
lynxeyed_atsu |
0:63ed631d8c3a
|
942
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
943
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
944
|
#if defined ( __CC_ARM )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
945
|
#pragma no_anon_unions
|
lynxeyed_atsu |
0:63ed631d8c3a
|
946
|
#endif
|
lynxeyed_atsu |
0:63ed631d8c3a
|
947
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
948
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
949
|
/******************************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
950
|
/* Peripheral memory map */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
951
|
/******************************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
952
|
/* Base addresses */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
953
|
#define LPC_FLASH_BASE (0x00000000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
954
|
#define LPC_RAM_BASE (0x10000000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
955
|
#ifdef __LPC17XX_REV00
|
lynxeyed_atsu |
0:63ed631d8c3a
|
956
|
#define LPC_AHBRAM0_BASE (0x20000000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
957
|
#define LPC_AHBRAM1_BASE (0x20004000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
958
|
#else
|
lynxeyed_atsu |
0:63ed631d8c3a
|
959
|
#define LPC_AHBRAM0_BASE (0x2007C000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
960
|
#define LPC_AHBRAM1_BASE (0x20080000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
961
|
#endif
|
lynxeyed_atsu |
0:63ed631d8c3a
|
962
|
#define LPC_GPIO_BASE (0x2009C000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
963
|
#define LPC_APB0_BASE (0x40000000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
964
|
#define LPC_APB1_BASE (0x40080000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
965
|
#define LPC_AHB_BASE (0x50000000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
966
|
#define LPC_CM3_BASE (0xE0000000UL)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
967
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
968
|
/* APB0 peripherals */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
969
|
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
970
|
#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
971
|
#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
972
|
#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
973
|
#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
974
|
#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
975
|
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
976
|
#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
977
|
#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
978
|
#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
979
|
#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
980
|
#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
981
|
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
982
|
#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
983
|
#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
984
|
#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
985
|
#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
986
|
#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
987
|
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
988
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
989
|
/* APB1 peripherals */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
990
|
#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
991
|
#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
992
|
#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
993
|
#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
994
|
#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
995
|
#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
996
|
#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
997
|
#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
998
|
#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
999
|
#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1000
|
#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1001
|
#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1002
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1003
|
/* AHB peripherals */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1004
|
#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1005
|
#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1006
|
#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1007
|
#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1008
|
#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1009
|
#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1010
|
#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1011
|
#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1012
|
#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1013
|
#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1014
|
#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1015
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1016
|
/* GPIOs */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1017
|
#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1018
|
#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1019
|
#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1020
|
#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1021
|
#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1022
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1023
|
/******************************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1024
|
/* Peripheral declaration */
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1025
|
/******************************************************************************/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1026
|
#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1027
|
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1028
|
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1029
|
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1030
|
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1031
|
#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1032
|
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1033
|
#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1034
|
#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1035
|
#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1036
|
#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1037
|
#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1038
|
#define LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1039
|
#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1040
|
#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1041
|
#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1042
|
#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1043
|
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1044
|
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1045
|
#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1046
|
#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1047
|
#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1048
|
#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1049
|
#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1050
|
#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1051
|
#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1052
|
#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1053
|
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1054
|
#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1055
|
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1056
|
#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1057
|
#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1058
|
#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1059
|
#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1060
|
#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1061
|
#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1062
|
#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1063
|
#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1064
|
#define DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4))
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1065
|
#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1066
|
#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1067
|
#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1068
|
#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1069
|
#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1070
|
#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1071
|
#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1072
|
#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1073
|
#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1074
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1075
|
/**
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1076
|
* @}
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1077
|
*/
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1078
|
|
lynxeyed_atsu |
0:63ed631d8c3a
|
1079
|
#endif // __LPC17xx_H__
|