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/***********************************************************************//**
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* @file lpc17xx_clkpwr.h
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* @brief Contains all macro definitions and function prototypes
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* support for Clock and Power Control firmware library on LPC17xx
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* @version 2.0
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* @date 21. May. 2010
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* @author NXP MCU SW Application Team
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**************************************************************************/
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/* Peripheral group ----------------------------------------------------------- */
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/** @defgroup CLKPWR CLKPWR
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* @ingroup LPC1700CMSIS_FwLib_Drivers
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* @{
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*/
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#ifndef LPC17XX_CLKPWR_H_
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#define LPC17XX_CLKPWR_H_
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/* Includes ------------------------------------------------------------------- */
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#include "LPC17xx.h"
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#include "lpc_types.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Public Macros -------------------------------------------------------------- */
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/** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros
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* @{
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*/
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/**********************************************************************
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* Peripheral Clock Selection Definitions
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**********************************************************************/
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/** Peripheral clock divider bit position for WDT */
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#define CLKPWR_PCLKSEL_WDT ((uint32_t)(0))
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/** Peripheral clock divider bit position for TIMER0 */
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#define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2))
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/** Peripheral clock divider bit position for TIMER1 */
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#define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4))
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/** Peripheral clock divider bit position for UART0 */
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#define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6))
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/** Peripheral clock divider bit position for UART1 */
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#define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8))
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/** Peripheral clock divider bit position for PWM1 */
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#define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12))
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/** Peripheral clock divider bit position for I2C0 */
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#define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14))
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/** Peripheral clock divider bit position for SPI */
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#define CLKPWR_PCLKSEL_SPI ((uint32_t)(16))
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/** Peripheral clock divider bit position for SSP1 */
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#define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20))
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/** Peripheral clock divider bit position for DAC */
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#define CLKPWR_PCLKSEL_DAC ((uint32_t)(22))
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/** Peripheral clock divider bit position for ADC */
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#define CLKPWR_PCLKSEL_ADC ((uint32_t)(24))
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/** Peripheral clock divider bit position for CAN1 */
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#define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26))
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/** Peripheral clock divider bit position for CAN2 */
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#define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28))
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/** Peripheral clock divider bit position for ACF */
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#define CLKPWR_PCLKSEL_ACF ((uint32_t)(30))
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/** Peripheral clock divider bit position for QEI */
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#define CLKPWR_PCLKSEL_QEI ((uint32_t)(32))
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/** Peripheral clock divider bit position for PCB */
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#define CLKPWR_PCLKSEL_PCB ((uint32_t)(36))
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/** Peripheral clock divider bit position for I2C1 */
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#define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38))
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/** Peripheral clock divider bit position for SSP0 */
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#define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42))
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/** Peripheral clock divider bit position for TIMER2 */
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#define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44))
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/** Peripheral clock divider bit position for TIMER3 */
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#define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46))
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/** Peripheral clock divider bit position for UART2 */
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#define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48))
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/** Peripheral clock divider bit position for UART3 */
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#define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50))
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/** Peripheral clock divider bit position for I2C2 */
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#define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52))
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/** Peripheral clock divider bit position for I2S */
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#define CLKPWR_PCLKSEL_I2S ((uint32_t)(54))
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/** Peripheral clock divider bit position for RIT */
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#define CLKPWR_PCLKSEL_RIT ((uint32_t)(58))
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/** Peripheral clock divider bit position for SYSCON */
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#define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60))
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/** Peripheral clock divider bit position for MC */
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#define CLKPWR_PCLKSEL_MC ((uint32_t)(62))
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/** Macro for Peripheral Clock Selection register bit values
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* Note: When CCLK_DIV_8, Peripheral�s clock is selected to
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* PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering
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* when �11�selects PCLK_xyz = CCLK/6 */
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/* Peripheral clock divider is set to 4 from CCLK */
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#define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0))
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/** Peripheral clock divider is the same with CCLK */
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#define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1))
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/** Peripheral clock divider is set to 2 from CCLK */
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#define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2))
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/********************************************************************
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* Power Control for Peripherals Definitions
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**********************************************************************/
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/** Timer/Counter 0 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1))
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/* Timer/Counter 1 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2))
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/** UART0 power/clock control bit */
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#define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3))
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/** UART1 power/clock control bit */
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#define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4))
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/** PWM1 power/clock control bit */
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#define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6))
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/** The I2C0 interface power/clock control bit */
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#define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7))
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/** The SPI interface power/clock control bit */
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#define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8))
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/** The RTC power/clock control bit */
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#define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9))
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/** The SSP1 interface power/clock control bit */
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#define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10))
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/** A/D converter 0 (ADC0) power/clock control bit */
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#define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12))
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/** CAN Controller 1 power/clock control bit */
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#define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13))
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/** CAN Controller 2 power/clock control bit */
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#define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14))
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/** GPIO power/clock control bit */
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#define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15))
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/** Repetitive Interrupt Timer power/clock control bit */
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#define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16))
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/** Motor Control PWM */
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#define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17))
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/** Quadrature Encoder Interface power/clock control bit */
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#define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18))
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/** The I2C1 interface power/clock control bit */
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#define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19))
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/** The SSP0 interface power/clock control bit */
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#define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21))
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/** Timer 2 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22))
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155
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/** Timer 3 power/clock control bit */
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#define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23))
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157
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/** UART 2 power/clock control bit */
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#define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24))
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/** UART 3 power/clock control bit */
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#define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25))
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/** I2C interface 2 power/clock control bit */
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#define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26))
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/** I2S interface power/clock control bit*/
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#define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27))
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165
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/** GP DMA function power/clock control bit*/
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166
|
#define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29))
|
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|
167
|
/** Ethernet block power/clock control bit*/
|
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168
|
#define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
|
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|
169
|
/** USB interface power/clock control bit*/
|
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170
|
#define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31))
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171
|
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172
|
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|
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|
/**
|
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174
|
* @}
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175
|
*/
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176
|
/* Private Macros ------------------------------------------------------------- */
|
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177
|
/** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros
|
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178
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* @{
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179
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*/
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|
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|
/* --------------------- BIT DEFINITIONS -------------------------------------- */
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182
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/*********************************************************************//**
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183
|
* Macro defines for Clock Source Select Register
|
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0:63ed631d8c3a
|
184
|
**********************************************************************/
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185
|
/** Internal RC oscillator */
|
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186
|
#define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00))
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187
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/** Main oscillator */
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188
|
#define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01))
|
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189
|
/** RTC oscillator */
|
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190
|
#define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02))
|
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191
|
/** Clock source selection bit mask */
|
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192
|
#define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03))
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193
|
|
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|
194
|
/*********************************************************************//**
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195
|
* Macro defines for Clock Output Configuration Register
|
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|
196
|
**********************************************************************/
|
| lynxeyed_atsu |
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|
197
|
/* Clock Output Configuration register definition */
|
| lynxeyed_atsu |
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|
198
|
/** Selects the CPU clock as the CLKOUT source */
|
| lynxeyed_atsu |
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199
|
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00))
|
| lynxeyed_atsu |
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|
200
|
/** Selects the main oscillator as the CLKOUT source */
|
| lynxeyed_atsu |
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|
201
|
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01))
|
| lynxeyed_atsu |
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|
202
|
/** Selects the Internal RC oscillator as the CLKOUT source */
|
| lynxeyed_atsu |
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203
|
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02))
|
| lynxeyed_atsu |
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|
204
|
/** Selects the USB clock as the CLKOUT source */
|
| lynxeyed_atsu |
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|
205
|
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03))
|
| lynxeyed_atsu |
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|
206
|
/** Selects the RTC oscillator as the CLKOUT source */
|
| lynxeyed_atsu |
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|
207
|
#define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
208
|
/** Integer value to divide the output clock by, minus one */
|
| lynxeyed_atsu |
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|
209
|
#define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4))
|
| lynxeyed_atsu |
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|
210
|
/** CLKOUT enable control */
|
| lynxeyed_atsu |
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|
211
|
#define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
212
|
/** CLKOUT activity indication */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
213
|
#define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
214
|
/** Clock source selection bit mask */
|
| lynxeyed_atsu |
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|
215
|
#define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
216
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
217
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
218
|
* Macro defines for PPL0 Control Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
219
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
220
|
/** PLL 0 control enable */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
221
|
#define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
222
|
/** PLL 0 control connect */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
223
|
#define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
224
|
/** PLL 0 control bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
225
|
#define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
226
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
227
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
228
|
* Macro defines for PPL0 Configuration Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
229
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
230
|
/** PLL 0 Configuration MSEL field */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
231
|
#define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
232
|
/** PLL 0 Configuration NSEL field */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
233
|
#define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
234
|
/** PLL 0 Configuration bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
235
|
#define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
236
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
237
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
238
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
239
|
* Macro defines for PPL0 Status Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
240
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
241
|
/** PLL 0 MSEL value */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
242
|
#define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
243
|
/** PLL NSEL get value */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
244
|
#define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
245
|
/** PLL status enable bit */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
246
|
#define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
247
|
/** PLL status Connect bit */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
248
|
#define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
249
|
/** PLL status lock */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
250
|
#define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
251
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
252
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
253
|
* Macro defines for PPL0 Feed Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
254
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
255
|
/** PLL0 Feed bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
256
|
#define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
257
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
258
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
259
|
* Macro defines for PLL1 Control Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
260
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
261
|
/** USB PLL control enable */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
262
|
#define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
263
|
/** USB PLL control connect */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
264
|
#define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
265
|
/** USB PLL control bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
266
|
#define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
267
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
268
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
269
|
* Macro defines for PLL1 Configuration Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
270
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
271
|
/** USB PLL MSEL set value */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
272
|
#define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
273
|
/** USB PLL PSEL set value */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
274
|
#define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
275
|
/** USB PLL configuration bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
276
|
#define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
277
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
278
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
279
|
* Macro defines for PLL1 Status Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
280
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
281
|
/** USB PLL MSEL get value */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
282
|
#define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
283
|
/** USB PLL PSEL get value */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
284
|
#define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
285
|
/** USB PLL status enable bit */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
286
|
#define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
287
|
/** USB PLL status Connect bit */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
288
|
#define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
289
|
/** USB PLL status lock */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
290
|
#define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
291
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
292
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
293
|
* Macro defines for PLL1 Feed Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
294
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
295
|
/** PLL1 Feed bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
296
|
#define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
297
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
298
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
299
|
* Macro defines for CPU Clock Configuration Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
300
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
301
|
/** CPU Clock configuration bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
302
|
#define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
303
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
304
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
305
|
* Macro defines for USB Clock Configuration Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
306
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
307
|
/** USB Clock Configuration bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
308
|
#define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
309
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
310
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
311
|
* Macro defines for IRC Trim Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
312
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
313
|
/** IRC Trim bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
314
|
#define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
315
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
316
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
317
|
* Macro defines for Peripheral Clock Selection Register 0 and 1
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
318
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
319
|
/** Peripheral Clock Selection 0 mask bit */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
320
|
#define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
321
|
/** Peripheral Clock Selection 1 mask bit */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
322
|
#define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
323
|
/** Macro to set peripheral clock of each type
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
324
|
* p: position of two bits that hold divider of peripheral clock
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
325
|
* n: value of divider of peripheral clock to be set */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
326
|
#define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
327
|
/** Macro to mask peripheral clock of each type */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
328
|
#define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03)
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
329
|
/** Macro to get peripheral clock of each type */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
330
|
#define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
331
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
332
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
333
|
* Macro defines for Power Mode Control Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
334
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
335
|
/** Power mode control bit 0 */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
336
|
#define CLKPWR_PCON_PM0 ((uint32_t)(1<<0))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
337
|
/** Power mode control bit 1 */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
338
|
#define CLKPWR_PCON_PM1 ((uint32_t)(1<<1))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
339
|
/** Brown-Out Reduced Power Mode */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
340
|
#define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
341
|
/** Brown-Out Global Disable */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
342
|
#define CLKPWR_PCON_BOGD ((uint32_t)(1<<3))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
343
|
/** Brown Out Reset Disable */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
344
|
#define CLKPWR_PCON_BORD ((uint32_t)(1<<4))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
345
|
/** Sleep Mode entry flag */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
346
|
#define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
347
|
/** Deep Sleep entry flag */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
348
|
#define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
349
|
/** Power-down entry flag */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
350
|
#define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
351
|
/** Deep Power-down entry flag */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
352
|
#define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11))
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
353
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
354
|
/*********************************************************************//**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
355
|
* Macro defines for Power Control for Peripheral Register
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
356
|
**********************************************************************/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
357
|
/** Power Control for Peripherals bit mask */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
358
|
#define CLKPWR_PCONP_BITMASK 0xEFEFF7DE
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
359
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
360
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
361
|
* @}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
362
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
363
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
364
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
365
|
/* Public Functions ----------------------------------------------------------- */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
366
|
/** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
367
|
* @{
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
368
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
369
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
370
|
void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
371
|
uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
372
|
uint32_t CLKPWR_GetPCLK (uint32_t ClkType);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
373
|
void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
374
|
void CLKPWR_Sleep(void);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
375
|
void CLKPWR_DeepSleep(void);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
376
|
void CLKPWR_PowerDown(void);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
377
|
void CLKPWR_DeepPowerDown(void);
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
378
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
379
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
380
|
* @}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
381
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
382
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
383
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
384
|
#ifdef __cplusplus
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
385
|
}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
386
|
#endif
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
387
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
388
|
#endif /* LPC17XX_CLKPWR_H_ */
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
389
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
390
|
/**
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
391
|
* @}
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
392
|
*/
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
393
|
|
| lynxeyed_atsu |
0:63ed631d8c3a
|
394
|
/* --------------------------------- End Of File ------------------------------ */
|
xeye_ atsu