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LPC17xx.h File Reference
CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series. More...
Go to the source code of this file.
Data Structures | |
| struct | LPC_SC_TypeDef |
| System Control (SC) register structure definition. More... | |
| struct | LPC_PINCON_TypeDef |
| Pin Connect Block (PINCON) register structure definition. More... | |
| struct | LPC_GPIO_TypeDef |
| General Purpose Input/Output (GPIO) register structure definition. More... | |
| struct | LPC_GPIOINT_TypeDef |
| General Purpose Input/Output interrupt (GPIOINT) register structure definition. More... | |
| struct | LPC_TIM_TypeDef |
| Timer (TIM) register structure definition. More... | |
| struct | LPC_PWM_TypeDef |
| Pulse-Width Modulation (PWM) register structure definition. More... | |
| struct | LPC_UART_TypeDef |
| Universal Asynchronous Receiver Transmitter (UART) register structure definition. More... | |
| struct | LPC_UART0_TypeDef |
| Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition. More... | |
| struct | LPC_UART1_TypeDef |
| Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition. More... | |
| struct | LPC_SPI_TypeDef |
| Serial Peripheral Interface (SPI) register structure definition. More... | |
| struct | LPC_SSP_TypeDef |
| Synchronous Serial Communication (SSP) register structure definition. More... | |
| struct | LPC_I2C_TypeDef |
| Inter-Integrated Circuit (I2C) register structure definition. More... | |
| struct | LPC_I2S_TypeDef |
| Inter IC Sound (I2S) register structure definition. More... | |
| struct | LPC_RIT_TypeDef |
| Repetitive Interrupt Timer (RIT) register structure definition. More... | |
| struct | LPC_RTC_TypeDef |
| Real-Time Clock (RTC) register structure definition. More... | |
| struct | LPC_WDT_TypeDef |
| Watchdog Timer (WDT) register structure definition. More... | |
| struct | LPC_ADC_TypeDef |
| Analog-to-Digital Converter (ADC) register structure definition. More... | |
| struct | LPC_DAC_TypeDef |
| Digital-to-Analog Converter (DAC) register structure definition. More... | |
| struct | LPC_MCPWM_TypeDef |
| Motor Control Pulse-Width Modulation (MCPWM) register structure definition. More... | |
| struct | LPC_QEI_TypeDef |
| Quadrature Encoder Interface (QEI) register structure definition. More... | |
| struct | LPC_CANAF_RAM_TypeDef |
| Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition. More... | |
| struct | LPC_CANAF_TypeDef |
| Controller Area Network Acceptance Filter(CANAF) register structure definition. More... | |
| struct | LPC_CANCR_TypeDef |
| Controller Area Network Central (CANCR) register structure definition. More... | |
| struct | LPC_CAN_TypeDef |
| Controller Area Network Controller (CAN) register structure definition. More... | |
| struct | LPC_GPDMA_TypeDef |
| General Purpose Direct Memory Access (GPDMA) register structure definition. More... | |
| struct | LPC_GPDMACH_TypeDef |
| General Purpose Direct Memory Access Channel (GPDMACH) register structure definition. More... | |
| struct | LPC_USB_TypeDef |
| Universal Serial Bus (USB) register structure definition. More... | |
| struct | LPC_EMAC_TypeDef |
| Ethernet Media Access Controller (EMAC) register structure definition. More... | |
Typedefs | |
| typedef enum IRQn | IRQn_Type |
| IRQ interrupt source definition. | |
Enumerations | |
| enum | IRQn { NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WDT_IRQn = 0, TIMER0_IRQn = 1, TIMER1_IRQn = 2, TIMER2_IRQn = 3, TIMER3_IRQn = 4, UART0_IRQn = 5, UART1_IRQn = 6, UART2_IRQn = 7, UART3_IRQn = 8, PWM1_IRQn = 9, I2C0_IRQn = 10, I2C1_IRQn = 11, I2C2_IRQn = 12, SPI_IRQn = 13, SSP0_IRQn = 14, SSP1_IRQn = 15, PLL0_IRQn = 16, RTC_IRQn = 17, EINT0_IRQn = 18, EINT1_IRQn = 19, EINT2_IRQn = 20, EINT3_IRQn = 21, ADC_IRQn = 22, BOD_IRQn = 23, USB_IRQn = 24, CAN_IRQn = 25, DMA_IRQn = 26, I2S_IRQn = 27, ENET_IRQn = 28, RIT_IRQn = 29, MCPWM_IRQn = 30, QEI_IRQn = 31, PLL1_IRQn = 32, USBActivity_IRQn = 33, CANActivity_IRQn = 34 } |
IRQ interrupt source definition. More... | |
Detailed Description
CMSIS Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC17xx Device Series.
- Version:
- : V1.08
- Date:
- : 21. December 2009
- Note:
- Copyright (C) 2009 ARM Limited. All rights reserved.
- ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.
- THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Definition in file LPC17xx.h.
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