xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

Dependencies:   mbed

aic23b_comm.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:
lynxeyed_atsu
Date:
Sat Feb 26 03:55:12 2011 +0000
Revision:
0:e8bfffbb3ab6

        

        
Who changed what in which revision?

        

            
                
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#include "mbed.h"





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//extern void aic23b_init(void);





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//extern int aic23b_send(int addr,char ctrl_address,char ctrl_data);





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// Register map of TLV320AIC23B. See "TLV320AIC23B Data Manual" section 3.1.3





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// I2C ADDRESS(MODE=0,CS=0)=0011010b 





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#define AIC23B_ADDRESS  (52)





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///////////////////////////////////////////////////////////////////////





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// Control Address Bits 





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#define LEFT_LINE_INPUT_CHANNEL_VOLUME_CONTROL      (0x00 << 1)





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#define RIGHT_LINE_INPUT_CHANNEL_VOLUME_CONTROL     (0x01 << 1)





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#define LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL       ((0x02 << 1)|1)





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#define RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL      ((0x03 << 1)|1)





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#define ANALOG_AUDIO_PATH_CONTROL                   (0x04 << 1)





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#define DIGITAL_AUDIO_PATH_CONTROL                  (0x05 << 1)





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#define POWER_DOWN_CONTROL                          (0x06 << 1)





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#define DIGITAL_AUDIO_INTERFACE_FORMAT              (0x07 << 1)





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#define SAMPLE_RATE_CONTROL                         (0x08 << 1)





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#define DIGITAL_INTERFACE_ACTIVATION                (0x09 << 1)





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#define RESET_REFGISTER                             (0x0F << 1)





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///////////////////////////////////////////////////////////////////////





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// Control Data Bits





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// LEFT_LINE_INPUT_CHANNEL_VOLUME_CONTROL(Address:0x00)





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// (bit7)LIM:   Left line input mute 0=Normal 1=Muted





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// (bit6)X:     Reserved





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// (bit5)X:     Reserved





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// (bit4)LIV4:





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// (bit3)LIV3:





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// (bit2)LIV2:





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// (bit1)LIV1:





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// (bit0)LIV0:  Left line input volume control(10111=0dB default)





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#define LIM_MUTE_DISABLED   (0<<7)





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#define LIV_VOLUME_DEFAULT  (0x17<<0)





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// ----------------------------------------------------------------------





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// RIGHT_LINE_INPUT_CHANNEL_VOLUME_CONTROL(Address:0x01)





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// (bit7)RIM:   Right line input mute 0=Normal 1=Muted





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// (bit6)X:     Reserved





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// (bit5)X:     Reserved





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// (bit4)RIV4:





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// (bit3)RIV3:





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// (bit2)RIV2:





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// (bit1)RIV1:





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// (bit0)RIV0:  Right line input volume control(10111=0dB default)





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#define RIM_MUTE_DISABLED   (0<<7)





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#define RIV_VOLUME_DEFAULT  (0x17<<0)





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// ----------------------------------------------------------------------





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// LEFT_CHANNEL_HEADPHONE_VOLUME_CONTROL(Address:0x02)





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// (bit7)LZC:   Left-channel Zero-cross detect 0=Off 1=On





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// (bit6)LHV6:





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// (bit5)LHV5:





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// (bit4)LHV4:





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// (bit3)LHV3:





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// (bit2)LHV2:





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// (bit1)LHV1:





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// (bit0)LHV0:  Left headphone volume control(1111001=0dB default,0110000=-73dB Mute)





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#define LZC_ZERO_CROSS_DETECT_ON    (1<<7)





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#define LHV_VOLUME_DEFAULT          100//(0x79<<0)





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// ----------------------------------------------------------------------





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// RIGHT_CHANNEL_HEADPHONE_VOLUME_CONTROL(Address:0x03)





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// (bit7)RZC:   Right-channel Zero-cross detect 0=Off 1=On





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// (bit6)RHV6:





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// (bit5)RHV5:





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// (bit4)RHV4:





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// (bit3)RHV3:





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// (bit2)RHV2:





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// (bit1)RHV1:





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// (bit0)RHV0:  Right headphone volume control(1111001=0dB default,0110000=-73dB Mute)





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#define RZC_ZERO_CROSS_DETECT_ON    (1<<7)





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#define RHV_VOLUME_DEFAULT          100//(0x79<<0)





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// ----------------------------------------------------------------------





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// ANALOG_AUDIO_PATH_CONTROL(Address:0x04)





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// (bit7)STA1:   





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// (bit6)STA0:





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// (bit5)STE:   (See "TLV320AIC23B DATA MANUAL" pp.3-3)





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// (bit4)DAC:   DAC select              0=DAC off   1=DAC on





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// (bit3)BYP:   Bypass                  0=Disabled  1=Enabled





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// (bit2)INSEL: Input select for ADC    0=Line,     1=Microphone  





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// (bit1)MICM:  Microphone mute         0=Normal,   1=Muted





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// (bit0)MICB:  Microphone boost        0=dB,       1=20dB





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// ----------------------------------------------------------------------





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// DIGITAL_AUDIO_PATH_CONTROL(Address:0x05)





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// (bit7)X:         Reserved   





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// (bit6)X:         Reserved





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// (bit5)X:         Reserved





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// (bit4)X:         Reserved





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// (bit3)DACM:      DAC soft mute           0=Disabled  1=Enabled





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// (bit2)DEEMP1:    





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// (bit1)DEEMP0:    De-enphasis control     0=Normal,   1=Muted





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// (bit0)ADCHP:     ADC high-pass filter    0=dB,       1=20dB





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#define DAC_MUTE_DISABLED       (0<<3)





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#define DE_EMPHASIS_DISABLED    (0x0 << 0)





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#define DE_EMPHASIS_32_KHZ      (0x1 << 0)





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#define DE_EMPHASIS_44_1_KHZ    (0x2 << 0)





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#define DE_EMPHASIS_48_KHZ      (0x3 << 0)





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// ----------------------------------------------------------------------





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// POWER_DOWN_CONTROL(Address:0x06)





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// (bit7)OFF:   Device power        0=On,   1=Off  





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// (bit6)CLK:   Clock               0=On,   1=Off





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// (bit5)OSC:   Oscillator          0=On,   1=Off





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// (bit4)OUT:   Outputs             0=On,   1=Off





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// (bit3)DAC:   DAC                 0=On,   1=Off





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// (bit2)ADC:   ADC                 0=On,   1=Off





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// (bit1)MIC:   Microphone input    0=On,   1=Off





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// (bit0)LINE:  Line input          0=On,   1=Off





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#define DEVICE_POWER_ON     (0<<7)





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#define CLOCK_ON            (0<<6)





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#define OSCILLATOR_ON       (0<<5)





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#define OUTPUTS_ON          (0<<4)





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#define DAC_ON              (0<<3)





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#define ADC_ON              (0<<2)





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#define MICROPHONE_INPUT_ON (0<<1)





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#define LINE_INPUT_ON       (0<<0)





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// ----------------------------------------------------------------------





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// DIGITAL_AUDUIO_INTERFACE_FORMAT(Address:0x07)





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// (bit7)X:         Reserved





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// (bit6)MS:        Master/Slave mode       0=Slave,    1=Master





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// (bit5)LRSWAP:    DAC left/right swap     0=Disabled, 1=Enabled





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// (bit4)LRP:       0=R-ch ON,LRCLKIN high, 1=R-ch ON,LRCLKIN low





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// (bit3)IWL1:





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// (bit2)IWL0:      Input bit length        00=16bit,   01=20bit,   10=24bit,   11=32bit





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// (bit1)FOR1:





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// (bit0)FOR0:      Data format             11=DSP,     10=I2S,     01=MSB first left algn.,   00=MSB right algn.





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#define MASTER_MODE                 (1<<6)





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#define INPUT_DATA_16_BIT_LENGTH    (0x00<<2)





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#define INPUT_DATA_20_BIT_LENGTH    (0x01<<2)





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#define INPUT_DATA_24_BIT_LENGTH    (0x02<<2)





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#define INPUT_DATA_32_BIT_LENGTH    (0x03<<2)





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#define DSP_FORMAT                  (0x03<<0)





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#define I2S_FORMAT                  (0x02<<0)





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#define MSB_FIRST_LEFT_ALIGN        (0x01<<0)





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#define MSB_FIRST_RIGHT_ALIGN       (0x00<<0)





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// ----------------------------------------------------------------------





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// SAMPLE_RATE_CONTROL(Address:0x08)





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// (bit7)CLKOUT:    Clock output divider    0=MCLK, 1=MCLK/2





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// (bit6)CLKIN:     Clock input divider     0=MCLK, 1=MCLK/2





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// (bit5)SR3:





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// (bit4)SR2:





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// (bit3)SR1:





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// (bit2)SR0:       (See "TLV320AIC23B DATA MANUAL" section 3.3.2.1 and 3.3.2.2)





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// (bit1)BOSR:





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// (bit0)USB/Normal:    Clock mode select   0=Normal,   1=USB





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#define SR_USB_44_1_KHZ_MODE         (0x08<<2)





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#define BOSR_USB_44_1_KHZ_MODE       (0x01<<1)





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#define USE_USB_CLOCK_44_1_KHZ_MODE  (0x01<<0)





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// ----------------------------------------------------------------------





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// DIGITAL_INTERFACE_ACTIVATION(Address:0x09)





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// (bit7)RES:





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// (bit6)RES:





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// (bit5)X:         Reserved





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// (bit4)X:         Reserved





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// (bit3)X:         Reserved





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// (bit2)X:         Reserved





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// (bit1)X:         Reserved





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// (bit0)ACT:       Activate interface      0=Inactive, 1=Active





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#define DIGITAL_INTERFACE_ACTIVE   (0x01<<0)





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// ----------------------------------------------------------------------





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// RESET_REGISTER(Address:0x0F)





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// (bit7)RES:





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// (bit6)RES:





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// (bit5)RES:





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// (bit4)RES:





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// (bit3)RES:





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// (bit2)RES:





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// (bit1)RES:





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// (bit0)RES:       Write 00000000 to this register triggers reset





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#define RESET  (0x00<<0)