xeye_ atsu
LINKED LIST TEST on mbed
I2S_Example/system_LPC17xx.c@0:e8bfffbb3ab6, 2011-02-26 (annotated)
- Committer:
- lynxeyed_atsu
- Date:
- Sat Feb 26 03:55:12 2011 +0000
- Revision:
- 0:e8bfffbb3ab6
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 1 | /**************************************************************************//** |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 2 | * @file system_LPC17xx.c |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 3 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 4 | * for the NXP LPC17xx Device Series |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 5 | * @version V1.03 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 6 | * @date 07. October 2009 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 7 | * |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 8 | * @note |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 9 | * Copyright (C) 2009 ARM Limited. All rights reserved. |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 10 | * |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 11 | * @par |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 12 | * ARM Limited (ARM) is supplying this software for use with Cortex-M |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 13 | * processor based microcontrollers. This file can be freely distributed |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 14 | * within development tools that are supporting such ARM based processors. |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 15 | * |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 16 | * @par |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 17 | * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 18 | * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 20 | * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 21 | * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 22 | * |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 23 | ******************************************************************************/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 24 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 25 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 26 | #include <stdint.h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 27 | #include "LPC17xx.h" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 28 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 29 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 30 | /** @addtogroup LPC17xx_System |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 31 | * @{ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 32 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 33 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 34 | /* |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 35 | //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 36 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 37 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 38 | /*--------------------- Clock Configuration ---------------------------------- |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 39 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 40 | // <e> Clock Configuration |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 41 | // <h> System Controls and Status Register (SCS) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 42 | // <o1.4> OSCRANGE: Main Oscillator Range Select |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 43 | // <0=> 1 MHz to 20 MHz |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 44 | // <1=> 15 MHz to 24 MHz |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 45 | // <e1.5> OSCEN: Main Oscillator Enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 46 | // </e> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 47 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 48 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 49 | // <h> Clock Source Select Register (CLKSRCSEL) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 50 | // <o2.0..1> CLKSRC: PLL Clock Source Selection |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 51 | // <0=> Internal RC oscillator |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 52 | // <1=> Main oscillator |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 53 | // <2=> RTC oscillator |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 54 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 55 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 56 | // <e3> PLL0 Configuration (Main PLL) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 57 | // <h> PLL0 Configuration Register (PLL0CFG) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 58 | // <i> F_cco0 = (2 * M * F_in) / N |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 59 | // <i> F_in must be in the range of 32 kHz to 50 MHz |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 60 | // <i> F_cco0 must be in the range of 275 MHz to 550 MHz |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 61 | // <o4.0..14> MSEL: PLL Multiplier Selection |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 62 | // <6-32768><#-1> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 63 | // <i> M Value |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 64 | // <o4.16..23> NSEL: PLL Divider Selection |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 65 | // <1-256><#-1> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 66 | // <i> N Value |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 67 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 68 | // </e> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 69 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 70 | // <e5> PLL1 Configuration (USB PLL) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 71 | // <h> PLL1 Configuration Register (PLL1CFG) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 72 | // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 73 | // <i> F_cco1 = F_osc * M * 2 * P |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 74 | // <i> F_cco1 must be in the range of 156 MHz to 320 MHz |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 75 | // <o6.0..4> MSEL: PLL Multiplier Selection |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 76 | // <1-32><#-1> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 77 | // <i> M Value (for USB maximum value is 4) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 78 | // <o6.5..6> PSEL: PLL Divider Selection |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 79 | // <0=> 1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 80 | // <1=> 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 81 | // <2=> 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 82 | // <3=> 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 83 | // <i> P Value |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 84 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 85 | // </e> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 86 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 87 | // <h> CPU Clock Configuration Register (CCLKCFG) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 88 | // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 89 | // <3-256><#-1> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 90 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 91 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 92 | // <h> USB Clock Configuration Register (USBCLKCFG) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 93 | // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 94 | // <0-15> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 95 | // <i> Divide is USBSEL + 1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 96 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 97 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 98 | // <h> Peripheral Clock Selection Register 0 (PCLKSEL0) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 99 | // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 100 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 101 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 102 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 103 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 104 | // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 105 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 106 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 107 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 108 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 109 | // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 110 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 111 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 112 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 113 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 114 | // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 115 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 116 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 117 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 118 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 119 | // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 120 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 121 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 122 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 123 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 124 | // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 125 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 126 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 127 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 128 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 129 | // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 130 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 131 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 132 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 133 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 134 | // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 135 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 136 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 137 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 138 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 139 | // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 140 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 141 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 142 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 143 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 144 | // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 145 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 146 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 147 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 148 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 149 | // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 150 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 151 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 152 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 153 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 154 | // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 155 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 156 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 157 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 158 | // <3=> Pclk = Hclk / 6 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 159 | // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 160 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 161 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 162 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 163 | // <3=> Pclk = Hclk / 6 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 164 | // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 165 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 166 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 167 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 168 | // <3=> Pclk = Hclk / 6 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 169 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 170 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 171 | // <h> Peripheral Clock Selection Register 1 (PCLKSEL1) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 172 | // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 173 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 174 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 175 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 176 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 177 | // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 178 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 179 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 180 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 181 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 182 | // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 183 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 184 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 185 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 186 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 187 | // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 188 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 189 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 190 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 191 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 192 | // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 193 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 194 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 195 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 196 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 197 | // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 198 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 199 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 200 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 201 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 202 | // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 203 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 204 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 205 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 206 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 207 | // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 208 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 209 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 210 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 211 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 212 | // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 213 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 214 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 215 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 216 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 217 | // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 218 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 219 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 220 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 221 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 222 | // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 223 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 224 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 225 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 226 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 227 | // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 228 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 229 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 230 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 231 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 232 | // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 233 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 234 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 235 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 236 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 237 | // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 238 | // <0=> Pclk = Cclk / 4 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 239 | // <1=> Pclk = Cclk |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 240 | // <2=> Pclk = Cclk / 2 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 241 | // <3=> Pclk = Hclk / 8 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 242 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 243 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 244 | // <h> Power Control for Peripherals Register (PCONP) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 245 | // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 246 | // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 247 | // <o11.3> PCUART0: UART 0 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 248 | // <o11.4> PCUART1: UART 1 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 249 | // <o11.6> PCPWM1: PWM 1 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 250 | // <o11.7> PCI2C0: I2C interface 0 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 251 | // <o11.8> PCSPI: SPI interface power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 252 | // <o11.9> PCRTC: RTC power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 253 | // <o11.10> PCSSP1: SSP interface 1 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 254 | // <o11.12> PCAD: A/D converter power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 255 | // <o11.13> PCCAN1: CAN controller 1 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 256 | // <o11.14> PCCAN2: CAN controller 2 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 257 | // <o11.15> PCGPIO: GPIOs power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 258 | // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 259 | // <o11.17> PCMC: Motor control PWM power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 260 | // <o11.18> PCQEI: Quadrature encoder interface power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 261 | // <o11.19> PCI2C1: I2C interface 1 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 262 | // <o11.21> PCSSP0: SSP interface 0 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 263 | // <o11.22> PCTIM2: Timer 2 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 264 | // <o11.23> PCTIM3: Timer 3 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 265 | // <o11.24> PCUART2: UART 2 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 266 | // <o11.25> PCUART3: UART 3 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 267 | // <o11.26> PCI2C2: I2C interface 2 power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 268 | // <o11.27> PCI2S: I2S interface power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 269 | // <o11.29> PCGPDMA: GP DMA function power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 270 | // <o11.30> PCENET: Ethernet block power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 271 | // <o11.31> PCUSB: USB interface power/clock enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 272 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 273 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 274 | // <h> Clock Output Configuration Register (CLKOUTCFG) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 275 | // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 276 | // <0=> CPU clock |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 277 | // <1=> Main oscillator |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 278 | // <2=> Internal RC oscillator |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 279 | // <3=> USB clock |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 280 | // <4=> RTC oscillator |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 281 | // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 282 | // <1-16><#-1> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 283 | // <o12.8> CLKOUT_EN: CLKOUT enable control |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 284 | // </h> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 285 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 286 | // </e> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 287 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 288 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 289 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 290 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 291 | /** @addtogroup LPC17xx_System_Defines LPC17xx System Defines |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 292 | @{ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 293 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 294 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 295 | #define CLOCK_SETUP 1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 296 | #define SCS_Val 0x00000020 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 297 | #define CLKSRCSEL_Val 0x00000001 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 298 | #define PLL0_SETUP 1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 299 | #define PLL0CFG_Val 0x00050063 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 300 | #define PLL1_SETUP 1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 301 | #define PLL1CFG_Val 0x00000023 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 302 | #define CCLKCFG_Val 0x00000003 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 303 | #define USBCLKCFG_Val 0x00000000 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 304 | #define PCLKSEL0_Val 0x00000000 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 305 | #define PCLKSEL1_Val 0x00000000 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 306 | #define PCONP_Val 0x042887DE |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 307 | #define CLKOUTCFG_Val 0x00000000 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 308 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 309 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 310 | /*--------------------- Flash Accelerator Configuration ---------------------- |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 311 | // |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 312 | // <e> Flash Accelerator Configuration |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 313 | // <o1.0..11> Reserved |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 314 | // <o1.12..15> FLASHTIM: Flash Access Time |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 315 | // <0=> 1 CPU clock (for CPU clock up to 20 MHz) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 316 | // <1=> 2 CPU clocks (for CPU clock up to 40 MHz) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 317 | // <2=> 3 CPU clocks (for CPU clock up to 60 MHz) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 318 | // <3=> 4 CPU clocks (for CPU clock up to 80 MHz) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 319 | // <4=> 5 CPU clocks (for CPU clock up to 100 MHz) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 320 | // <5=> 6 CPU clocks (for any CPU clock) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 321 | // </e> |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 322 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 323 | #define FLASH_SETUP 1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 324 | #define FLASHCFG_Val 0x0000303A |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 325 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 326 | /* |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 327 | //-------- <<< end of configuration section >>> ------------------------------ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 328 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 329 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 330 | /*---------------------------------------------------------------------------- |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 331 | Check the register settings |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 332 | *----------------------------------------------------------------------------*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 333 | #define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 334 | #define CHECK_RSVD(val, mask) (val & mask) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 335 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 336 | /* Clock Configuration -------------------------------------------------------*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 337 | #if (CHECK_RSVD((SCS_Val), ~0x00000030)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 338 | #error "SCS: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 339 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 340 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 341 | #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 342 | #error "CLKSRCSEL: Value out of range!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 343 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 344 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 345 | #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 346 | #error "PLL0CFG: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 347 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 348 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 349 | #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 350 | #error "PLL1CFG: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 351 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 352 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 353 | #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2))) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 354 | #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 355 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 356 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 357 | #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 358 | #error "USBCLKCFG: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 359 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 360 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 361 | #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 362 | #error "PCLKSEL0: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 363 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 364 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 365 | #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 366 | #error "PCLKSEL1: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 367 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 368 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 369 | #if (CHECK_RSVD((PCONP_Val), 0x10100821)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 370 | #error "PCONP: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 371 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 372 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 373 | #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 374 | #error "CLKOUTCFG: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 375 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 376 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 377 | /* Flash Accelerator Configuration -------------------------------------------*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 378 | #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F)) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 379 | #error "FLASHCFG: Invalid values of reserved bits!" |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 380 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 381 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 382 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 383 | /*---------------------------------------------------------------------------- |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 384 | DEFINES |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 385 | *----------------------------------------------------------------------------*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 386 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 387 | /*---------------------------------------------------------------------------- |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 388 | Define clocks |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 389 | *----------------------------------------------------------------------------*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 390 | #define XTAL (12000000UL) /* Oscillator frequency */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 391 | #define OSC_CLK ( XTAL) /* Main oscillator frequency */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 392 | #define RTC_CLK ( 32768UL) /* RTC oscillator frequency */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 393 | #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 394 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 395 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 396 | /* F_cco0 = (2 * M * F_in) / N */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 397 | #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 398 | #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 399 | #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 400 | #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 401 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 402 | /* Determine core clock frequency according to settings */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 403 | #if (PLL0_SETUP) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 404 | #if ((CLKSRCSEL_Val & 0x03) == 1) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 405 | #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 406 | #elif ((CLKSRCSEL_Val & 0x03) == 2) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 407 | #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 408 | #else |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 409 | #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 410 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 411 | #else |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 412 | #if ((CLKSRCSEL_Val & 0x03) == 1) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 413 | #define __CORE_CLK (OSC_CLK / __CCLK_DIV) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 414 | #elif ((CLKSRCSEL_Val & 0x03) == 2) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 415 | #define __CORE_CLK (RTC_CLK / __CCLK_DIV) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 416 | #else |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 417 | #define __CORE_CLK (IRC_OSC / __CCLK_DIV) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 418 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 419 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 420 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 421 | /** |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 422 | * @} |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 423 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 424 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 425 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 426 | /** @addtogroup LPC17xx_System_Public_Variables LPC17xx System Public Variables |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 427 | @{ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 428 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 429 | /*---------------------------------------------------------------------------- |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 430 | Clock Variable definitions |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 431 | *----------------------------------------------------------------------------*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 432 | //uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 433 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 434 | /** |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 435 | * @} |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 436 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 437 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 438 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 439 | /** @addtogroup LPC17xx_System_Public_Functions LPC17xx System Public Functions |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 440 | @{ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 441 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 442 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 443 | /*---------------------------------------------------------------------------- |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 444 | Clock functions |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 445 | *----------------------------------------------------------------------------*/ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 446 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 447 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 448 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 449 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 450 | /** |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 451 | * Initialize the system |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 452 | * |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 453 | * @param none |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 454 | * @return none |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 455 | * |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 456 | * @brief Setup the microcontroller system. |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 457 | * Initialize the System. |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 458 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 459 | /* |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 460 | void SystemInit (void) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 461 | { |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 462 | #if (CLOCK_SETUP) // Clock Setup |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 463 | LPC_SC->SCS = SCS_Val; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 464 | if (LPC_SC->SCS & (1 << 5)) { // If Main Oscillator is enabled |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 465 | while ((LPC_SC->SCS & (1<<6)) == 0);// Wait for Oscillator to be ready |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 466 | } |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 467 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 468 | LPC_SC->CCLKCFG = CCLKCFG_Val; // Setup Clock Divider |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 469 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 470 | LPC_SC->PCLKSEL0 = PCLKSEL0_Val; // Peripheral Clock Selection |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 471 | LPC_SC->PCLKSEL1 = PCLKSEL1_Val; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 472 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 473 | #if (PLL0_SETUP) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 474 | LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; // Select Clock Source for PLL0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 475 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 476 | LPC_SC->PLL0CFG = PLL0CFG_Val; // configure PLL0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 477 | LPC_SC->PLL0FEED = 0xAA; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 478 | LPC_SC->PLL0FEED = 0x55; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 479 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 480 | LPC_SC->PLL0CON = 0x01; // PLL0 Enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 481 | LPC_SC->PLL0FEED = 0xAA; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 482 | LPC_SC->PLL0FEED = 0x55; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 483 | while (!(LPC_SC->PLL0STAT & (1<<26)));// Wait for PLOCK0 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 484 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 485 | LPC_SC->PLL0CON = 0x03; // PLL0 Enable & Connect |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 486 | LPC_SC->PLL0FEED = 0xAA; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 487 | LPC_SC->PLL0FEED = 0x55; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 488 | while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));//Wait for PLLC0_STAT & PLLE0_STAT |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 489 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 490 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 491 | #if (PLL1_SETUP) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 492 | LPC_SC->PLL1CFG = PLL1CFG_Val; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 493 | LPC_SC->PLL1FEED = 0xAA; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 494 | LPC_SC->PLL1FEED = 0x55; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 495 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 496 | LPC_SC->PLL1CON = 0x01; // PLL1 Enable |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 497 | LPC_SC->PLL1FEED = 0xAA; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 498 | LPC_SC->PLL1FEED = 0x55; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 499 | while (!(LPC_SC->PLL1STAT & (1<<10)));// Wait for PLOCK1 |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 500 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 501 | LPC_SC->PLL1CON = 0x03; // PLL1 Enable & Connect |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 502 | LPC_SC->PLL1FEED = 0xAA; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 503 | LPC_SC->PLL1FEED = 0x55; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 504 | while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));// Wait for PLLC1_STAT & PLLE1_STAT |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 505 | #else |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 506 | LPC_SC->USBCLKCFG = USBCLKCFG_Val; // Setup USB Clock Divider |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 507 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 508 | LPC_SC->PCONP = PCONP_Val; // Power Control for Peripherals |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 509 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 510 | LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; // Clock Output Configuration |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 511 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 512 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 513 | #if (FLASH_SETUP == 1) // Flash Accelerator Setup |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 514 | LPC_SC->FLASHCFG = FLASHCFG_Val; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 515 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 516 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 517 | // Set Vector table offset value |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 518 | #if (__RAM_MODE__==1) |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 519 | SCB->VTOR = 0x10000000 & 0x3FFFFF80; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 520 | #else |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 521 | SCB->VTOR = 0x00000000 & 0x3FFFFF80; |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 522 | #endif |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 523 | } |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 524 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 525 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 526 | /** |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 527 | * @} |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 528 | */ |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 529 | |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 530 | /** |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 531 | * @} |
| lynxeyed_atsu | 0:e8bfffbb3ab6 | 532 | */ |