DMA_LLI_TEST - LINKED LIST TEST on mbed

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xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

I2S_Example/lpc17xx_i2s.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:: lynxeyed_atsu
Date:: Sat Feb 26 03:55:12 2011 +0000
Revision:: 0:e8bfffbb3ab6

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:e8bfffbb3ab6	1	/*********************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	2	* @file lpc17xx_i2s.h
lynxeyed_atsu	0:e8bfffbb3ab6	3	* @brief Contains all macro definitions and function prototypes
lynxeyed_atsu	0:e8bfffbb3ab6	4	* support for I2S firmware library on LPC17xx
lynxeyed_atsu	0:e8bfffbb3ab6	5	* @version 3.0
lynxeyed_atsu	0:e8bfffbb3ab6	6	* @date 18. June. 2010
lynxeyed_atsu	0:e8bfffbb3ab6	7	* @author NXP MCU SW Application Team
lynxeyed_atsu	0:e8bfffbb3ab6	8	**************************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	9	* Software that is described herein is for illustrative purposes only
lynxeyed_atsu	0:e8bfffbb3ab6	10	* which provides customers with programming information regarding the
lynxeyed_atsu	0:e8bfffbb3ab6	11	* products. This software is supplied "AS IS" without any warranties.
lynxeyed_atsu	0:e8bfffbb3ab6	12	* NXP Semiconductors assumes no responsibility or liability for the
lynxeyed_atsu	0:e8bfffbb3ab6	13	* use of the software, conveys no license or title under any patent,
lynxeyed_atsu	0:e8bfffbb3ab6	14	* copyright, or mask work right to the product. NXP Semiconductors
lynxeyed_atsu	0:e8bfffbb3ab6	15	* reserves the right to make changes in the software without
lynxeyed_atsu	0:e8bfffbb3ab6	16	* notification. NXP Semiconductors also make no representation or
lynxeyed_atsu	0:e8bfffbb3ab6	17	* warranty that such application will be suitable for the specified
lynxeyed_atsu	0:e8bfffbb3ab6	18	* use without further testing or modification.
lynxeyed_atsu	0:e8bfffbb3ab6	19	**************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	20
lynxeyed_atsu	0:e8bfffbb3ab6	21	/* Peripheral group ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	22	/** @defgroup I2S I2S
lynxeyed_atsu	0:e8bfffbb3ab6	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
lynxeyed_atsu	0:e8bfffbb3ab6	24	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	25	*/
lynxeyed_atsu	0:e8bfffbb3ab6	26
lynxeyed_atsu	0:e8bfffbb3ab6	27	#ifndef LPC17XX_I2S_H_
lynxeyed_atsu	0:e8bfffbb3ab6	28	#define LPC17XX_I2S_H_
lynxeyed_atsu	0:e8bfffbb3ab6	29
lynxeyed_atsu	0:e8bfffbb3ab6	30	/* Includes ------------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	31	#include "LPC17xx.h"
lynxeyed_atsu	0:e8bfffbb3ab6	32	#include "lpc_types.h"
lynxeyed_atsu	0:e8bfffbb3ab6	33
lynxeyed_atsu	0:e8bfffbb3ab6	34
lynxeyed_atsu	0:e8bfffbb3ab6	35	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	36	extern "C"
lynxeyed_atsu	0:e8bfffbb3ab6	37	{
lynxeyed_atsu	0:e8bfffbb3ab6	38	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	39
lynxeyed_atsu	0:e8bfffbb3ab6	40	/* Public Macros -------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	41	/** @defgroup I2S_Public_Macros I2S Public Macros
lynxeyed_atsu	0:e8bfffbb3ab6	42	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	43	*/
lynxeyed_atsu	0:e8bfffbb3ab6	44
lynxeyed_atsu	0:e8bfffbb3ab6	45	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	46	* I2S configuration parameter defines
lynxeyed_atsu	0:e8bfffbb3ab6	47	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	48	/** I2S Wordwidth bit */
lynxeyed_atsu	0:e8bfffbb3ab6	49	#define I2S_WORDWIDTH_8 ((uint32_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	50	#define I2S_WORDWIDTH_16 ((uint32_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	51	#define I2S_WORDWIDTH_32 ((uint32_t)(3))
lynxeyed_atsu	0:e8bfffbb3ab6	52	/** I2S Channel bit */
lynxeyed_atsu	0:e8bfffbb3ab6	53	#define I2S_STEREO ((uint32_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	54	#define I2S_MONO ((uint32_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	55	/** I2S Master/Slave mode bit */
lynxeyed_atsu	0:e8bfffbb3ab6	56	#define I2S_MASTER_MODE ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	57	#define I2S_SLAVE_MODE ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	58	/** I2S Stop bit */
lynxeyed_atsu	0:e8bfffbb3ab6	59	#define I2S_STOP_ENABLE ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	60	#define I2S_STOP_DISABLE ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	61	/** I2S Reset bit */
lynxeyed_atsu	0:e8bfffbb3ab6	62	#define I2S_RESET_ENABLE ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	63	#define I2S_RESET_DISABLE ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	64	/** I2S Mute bit */
lynxeyed_atsu	0:e8bfffbb3ab6	65	#define I2S_MUTE_ENABLE ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	66	#define I2S_MUTE_DISABLE ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	67	/** I2S Transmit/Receive bit */
lynxeyed_atsu	0:e8bfffbb3ab6	68	#define I2S_TX_MODE ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	69	#define I2S_RX_MODE ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	70	/** I2S Clock Select bit */
lynxeyed_atsu	0:e8bfffbb3ab6	71	#define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	72	#define I2S_CLKSEL_MCLK ((uint8_t)(2))
lynxeyed_atsu	0:e8bfffbb3ab6	73	/** I2S 4-pin Mode bit */
lynxeyed_atsu	0:e8bfffbb3ab6	74	#define I2S_4PIN_ENABLE ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	75	#define I2S_4PIN_DISABLE ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	76	/** I2S MCLK Enable bit */
lynxeyed_atsu	0:e8bfffbb3ab6	77	#define I2S_MCLK_ENABLE ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	78	#define I2S_MCLK_DISABLE ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	79	/** I2S select DMA bit */
lynxeyed_atsu	0:e8bfffbb3ab6	80	#define I2S_DMA_1 ((uint8_t)(0))
lynxeyed_atsu	0:e8bfffbb3ab6	81	#define I2S_DMA_2 ((uint8_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	82
lynxeyed_atsu	0:e8bfffbb3ab6	83	/**
lynxeyed_atsu	0:e8bfffbb3ab6	84	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	85	*/
lynxeyed_atsu	0:e8bfffbb3ab6	86
lynxeyed_atsu	0:e8bfffbb3ab6	87	/* Private Macros ------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	88	/** @defgroup I2S_Private_Macros I2S Private Macros
lynxeyed_atsu	0:e8bfffbb3ab6	89	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	90	*/
lynxeyed_atsu	0:e8bfffbb3ab6	91
lynxeyed_atsu	0:e8bfffbb3ab6	92	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	93	* Macro defines for DAO-Digital Audio Output register
lynxeyed_atsu	0:e8bfffbb3ab6	94	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	95	/** I2S wordwide - the number of bytes in data*/
lynxeyed_atsu	0:e8bfffbb3ab6	96	#define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
lynxeyed_atsu	0:e8bfffbb3ab6	97	#define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
lynxeyed_atsu	0:e8bfffbb3ab6	98	#define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
lynxeyed_atsu	0:e8bfffbb3ab6	99	/** I2S control mono or stereo format */
lynxeyed_atsu	0:e8bfffbb3ab6	100	#define I2S_DAO_MONO ((uint32_t)(1<<2))
lynxeyed_atsu	0:e8bfffbb3ab6	101	/** I2S control stop mode */
lynxeyed_atsu	0:e8bfffbb3ab6	102	#define I2S_DAO_STOP ((uint32_t)(1<<3))
lynxeyed_atsu	0:e8bfffbb3ab6	103	/** I2S control reset mode */
lynxeyed_atsu	0:e8bfffbb3ab6	104	#define I2S_DAO_RESET ((uint32_t)(1<<4))
lynxeyed_atsu	0:e8bfffbb3ab6	105	/** I2S control master/slave mode */
lynxeyed_atsu	0:e8bfffbb3ab6	106	#define I2S_DAO_SLAVE ((uint32_t)(1<<5))
lynxeyed_atsu	0:e8bfffbb3ab6	107	/** I2S word select half period minus one */
lynxeyed_atsu	0:e8bfffbb3ab6	108	#define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
lynxeyed_atsu	0:e8bfffbb3ab6	109	/** I2S control mute mode */
lynxeyed_atsu	0:e8bfffbb3ab6	110	#define I2S_DAO_MUTE ((uint32_t)(1<<15))
lynxeyed_atsu	0:e8bfffbb3ab6	111
lynxeyed_atsu	0:e8bfffbb3ab6	112	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	113	* Macro defines for DAI-Digital Audio Input register
lynxeyed_atsu	0:e8bfffbb3ab6	114	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	115	/** I2S wordwide - the number of bytes in data*/
lynxeyed_atsu	0:e8bfffbb3ab6	116	#define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0)) /** 8 bit */
lynxeyed_atsu	0:e8bfffbb3ab6	117	#define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1)) /** 16 bit */
lynxeyed_atsu	0:e8bfffbb3ab6	118	#define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3)) /** 32 bit */
lynxeyed_atsu	0:e8bfffbb3ab6	119	/** I2S control mono or stereo format */
lynxeyed_atsu	0:e8bfffbb3ab6	120	#define I2S_DAI_MONO ((uint32_t)(1<<2))
lynxeyed_atsu	0:e8bfffbb3ab6	121	/** I2S control stop mode */
lynxeyed_atsu	0:e8bfffbb3ab6	122	#define I2S_DAI_STOP ((uint32_t)(1<<3))
lynxeyed_atsu	0:e8bfffbb3ab6	123	/** I2S control reset mode */
lynxeyed_atsu	0:e8bfffbb3ab6	124	#define I2S_DAI_RESET ((uint32_t)(1<<4))
lynxeyed_atsu	0:e8bfffbb3ab6	125	/** I2S control master/slave mode */
lynxeyed_atsu	0:e8bfffbb3ab6	126	#define I2S_DAI_SLAVE ((uint32_t)(1<<5))
lynxeyed_atsu	0:e8bfffbb3ab6	127	/** I2S word select half period minus one (9 bits)*/
lynxeyed_atsu	0:e8bfffbb3ab6	128	#define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
lynxeyed_atsu	0:e8bfffbb3ab6	129	/** I2S control mute mode */
lynxeyed_atsu	0:e8bfffbb3ab6	130	#define I2S_DAI_MUTE ((uint32_t)(1<<15))
lynxeyed_atsu	0:e8bfffbb3ab6	131
lynxeyed_atsu	0:e8bfffbb3ab6	132	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	133	* Macro defines for STAT register (Status Feedback register)
lynxeyed_atsu	0:e8bfffbb3ab6	134	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	135	/** I2S Status Receive or Transmit Interrupt */
lynxeyed_atsu	0:e8bfffbb3ab6	136	#define I2S_STATE_IRQ ((uint32_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	137	/** I2S Status Receive or Transmit DMA1 */
lynxeyed_atsu	0:e8bfffbb3ab6	138	#define I2S_STATE_DMA1 ((uint32_t)(1<<1))
lynxeyed_atsu	0:e8bfffbb3ab6	139	/** I2S Status Receive or Transmit DMA2 */
lynxeyed_atsu	0:e8bfffbb3ab6	140	#define I2S_STATE_DMA2 ((uint32_t)(1<<2))
lynxeyed_atsu	0:e8bfffbb3ab6	141	/** I2S Status Current level of the Receive FIFO (5 bits)*/
lynxeyed_atsu	0:e8bfffbb3ab6	142	#define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	143	/** I2S Status Current level of the Transmit FIFO (5 bits)*/
lynxeyed_atsu	0:e8bfffbb3ab6	144	#define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
lynxeyed_atsu	0:e8bfffbb3ab6	145
lynxeyed_atsu	0:e8bfffbb3ab6	146	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	147	* Macro defines for DMA1 register (DMA1 Configuration register)
lynxeyed_atsu	0:e8bfffbb3ab6	148	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	149	/** I2S control DMA1 for I2S receive */
lynxeyed_atsu	0:e8bfffbb3ab6	150	#define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	151	/** I2S control DMA1 for I2S transmit */
lynxeyed_atsu	0:e8bfffbb3ab6	152	#define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
lynxeyed_atsu	0:e8bfffbb3ab6	153	/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
lynxeyed_atsu	0:e8bfffbb3ab6	154	#define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	155	/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
lynxeyed_atsu	0:e8bfffbb3ab6	156	#define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
lynxeyed_atsu	0:e8bfffbb3ab6	157
lynxeyed_atsu	0:e8bfffbb3ab6	158	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	159	* Macro defines for DMA2 register (DMA2 Configuration register)
lynxeyed_atsu	0:e8bfffbb3ab6	160	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	161	/** I2S control DMA2 for I2S receive */
lynxeyed_atsu	0:e8bfffbb3ab6	162	#define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	163	/** I2S control DMA1 for I2S transmit */
lynxeyed_atsu	0:e8bfffbb3ab6	164	#define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
lynxeyed_atsu	0:e8bfffbb3ab6	165	/** I2S set FIFO level that trigger a receive DMA request on DMA1 */
lynxeyed_atsu	0:e8bfffbb3ab6	166	#define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	167	/** I2S set FIFO level that trigger a transmit DMA request on DMA1 */
lynxeyed_atsu	0:e8bfffbb3ab6	168	#define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
lynxeyed_atsu	0:e8bfffbb3ab6	169
lynxeyed_atsu	0:e8bfffbb3ab6	170	/*******************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	171	* Macro defines for IRQ register (Interrupt Request Control register)
lynxeyed_atsu	0:e8bfffbb3ab6	172	**********************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	173	/** I2S control I2S receive interrupt */
lynxeyed_atsu	0:e8bfffbb3ab6	174	#define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
lynxeyed_atsu	0:e8bfffbb3ab6	175	/** I2S control I2S transmit interrupt */
lynxeyed_atsu	0:e8bfffbb3ab6	176	#define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
lynxeyed_atsu	0:e8bfffbb3ab6	177	/** I2S set the FIFO level on which to create an irq request */
lynxeyed_atsu	0:e8bfffbb3ab6	178	#define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	179	/** I2S set the FIFO level on which to create an irq request */
lynxeyed_atsu	0:e8bfffbb3ab6	180	#define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
lynxeyed_atsu	0:e8bfffbb3ab6	181
lynxeyed_atsu	0:e8bfffbb3ab6	182	/******************************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	183	* Macro defines for TXRATE/RXRATE register (Transmit/Receive Clock Rate register)
lynxeyed_atsu	0:e8bfffbb3ab6	184	*********************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	185	/** I2S Transmit MCLK rate denominator */
lynxeyed_atsu	0:e8bfffbb3ab6	186	#define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	187	/** I2S Transmit MCLK rate denominator */
lynxeyed_atsu	0:e8bfffbb3ab6	188	#define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	189	/** I2S Receive MCLK rate denominator */
lynxeyed_atsu	0:e8bfffbb3ab6	190	#define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
lynxeyed_atsu	0:e8bfffbb3ab6	191	/** I2S Receive MCLK rate denominator */
lynxeyed_atsu	0:e8bfffbb3ab6	192	#define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
lynxeyed_atsu	0:e8bfffbb3ab6	193
lynxeyed_atsu	0:e8bfffbb3ab6	194	/***********************************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	195	* Macro defines for TXBITRATE & RXBITRATE register (Transmit/Receive Bit Rate register)
lynxeyed_atsu	0:e8bfffbb3ab6	196	**************************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	197	#define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
lynxeyed_atsu	0:e8bfffbb3ab6	198	#define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
lynxeyed_atsu	0:e8bfffbb3ab6	199
lynxeyed_atsu	0:e8bfffbb3ab6	200	/********************************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	201	* Macro defines for TXMODE/RXMODE register (Transmit/Receive Mode Control register)
lynxeyed_atsu	0:e8bfffbb3ab6	202	************************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	203	/** I2S Transmit select clock source (2 bits)*/
lynxeyed_atsu	0:e8bfffbb3ab6	204	#define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	205	/** I2S Transmit control 4-pin mode */
lynxeyed_atsu	0:e8bfffbb3ab6	206	#define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
lynxeyed_atsu	0:e8bfffbb3ab6	207	/** I2S Transmit control the TX_MCLK output */
lynxeyed_atsu	0:e8bfffbb3ab6	208	#define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
lynxeyed_atsu	0:e8bfffbb3ab6	209	/** I2S Receive select clock source */
lynxeyed_atsu	0:e8bfffbb3ab6	210	#define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
lynxeyed_atsu	0:e8bfffbb3ab6	211	/** I2S Receive control 4-pin mode */
lynxeyed_atsu	0:e8bfffbb3ab6	212	#define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
lynxeyed_atsu	0:e8bfffbb3ab6	213	/** I2S Receive control the TX_MCLK output */
lynxeyed_atsu	0:e8bfffbb3ab6	214	#define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
lynxeyed_atsu	0:e8bfffbb3ab6	215
lynxeyed_atsu	0:e8bfffbb3ab6	216
lynxeyed_atsu	0:e8bfffbb3ab6	217	/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	218	/** Macro to determine if it is valid I2S peripheral */
lynxeyed_atsu	0:e8bfffbb3ab6	219	#define PARAM_I2Sx(n) (((uint32_t )n)==((uint32_t )LPC_I2S))
lynxeyed_atsu	0:e8bfffbb3ab6	220	/** Macro to check Data to send valid */
lynxeyed_atsu	0:e8bfffbb3ab6	221	#define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
lynxeyed_atsu	0:e8bfffbb3ab6	222	/* Macro check I2S word width type */
lynxeyed_atsu	0:e8bfffbb3ab6	223	#define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)\|\|(n==I2S_WORDWIDTH_16)\
lynxeyed_atsu	0:e8bfffbb3ab6	224	\|\|(n==I2S_WORDWIDTH_32))
lynxeyed_atsu	0:e8bfffbb3ab6	225	/* Macro check I2S channel type */
lynxeyed_atsu	0:e8bfffbb3ab6	226	#define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)\|\|(n==I2S_MONO))
lynxeyed_atsu	0:e8bfffbb3ab6	227	/* Macro check I2S master/slave mode */
lynxeyed_atsu	0:e8bfffbb3ab6	228	#define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)\|\|(n==I2S_SLAVE_MODE))
lynxeyed_atsu	0:e8bfffbb3ab6	229	/* Macro check I2S stop mode */
lynxeyed_atsu	0:e8bfffbb3ab6	230	#define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)\|\|(n==I2S_STOP_DISABLE))
lynxeyed_atsu	0:e8bfffbb3ab6	231	/* Macro check I2S reset mode */
lynxeyed_atsu	0:e8bfffbb3ab6	232	#define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)\|\|(n==I2S_RESET_DISABLE))
lynxeyed_atsu	0:e8bfffbb3ab6	233	/* Macro check I2S reset mode */
lynxeyed_atsu	0:e8bfffbb3ab6	234	#define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)\|\|(n==I2S_MUTE_DISABLE))
lynxeyed_atsu	0:e8bfffbb3ab6	235	/* Macro check I2S transmit/receive mode */
lynxeyed_atsu	0:e8bfffbb3ab6	236	#define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)\|\|(n==I2S_RX_MODE))
lynxeyed_atsu	0:e8bfffbb3ab6	237	/* Macro check I2S clock select mode */
lynxeyed_atsu	0:e8bfffbb3ab6	238	#define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)\|\|(n==I2S_CLKSEL_MCLK))
lynxeyed_atsu	0:e8bfffbb3ab6	239	/* Macro check I2S 4-pin mode */
lynxeyed_atsu	0:e8bfffbb3ab6	240	#define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)\|\|(n==I2S_4PIN_DISABLE))
lynxeyed_atsu	0:e8bfffbb3ab6	241	/* Macro check I2S MCLK mode */
lynxeyed_atsu	0:e8bfffbb3ab6	242	#define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)\|\|(n==I2S_MCLK_DISABLE))
lynxeyed_atsu	0:e8bfffbb3ab6	243	/* Macro check I2S DMA mode */
lynxeyed_atsu	0:e8bfffbb3ab6	244	#define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)\|\|(n==I2S_DMA_2))
lynxeyed_atsu	0:e8bfffbb3ab6	245	/* Macro check I2S DMA depth value */
lynxeyed_atsu	0:e8bfffbb3ab6	246	#define PARAM_I2S_DMA_DEPTH(n) ((n>=0)\|\|(n<=31))
lynxeyed_atsu	0:e8bfffbb3ab6	247	/* Macro check I2S irq level value */
lynxeyed_atsu	0:e8bfffbb3ab6	248	#define PARAM_I2S_IRQ_LEVEL(n) ((n>=0)\|\|(n<=31))
lynxeyed_atsu	0:e8bfffbb3ab6	249	/* Macro check I2S half-period value */
lynxeyed_atsu	0:e8bfffbb3ab6	250	#define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
lynxeyed_atsu	0:e8bfffbb3ab6	251	/* Macro check I2S bit-rate value */
lynxeyed_atsu	0:e8bfffbb3ab6	252	#define PARAM_I2S_BITRATE(n) ((n>=0)&&(n<=63))
lynxeyed_atsu	0:e8bfffbb3ab6	253	/**
lynxeyed_atsu	0:e8bfffbb3ab6	254	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	255	*/
lynxeyed_atsu	0:e8bfffbb3ab6	256
lynxeyed_atsu	0:e8bfffbb3ab6	257
lynxeyed_atsu	0:e8bfffbb3ab6	258
lynxeyed_atsu	0:e8bfffbb3ab6	259	/* Public Types --------------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	260	/** @defgroup I2S_Public_Types I2S Public Types
lynxeyed_atsu	0:e8bfffbb3ab6	261	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	262	*/
lynxeyed_atsu	0:e8bfffbb3ab6	263
lynxeyed_atsu	0:e8bfffbb3ab6	264	/**
lynxeyed_atsu	0:e8bfffbb3ab6	265	* @brief I2S configuration structure definition
lynxeyed_atsu	0:e8bfffbb3ab6	266	*/
lynxeyed_atsu	0:e8bfffbb3ab6	267	typedef struct {
lynxeyed_atsu	0:e8bfffbb3ab6	268	uint8_t wordwidth; /** the number of bytes in data as follow:
lynxeyed_atsu	0:e8bfffbb3ab6	269	-I2S_WORDWIDTH_8: 8 bit data
lynxeyed_atsu	0:e8bfffbb3ab6	270	-I2S_WORDWIDTH_16: 16 bit data
lynxeyed_atsu	0:e8bfffbb3ab6	271	-I2S_WORDWIDTH_32: 32 bit data */
lynxeyed_atsu	0:e8bfffbb3ab6	272	uint8_t mono; /** Set mono/stereo mode, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	273	- I2S_STEREO: stereo mode
lynxeyed_atsu	0:e8bfffbb3ab6	274	- I2S_MONO: mono mode */
lynxeyed_atsu	0:e8bfffbb3ab6	275	uint8_t stop; /** Disables accesses on FIFOs, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	276	- I2S_STOP_ENABLE: enable stop mode
lynxeyed_atsu	0:e8bfffbb3ab6	277	- I2S_STOP_DISABLE: disable stop mode */
lynxeyed_atsu	0:e8bfffbb3ab6	278	uint8_t reset; /** Asynchronously reset tje transmit channel and FIFO, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	279	- I2S_RESET_ENABLE: enable reset mode
lynxeyed_atsu	0:e8bfffbb3ab6	280	- I2S_RESET_DISABLE: disable reset mode */
lynxeyed_atsu	0:e8bfffbb3ab6	281	uint8_t ws_sel; /** Set Master/Slave mode, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	282	- I2S_MASTER_MODE: I2S master mode
lynxeyed_atsu	0:e8bfffbb3ab6	283	- I2S_SLAVE_MODE: I2S slave mode */
lynxeyed_atsu	0:e8bfffbb3ab6	284	uint8_t mute; /** MUTE mode: when true, the transmit channel sends only zeroes, shoule be:
lynxeyed_atsu	0:e8bfffbb3ab6	285	- I2S_MUTE_ENABLE: enable mute mode
lynxeyed_atsu	0:e8bfffbb3ab6	286	- I2S_MUTE_DISABLE: disable mute mode */
lynxeyed_atsu	0:e8bfffbb3ab6	287	uint8_t Reserved0[2];
lynxeyed_atsu	0:e8bfffbb3ab6	288	} I2S_CFG_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	289
lynxeyed_atsu	0:e8bfffbb3ab6	290	/**
lynxeyed_atsu	0:e8bfffbb3ab6	291	* @brief I2S DMA configuration structure definition
lynxeyed_atsu	0:e8bfffbb3ab6	292	*/
lynxeyed_atsu	0:e8bfffbb3ab6	293	typedef struct {
lynxeyed_atsu	0:e8bfffbb3ab6	294	uint8_t DMAIndex; /** Select DMA1 or DMA2, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	295	- I2S_DMA_1: DMA1
lynxeyed_atsu	0:e8bfffbb3ab6	296	- I2S_DMA_2: DMA2 */
lynxeyed_atsu	0:e8bfffbb3ab6	297	uint8_t depth; /** FIFO level that triggers a DMA request */
lynxeyed_atsu	0:e8bfffbb3ab6	298	uint8_t Reserved0[2];
lynxeyed_atsu	0:e8bfffbb3ab6	299	}I2S_DMAConf_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	300
lynxeyed_atsu	0:e8bfffbb3ab6	301	/**
lynxeyed_atsu	0:e8bfffbb3ab6	302	* @brief I2S mode configuration structure definition
lynxeyed_atsu	0:e8bfffbb3ab6	303	*/
lynxeyed_atsu	0:e8bfffbb3ab6	304	typedef struct{
lynxeyed_atsu	0:e8bfffbb3ab6	305	uint8_t clksel; /** Clock source selection, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	306	- I2S_CLKSEL_FRDCLK: Select the fractional rate divider clock output
lynxeyed_atsu	0:e8bfffbb3ab6	307	- I2S_CLKSEL_MCLK: Select the MCLK signal as the clock source */
lynxeyed_atsu	0:e8bfffbb3ab6	308	uint8_t fpin; /** Select four pin mode, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	309	- I2S_4PIN_ENABLE: 4-pin enable
lynxeyed_atsu	0:e8bfffbb3ab6	310	- I2S_4PIN_DISABLE: 4-pin disable */
lynxeyed_atsu	0:e8bfffbb3ab6	311	uint8_t mcena; /** Select MCLK mode, should be:
lynxeyed_atsu	0:e8bfffbb3ab6	312	- I2S_MCLK_ENABLE: MCLK enable for output
lynxeyed_atsu	0:e8bfffbb3ab6	313	- I2S_MCLK_DISABLE: MCLK disable for output */
lynxeyed_atsu	0:e8bfffbb3ab6	314	uint8_t Reserved;
lynxeyed_atsu	0:e8bfffbb3ab6	315	}I2S_MODEConf_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	316
lynxeyed_atsu	0:e8bfffbb3ab6	317
lynxeyed_atsu	0:e8bfffbb3ab6	318	/**
lynxeyed_atsu	0:e8bfffbb3ab6	319	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	320	*/
lynxeyed_atsu	0:e8bfffbb3ab6	321
lynxeyed_atsu	0:e8bfffbb3ab6	322
lynxeyed_atsu	0:e8bfffbb3ab6	323	/* Public Functions ----------------------------------------------------------- */
lynxeyed_atsu	0:e8bfffbb3ab6	324	/** @defgroup I2S_Public_Functions I2S Public Functions
lynxeyed_atsu	0:e8bfffbb3ab6	325	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	326	*/
lynxeyed_atsu	0:e8bfffbb3ab6	327	/* I2S Init/DeInit functions ---------*/
lynxeyed_atsu	0:e8bfffbb3ab6	328	void I2S_Init(LPC_I2S_TypeDef *I2Sx);
lynxeyed_atsu	0:e8bfffbb3ab6	329	void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
lynxeyed_atsu	0:e8bfffbb3ab6	330
lynxeyed_atsu	0:e8bfffbb3ab6	331	/* I2S configuration functions --------*/
lynxeyed_atsu	0:e8bfffbb3ab6	332	void I2S_Config(LPC_I2S_TypeDef I2Sx, uint8_t TRMode, I2S_CFG_Type ConfigStruct);
lynxeyed_atsu	0:e8bfffbb3ab6	333	Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	334	void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	335	void I2S_ModeConfig(LPC_I2S_TypeDef I2Sx, I2S_MODEConf_Type ModeConfig, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	336	uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	337
lynxeyed_atsu	0:e8bfffbb3ab6	338	/* I2S operate functions -------------*/
lynxeyed_atsu	0:e8bfffbb3ab6	339	void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
lynxeyed_atsu	0:e8bfffbb3ab6	340	uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
lynxeyed_atsu	0:e8bfffbb3ab6	341	void I2S_Start(LPC_I2S_TypeDef *I2Sx);
lynxeyed_atsu	0:e8bfffbb3ab6	342	void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	343	void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	344	void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	345
lynxeyed_atsu	0:e8bfffbb3ab6	346	/* I2S DMA functions ----------------*/
lynxeyed_atsu	0:e8bfffbb3ab6	347	void I2S_DMAConfig(LPC_I2S_TypeDef I2Sx, I2S_DMAConf_Type DMAConfig, uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	348	void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
lynxeyed_atsu	0:e8bfffbb3ab6	349
lynxeyed_atsu	0:e8bfffbb3ab6	350	/* I2S IRQ functions ----------------*/
lynxeyed_atsu	0:e8bfffbb3ab6	351	void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
lynxeyed_atsu	0:e8bfffbb3ab6	352	void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
lynxeyed_atsu	0:e8bfffbb3ab6	353	FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	354	uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
lynxeyed_atsu	0:e8bfffbb3ab6	355
lynxeyed_atsu	0:e8bfffbb3ab6	356	/**
lynxeyed_atsu	0:e8bfffbb3ab6	357	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	358	*/
lynxeyed_atsu	0:e8bfffbb3ab6	359
lynxeyed_atsu	0:e8bfffbb3ab6	360
lynxeyed_atsu	0:e8bfffbb3ab6	361	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	362	}
lynxeyed_atsu	0:e8bfffbb3ab6	363	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	364
lynxeyed_atsu	0:e8bfffbb3ab6	365
lynxeyed_atsu	0:e8bfffbb3ab6	366	#endif /* LPC17XX_SSP_H_ */
lynxeyed_atsu	0:e8bfffbb3ab6	367
lynxeyed_atsu	0:e8bfffbb3ab6	368	/**
lynxeyed_atsu	0:e8bfffbb3ab6	369	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	370	*/
lynxeyed_atsu	0:e8bfffbb3ab6	371
lynxeyed_atsu	0:e8bfffbb3ab6	372	/* --------------------------------- End Of File ------------------------------ */

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Feb 2011
Imports:	12
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

I2S_Example/lpc17xx_i2s.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

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