DMA_LLI_TEST - LINKED LIST TEST on mbed

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xeye_ atsu / Mbed 2 deprecated DMA_LLI_TEST

LINKED LIST TEST on mbed

I2S_Example/core_cm3.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

Committer:: lynxeyed_atsu
Date:: Sat Feb 26 03:55:12 2011 +0000
Revision:: 0:e8bfffbb3ab6

Who changed what in which revision?

User	Revision	Line number	New contents of line
lynxeyed_atsu	0:e8bfffbb3ab6	1	/************************************************************************//
lynxeyed_atsu	0:e8bfffbb3ab6	2	* @file core_cm3.h
lynxeyed_atsu	0:e8bfffbb3ab6	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
lynxeyed_atsu	0:e8bfffbb3ab6	4	* @version V1.30
lynxeyed_atsu	0:e8bfffbb3ab6	5	* @date 30. October 2009
lynxeyed_atsu	0:e8bfffbb3ab6	6	*
lynxeyed_atsu	0:e8bfffbb3ab6	7	* @note
lynxeyed_atsu	0:e8bfffbb3ab6	8	* Copyright (C) 2009 ARM Limited. All rights reserved.
lynxeyed_atsu	0:e8bfffbb3ab6	9	*
lynxeyed_atsu	0:e8bfffbb3ab6	10	* @par
lynxeyed_atsu	0:e8bfffbb3ab6	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
lynxeyed_atsu	0:e8bfffbb3ab6	12	* processor based microcontrollers. This file can be freely distributed
lynxeyed_atsu	0:e8bfffbb3ab6	13	* within development tools that are supporting such ARM based processors.
lynxeyed_atsu	0:e8bfffbb3ab6	14	*
lynxeyed_atsu	0:e8bfffbb3ab6	15	* @par
lynxeyed_atsu	0:e8bfffbb3ab6	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
lynxeyed_atsu	0:e8bfffbb3ab6	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
lynxeyed_atsu	0:e8bfffbb3ab6	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
lynxeyed_atsu	0:e8bfffbb3ab6	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
lynxeyed_atsu	0:e8bfffbb3ab6	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
lynxeyed_atsu	0:e8bfffbb3ab6	21	*
lynxeyed_atsu	0:e8bfffbb3ab6	22	******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	23
lynxeyed_atsu	0:e8bfffbb3ab6	24	#ifndef __CM3_CORE_H__
lynxeyed_atsu	0:e8bfffbb3ab6	25	#define __CM3_CORE_H__
lynxeyed_atsu	0:e8bfffbb3ab6	26
lynxeyed_atsu	0:e8bfffbb3ab6	27	/** @addtogroup CMSIS
lynxeyed_atsu	0:e8bfffbb3ab6	28	* @{
lynxeyed_atsu	0:e8bfffbb3ab6	29	*/
lynxeyed_atsu	0:e8bfffbb3ab6	30
lynxeyed_atsu	0:e8bfffbb3ab6	31	/** @addtogroup CMSIS_CM3_core_LintCinfiguration CMSIS CM3 Core Lint Configuration
lynxeyed_atsu	0:e8bfffbb3ab6	32	*
lynxeyed_atsu	0:e8bfffbb3ab6	33	* List of Lint messages which will be suppressed and not shown:
lynxeyed_atsu	0:e8bfffbb3ab6	34	* - Error 10: \n
lynxeyed_atsu	0:e8bfffbb3ab6	35	* register uint32_t __regBasePri __asm("basepri"); \n
lynxeyed_atsu	0:e8bfffbb3ab6	36	* Error 10: Expecting ';'
lynxeyed_atsu	0:e8bfffbb3ab6	37	* .
lynxeyed_atsu	0:e8bfffbb3ab6	38	* - Error 530: \n
lynxeyed_atsu	0:e8bfffbb3ab6	39	* return(__regBasePri); \n
lynxeyed_atsu	0:e8bfffbb3ab6	40	* Warning 530: Symbol '__regBasePri' (line 264) not initialized
lynxeyed_atsu	0:e8bfffbb3ab6	41	* .
lynxeyed_atsu	0:e8bfffbb3ab6	42	* - Error 550: \n
lynxeyed_atsu	0:e8bfffbb3ab6	43	* __regBasePri = (basePri & 0x1ff); \n
lynxeyed_atsu	0:e8bfffbb3ab6	44	* Warning 550: Symbol '__regBasePri' (line 271) not accessed
lynxeyed_atsu	0:e8bfffbb3ab6	45	* .
lynxeyed_atsu	0:e8bfffbb3ab6	46	* - Error 754: \n
lynxeyed_atsu	0:e8bfffbb3ab6	47	* uint32_t RESERVED0[24]; \n
lynxeyed_atsu	0:e8bfffbb3ab6	48	* Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced
lynxeyed_atsu	0:e8bfffbb3ab6	49	* .
lynxeyed_atsu	0:e8bfffbb3ab6	50	* - Error 750: \n
lynxeyed_atsu	0:e8bfffbb3ab6	51	* #define __CM3_CORE_H__ \n
lynxeyed_atsu	0:e8bfffbb3ab6	52	* Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced
lynxeyed_atsu	0:e8bfffbb3ab6	53	* .
lynxeyed_atsu	0:e8bfffbb3ab6	54	* - Error 528: \n
lynxeyed_atsu	0:e8bfffbb3ab6	55	* static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
lynxeyed_atsu	0:e8bfffbb3ab6	56	* Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced
lynxeyed_atsu	0:e8bfffbb3ab6	57	* .
lynxeyed_atsu	0:e8bfffbb3ab6	58	* - Error 751: \n
lynxeyed_atsu	0:e8bfffbb3ab6	59	* } InterruptType_Type; \n
lynxeyed_atsu	0:e8bfffbb3ab6	60	* Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced
lynxeyed_atsu	0:e8bfffbb3ab6	61	* .
lynxeyed_atsu	0:e8bfffbb3ab6	62	* Note: To re-enable a Message, insert a space before 'lint' *
lynxeyed_atsu	0:e8bfffbb3ab6	63	*
lynxeyed_atsu	0:e8bfffbb3ab6	64	*/
lynxeyed_atsu	0:e8bfffbb3ab6	65
lynxeyed_atsu	0:e8bfffbb3ab6	66	/lint -save /
lynxeyed_atsu	0:e8bfffbb3ab6	67	/lint -e10 /
lynxeyed_atsu	0:e8bfffbb3ab6	68	/lint -e530 /
lynxeyed_atsu	0:e8bfffbb3ab6	69	/lint -e550 /
lynxeyed_atsu	0:e8bfffbb3ab6	70	/lint -e754 /
lynxeyed_atsu	0:e8bfffbb3ab6	71	/lint -e750 /
lynxeyed_atsu	0:e8bfffbb3ab6	72	/lint -e528 /
lynxeyed_atsu	0:e8bfffbb3ab6	73	/lint -e751 /
lynxeyed_atsu	0:e8bfffbb3ab6	74
lynxeyed_atsu	0:e8bfffbb3ab6	75
lynxeyed_atsu	0:e8bfffbb3ab6	76	/** @addtogroup CMSIS_CM3_core_definitions CMSIS CM3 Core Definitions
lynxeyed_atsu	0:e8bfffbb3ab6	77	This file defines all structures and symbols for CMSIS core:
lynxeyed_atsu	0:e8bfffbb3ab6	78	- CMSIS version number
lynxeyed_atsu	0:e8bfffbb3ab6	79	- Cortex-M core registers and bitfields
lynxeyed_atsu	0:e8bfffbb3ab6	80	- Cortex-M core peripheral base address
lynxeyed_atsu	0:e8bfffbb3ab6	81	@{
lynxeyed_atsu	0:e8bfffbb3ab6	82	*/
lynxeyed_atsu	0:e8bfffbb3ab6	83
lynxeyed_atsu	0:e8bfffbb3ab6	84	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	85	extern "C" {
lynxeyed_atsu	0:e8bfffbb3ab6	86	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	87
lynxeyed_atsu	0:e8bfffbb3ab6	88	#define __CM3_CMSIS_VERSION_MAIN (0x01) /!< [31:16] CMSIS HAL main version /
lynxeyed_atsu	0:e8bfffbb3ab6	89	#define __CM3_CMSIS_VERSION_SUB (0x30) /!< [15:0] CMSIS HAL sub version /
lynxeyed_atsu	0:e8bfffbb3ab6	90	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| __CM3_CMSIS_VERSION_SUB) /!< CMSIS HAL version number /
lynxeyed_atsu	0:e8bfffbb3ab6	91
lynxeyed_atsu	0:e8bfffbb3ab6	92	#define __CORTEX_M (0x03) /!< Cortex core /
lynxeyed_atsu	0:e8bfffbb3ab6	93
lynxeyed_atsu	0:e8bfffbb3ab6	94	#include <stdint.h> /* Include standard types */
lynxeyed_atsu	0:e8bfffbb3ab6	95
lynxeyed_atsu	0:e8bfffbb3ab6	96	#if defined (__ICCARM__)
lynxeyed_atsu	0:e8bfffbb3ab6	97	#include <intrinsics.h> /* IAR Intrinsics */
lynxeyed_atsu	0:e8bfffbb3ab6	98	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	99
lynxeyed_atsu	0:e8bfffbb3ab6	100
lynxeyed_atsu	0:e8bfffbb3ab6	101	#ifndef __NVIC_PRIO_BITS
lynxeyed_atsu	0:e8bfffbb3ab6	102	#define __NVIC_PRIO_BITS 4 /!< standard definition for NVIC Priority Bits /
lynxeyed_atsu	0:e8bfffbb3ab6	103	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	104
lynxeyed_atsu	0:e8bfffbb3ab6	105
lynxeyed_atsu	0:e8bfffbb3ab6	106
lynxeyed_atsu	0:e8bfffbb3ab6	107
lynxeyed_atsu	0:e8bfffbb3ab6	108	/**
lynxeyed_atsu	0:e8bfffbb3ab6	109	* IO definitions
lynxeyed_atsu	0:e8bfffbb3ab6	110	*
lynxeyed_atsu	0:e8bfffbb3ab6	111	* define access restrictions to peripheral registers
lynxeyed_atsu	0:e8bfffbb3ab6	112	*/
lynxeyed_atsu	0:e8bfffbb3ab6	113
lynxeyed_atsu	0:e8bfffbb3ab6	114	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	115	#define __I volatile /!< defines 'read only' permissions /
lynxeyed_atsu	0:e8bfffbb3ab6	116	#else
lynxeyed_atsu	0:e8bfffbb3ab6	117	#define __I volatile const /!< defines 'read only' permissions /
lynxeyed_atsu	0:e8bfffbb3ab6	118	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	119	#define __O volatile /!< defines 'write only' permissions /
lynxeyed_atsu	0:e8bfffbb3ab6	120	#define __IO volatile /!< defines 'read / write' permissions /
lynxeyed_atsu	0:e8bfffbb3ab6	121
lynxeyed_atsu	0:e8bfffbb3ab6	122
lynxeyed_atsu	0:e8bfffbb3ab6	123
lynxeyed_atsu	0:e8bfffbb3ab6	124	/*******************************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	125	* Register Abstraction
lynxeyed_atsu	0:e8bfffbb3ab6	126	******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	127	/** @addtogroup CMSIS_CM3_core_register CMSIS CM3 Core Register
lynxeyed_atsu	0:e8bfffbb3ab6	128	@{
lynxeyed_atsu	0:e8bfffbb3ab6	129	*/
lynxeyed_atsu	0:e8bfffbb3ab6	130
lynxeyed_atsu	0:e8bfffbb3ab6	131
lynxeyed_atsu	0:e8bfffbb3ab6	132	/** @addtogroup CMSIS_CM3_NVIC CMSIS CM3 NVIC
lynxeyed_atsu	0:e8bfffbb3ab6	133	memory mapped structure for Nested Vectored Interrupt Controller (NVIC)
lynxeyed_atsu	0:e8bfffbb3ab6	134	@{
lynxeyed_atsu	0:e8bfffbb3ab6	135	*/
lynxeyed_atsu	0:e8bfffbb3ab6	136	/** @brief Nested Vectored Interrupt Controller (NVIC) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	137	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	138	{
lynxeyed_atsu	0:e8bfffbb3ab6	139	__IO uint32_t ISER[8]; /!< Offset: 0x000 Interrupt Set Enable Register /
lynxeyed_atsu	0:e8bfffbb3ab6	140	uint32_t RESERVED0[24];
lynxeyed_atsu	0:e8bfffbb3ab6	141	__IO uint32_t ICER[8]; /!< Offset: 0x080 Interrupt Clear Enable Register /
lynxeyed_atsu	0:e8bfffbb3ab6	142	uint32_t RSERVED1[24];
lynxeyed_atsu	0:e8bfffbb3ab6	143	__IO uint32_t ISPR[8]; /!< Offset: 0x100 Interrupt Set Pending Register /
lynxeyed_atsu	0:e8bfffbb3ab6	144	uint32_t RESERVED2[24];
lynxeyed_atsu	0:e8bfffbb3ab6	145	__IO uint32_t ICPR[8]; /!< Offset: 0x180 Interrupt Clear Pending Register /
lynxeyed_atsu	0:e8bfffbb3ab6	146	uint32_t RESERVED3[24];
lynxeyed_atsu	0:e8bfffbb3ab6	147	__IO uint32_t IABR[8]; /!< Offset: 0x200 Interrupt Active bit Register /
lynxeyed_atsu	0:e8bfffbb3ab6	148	uint32_t RESERVED4[56];
lynxeyed_atsu	0:e8bfffbb3ab6	149	__IO uint8_t IP[240]; /!< Offset: 0x300 Interrupt Priority Register (8Bit wide) /
lynxeyed_atsu	0:e8bfffbb3ab6	150	uint32_t RESERVED5[644];
lynxeyed_atsu	0:e8bfffbb3ab6	151	__O uint32_t STIR; /!< Offset: 0xE00 Software Trigger Interrupt Register /
lynxeyed_atsu	0:e8bfffbb3ab6	152	} NVIC_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	153	/@}/ /* end of group CMSIS_CM3_NVIC */
lynxeyed_atsu	0:e8bfffbb3ab6	154
lynxeyed_atsu	0:e8bfffbb3ab6	155
lynxeyed_atsu	0:e8bfffbb3ab6	156	/** @addtogroup CMSIS_CM3_SCB CMSIS CM3 SCB
lynxeyed_atsu	0:e8bfffbb3ab6	157	memory mapped structure for System Control Block (SCB)
lynxeyed_atsu	0:e8bfffbb3ab6	158	@{
lynxeyed_atsu	0:e8bfffbb3ab6	159	*/
lynxeyed_atsu	0:e8bfffbb3ab6	160	/** @brief System Control Block (SCB) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	161	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	162	{
lynxeyed_atsu	0:e8bfffbb3ab6	163	__I uint32_t CPUID; /!< Offset: 0x00 CPU ID Base Register /
lynxeyed_atsu	0:e8bfffbb3ab6	164	__IO uint32_t ICSR; /!< Offset: 0x04 Interrupt Control State Register /
lynxeyed_atsu	0:e8bfffbb3ab6	165	__IO uint32_t VTOR; /!< Offset: 0x08 Vector Table Offset Register /
lynxeyed_atsu	0:e8bfffbb3ab6	166	__IO uint32_t AIRCR; /!< Offset: 0x0C Application Interrupt / Reset Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	167	__IO uint32_t SCR; /!< Offset: 0x10 System Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	168	__IO uint32_t CCR; /!< Offset: 0x14 Configuration Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	169	__IO uint8_t SHP[12]; /!< Offset: 0x18 System Handlers Priority Registers (4-7, 8-11, 12-15) /
lynxeyed_atsu	0:e8bfffbb3ab6	170	__IO uint32_t SHCSR; /!< Offset: 0x24 System Handler Control and State Register /
lynxeyed_atsu	0:e8bfffbb3ab6	171	__IO uint32_t CFSR; /!< Offset: 0x28 Configurable Fault Status Register /
lynxeyed_atsu	0:e8bfffbb3ab6	172	__IO uint32_t HFSR; /!< Offset: 0x2C Hard Fault Status Register /
lynxeyed_atsu	0:e8bfffbb3ab6	173	__IO uint32_t DFSR; /!< Offset: 0x30 Debug Fault Status Register /
lynxeyed_atsu	0:e8bfffbb3ab6	174	__IO uint32_t MMFAR; /!< Offset: 0x34 Mem Manage Address Register /
lynxeyed_atsu	0:e8bfffbb3ab6	175	__IO uint32_t BFAR; /!< Offset: 0x38 Bus Fault Address Register /
lynxeyed_atsu	0:e8bfffbb3ab6	176	__IO uint32_t AFSR; /!< Offset: 0x3C Auxiliary Fault Status Register /
lynxeyed_atsu	0:e8bfffbb3ab6	177	__I uint32_t PFR[2]; /!< Offset: 0x40 Processor Feature Register /
lynxeyed_atsu	0:e8bfffbb3ab6	178	__I uint32_t DFR; /!< Offset: 0x48 Debug Feature Register /
lynxeyed_atsu	0:e8bfffbb3ab6	179	__I uint32_t ADR; /!< Offset: 0x4C Auxiliary Feature Register /
lynxeyed_atsu	0:e8bfffbb3ab6	180	__I uint32_t MMFR[4]; /!< Offset: 0x50 Memory Model Feature Register /
lynxeyed_atsu	0:e8bfffbb3ab6	181	__I uint32_t ISAR[5]; /!< Offset: 0x60 ISA Feature Register /
lynxeyed_atsu	0:e8bfffbb3ab6	182	} SCB_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	183
lynxeyed_atsu	0:e8bfffbb3ab6	184	/* SCB CPUID Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	185	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
lynxeyed_atsu	0:e8bfffbb3ab6	186	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	187
lynxeyed_atsu	0:e8bfffbb3ab6	188	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	189	#define SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	190
lynxeyed_atsu	0:e8bfffbb3ab6	191	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
lynxeyed_atsu	0:e8bfffbb3ab6	192	#define SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	193
lynxeyed_atsu	0:e8bfffbb3ab6	194	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
lynxeyed_atsu	0:e8bfffbb3ab6	195	#define SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	196
lynxeyed_atsu	0:e8bfffbb3ab6	197	/* SCB Interrupt Control State Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	198	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
lynxeyed_atsu	0:e8bfffbb3ab6	199	#define SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	200
lynxeyed_atsu	0:e8bfffbb3ab6	201	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
lynxeyed_atsu	0:e8bfffbb3ab6	202	#define SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	203
lynxeyed_atsu	0:e8bfffbb3ab6	204	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	205	#define SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	206
lynxeyed_atsu	0:e8bfffbb3ab6	207	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
lynxeyed_atsu	0:e8bfffbb3ab6	208	#define SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	209
lynxeyed_atsu	0:e8bfffbb3ab6	210	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	211	#define SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	212
lynxeyed_atsu	0:e8bfffbb3ab6	213	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	214	#define SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	215
lynxeyed_atsu	0:e8bfffbb3ab6	216	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
lynxeyed_atsu	0:e8bfffbb3ab6	217	#define SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	218
lynxeyed_atsu	0:e8bfffbb3ab6	219	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
lynxeyed_atsu	0:e8bfffbb3ab6	220	#define SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	221
lynxeyed_atsu	0:e8bfffbb3ab6	222	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	223	#define SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	224
lynxeyed_atsu	0:e8bfffbb3ab6	225	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	226	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	227
lynxeyed_atsu	0:e8bfffbb3ab6	228	/* SCB Interrupt Control State Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	229	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	230	#define SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	231
lynxeyed_atsu	0:e8bfffbb3ab6	232	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
lynxeyed_atsu	0:e8bfffbb3ab6	233	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	234
lynxeyed_atsu	0:e8bfffbb3ab6	235	/* SCB Application Interrupt and Reset Control Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	236	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
lynxeyed_atsu	0:e8bfffbb3ab6	237	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	238
lynxeyed_atsu	0:e8bfffbb3ab6	239	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	240	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	241
lynxeyed_atsu	0:e8bfffbb3ab6	242	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
lynxeyed_atsu	0:e8bfffbb3ab6	243	#define SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	244
lynxeyed_atsu	0:e8bfffbb3ab6	245	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	246	#define SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	247
lynxeyed_atsu	0:e8bfffbb3ab6	248	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
lynxeyed_atsu	0:e8bfffbb3ab6	249	#define SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	250
lynxeyed_atsu	0:e8bfffbb3ab6	251	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	252	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	253
lynxeyed_atsu	0:e8bfffbb3ab6	254	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
lynxeyed_atsu	0:e8bfffbb3ab6	255	#define SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	256
lynxeyed_atsu	0:e8bfffbb3ab6	257	/* SCB System Control Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	258	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
lynxeyed_atsu	0:e8bfffbb3ab6	259	#define SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	260
lynxeyed_atsu	0:e8bfffbb3ab6	261	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	262	#define SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	263
lynxeyed_atsu	0:e8bfffbb3ab6	264	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	265	#define SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	266
lynxeyed_atsu	0:e8bfffbb3ab6	267	/* SCB Configuration Control Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	268	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
lynxeyed_atsu	0:e8bfffbb3ab6	269	#define SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	270
lynxeyed_atsu	0:e8bfffbb3ab6	271	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
lynxeyed_atsu	0:e8bfffbb3ab6	272	#define SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	273
lynxeyed_atsu	0:e8bfffbb3ab6	274	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	275	#define SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	276
lynxeyed_atsu	0:e8bfffbb3ab6	277	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	278	#define SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	279
lynxeyed_atsu	0:e8bfffbb3ab6	280	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
lynxeyed_atsu	0:e8bfffbb3ab6	281	#define SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	282
lynxeyed_atsu	0:e8bfffbb3ab6	283	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	284	#define SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	285
lynxeyed_atsu	0:e8bfffbb3ab6	286	/* SCB System Handler Control and State Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	287	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	288	#define SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	289
lynxeyed_atsu	0:e8bfffbb3ab6	290	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	291	#define SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	292
lynxeyed_atsu	0:e8bfffbb3ab6	293	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	294	#define SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	295
lynxeyed_atsu	0:e8bfffbb3ab6	296	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
lynxeyed_atsu	0:e8bfffbb3ab6	297	#define SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	298
lynxeyed_atsu	0:e8bfffbb3ab6	299	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
lynxeyed_atsu	0:e8bfffbb3ab6	300	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	301
lynxeyed_atsu	0:e8bfffbb3ab6	302	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
lynxeyed_atsu	0:e8bfffbb3ab6	303	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	304
lynxeyed_atsu	0:e8bfffbb3ab6	305	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
lynxeyed_atsu	0:e8bfffbb3ab6	306	#define SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	307
lynxeyed_atsu	0:e8bfffbb3ab6	308	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	309	#define SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	310
lynxeyed_atsu	0:e8bfffbb3ab6	311	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	312	#define SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	313
lynxeyed_atsu	0:e8bfffbb3ab6	314	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	315	#define SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	316
lynxeyed_atsu	0:e8bfffbb3ab6	317	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	318	#define SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	319
lynxeyed_atsu	0:e8bfffbb3ab6	320	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	321	#define SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	322
lynxeyed_atsu	0:e8bfffbb3ab6	323	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	324	#define SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	325
lynxeyed_atsu	0:e8bfffbb3ab6	326	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	327	#define SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	328
lynxeyed_atsu	0:e8bfffbb3ab6	329	/* SCB Configurable Fault Status Registers Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	330	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
lynxeyed_atsu	0:e8bfffbb3ab6	331	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	332
lynxeyed_atsu	0:e8bfffbb3ab6	333	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
lynxeyed_atsu	0:e8bfffbb3ab6	334	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	335
lynxeyed_atsu	0:e8bfffbb3ab6	336	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
lynxeyed_atsu	0:e8bfffbb3ab6	337	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	338
lynxeyed_atsu	0:e8bfffbb3ab6	339	/* SCB Hard Fault Status Registers Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	340	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	341	#define SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	342
lynxeyed_atsu	0:e8bfffbb3ab6	343	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
lynxeyed_atsu	0:e8bfffbb3ab6	344	#define SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	345
lynxeyed_atsu	0:e8bfffbb3ab6	346	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
lynxeyed_atsu	0:e8bfffbb3ab6	347	#define SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	348
lynxeyed_atsu	0:e8bfffbb3ab6	349	/* SCB Debug Fault Status Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	350	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
lynxeyed_atsu	0:e8bfffbb3ab6	351	#define SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	352
lynxeyed_atsu	0:e8bfffbb3ab6	353	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
lynxeyed_atsu	0:e8bfffbb3ab6	354	#define SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	355
lynxeyed_atsu	0:e8bfffbb3ab6	356	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	357	#define SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	358
lynxeyed_atsu	0:e8bfffbb3ab6	359	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	360	#define SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	361
lynxeyed_atsu	0:e8bfffbb3ab6	362	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
lynxeyed_atsu	0:e8bfffbb3ab6	363	#define SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	364	/@}/ /* end of group CMSIS_CM3_SCB */
lynxeyed_atsu	0:e8bfffbb3ab6	365
lynxeyed_atsu	0:e8bfffbb3ab6	366
lynxeyed_atsu	0:e8bfffbb3ab6	367	/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
lynxeyed_atsu	0:e8bfffbb3ab6	368	memory mapped structure for SysTick
lynxeyed_atsu	0:e8bfffbb3ab6	369	@{
lynxeyed_atsu	0:e8bfffbb3ab6	370	*/
lynxeyed_atsu	0:e8bfffbb3ab6	371	/** @brief System Tick Timer (SysTick) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	372	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	373	{
lynxeyed_atsu	0:e8bfffbb3ab6	374	__IO uint32_t CTRL; /!< Offset: 0x00 SysTick Control and Status Register /
lynxeyed_atsu	0:e8bfffbb3ab6	375	__IO uint32_t RELOAD; /!< Offset: 0x04 SysTick Reload Value Register /
lynxeyed_atsu	0:e8bfffbb3ab6	376	__IO uint32_t CURR; /!< Offset: 0x08 SysTick Current Value Register /
lynxeyed_atsu	0:e8bfffbb3ab6	377	__IO uint32_t CALIB; /!< Offset: 0x0C SysTick Calibration Register /
lynxeyed_atsu	0:e8bfffbb3ab6	378	} SysTick_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	379
lynxeyed_atsu	0:e8bfffbb3ab6	380	/* SysTick Control / Status Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	381	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
lynxeyed_atsu	0:e8bfffbb3ab6	382	#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	383
lynxeyed_atsu	0:e8bfffbb3ab6	384	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	385	#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	386
lynxeyed_atsu	0:e8bfffbb3ab6	387	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	388	#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	389
lynxeyed_atsu	0:e8bfffbb3ab6	390	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	391	#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	392
lynxeyed_atsu	0:e8bfffbb3ab6	393	/* SysTick Reload Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	394	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
lynxeyed_atsu	0:e8bfffbb3ab6	395	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	396
lynxeyed_atsu	0:e8bfffbb3ab6	397	/* SysTick Current Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	398	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	399	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	400
lynxeyed_atsu	0:e8bfffbb3ab6	401	/* SysTick Calibration Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	402	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
lynxeyed_atsu	0:e8bfffbb3ab6	403	#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	404
lynxeyed_atsu	0:e8bfffbb3ab6	405	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
lynxeyed_atsu	0:e8bfffbb3ab6	406	#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	407
lynxeyed_atsu	0:e8bfffbb3ab6	408	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
lynxeyed_atsu	0:e8bfffbb3ab6	409	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	410	/@}/ /* end of group CMSIS_CM3_SysTick */
lynxeyed_atsu	0:e8bfffbb3ab6	411
lynxeyed_atsu	0:e8bfffbb3ab6	412
lynxeyed_atsu	0:e8bfffbb3ab6	413	/** @addtogroup CMSIS_CM3_ITM CMSIS CM3 ITM
lynxeyed_atsu	0:e8bfffbb3ab6	414	memory mapped structure for Instrumentation Trace Macrocell (ITM)
lynxeyed_atsu	0:e8bfffbb3ab6	415	@{
lynxeyed_atsu	0:e8bfffbb3ab6	416	*/
lynxeyed_atsu	0:e8bfffbb3ab6	417	/** @brief Instrumentation Trace Macrocell (ITM) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	418	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	419	{
lynxeyed_atsu	0:e8bfffbb3ab6	420	__O union
lynxeyed_atsu	0:e8bfffbb3ab6	421	{
lynxeyed_atsu	0:e8bfffbb3ab6	422	__O uint8_t u8; /!< Offset: ITM Stimulus Port 8-bit /
lynxeyed_atsu	0:e8bfffbb3ab6	423	__O uint16_t u16; /!< Offset: ITM Stimulus Port 16-bit /
lynxeyed_atsu	0:e8bfffbb3ab6	424	__O uint32_t u32; /!< Offset: ITM Stimulus Port 32-bit /
lynxeyed_atsu	0:e8bfffbb3ab6	425	} PORT [32]; /!< Offset: 0x00 ITM Stimulus Port Registers /
lynxeyed_atsu	0:e8bfffbb3ab6	426	uint32_t RESERVED0[864];
lynxeyed_atsu	0:e8bfffbb3ab6	427	__IO uint32_t TER; /!< Offset: ITM Trace Enable Register /
lynxeyed_atsu	0:e8bfffbb3ab6	428	uint32_t RESERVED1[15];
lynxeyed_atsu	0:e8bfffbb3ab6	429	__IO uint32_t TPR; /!< Offset: ITM Trace Privilege Register /
lynxeyed_atsu	0:e8bfffbb3ab6	430	uint32_t RESERVED2[15];
lynxeyed_atsu	0:e8bfffbb3ab6	431	__IO uint32_t TCR; /!< Offset: ITM Trace Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	432	uint32_t RESERVED3[29];
lynxeyed_atsu	0:e8bfffbb3ab6	433	__IO uint32_t IWR; /!< Offset: ITM Integration Write Register /
lynxeyed_atsu	0:e8bfffbb3ab6	434	__IO uint32_t IRR; /!< Offset: ITM Integration Read Register /
lynxeyed_atsu	0:e8bfffbb3ab6	435	__IO uint32_t IMCR; /!< Offset: ITM Integration Mode Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	436	uint32_t RESERVED4[43];
lynxeyed_atsu	0:e8bfffbb3ab6	437	__IO uint32_t LAR; /!< Offset: ITM Lock Access Register /
lynxeyed_atsu	0:e8bfffbb3ab6	438	__IO uint32_t LSR; /!< Offset: ITM Lock Status Register /
lynxeyed_atsu	0:e8bfffbb3ab6	439	uint32_t RESERVED5[6];
lynxeyed_atsu	0:e8bfffbb3ab6	440	__I uint32_t PID4; /!< Offset: ITM Peripheral Identification Register #4 /
lynxeyed_atsu	0:e8bfffbb3ab6	441	__I uint32_t PID5; /!< Offset: ITM Peripheral Identification Register #5 /
lynxeyed_atsu	0:e8bfffbb3ab6	442	__I uint32_t PID6; /!< Offset: ITM Peripheral Identification Register #6 /
lynxeyed_atsu	0:e8bfffbb3ab6	443	__I uint32_t PID7; /!< Offset: ITM Peripheral Identification Register #7 /
lynxeyed_atsu	0:e8bfffbb3ab6	444	__I uint32_t PID0; /!< Offset: ITM Peripheral Identification Register #0 /
lynxeyed_atsu	0:e8bfffbb3ab6	445	__I uint32_t PID1; /!< Offset: ITM Peripheral Identification Register #1 /
lynxeyed_atsu	0:e8bfffbb3ab6	446	__I uint32_t PID2; /!< Offset: ITM Peripheral Identification Register #2 /
lynxeyed_atsu	0:e8bfffbb3ab6	447	__I uint32_t PID3; /!< Offset: ITM Peripheral Identification Register #3 /
lynxeyed_atsu	0:e8bfffbb3ab6	448	__I uint32_t CID0; /!< Offset: ITM Component Identification Register #0 /
lynxeyed_atsu	0:e8bfffbb3ab6	449	__I uint32_t CID1; /!< Offset: ITM Component Identification Register #1 /
lynxeyed_atsu	0:e8bfffbb3ab6	450	__I uint32_t CID2; /!< Offset: ITM Component Identification Register #2 /
lynxeyed_atsu	0:e8bfffbb3ab6	451	__I uint32_t CID3; /!< Offset: ITM Component Identification Register #3 /
lynxeyed_atsu	0:e8bfffbb3ab6	452	} ITM_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	453
lynxeyed_atsu	0:e8bfffbb3ab6	454	/* ITM Trace Privilege Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	455	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
lynxeyed_atsu	0:e8bfffbb3ab6	456	#define ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	457
lynxeyed_atsu	0:e8bfffbb3ab6	458	/* ITM Trace Control Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	459	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
lynxeyed_atsu	0:e8bfffbb3ab6	460	#define ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	461
lynxeyed_atsu	0:e8bfffbb3ab6	462	#define ITM_TCR_ATBID_Pos 16 /!< ITM TCR: ATBID Position /
lynxeyed_atsu	0:e8bfffbb3ab6	463	#define ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos) /!< ITM TCR: ATBID Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	464
lynxeyed_atsu	0:e8bfffbb3ab6	465	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
lynxeyed_atsu	0:e8bfffbb3ab6	466	#define ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	467
lynxeyed_atsu	0:e8bfffbb3ab6	468	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	469	#define ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	470
lynxeyed_atsu	0:e8bfffbb3ab6	471	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	472	#define ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	473
lynxeyed_atsu	0:e8bfffbb3ab6	474	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	475	#define ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	476
lynxeyed_atsu	0:e8bfffbb3ab6	477	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	478	#define ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	479
lynxeyed_atsu	0:e8bfffbb3ab6	480	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
lynxeyed_atsu	0:e8bfffbb3ab6	481	#define ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	482
lynxeyed_atsu	0:e8bfffbb3ab6	483	/* ITM Integration Write Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	484	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
lynxeyed_atsu	0:e8bfffbb3ab6	485	#define ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	486
lynxeyed_atsu	0:e8bfffbb3ab6	487	/* ITM Integration Read Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	488	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
lynxeyed_atsu	0:e8bfffbb3ab6	489	#define ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	490
lynxeyed_atsu	0:e8bfffbb3ab6	491	/* ITM Integration Mode Control Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	492	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
lynxeyed_atsu	0:e8bfffbb3ab6	493	#define ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	494
lynxeyed_atsu	0:e8bfffbb3ab6	495	/* ITM Lock Status Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	496	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
lynxeyed_atsu	0:e8bfffbb3ab6	497	#define ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	498
lynxeyed_atsu	0:e8bfffbb3ab6	499	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
lynxeyed_atsu	0:e8bfffbb3ab6	500	#define ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	501
lynxeyed_atsu	0:e8bfffbb3ab6	502	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
lynxeyed_atsu	0:e8bfffbb3ab6	503	#define ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	504	/@}/ /* end of group CMSIS_CM3_ITM */
lynxeyed_atsu	0:e8bfffbb3ab6	505
lynxeyed_atsu	0:e8bfffbb3ab6	506
lynxeyed_atsu	0:e8bfffbb3ab6	507	/** @addtogroup CMSIS_CM3_InterruptType CMSIS CM3 Interrupt Type
lynxeyed_atsu	0:e8bfffbb3ab6	508	memory mapped structure for Interrupt Type
lynxeyed_atsu	0:e8bfffbb3ab6	509	@{
lynxeyed_atsu	0:e8bfffbb3ab6	510	*/
lynxeyed_atsu	0:e8bfffbb3ab6	511	/** @brief Instrumentation Trace Macrocell (ITM) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	512	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	513	{
lynxeyed_atsu	0:e8bfffbb3ab6	514	uint32_t RESERVED0;
lynxeyed_atsu	0:e8bfffbb3ab6	515	__I uint32_t ICTR; /!< Offset: 0x04 Interrupt Control Type Register /
lynxeyed_atsu	0:e8bfffbb3ab6	516	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
lynxeyed_atsu	0:e8bfffbb3ab6	517	__IO uint32_t ACTLR; /!< Offset: 0x08 Auxiliary Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	518	#else
lynxeyed_atsu	0:e8bfffbb3ab6	519	uint32_t RESERVED1;
lynxeyed_atsu	0:e8bfffbb3ab6	520	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	521	} InterruptType_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	522
lynxeyed_atsu	0:e8bfffbb3ab6	523	/* Interrupt Controller Type Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	524	#define InterruptType_ICTR_INTLINESNUM_Pos 0 /!< InterruptType ICTR: INTLINESNUM Position /
lynxeyed_atsu	0:e8bfffbb3ab6	525	#define InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos) /!< InterruptType ICTR: INTLINESNUM Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	526
lynxeyed_atsu	0:e8bfffbb3ab6	527	/* Auxiliary Control Register Definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	528	#define InterruptType_ACTLR_DISFOLD_Pos 2 /!< InterruptType ACTLR: DISFOLD Position /
lynxeyed_atsu	0:e8bfffbb3ab6	529	#define InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos) /!< InterruptType ACTLR: DISFOLD Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	530
lynxeyed_atsu	0:e8bfffbb3ab6	531	#define InterruptType_ACTLR_DISDEFWBUF_Pos 1 /!< InterruptType ACTLR: DISDEFWBUF Position /
lynxeyed_atsu	0:e8bfffbb3ab6	532	#define InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos) /!< InterruptType ACTLR: DISDEFWBUF Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	533
lynxeyed_atsu	0:e8bfffbb3ab6	534	#define InterruptType_ACTLR_DISMCYCINT_Pos 0 /!< InterruptType ACTLR: DISMCYCINT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	535	#define InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos) /!< InterruptType ACTLR: DISMCYCINT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	536	/@}/ /* end of group CMSIS_CM3_InterruptType */
lynxeyed_atsu	0:e8bfffbb3ab6	537
lynxeyed_atsu	0:e8bfffbb3ab6	538
lynxeyed_atsu	0:e8bfffbb3ab6	539	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
lynxeyed_atsu	0:e8bfffbb3ab6	540	/** @addtogroup CMSIS_CM3_MPU CMSIS CM3 MPU
lynxeyed_atsu	0:e8bfffbb3ab6	541	memory mapped structure for Memory Protection Unit (MPU)
lynxeyed_atsu	0:e8bfffbb3ab6	542	@{
lynxeyed_atsu	0:e8bfffbb3ab6	543	*/
lynxeyed_atsu	0:e8bfffbb3ab6	544	/** @brief Memory Protection Unit (MPU) register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	545	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	546	{
lynxeyed_atsu	0:e8bfffbb3ab6	547	__I uint32_t TYPE; /!< Offset: 0x00 MPU Type Register /
lynxeyed_atsu	0:e8bfffbb3ab6	548	__IO uint32_t CTRL; /!< Offset: 0x04 MPU Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	549	__IO uint32_t RNR; /!< Offset: 0x08 MPU Region RNRber Register /
lynxeyed_atsu	0:e8bfffbb3ab6	550	__IO uint32_t RBAR; /!< Offset: 0x0C MPU Region Base Address Register /
lynxeyed_atsu	0:e8bfffbb3ab6	551	__IO uint32_t RASR; /!< Offset: 0x10 MPU Region Attribute and Size Register /
lynxeyed_atsu	0:e8bfffbb3ab6	552	__IO uint32_t RBAR_A1; /!< Offset: 0x14 MPU Alias 1 Region Base Address Register /
lynxeyed_atsu	0:e8bfffbb3ab6	553	__IO uint32_t RASR_A1; /!< Offset: 0x18 MPU Alias 1 Region Attribute and Size Register /
lynxeyed_atsu	0:e8bfffbb3ab6	554	__IO uint32_t RBAR_A2; /!< Offset: 0x1C MPU Alias 2 Region Base Address Register /
lynxeyed_atsu	0:e8bfffbb3ab6	555	__IO uint32_t RASR_A2; /!< Offset: 0x20 MPU Alias 2 Region Attribute and Size Register /
lynxeyed_atsu	0:e8bfffbb3ab6	556	__IO uint32_t RBAR_A3; /!< Offset: 0x24 MPU Alias 3 Region Base Address Register /
lynxeyed_atsu	0:e8bfffbb3ab6	557	__IO uint32_t RASR_A3; /!< Offset: 0x28 MPU Alias 3 Region Attribute and Size Register /
lynxeyed_atsu	0:e8bfffbb3ab6	558	} MPU_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	559
lynxeyed_atsu	0:e8bfffbb3ab6	560	/* MPU Type Register */
lynxeyed_atsu	0:e8bfffbb3ab6	561	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
lynxeyed_atsu	0:e8bfffbb3ab6	562	#define MPU_TYPE_IREGION_Msk (0xFFul << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	563
lynxeyed_atsu	0:e8bfffbb3ab6	564	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
lynxeyed_atsu	0:e8bfffbb3ab6	565	#define MPU_TYPE_DREGION_Msk (0xFFul << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	566
lynxeyed_atsu	0:e8bfffbb3ab6	567	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	568	#define MPU_TYPE_SEPARATE_Msk (1ul << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	569
lynxeyed_atsu	0:e8bfffbb3ab6	570	/* MPU Control Register */
lynxeyed_atsu	0:e8bfffbb3ab6	571	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	572	#define MPU_CTRL_PRIVDEFENA_Msk (1ul << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	573
lynxeyed_atsu	0:e8bfffbb3ab6	574	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	575	#define MPU_CTRL_HFNMIENA_Msk (1ul << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	576
lynxeyed_atsu	0:e8bfffbb3ab6	577	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
lynxeyed_atsu	0:e8bfffbb3ab6	578	#define MPU_CTRL_ENABLE_Msk (1ul << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	579
lynxeyed_atsu	0:e8bfffbb3ab6	580	/* MPU Region Number Register */
lynxeyed_atsu	0:e8bfffbb3ab6	581	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
lynxeyed_atsu	0:e8bfffbb3ab6	582	#define MPU_RNR_REGION_Msk (0xFFul << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	583
lynxeyed_atsu	0:e8bfffbb3ab6	584	/* MPU Region Base Address Register */
lynxeyed_atsu	0:e8bfffbb3ab6	585	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	586	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFul << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	587
lynxeyed_atsu	0:e8bfffbb3ab6	588	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
lynxeyed_atsu	0:e8bfffbb3ab6	589	#define MPU_RBAR_VALID_Msk (1ul << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	590
lynxeyed_atsu	0:e8bfffbb3ab6	591	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
lynxeyed_atsu	0:e8bfffbb3ab6	592	#define MPU_RBAR_REGION_Msk (0xFul << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	593
lynxeyed_atsu	0:e8bfffbb3ab6	594	/* MPU Region Attribute and Size Register */
lynxeyed_atsu	0:e8bfffbb3ab6	595	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: XN Position /
lynxeyed_atsu	0:e8bfffbb3ab6	596	#define MPU_RASR_XN_Msk (1ul << MPU_RASR_XN_Pos) /!< MPU RASR: XN Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	597
lynxeyed_atsu	0:e8bfffbb3ab6	598	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: AP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	599	#define MPU_RASR_AP_Msk (7ul << MPU_RASR_AP_Pos) /!< MPU RASR: AP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	600
lynxeyed_atsu	0:e8bfffbb3ab6	601	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: TEX Position /
lynxeyed_atsu	0:e8bfffbb3ab6	602	#define MPU_RASR_TEX_Msk (7ul << MPU_RASR_TEX_Pos) /!< MPU RASR: TEX Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	603
lynxeyed_atsu	0:e8bfffbb3ab6	604	#define MPU_RASR_S_Pos 18 /!< MPU RASR: Shareable bit Position /
lynxeyed_atsu	0:e8bfffbb3ab6	605	#define MPU_RASR_S_Msk (1ul << MPU_RASR_S_Pos) /!< MPU RASR: Shareable bit Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	606
lynxeyed_atsu	0:e8bfffbb3ab6	607	#define MPU_RASR_C_Pos 17 /!< MPU RASR: Cacheable bit Position /
lynxeyed_atsu	0:e8bfffbb3ab6	608	#define MPU_RASR_C_Msk (1ul << MPU_RASR_C_Pos) /!< MPU RASR: Cacheable bit Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	609
lynxeyed_atsu	0:e8bfffbb3ab6	610	#define MPU_RASR_B_Pos 16 /!< MPU RASR: Bufferable bit Position /
lynxeyed_atsu	0:e8bfffbb3ab6	611	#define MPU_RASR_B_Msk (1ul << MPU_RASR_B_Pos) /!< MPU RASR: Bufferable bit Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	612
lynxeyed_atsu	0:e8bfffbb3ab6	613	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
lynxeyed_atsu	0:e8bfffbb3ab6	614	#define MPU_RASR_SRD_Msk (0xFFul << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	615
lynxeyed_atsu	0:e8bfffbb3ab6	616	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
lynxeyed_atsu	0:e8bfffbb3ab6	617	#define MPU_RASR_SIZE_Msk (0x1Ful << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	618
lynxeyed_atsu	0:e8bfffbb3ab6	619	#define MPU_RASR_ENA_Pos 0 /!< MPU RASR: Region enable bit Position /
lynxeyed_atsu	0:e8bfffbb3ab6	620	#define MPU_RASR_ENA_Msk (0x1Ful << MPU_RASR_ENA_Pos) /!< MPU RASR: Region enable bit Disable Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	621
lynxeyed_atsu	0:e8bfffbb3ab6	622	/@}/ /* end of group CMSIS_CM3_MPU */
lynxeyed_atsu	0:e8bfffbb3ab6	623	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	624
lynxeyed_atsu	0:e8bfffbb3ab6	625
lynxeyed_atsu	0:e8bfffbb3ab6	626	/** @addtogroup CMSIS_CM3_CoreDebug CMSIS CM3 Core Debug
lynxeyed_atsu	0:e8bfffbb3ab6	627	memory mapped structure for Core Debug Register
lynxeyed_atsu	0:e8bfffbb3ab6	628	@{
lynxeyed_atsu	0:e8bfffbb3ab6	629	*/
lynxeyed_atsu	0:e8bfffbb3ab6	630	/** @brief Core Debug register structure definition */
lynxeyed_atsu	0:e8bfffbb3ab6	631	typedef struct
lynxeyed_atsu	0:e8bfffbb3ab6	632	{
lynxeyed_atsu	0:e8bfffbb3ab6	633	__IO uint32_t DHCSR; /!< Offset: 0x00 Debug Halting Control and Status Register /
lynxeyed_atsu	0:e8bfffbb3ab6	634	__O uint32_t DCRSR; /!< Offset: 0x04 Debug Core Register Selector Register /
lynxeyed_atsu	0:e8bfffbb3ab6	635	__IO uint32_t DCRDR; /!< Offset: 0x08 Debug Core Register Data Register /
lynxeyed_atsu	0:e8bfffbb3ab6	636	__IO uint32_t DEMCR; /!< Offset: 0x0C Debug Exception and Monitor Control Register /
lynxeyed_atsu	0:e8bfffbb3ab6	637	} CoreDebug_Type;
lynxeyed_atsu	0:e8bfffbb3ab6	638
lynxeyed_atsu	0:e8bfffbb3ab6	639	/* Debug Halting Control and Status Register */
lynxeyed_atsu	0:e8bfffbb3ab6	640	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
lynxeyed_atsu	0:e8bfffbb3ab6	641	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	642
lynxeyed_atsu	0:e8bfffbb3ab6	643	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
lynxeyed_atsu	0:e8bfffbb3ab6	644	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	645
lynxeyed_atsu	0:e8bfffbb3ab6	646	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
lynxeyed_atsu	0:e8bfffbb3ab6	647	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	648
lynxeyed_atsu	0:e8bfffbb3ab6	649	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	650	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	651
lynxeyed_atsu	0:e8bfffbb3ab6	652	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	653	#define CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	654
lynxeyed_atsu	0:e8bfffbb3ab6	655	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	656	#define CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	657
lynxeyed_atsu	0:e8bfffbb3ab6	658	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
lynxeyed_atsu	0:e8bfffbb3ab6	659	#define CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	660
lynxeyed_atsu	0:e8bfffbb3ab6	661	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
lynxeyed_atsu	0:e8bfffbb3ab6	662	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	663
lynxeyed_atsu	0:e8bfffbb3ab6	664	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
lynxeyed_atsu	0:e8bfffbb3ab6	665	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	666
lynxeyed_atsu	0:e8bfffbb3ab6	667	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	668	#define CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	669
lynxeyed_atsu	0:e8bfffbb3ab6	670	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
lynxeyed_atsu	0:e8bfffbb3ab6	671	#define CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	672
lynxeyed_atsu	0:e8bfffbb3ab6	673	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
lynxeyed_atsu	0:e8bfffbb3ab6	674	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	675
lynxeyed_atsu	0:e8bfffbb3ab6	676	/* Debug Core Register Selector Register */
lynxeyed_atsu	0:e8bfffbb3ab6	677	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	678	#define CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	679
lynxeyed_atsu	0:e8bfffbb3ab6	680	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
lynxeyed_atsu	0:e8bfffbb3ab6	681	#define CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	682
lynxeyed_atsu	0:e8bfffbb3ab6	683	/* Debug Exception and Monitor Control Register */
lynxeyed_atsu	0:e8bfffbb3ab6	684	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
lynxeyed_atsu	0:e8bfffbb3ab6	685	#define CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	686
lynxeyed_atsu	0:e8bfffbb3ab6	687	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
lynxeyed_atsu	0:e8bfffbb3ab6	688	#define CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	689
lynxeyed_atsu	0:e8bfffbb3ab6	690	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
lynxeyed_atsu	0:e8bfffbb3ab6	691	#define CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	692
lynxeyed_atsu	0:e8bfffbb3ab6	693	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
lynxeyed_atsu	0:e8bfffbb3ab6	694	#define CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	695
lynxeyed_atsu	0:e8bfffbb3ab6	696	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
lynxeyed_atsu	0:e8bfffbb3ab6	697	#define CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	698
lynxeyed_atsu	0:e8bfffbb3ab6	699	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	700	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	701
lynxeyed_atsu	0:e8bfffbb3ab6	702	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	703	#define CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	704
lynxeyed_atsu	0:e8bfffbb3ab6	705	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	706	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	707
lynxeyed_atsu	0:e8bfffbb3ab6	708	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	709	#define CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	710
lynxeyed_atsu	0:e8bfffbb3ab6	711	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	712	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	713
lynxeyed_atsu	0:e8bfffbb3ab6	714	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	715	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	716
lynxeyed_atsu	0:e8bfffbb3ab6	717	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
lynxeyed_atsu	0:e8bfffbb3ab6	718	#define CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	719
lynxeyed_atsu	0:e8bfffbb3ab6	720	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
lynxeyed_atsu	0:e8bfffbb3ab6	721	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
lynxeyed_atsu	0:e8bfffbb3ab6	722	/@}/ /* end of group CMSIS_CM3_CoreDebug */
lynxeyed_atsu	0:e8bfffbb3ab6	723
lynxeyed_atsu	0:e8bfffbb3ab6	724
lynxeyed_atsu	0:e8bfffbb3ab6	725	/* Memory mapping of Cortex-M3 Hardware */
lynxeyed_atsu	0:e8bfffbb3ab6	726	#define SCS_BASE (0xE000E000) /!< System Control Space Base Address /
lynxeyed_atsu	0:e8bfffbb3ab6	727	#define ITM_BASE (0xE0000000) /!< ITM Base Address /
lynxeyed_atsu	0:e8bfffbb3ab6	728	#define CoreDebug_BASE (0xE000EDF0) /!< Core Debug Base Address /
lynxeyed_atsu	0:e8bfffbb3ab6	729	#define SysTick_BASE (SCS_BASE + 0x0010) /!< SysTick Base Address /
lynxeyed_atsu	0:e8bfffbb3ab6	730	#define NVIC_BASE (SCS_BASE + 0x0100) /!< NVIC Base Address /
lynxeyed_atsu	0:e8bfffbb3ab6	731	#define SCB_BASE (SCS_BASE + 0x0D00) /!< System Control Block Base Address /
lynxeyed_atsu	0:e8bfffbb3ab6	732
lynxeyed_atsu	0:e8bfffbb3ab6	733	#define InterruptType ((InterruptType_Type ) SCS_BASE) /!< Interrupt Type Register */
lynxeyed_atsu	0:e8bfffbb3ab6	734	#define SCB ((SCB_Type ) SCB_BASE) /!< SCB configuration struct */
lynxeyed_atsu	0:e8bfffbb3ab6	735	#define SysTick ((SysTick_Type ) SysTick_BASE) /!< SysTick configuration struct */
lynxeyed_atsu	0:e8bfffbb3ab6	736	#define NVIC ((NVIC_Type ) NVIC_BASE) /!< NVIC configuration struct */
lynxeyed_atsu	0:e8bfffbb3ab6	737	#define ITM ((ITM_Type ) ITM_BASE) /!< ITM configuration struct */
lynxeyed_atsu	0:e8bfffbb3ab6	738	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
lynxeyed_atsu	0:e8bfffbb3ab6	739
lynxeyed_atsu	0:e8bfffbb3ab6	740	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
lynxeyed_atsu	0:e8bfffbb3ab6	741	#define MPU_BASE (SCS_BASE + 0x0D90) /!< Memory Protection Unit /
lynxeyed_atsu	0:e8bfffbb3ab6	742	#define MPU ((MPU_Type) MPU_BASE) /!< Memory Protection Unit */
lynxeyed_atsu	0:e8bfffbb3ab6	743	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	744
lynxeyed_atsu	0:e8bfffbb3ab6	745	/@}/ /* end of group CMSIS_CM3_core_register */
lynxeyed_atsu	0:e8bfffbb3ab6	746
lynxeyed_atsu	0:e8bfffbb3ab6	747
lynxeyed_atsu	0:e8bfffbb3ab6	748	/*******************************************************************************
lynxeyed_atsu	0:e8bfffbb3ab6	749	* Hardware Abstraction Layer
lynxeyed_atsu	0:e8bfffbb3ab6	750	******************************************************************************/
lynxeyed_atsu	0:e8bfffbb3ab6	751
lynxeyed_atsu	0:e8bfffbb3ab6	752	#if defined ( __CC_ARM )
lynxeyed_atsu	0:e8bfffbb3ab6	753	#define __ASM __asm /!< asm keyword for ARM Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	754	#define __INLINE __inline /!< inline keyword for ARM Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	755
lynxeyed_atsu	0:e8bfffbb3ab6	756	#elif defined ( __ICCARM__ )
lynxeyed_atsu	0:e8bfffbb3ab6	757	#define __ASM __asm /!< asm keyword for IAR Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	758	#define __INLINE inline /!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! /
lynxeyed_atsu	0:e8bfffbb3ab6	759
lynxeyed_atsu	0:e8bfffbb3ab6	760	#elif defined ( __GNUC__ )
lynxeyed_atsu	0:e8bfffbb3ab6	761	#define __ASM __asm /!< asm keyword for GNU Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	762	#define __INLINE inline /!< inline keyword for GNU Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	763
lynxeyed_atsu	0:e8bfffbb3ab6	764	#elif defined ( __TASKING__ )
lynxeyed_atsu	0:e8bfffbb3ab6	765	#define __ASM __asm /!< asm keyword for TASKING Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	766	#define __INLINE inline /!< inline keyword for TASKING Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	767
lynxeyed_atsu	0:e8bfffbb3ab6	768	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	769
lynxeyed_atsu	0:e8bfffbb3ab6	770
lynxeyed_atsu	0:e8bfffbb3ab6	771	/* ################### Compiler specific Intrinsics ########################### */
lynxeyed_atsu	0:e8bfffbb3ab6	772
lynxeyed_atsu	0:e8bfffbb3ab6	773	#if defined ( __CC_ARM ) /------------------RealView Compiler -----------------/
lynxeyed_atsu	0:e8bfffbb3ab6	774	/* ARM armcc specific functions */
lynxeyed_atsu	0:e8bfffbb3ab6	775
lynxeyed_atsu	0:e8bfffbb3ab6	776	#define __enable_fault_irq __enable_fiq
lynxeyed_atsu	0:e8bfffbb3ab6	777	#define __disable_fault_irq __disable_fiq
lynxeyed_atsu	0:e8bfffbb3ab6	778
lynxeyed_atsu	0:e8bfffbb3ab6	779	#define __NOP __nop
lynxeyed_atsu	0:e8bfffbb3ab6	780	#define __WFI __wfi
lynxeyed_atsu	0:e8bfffbb3ab6	781	#define __WFE __wfe
lynxeyed_atsu	0:e8bfffbb3ab6	782	#define __SEV __sev
lynxeyed_atsu	0:e8bfffbb3ab6	783	#define __ISB() __isb(0)
lynxeyed_atsu	0:e8bfffbb3ab6	784	#define __DSB() __dsb(0)
lynxeyed_atsu	0:e8bfffbb3ab6	785	#define __DMB() __dmb(0)
lynxeyed_atsu	0:e8bfffbb3ab6	786	#define __REV __rev
lynxeyed_atsu	0:e8bfffbb3ab6	787	#define __RBIT __rbit
lynxeyed_atsu	0:e8bfffbb3ab6	788	#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
lynxeyed_atsu	0:e8bfffbb3ab6	789	#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
lynxeyed_atsu	0:e8bfffbb3ab6	790	#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
lynxeyed_atsu	0:e8bfffbb3ab6	791	#define __STREXB(value, ptr) __strex(value, ptr)
lynxeyed_atsu	0:e8bfffbb3ab6	792	#define __STREXH(value, ptr) __strex(value, ptr)
lynxeyed_atsu	0:e8bfffbb3ab6	793	#define __STREXW(value, ptr) __strex(value, ptr)
lynxeyed_atsu	0:e8bfffbb3ab6	794
lynxeyed_atsu	0:e8bfffbb3ab6	795
lynxeyed_atsu	0:e8bfffbb3ab6	796	/* intrinsic unsigned long long __ldrexd(volatile void ptr) /
lynxeyed_atsu	0:e8bfffbb3ab6	797	/* intrinsic int __strexd(unsigned long long val, volatile void ptr) /
lynxeyed_atsu	0:e8bfffbb3ab6	798	/* intrinsic void __enable_irq(); */
lynxeyed_atsu	0:e8bfffbb3ab6	799	/* intrinsic void __disable_irq(); */
lynxeyed_atsu	0:e8bfffbb3ab6	800
lynxeyed_atsu	0:e8bfffbb3ab6	801
lynxeyed_atsu	0:e8bfffbb3ab6	802	/**
lynxeyed_atsu	0:e8bfffbb3ab6	803	* @brief Return the Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	804	*
lynxeyed_atsu	0:e8bfffbb3ab6	805	* @return ProcessStackPointer
lynxeyed_atsu	0:e8bfffbb3ab6	806	*
lynxeyed_atsu	0:e8bfffbb3ab6	807	* Return the actual process stack pointer
lynxeyed_atsu	0:e8bfffbb3ab6	808	*/
lynxeyed_atsu	0:e8bfffbb3ab6	809	extern uint32_t __get_PSP(void);
lynxeyed_atsu	0:e8bfffbb3ab6	810
lynxeyed_atsu	0:e8bfffbb3ab6	811	/**
lynxeyed_atsu	0:e8bfffbb3ab6	812	* @brief Set the Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	813	*
lynxeyed_atsu	0:e8bfffbb3ab6	814	* @param topOfProcStack Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	815	*
lynxeyed_atsu	0:e8bfffbb3ab6	816	* Assign the value ProcessStackPointer to the MSP
lynxeyed_atsu	0:e8bfffbb3ab6	817	* (process stack pointer) Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	818	*/
lynxeyed_atsu	0:e8bfffbb3ab6	819	extern void __set_PSP(uint32_t topOfProcStack);
lynxeyed_atsu	0:e8bfffbb3ab6	820
lynxeyed_atsu	0:e8bfffbb3ab6	821	/**
lynxeyed_atsu	0:e8bfffbb3ab6	822	* @brief Return the Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	823	*
lynxeyed_atsu	0:e8bfffbb3ab6	824	* @return Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	825	*
lynxeyed_atsu	0:e8bfffbb3ab6	826	* Return the current value of the MSP (main stack pointer)
lynxeyed_atsu	0:e8bfffbb3ab6	827	* Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	828	*/
lynxeyed_atsu	0:e8bfffbb3ab6	829	extern uint32_t __get_MSP(void);
lynxeyed_atsu	0:e8bfffbb3ab6	830
lynxeyed_atsu	0:e8bfffbb3ab6	831	/**
lynxeyed_atsu	0:e8bfffbb3ab6	832	* @brief Set the Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	833	*
lynxeyed_atsu	0:e8bfffbb3ab6	834	* @param topOfMainStack Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	835	*
lynxeyed_atsu	0:e8bfffbb3ab6	836	* Assign the value mainStackPointer to the MSP
lynxeyed_atsu	0:e8bfffbb3ab6	837	* (main stack pointer) Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	838	*/
lynxeyed_atsu	0:e8bfffbb3ab6	839	extern void __set_MSP(uint32_t topOfMainStack);
lynxeyed_atsu	0:e8bfffbb3ab6	840
lynxeyed_atsu	0:e8bfffbb3ab6	841	/**
lynxeyed_atsu	0:e8bfffbb3ab6	842	* @brief Reverse byte order in unsigned short value
lynxeyed_atsu	0:e8bfffbb3ab6	843	*
lynxeyed_atsu	0:e8bfffbb3ab6	844	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	845	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	846	*
lynxeyed_atsu	0:e8bfffbb3ab6	847	* Reverse byte order in unsigned short value
lynxeyed_atsu	0:e8bfffbb3ab6	848	*/
lynxeyed_atsu	0:e8bfffbb3ab6	849	extern uint32_t __REV16(uint16_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	850
lynxeyed_atsu	0:e8bfffbb3ab6	851	/**
lynxeyed_atsu	0:e8bfffbb3ab6	852	* @brief Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:e8bfffbb3ab6	853	*
lynxeyed_atsu	0:e8bfffbb3ab6	854	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	855	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	856	*
lynxeyed_atsu	0:e8bfffbb3ab6	857	* Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:e8bfffbb3ab6	858	*/
lynxeyed_atsu	0:e8bfffbb3ab6	859	extern int32_t __REVSH(int16_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	860
lynxeyed_atsu	0:e8bfffbb3ab6	861
lynxeyed_atsu	0:e8bfffbb3ab6	862	#if (__ARMCC_VERSION < 400000)
lynxeyed_atsu	0:e8bfffbb3ab6	863
lynxeyed_atsu	0:e8bfffbb3ab6	864	/**
lynxeyed_atsu	0:e8bfffbb3ab6	865	* @brief Remove the exclusive lock created by ldrex
lynxeyed_atsu	0:e8bfffbb3ab6	866	*
lynxeyed_atsu	0:e8bfffbb3ab6	867	* Removes the exclusive lock which is created by ldrex.
lynxeyed_atsu	0:e8bfffbb3ab6	868	*/
lynxeyed_atsu	0:e8bfffbb3ab6	869	extern void __CLREX(void);
lynxeyed_atsu	0:e8bfffbb3ab6	870
lynxeyed_atsu	0:e8bfffbb3ab6	871	/**
lynxeyed_atsu	0:e8bfffbb3ab6	872	* @brief Return the Base Priority value
lynxeyed_atsu	0:e8bfffbb3ab6	873	*
lynxeyed_atsu	0:e8bfffbb3ab6	874	* @return BasePriority
lynxeyed_atsu	0:e8bfffbb3ab6	875	*
lynxeyed_atsu	0:e8bfffbb3ab6	876	* Return the content of the base priority register
lynxeyed_atsu	0:e8bfffbb3ab6	877	*/
lynxeyed_atsu	0:e8bfffbb3ab6	878	extern uint32_t __get_BASEPRI(void);
lynxeyed_atsu	0:e8bfffbb3ab6	879
lynxeyed_atsu	0:e8bfffbb3ab6	880	/**
lynxeyed_atsu	0:e8bfffbb3ab6	881	* @brief Set the Base Priority value
lynxeyed_atsu	0:e8bfffbb3ab6	882	*
lynxeyed_atsu	0:e8bfffbb3ab6	883	* @param basePri BasePriority
lynxeyed_atsu	0:e8bfffbb3ab6	884	*
lynxeyed_atsu	0:e8bfffbb3ab6	885	* Set the base priority register
lynxeyed_atsu	0:e8bfffbb3ab6	886	*/
lynxeyed_atsu	0:e8bfffbb3ab6	887	extern void __set_BASEPRI(uint32_t basePri);
lynxeyed_atsu	0:e8bfffbb3ab6	888
lynxeyed_atsu	0:e8bfffbb3ab6	889	/**
lynxeyed_atsu	0:e8bfffbb3ab6	890	* @brief Return the Priority Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	891	*
lynxeyed_atsu	0:e8bfffbb3ab6	892	* @return PriMask
lynxeyed_atsu	0:e8bfffbb3ab6	893	*
lynxeyed_atsu	0:e8bfffbb3ab6	894	* Return state of the priority mask bit from the priority mask register
lynxeyed_atsu	0:e8bfffbb3ab6	895	*/
lynxeyed_atsu	0:e8bfffbb3ab6	896	extern uint32_t __get_PRIMASK(void);
lynxeyed_atsu	0:e8bfffbb3ab6	897
lynxeyed_atsu	0:e8bfffbb3ab6	898	/**
lynxeyed_atsu	0:e8bfffbb3ab6	899	* @brief Set the Priority Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	900	*
lynxeyed_atsu	0:e8bfffbb3ab6	901	* @param priMask PriMask
lynxeyed_atsu	0:e8bfffbb3ab6	902	*
lynxeyed_atsu	0:e8bfffbb3ab6	903	* Set the priority mask bit in the priority mask register
lynxeyed_atsu	0:e8bfffbb3ab6	904	*/
lynxeyed_atsu	0:e8bfffbb3ab6	905	extern void __set_PRIMASK(uint32_t priMask);
lynxeyed_atsu	0:e8bfffbb3ab6	906
lynxeyed_atsu	0:e8bfffbb3ab6	907	/**
lynxeyed_atsu	0:e8bfffbb3ab6	908	* @brief Return the Fault Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	909	*
lynxeyed_atsu	0:e8bfffbb3ab6	910	* @return FaultMask
lynxeyed_atsu	0:e8bfffbb3ab6	911	*
lynxeyed_atsu	0:e8bfffbb3ab6	912	* Return the content of the fault mask register
lynxeyed_atsu	0:e8bfffbb3ab6	913	*/
lynxeyed_atsu	0:e8bfffbb3ab6	914	extern uint32_t __get_FAULTMASK(void);
lynxeyed_atsu	0:e8bfffbb3ab6	915
lynxeyed_atsu	0:e8bfffbb3ab6	916	/**
lynxeyed_atsu	0:e8bfffbb3ab6	917	* @brief Set the Fault Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	918	*
lynxeyed_atsu	0:e8bfffbb3ab6	919	* @param faultMask faultMask value
lynxeyed_atsu	0:e8bfffbb3ab6	920	*
lynxeyed_atsu	0:e8bfffbb3ab6	921	* Set the fault mask register
lynxeyed_atsu	0:e8bfffbb3ab6	922	*/
lynxeyed_atsu	0:e8bfffbb3ab6	923	extern void __set_FAULTMASK(uint32_t faultMask);
lynxeyed_atsu	0:e8bfffbb3ab6	924
lynxeyed_atsu	0:e8bfffbb3ab6	925	/**
lynxeyed_atsu	0:e8bfffbb3ab6	926	* @brief Return the Control Register value
lynxeyed_atsu	0:e8bfffbb3ab6	927	*
lynxeyed_atsu	0:e8bfffbb3ab6	928	* @return Control value
lynxeyed_atsu	0:e8bfffbb3ab6	929	*
lynxeyed_atsu	0:e8bfffbb3ab6	930	* Return the content of the control register
lynxeyed_atsu	0:e8bfffbb3ab6	931	*/
lynxeyed_atsu	0:e8bfffbb3ab6	932	extern uint32_t __get_CONTROL(void);
lynxeyed_atsu	0:e8bfffbb3ab6	933
lynxeyed_atsu	0:e8bfffbb3ab6	934	/**
lynxeyed_atsu	0:e8bfffbb3ab6	935	* @brief Set the Control Register value
lynxeyed_atsu	0:e8bfffbb3ab6	936	*
lynxeyed_atsu	0:e8bfffbb3ab6	937	* @param control Control value
lynxeyed_atsu	0:e8bfffbb3ab6	938	*
lynxeyed_atsu	0:e8bfffbb3ab6	939	* Set the control register
lynxeyed_atsu	0:e8bfffbb3ab6	940	*/
lynxeyed_atsu	0:e8bfffbb3ab6	941	extern void __set_CONTROL(uint32_t control);
lynxeyed_atsu	0:e8bfffbb3ab6	942
lynxeyed_atsu	0:e8bfffbb3ab6	943	#else /* (__ARMCC_VERSION >= 400000) */
lynxeyed_atsu	0:e8bfffbb3ab6	944
lynxeyed_atsu	0:e8bfffbb3ab6	945	/**
lynxeyed_atsu	0:e8bfffbb3ab6	946	* @brief Remove the exclusive lock created by ldrex
lynxeyed_atsu	0:e8bfffbb3ab6	947	*
lynxeyed_atsu	0:e8bfffbb3ab6	948	* Removes the exclusive lock which is created by ldrex.
lynxeyed_atsu	0:e8bfffbb3ab6	949	*/
lynxeyed_atsu	0:e8bfffbb3ab6	950	#define __CLREX __clrex
lynxeyed_atsu	0:e8bfffbb3ab6	951
lynxeyed_atsu	0:e8bfffbb3ab6	952	/**
lynxeyed_atsu	0:e8bfffbb3ab6	953	* @brief Return the Base Priority value
lynxeyed_atsu	0:e8bfffbb3ab6	954	*
lynxeyed_atsu	0:e8bfffbb3ab6	955	* @return BasePriority
lynxeyed_atsu	0:e8bfffbb3ab6	956	*
lynxeyed_atsu	0:e8bfffbb3ab6	957	* Return the content of the base priority register
lynxeyed_atsu	0:e8bfffbb3ab6	958	*/
lynxeyed_atsu	0:e8bfffbb3ab6	959	static __INLINE uint32_t __get_BASEPRI(void)
lynxeyed_atsu	0:e8bfffbb3ab6	960	{
lynxeyed_atsu	0:e8bfffbb3ab6	961	register uint32_t __regBasePri __ASM("basepri");
lynxeyed_atsu	0:e8bfffbb3ab6	962	return(__regBasePri);
lynxeyed_atsu	0:e8bfffbb3ab6	963	}
lynxeyed_atsu	0:e8bfffbb3ab6	964
lynxeyed_atsu	0:e8bfffbb3ab6	965	/**
lynxeyed_atsu	0:e8bfffbb3ab6	966	* @brief Set the Base Priority value
lynxeyed_atsu	0:e8bfffbb3ab6	967	*
lynxeyed_atsu	0:e8bfffbb3ab6	968	* @param basePri BasePriority
lynxeyed_atsu	0:e8bfffbb3ab6	969	*
lynxeyed_atsu	0:e8bfffbb3ab6	970	* Set the base priority register
lynxeyed_atsu	0:e8bfffbb3ab6	971	*/
lynxeyed_atsu	0:e8bfffbb3ab6	972	static __INLINE void __set_BASEPRI(uint32_t basePri)
lynxeyed_atsu	0:e8bfffbb3ab6	973	{
lynxeyed_atsu	0:e8bfffbb3ab6	974	register uint32_t __regBasePri __ASM("basepri");
lynxeyed_atsu	0:e8bfffbb3ab6	975	__regBasePri = (basePri & 0xff);
lynxeyed_atsu	0:e8bfffbb3ab6	976	}
lynxeyed_atsu	0:e8bfffbb3ab6	977
lynxeyed_atsu	0:e8bfffbb3ab6	978	/**
lynxeyed_atsu	0:e8bfffbb3ab6	979	* @brief Return the Priority Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	980	*
lynxeyed_atsu	0:e8bfffbb3ab6	981	* @return PriMask
lynxeyed_atsu	0:e8bfffbb3ab6	982	*
lynxeyed_atsu	0:e8bfffbb3ab6	983	* Return state of the priority mask bit from the priority mask register
lynxeyed_atsu	0:e8bfffbb3ab6	984	*/
lynxeyed_atsu	0:e8bfffbb3ab6	985	static __INLINE uint32_t __get_PRIMASK(void)
lynxeyed_atsu	0:e8bfffbb3ab6	986	{
lynxeyed_atsu	0:e8bfffbb3ab6	987	register uint32_t __regPriMask __ASM("primask");
lynxeyed_atsu	0:e8bfffbb3ab6	988	return(__regPriMask);
lynxeyed_atsu	0:e8bfffbb3ab6	989	}
lynxeyed_atsu	0:e8bfffbb3ab6	990
lynxeyed_atsu	0:e8bfffbb3ab6	991	/**
lynxeyed_atsu	0:e8bfffbb3ab6	992	* @brief Set the Priority Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	993	*
lynxeyed_atsu	0:e8bfffbb3ab6	994	* @param priMask PriMask
lynxeyed_atsu	0:e8bfffbb3ab6	995	*
lynxeyed_atsu	0:e8bfffbb3ab6	996	* Set the priority mask bit in the priority mask register
lynxeyed_atsu	0:e8bfffbb3ab6	997	*/
lynxeyed_atsu	0:e8bfffbb3ab6	998	static __INLINE void __set_PRIMASK(uint32_t priMask)
lynxeyed_atsu	0:e8bfffbb3ab6	999	{
lynxeyed_atsu	0:e8bfffbb3ab6	1000	register uint32_t __regPriMask __ASM("primask");
lynxeyed_atsu	0:e8bfffbb3ab6	1001	__regPriMask = (priMask);
lynxeyed_atsu	0:e8bfffbb3ab6	1002	}
lynxeyed_atsu	0:e8bfffbb3ab6	1003
lynxeyed_atsu	0:e8bfffbb3ab6	1004	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1005	* @brief Return the Fault Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	1006	*
lynxeyed_atsu	0:e8bfffbb3ab6	1007	* @return FaultMask
lynxeyed_atsu	0:e8bfffbb3ab6	1008	*
lynxeyed_atsu	0:e8bfffbb3ab6	1009	* Return the content of the fault mask register
lynxeyed_atsu	0:e8bfffbb3ab6	1010	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1011	static __INLINE uint32_t __get_FAULTMASK(void)
lynxeyed_atsu	0:e8bfffbb3ab6	1012	{
lynxeyed_atsu	0:e8bfffbb3ab6	1013	register uint32_t __regFaultMask __ASM("faultmask");
lynxeyed_atsu	0:e8bfffbb3ab6	1014	return(__regFaultMask);
lynxeyed_atsu	0:e8bfffbb3ab6	1015	}
lynxeyed_atsu	0:e8bfffbb3ab6	1016
lynxeyed_atsu	0:e8bfffbb3ab6	1017	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1018	* @brief Set the Fault Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	1019	*
lynxeyed_atsu	0:e8bfffbb3ab6	1020	* @param faultMask faultMask value
lynxeyed_atsu	0:e8bfffbb3ab6	1021	*
lynxeyed_atsu	0:e8bfffbb3ab6	1022	* Set the fault mask register
lynxeyed_atsu	0:e8bfffbb3ab6	1023	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1024	static __INLINE void __set_FAULTMASK(uint32_t faultMask)
lynxeyed_atsu	0:e8bfffbb3ab6	1025	{
lynxeyed_atsu	0:e8bfffbb3ab6	1026	register uint32_t __regFaultMask __ASM("faultmask");
lynxeyed_atsu	0:e8bfffbb3ab6	1027	__regFaultMask = (faultMask & 1);
lynxeyed_atsu	0:e8bfffbb3ab6	1028	}
lynxeyed_atsu	0:e8bfffbb3ab6	1029
lynxeyed_atsu	0:e8bfffbb3ab6	1030	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1031	* @brief Return the Control Register value
lynxeyed_atsu	0:e8bfffbb3ab6	1032	*
lynxeyed_atsu	0:e8bfffbb3ab6	1033	* @return Control value
lynxeyed_atsu	0:e8bfffbb3ab6	1034	*
lynxeyed_atsu	0:e8bfffbb3ab6	1035	* Return the content of the control register
lynxeyed_atsu	0:e8bfffbb3ab6	1036	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1037	static __INLINE uint32_t __get_CONTROL(void)
lynxeyed_atsu	0:e8bfffbb3ab6	1038	{
lynxeyed_atsu	0:e8bfffbb3ab6	1039	register uint32_t __regControl __ASM("control");
lynxeyed_atsu	0:e8bfffbb3ab6	1040	return(__regControl);
lynxeyed_atsu	0:e8bfffbb3ab6	1041	}
lynxeyed_atsu	0:e8bfffbb3ab6	1042
lynxeyed_atsu	0:e8bfffbb3ab6	1043	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1044	* @brief Set the Control Register value
lynxeyed_atsu	0:e8bfffbb3ab6	1045	*
lynxeyed_atsu	0:e8bfffbb3ab6	1046	* @param control Control value
lynxeyed_atsu	0:e8bfffbb3ab6	1047	*
lynxeyed_atsu	0:e8bfffbb3ab6	1048	* Set the control register
lynxeyed_atsu	0:e8bfffbb3ab6	1049	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1050	static __INLINE void __set_CONTROL(uint32_t control)
lynxeyed_atsu	0:e8bfffbb3ab6	1051	{
lynxeyed_atsu	0:e8bfffbb3ab6	1052	register uint32_t __regControl __ASM("control");
lynxeyed_atsu	0:e8bfffbb3ab6	1053	__regControl = control;
lynxeyed_atsu	0:e8bfffbb3ab6	1054	}
lynxeyed_atsu	0:e8bfffbb3ab6	1055
lynxeyed_atsu	0:e8bfffbb3ab6	1056	#endif /* __ARMCC_VERSION */
lynxeyed_atsu	0:e8bfffbb3ab6	1057
lynxeyed_atsu	0:e8bfffbb3ab6	1058
lynxeyed_atsu	0:e8bfffbb3ab6	1059
lynxeyed_atsu	0:e8bfffbb3ab6	1060	#elif (defined (__ICCARM__)) /------------------ ICC Compiler -------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	1061	/* IAR iccarm specific functions */
lynxeyed_atsu	0:e8bfffbb3ab6	1062
lynxeyed_atsu	0:e8bfffbb3ab6	1063	#define __enable_irq __enable_interrupt /!< global Interrupt enable /
lynxeyed_atsu	0:e8bfffbb3ab6	1064	#define __disable_irq __disable_interrupt /!< global Interrupt disable /
lynxeyed_atsu	0:e8bfffbb3ab6	1065
lynxeyed_atsu	0:e8bfffbb3ab6	1066	static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1067	static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1068
lynxeyed_atsu	0:e8bfffbb3ab6	1069	#define __NOP __no_operation /!< no operation intrinsic in IAR Compiler /
lynxeyed_atsu	0:e8bfffbb3ab6	1070	static __INLINE void __WFI() { __ASM ("wfi"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1071	static __INLINE void __WFE() { __ASM ("wfe"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1072	static __INLINE void __SEV() { __ASM ("sev"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1073	static __INLINE void __CLREX() { __ASM ("clrex"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1074
lynxeyed_atsu	0:e8bfffbb3ab6	1075	/* intrinsic void __ISB(void) */
lynxeyed_atsu	0:e8bfffbb3ab6	1076	/* intrinsic void __DSB(void) */
lynxeyed_atsu	0:e8bfffbb3ab6	1077	/* intrinsic void __DMB(void) */
lynxeyed_atsu	0:e8bfffbb3ab6	1078	/* intrinsic void __set_PRIMASK(); */
lynxeyed_atsu	0:e8bfffbb3ab6	1079	/* intrinsic void __get_PRIMASK(); */
lynxeyed_atsu	0:e8bfffbb3ab6	1080	/* intrinsic void __set_FAULTMASK(); */
lynxeyed_atsu	0:e8bfffbb3ab6	1081	/* intrinsic void __get_FAULTMASK(); */
lynxeyed_atsu	0:e8bfffbb3ab6	1082	/* intrinsic uint32_t __REV(uint32_t value); */
lynxeyed_atsu	0:e8bfffbb3ab6	1083	/* intrinsic uint32_t __REVSH(uint32_t value); */
lynxeyed_atsu	0:e8bfffbb3ab6	1084	/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
lynxeyed_atsu	0:e8bfffbb3ab6	1085	/* intrinsic unsigned long __LDREX(unsigned long ); /
lynxeyed_atsu	0:e8bfffbb3ab6	1086
lynxeyed_atsu	0:e8bfffbb3ab6	1087
lynxeyed_atsu	0:e8bfffbb3ab6	1088	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1089	* @brief Return the Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1090	*
lynxeyed_atsu	0:e8bfffbb3ab6	1091	* @return ProcessStackPointer
lynxeyed_atsu	0:e8bfffbb3ab6	1092	*
lynxeyed_atsu	0:e8bfffbb3ab6	1093	* Return the actual process stack pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1094	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1095	extern uint32_t __get_PSP(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1096
lynxeyed_atsu	0:e8bfffbb3ab6	1097	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1098	* @brief Set the Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1099	*
lynxeyed_atsu	0:e8bfffbb3ab6	1100	* @param topOfProcStack Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1101	*
lynxeyed_atsu	0:e8bfffbb3ab6	1102	* Assign the value ProcessStackPointer to the MSP
lynxeyed_atsu	0:e8bfffbb3ab6	1103	* (process stack pointer) Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	1104	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1105	extern void __set_PSP(uint32_t topOfProcStack);
lynxeyed_atsu	0:e8bfffbb3ab6	1106
lynxeyed_atsu	0:e8bfffbb3ab6	1107	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1108	* @brief Return the Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1109	*
lynxeyed_atsu	0:e8bfffbb3ab6	1110	* @return Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1111	*
lynxeyed_atsu	0:e8bfffbb3ab6	1112	* Return the current value of the MSP (main stack pointer)
lynxeyed_atsu	0:e8bfffbb3ab6	1113	* Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	1114	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1115	extern uint32_t __get_MSP(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1116
lynxeyed_atsu	0:e8bfffbb3ab6	1117	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1118	* @brief Set the Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1119	*
lynxeyed_atsu	0:e8bfffbb3ab6	1120	* @param topOfMainStack Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1121	*
lynxeyed_atsu	0:e8bfffbb3ab6	1122	* Assign the value mainStackPointer to the MSP
lynxeyed_atsu	0:e8bfffbb3ab6	1123	* (main stack pointer) Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	1124	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1125	extern void __set_MSP(uint32_t topOfMainStack);
lynxeyed_atsu	0:e8bfffbb3ab6	1126
lynxeyed_atsu	0:e8bfffbb3ab6	1127	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1128	* @brief Reverse byte order in unsigned short value
lynxeyed_atsu	0:e8bfffbb3ab6	1129	*
lynxeyed_atsu	0:e8bfffbb3ab6	1130	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	1131	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	1132	*
lynxeyed_atsu	0:e8bfffbb3ab6	1133	* Reverse byte order in unsigned short value
lynxeyed_atsu	0:e8bfffbb3ab6	1134	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1135	extern uint32_t __REV16(uint16_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	1136
lynxeyed_atsu	0:e8bfffbb3ab6	1137	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1138	* @brief Reverse bit order of value
lynxeyed_atsu	0:e8bfffbb3ab6	1139	*
lynxeyed_atsu	0:e8bfffbb3ab6	1140	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	1141	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	1142	*
lynxeyed_atsu	0:e8bfffbb3ab6	1143	* Reverse bit order of value
lynxeyed_atsu	0:e8bfffbb3ab6	1144	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1145	extern uint32_t __RBIT(uint32_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	1146
lynxeyed_atsu	0:e8bfffbb3ab6	1147	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1148	* @brief LDR Exclusive (8 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1149	*
lynxeyed_atsu	0:e8bfffbb3ab6	1150	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1151	* @return value of (*address)
lynxeyed_atsu	0:e8bfffbb3ab6	1152	*
lynxeyed_atsu	0:e8bfffbb3ab6	1153	* Exclusive LDR command for 8 bit values)
lynxeyed_atsu	0:e8bfffbb3ab6	1154	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1155	extern uint8_t __LDREXB(uint8_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1156
lynxeyed_atsu	0:e8bfffbb3ab6	1157	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1158	* @brief LDR Exclusive (16 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1159	*
lynxeyed_atsu	0:e8bfffbb3ab6	1160	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1161	* @return value of (*address)
lynxeyed_atsu	0:e8bfffbb3ab6	1162	*
lynxeyed_atsu	0:e8bfffbb3ab6	1163	* Exclusive LDR command for 16 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1164	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1165	extern uint16_t __LDREXH(uint16_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1166
lynxeyed_atsu	0:e8bfffbb3ab6	1167	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1168	* @brief LDR Exclusive (32 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1169	*
lynxeyed_atsu	0:e8bfffbb3ab6	1170	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1171	* @return value of (*address)
lynxeyed_atsu	0:e8bfffbb3ab6	1172	*
lynxeyed_atsu	0:e8bfffbb3ab6	1173	* Exclusive LDR command for 32 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1174	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1175	extern uint32_t __LDREXW(uint32_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1176
lynxeyed_atsu	0:e8bfffbb3ab6	1177	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1178	* @brief STR Exclusive (8 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1179	*
lynxeyed_atsu	0:e8bfffbb3ab6	1180	* @param value value to store
lynxeyed_atsu	0:e8bfffbb3ab6	1181	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1182	* @return successful / failed
lynxeyed_atsu	0:e8bfffbb3ab6	1183	*
lynxeyed_atsu	0:e8bfffbb3ab6	1184	* Exclusive STR command for 8 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1185	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1186	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1187
lynxeyed_atsu	0:e8bfffbb3ab6	1188	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1189	* @brief STR Exclusive (16 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1190	*
lynxeyed_atsu	0:e8bfffbb3ab6	1191	* @param value value to store
lynxeyed_atsu	0:e8bfffbb3ab6	1192	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1193	* @return successful / failed
lynxeyed_atsu	0:e8bfffbb3ab6	1194	*
lynxeyed_atsu	0:e8bfffbb3ab6	1195	* Exclusive STR command for 16 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1196	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1197	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1198
lynxeyed_atsu	0:e8bfffbb3ab6	1199	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1200	* @brief STR Exclusive (32 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1201	*
lynxeyed_atsu	0:e8bfffbb3ab6	1202	* @param value value to store
lynxeyed_atsu	0:e8bfffbb3ab6	1203	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1204	* @return successful / failed
lynxeyed_atsu	0:e8bfffbb3ab6	1205	*
lynxeyed_atsu	0:e8bfffbb3ab6	1206	* Exclusive STR command for 32 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1207	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1208	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1209
lynxeyed_atsu	0:e8bfffbb3ab6	1210
lynxeyed_atsu	0:e8bfffbb3ab6	1211
lynxeyed_atsu	0:e8bfffbb3ab6	1212	#elif (defined (__GNUC__)) /------------------ GNU Compiler ---------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	1213	/* GNU gcc specific functions */
lynxeyed_atsu	0:e8bfffbb3ab6	1214
lynxeyed_atsu	0:e8bfffbb3ab6	1215	static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1216	static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1217
lynxeyed_atsu	0:e8bfffbb3ab6	1218	static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1219	static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1220
lynxeyed_atsu	0:e8bfffbb3ab6	1221	static __INLINE void __NOP() { __ASM volatile ("nop"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1222	static __INLINE void __WFI() { __ASM volatile ("wfi"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1223	static __INLINE void __WFE() { __ASM volatile ("wfe"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1224	static __INLINE void __SEV() { __ASM volatile ("sev"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1225	static __INLINE void __ISB() { __ASM volatile ("isb"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1226	static __INLINE void __DSB() { __ASM volatile ("dsb"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1227	static __INLINE void __DMB() { __ASM volatile ("dmb"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1228	static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
lynxeyed_atsu	0:e8bfffbb3ab6	1229
lynxeyed_atsu	0:e8bfffbb3ab6	1230
lynxeyed_atsu	0:e8bfffbb3ab6	1231	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1232	* @brief Return the Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1233	*
lynxeyed_atsu	0:e8bfffbb3ab6	1234	* @return ProcessStackPointer
lynxeyed_atsu	0:e8bfffbb3ab6	1235	*
lynxeyed_atsu	0:e8bfffbb3ab6	1236	* Return the actual process stack pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1237	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1238	extern uint32_t __get_PSP(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1239
lynxeyed_atsu	0:e8bfffbb3ab6	1240	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1241	* @brief Set the Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1242	*
lynxeyed_atsu	0:e8bfffbb3ab6	1243	* @param topOfProcStack Process Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1244	*
lynxeyed_atsu	0:e8bfffbb3ab6	1245	* Assign the value ProcessStackPointer to the MSP
lynxeyed_atsu	0:e8bfffbb3ab6	1246	* (process stack pointer) Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	1247	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1248	extern void __set_PSP(uint32_t topOfProcStack);
lynxeyed_atsu	0:e8bfffbb3ab6	1249
lynxeyed_atsu	0:e8bfffbb3ab6	1250	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1251	* @brief Return the Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1252	*
lynxeyed_atsu	0:e8bfffbb3ab6	1253	* @return Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1254	*
lynxeyed_atsu	0:e8bfffbb3ab6	1255	* Return the current value of the MSP (main stack pointer)
lynxeyed_atsu	0:e8bfffbb3ab6	1256	* Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	1257	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1258	extern uint32_t __get_MSP(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1259
lynxeyed_atsu	0:e8bfffbb3ab6	1260	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1261	* @brief Set the Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1262	*
lynxeyed_atsu	0:e8bfffbb3ab6	1263	* @param topOfMainStack Main Stack Pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1264	*
lynxeyed_atsu	0:e8bfffbb3ab6	1265	* Assign the value mainStackPointer to the MSP
lynxeyed_atsu	0:e8bfffbb3ab6	1266	* (main stack pointer) Cortex processor register
lynxeyed_atsu	0:e8bfffbb3ab6	1267	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1268	extern void __set_MSP(uint32_t topOfMainStack);
lynxeyed_atsu	0:e8bfffbb3ab6	1269
lynxeyed_atsu	0:e8bfffbb3ab6	1270	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1271	* @brief Return the Base Priority value
lynxeyed_atsu	0:e8bfffbb3ab6	1272	*
lynxeyed_atsu	0:e8bfffbb3ab6	1273	* @return BasePriority
lynxeyed_atsu	0:e8bfffbb3ab6	1274	*
lynxeyed_atsu	0:e8bfffbb3ab6	1275	* Return the content of the base priority register
lynxeyed_atsu	0:e8bfffbb3ab6	1276	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1277	extern uint32_t __get_BASEPRI(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1278
lynxeyed_atsu	0:e8bfffbb3ab6	1279	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1280	* @brief Set the Base Priority value
lynxeyed_atsu	0:e8bfffbb3ab6	1281	*
lynxeyed_atsu	0:e8bfffbb3ab6	1282	* @param basePri BasePriority
lynxeyed_atsu	0:e8bfffbb3ab6	1283	*
lynxeyed_atsu	0:e8bfffbb3ab6	1284	* Set the base priority register
lynxeyed_atsu	0:e8bfffbb3ab6	1285	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1286	extern void __set_BASEPRI(uint32_t basePri);
lynxeyed_atsu	0:e8bfffbb3ab6	1287
lynxeyed_atsu	0:e8bfffbb3ab6	1288	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1289	* @brief Return the Priority Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	1290	*
lynxeyed_atsu	0:e8bfffbb3ab6	1291	* @return PriMask
lynxeyed_atsu	0:e8bfffbb3ab6	1292	*
lynxeyed_atsu	0:e8bfffbb3ab6	1293	* Return state of the priority mask bit from the priority mask register
lynxeyed_atsu	0:e8bfffbb3ab6	1294	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1295	extern uint32_t __get_PRIMASK(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1296
lynxeyed_atsu	0:e8bfffbb3ab6	1297	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1298	* @brief Set the Priority Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	1299	*
lynxeyed_atsu	0:e8bfffbb3ab6	1300	* @param priMask PriMask
lynxeyed_atsu	0:e8bfffbb3ab6	1301	*
lynxeyed_atsu	0:e8bfffbb3ab6	1302	* Set the priority mask bit in the priority mask register
lynxeyed_atsu	0:e8bfffbb3ab6	1303	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1304	extern void __set_PRIMASK(uint32_t priMask);
lynxeyed_atsu	0:e8bfffbb3ab6	1305
lynxeyed_atsu	0:e8bfffbb3ab6	1306	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1307	* @brief Return the Fault Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	1308	*
lynxeyed_atsu	0:e8bfffbb3ab6	1309	* @return FaultMask
lynxeyed_atsu	0:e8bfffbb3ab6	1310	*
lynxeyed_atsu	0:e8bfffbb3ab6	1311	* Return the content of the fault mask register
lynxeyed_atsu	0:e8bfffbb3ab6	1312	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1313	extern uint32_t __get_FAULTMASK(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1314
lynxeyed_atsu	0:e8bfffbb3ab6	1315	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1316	* @brief Set the Fault Mask value
lynxeyed_atsu	0:e8bfffbb3ab6	1317	*
lynxeyed_atsu	0:e8bfffbb3ab6	1318	* @param faultMask faultMask value
lynxeyed_atsu	0:e8bfffbb3ab6	1319	*
lynxeyed_atsu	0:e8bfffbb3ab6	1320	* Set the fault mask register
lynxeyed_atsu	0:e8bfffbb3ab6	1321	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1322	extern void __set_FAULTMASK(uint32_t faultMask);
lynxeyed_atsu	0:e8bfffbb3ab6	1323
lynxeyed_atsu	0:e8bfffbb3ab6	1324	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1325	* @brief Return the Control Register value
lynxeyed_atsu	0:e8bfffbb3ab6	1326	*
lynxeyed_atsu	0:e8bfffbb3ab6	1327	* @return Control value
lynxeyed_atsu	0:e8bfffbb3ab6	1328	*
lynxeyed_atsu	0:e8bfffbb3ab6	1329	* Return the content of the control register
lynxeyed_atsu	0:e8bfffbb3ab6	1330	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1331	extern uint32_t __get_CONTROL(void);
lynxeyed_atsu	0:e8bfffbb3ab6	1332
lynxeyed_atsu	0:e8bfffbb3ab6	1333	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1334	* @brief Set the Control Register value
lynxeyed_atsu	0:e8bfffbb3ab6	1335	*
lynxeyed_atsu	0:e8bfffbb3ab6	1336	* @param control Control value
lynxeyed_atsu	0:e8bfffbb3ab6	1337	*
lynxeyed_atsu	0:e8bfffbb3ab6	1338	* Set the control register
lynxeyed_atsu	0:e8bfffbb3ab6	1339	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1340	extern void __set_CONTROL(uint32_t control);
lynxeyed_atsu	0:e8bfffbb3ab6	1341
lynxeyed_atsu	0:e8bfffbb3ab6	1342	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1343	* @brief Reverse byte order in integer value
lynxeyed_atsu	0:e8bfffbb3ab6	1344	*
lynxeyed_atsu	0:e8bfffbb3ab6	1345	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	1346	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	1347	*
lynxeyed_atsu	0:e8bfffbb3ab6	1348	* Reverse byte order in integer value
lynxeyed_atsu	0:e8bfffbb3ab6	1349	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1350	extern uint32_t __REV(uint32_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	1351
lynxeyed_atsu	0:e8bfffbb3ab6	1352	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1353	* @brief Reverse byte order in unsigned short value
lynxeyed_atsu	0:e8bfffbb3ab6	1354	*
lynxeyed_atsu	0:e8bfffbb3ab6	1355	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	1356	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	1357	*
lynxeyed_atsu	0:e8bfffbb3ab6	1358	* Reverse byte order in unsigned short value
lynxeyed_atsu	0:e8bfffbb3ab6	1359	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1360	extern uint32_t __REV16(uint16_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	1361
lynxeyed_atsu	0:e8bfffbb3ab6	1362	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1363	* @brief Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:e8bfffbb3ab6	1364	*
lynxeyed_atsu	0:e8bfffbb3ab6	1365	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	1366	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	1367	*
lynxeyed_atsu	0:e8bfffbb3ab6	1368	* Reverse byte order in signed short value with sign extension to integer
lynxeyed_atsu	0:e8bfffbb3ab6	1369	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1370	extern int32_t __REVSH(int16_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	1371
lynxeyed_atsu	0:e8bfffbb3ab6	1372	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1373	* @brief Reverse bit order of value
lynxeyed_atsu	0:e8bfffbb3ab6	1374	*
lynxeyed_atsu	0:e8bfffbb3ab6	1375	* @param value value to reverse
lynxeyed_atsu	0:e8bfffbb3ab6	1376	* @return reversed value
lynxeyed_atsu	0:e8bfffbb3ab6	1377	*
lynxeyed_atsu	0:e8bfffbb3ab6	1378	* Reverse bit order of value
lynxeyed_atsu	0:e8bfffbb3ab6	1379	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1380	extern uint32_t __RBIT(uint32_t value);
lynxeyed_atsu	0:e8bfffbb3ab6	1381
lynxeyed_atsu	0:e8bfffbb3ab6	1382	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1383	* @brief LDR Exclusive (8 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1384	*
lynxeyed_atsu	0:e8bfffbb3ab6	1385	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1386	* @return value of (*address)
lynxeyed_atsu	0:e8bfffbb3ab6	1387	*
lynxeyed_atsu	0:e8bfffbb3ab6	1388	* Exclusive LDR command for 8 bit value
lynxeyed_atsu	0:e8bfffbb3ab6	1389	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1390	extern uint8_t __LDREXB(uint8_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1391
lynxeyed_atsu	0:e8bfffbb3ab6	1392	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1393	* @brief LDR Exclusive (16 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1394	*
lynxeyed_atsu	0:e8bfffbb3ab6	1395	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1396	* @return value of (*address)
lynxeyed_atsu	0:e8bfffbb3ab6	1397	*
lynxeyed_atsu	0:e8bfffbb3ab6	1398	* Exclusive LDR command for 16 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1399	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1400	extern uint16_t __LDREXH(uint16_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1401
lynxeyed_atsu	0:e8bfffbb3ab6	1402	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1403	* @brief LDR Exclusive (32 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1404	*
lynxeyed_atsu	0:e8bfffbb3ab6	1405	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1406	* @return value of (*address)
lynxeyed_atsu	0:e8bfffbb3ab6	1407	*
lynxeyed_atsu	0:e8bfffbb3ab6	1408	* Exclusive LDR command for 32 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1409	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1410	extern uint32_t __LDREXW(uint32_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1411
lynxeyed_atsu	0:e8bfffbb3ab6	1412	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1413	* @brief STR Exclusive (8 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1414	*
lynxeyed_atsu	0:e8bfffbb3ab6	1415	* @param value value to store
lynxeyed_atsu	0:e8bfffbb3ab6	1416	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1417	* @return successful / failed
lynxeyed_atsu	0:e8bfffbb3ab6	1418	*
lynxeyed_atsu	0:e8bfffbb3ab6	1419	* Exclusive STR command for 8 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1420	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1421	extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1422
lynxeyed_atsu	0:e8bfffbb3ab6	1423	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1424	* @brief STR Exclusive (16 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1425	*
lynxeyed_atsu	0:e8bfffbb3ab6	1426	* @param value value to store
lynxeyed_atsu	0:e8bfffbb3ab6	1427	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1428	* @return successful / failed
lynxeyed_atsu	0:e8bfffbb3ab6	1429	*
lynxeyed_atsu	0:e8bfffbb3ab6	1430	* Exclusive STR command for 16 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1431	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1432	extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1433
lynxeyed_atsu	0:e8bfffbb3ab6	1434	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1435	* @brief STR Exclusive (32 bit)
lynxeyed_atsu	0:e8bfffbb3ab6	1436	*
lynxeyed_atsu	0:e8bfffbb3ab6	1437	* @param value value to store
lynxeyed_atsu	0:e8bfffbb3ab6	1438	* @param *addr address pointer
lynxeyed_atsu	0:e8bfffbb3ab6	1439	* @return successful / failed
lynxeyed_atsu	0:e8bfffbb3ab6	1440	*
lynxeyed_atsu	0:e8bfffbb3ab6	1441	* Exclusive STR command for 32 bit values
lynxeyed_atsu	0:e8bfffbb3ab6	1442	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1443	extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
lynxeyed_atsu	0:e8bfffbb3ab6	1444
lynxeyed_atsu	0:e8bfffbb3ab6	1445
lynxeyed_atsu	0:e8bfffbb3ab6	1446	#elif (defined (__TASKING__)) /------------------ TASKING Compiler ---------------------/
lynxeyed_atsu	0:e8bfffbb3ab6	1447	/* TASKING carm specific functions */
lynxeyed_atsu	0:e8bfffbb3ab6	1448
lynxeyed_atsu	0:e8bfffbb3ab6	1449	/*
lynxeyed_atsu	0:e8bfffbb3ab6	1450	* The CMSIS functions have been implemented as intrinsics in the compiler.
lynxeyed_atsu	0:e8bfffbb3ab6	1451	* Please use "carm -?i" to get an up to date list of all instrinsics,
lynxeyed_atsu	0:e8bfffbb3ab6	1452	* Including the CMSIS ones.
lynxeyed_atsu	0:e8bfffbb3ab6	1453	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1454
lynxeyed_atsu	0:e8bfffbb3ab6	1455	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	1456
lynxeyed_atsu	0:e8bfffbb3ab6	1457
lynxeyed_atsu	0:e8bfffbb3ab6	1458	/** @addtogroup CMSIS_CM3_Core_FunctionInterface CMSIS CM3 Core Function Interface
lynxeyed_atsu	0:e8bfffbb3ab6	1459	Core Function Interface containing:
lynxeyed_atsu	0:e8bfffbb3ab6	1460	- Core NVIC Functions
lynxeyed_atsu	0:e8bfffbb3ab6	1461	- Core SysTick Functions
lynxeyed_atsu	0:e8bfffbb3ab6	1462	- Core Reset Functions
lynxeyed_atsu	0:e8bfffbb3ab6	1463	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1464	/@{/
lynxeyed_atsu	0:e8bfffbb3ab6	1465
lynxeyed_atsu	0:e8bfffbb3ab6	1466
lynxeyed_atsu	0:e8bfffbb3ab6	1467	/* ########################## NVIC functions #################################### */
lynxeyed_atsu	0:e8bfffbb3ab6	1468
lynxeyed_atsu	0:e8bfffbb3ab6	1469	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1470	* @brief Set the Priority Grouping in NVIC Interrupt Controller
lynxeyed_atsu	0:e8bfffbb3ab6	1471	*
lynxeyed_atsu	0:e8bfffbb3ab6	1472	* @param PriorityGroup is priority grouping field
lynxeyed_atsu	0:e8bfffbb3ab6	1473	*
lynxeyed_atsu	0:e8bfffbb3ab6	1474	* Set the priority grouping field using the required unlock sequence.
lynxeyed_atsu	0:e8bfffbb3ab6	1475	* The parameter priority_grouping is assigned to the field
lynxeyed_atsu	0:e8bfffbb3ab6	1476	* SCB->AIRCR [10:8] PRIGROUP field. Only values from 0..7 are used.
lynxeyed_atsu	0:e8bfffbb3ab6	1477	* In case of a conflict between priority grouping and available
lynxeyed_atsu	0:e8bfffbb3ab6	1478	* priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
lynxeyed_atsu	0:e8bfffbb3ab6	1479	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1480	static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
lynxeyed_atsu	0:e8bfffbb3ab6	1481	{
lynxeyed_atsu	0:e8bfffbb3ab6	1482	uint32_t reg_value;
lynxeyed_atsu	0:e8bfffbb3ab6	1483	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
lynxeyed_atsu	0:e8bfffbb3ab6	1484
lynxeyed_atsu	0:e8bfffbb3ab6	1485	reg_value = SCB->AIRCR; /* read old register configuration */
lynxeyed_atsu	0:e8bfffbb3ab6	1486	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
lynxeyed_atsu	0:e8bfffbb3ab6	1487	reg_value = (reg_value \|
lynxeyed_atsu	0:e8bfffbb3ab6	1488	(0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
lynxeyed_atsu	0:e8bfffbb3ab6	1489	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
lynxeyed_atsu	0:e8bfffbb3ab6	1490	SCB->AIRCR = reg_value;
lynxeyed_atsu	0:e8bfffbb3ab6	1491	}
lynxeyed_atsu	0:e8bfffbb3ab6	1492
lynxeyed_atsu	0:e8bfffbb3ab6	1493	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1494	* @brief Get the Priority Grouping from NVIC Interrupt Controller
lynxeyed_atsu	0:e8bfffbb3ab6	1495	*
lynxeyed_atsu	0:e8bfffbb3ab6	1496	* @return priority grouping field
lynxeyed_atsu	0:e8bfffbb3ab6	1497	*
lynxeyed_atsu	0:e8bfffbb3ab6	1498	* Get the priority grouping from NVIC Interrupt Controller.
lynxeyed_atsu	0:e8bfffbb3ab6	1499	* priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
lynxeyed_atsu	0:e8bfffbb3ab6	1500	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1501	static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
lynxeyed_atsu	0:e8bfffbb3ab6	1502	{
lynxeyed_atsu	0:e8bfffbb3ab6	1503	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
lynxeyed_atsu	0:e8bfffbb3ab6	1504	}
lynxeyed_atsu	0:e8bfffbb3ab6	1505
lynxeyed_atsu	0:e8bfffbb3ab6	1506	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1507	* @brief Enable Interrupt in NVIC Interrupt Controller
lynxeyed_atsu	0:e8bfffbb3ab6	1508	*
lynxeyed_atsu	0:e8bfffbb3ab6	1509	* @param IRQn The positive number of the external interrupt to enable
lynxeyed_atsu	0:e8bfffbb3ab6	1510	*
lynxeyed_atsu	0:e8bfffbb3ab6	1511	* Enable a device specific interupt in the NVIC interrupt controller.
lynxeyed_atsu	0:e8bfffbb3ab6	1512	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:e8bfffbb3ab6	1513	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1514	static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:e8bfffbb3ab6	1515	{
lynxeyed_atsu	0:e8bfffbb3ab6	1516	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
lynxeyed_atsu	0:e8bfffbb3ab6	1517	}
lynxeyed_atsu	0:e8bfffbb3ab6	1518
lynxeyed_atsu	0:e8bfffbb3ab6	1519	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1520	* @brief Disable the interrupt line for external interrupt specified
lynxeyed_atsu	0:e8bfffbb3ab6	1521	*
lynxeyed_atsu	0:e8bfffbb3ab6	1522	* @param IRQn The positive number of the external interrupt to disable
lynxeyed_atsu	0:e8bfffbb3ab6	1523	*
lynxeyed_atsu	0:e8bfffbb3ab6	1524	* Disable a device specific interupt in the NVIC interrupt controller.
lynxeyed_atsu	0:e8bfffbb3ab6	1525	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:e8bfffbb3ab6	1526	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1527	static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:e8bfffbb3ab6	1528	{
lynxeyed_atsu	0:e8bfffbb3ab6	1529	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
lynxeyed_atsu	0:e8bfffbb3ab6	1530	}
lynxeyed_atsu	0:e8bfffbb3ab6	1531
lynxeyed_atsu	0:e8bfffbb3ab6	1532	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1533	* @brief Read the interrupt pending bit for a device specific interrupt source
lynxeyed_atsu	0:e8bfffbb3ab6	1534	*
lynxeyed_atsu	0:e8bfffbb3ab6	1535	* @param IRQn The number of the device specifc interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1536	* @return 1 = interrupt pending, 0 = interrupt not pending
lynxeyed_atsu	0:e8bfffbb3ab6	1537	*
lynxeyed_atsu	0:e8bfffbb3ab6	1538	* Read the pending register in NVIC and return 1 if its status is pending,
lynxeyed_atsu	0:e8bfffbb3ab6	1539	* otherwise it returns 0
lynxeyed_atsu	0:e8bfffbb3ab6	1540	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1541	static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:e8bfffbb3ab6	1542	{
lynxeyed_atsu	0:e8bfffbb3ab6	1543	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
lynxeyed_atsu	0:e8bfffbb3ab6	1544	}
lynxeyed_atsu	0:e8bfffbb3ab6	1545
lynxeyed_atsu	0:e8bfffbb3ab6	1546	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1547	* @brief Set the pending bit for an external interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1548	*
lynxeyed_atsu	0:e8bfffbb3ab6	1549	* @param IRQn The number of the interrupt for set pending
lynxeyed_atsu	0:e8bfffbb3ab6	1550	*
lynxeyed_atsu	0:e8bfffbb3ab6	1551	* Set the pending bit for the specified interrupt.
lynxeyed_atsu	0:e8bfffbb3ab6	1552	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:e8bfffbb3ab6	1553	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1554	static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:e8bfffbb3ab6	1555	{
lynxeyed_atsu	0:e8bfffbb3ab6	1556	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
lynxeyed_atsu	0:e8bfffbb3ab6	1557	}
lynxeyed_atsu	0:e8bfffbb3ab6	1558
lynxeyed_atsu	0:e8bfffbb3ab6	1559	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1560	* @brief Clear the pending bit for an external interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1561	*
lynxeyed_atsu	0:e8bfffbb3ab6	1562	* @param IRQn The number of the interrupt for clear pending
lynxeyed_atsu	0:e8bfffbb3ab6	1563	*
lynxeyed_atsu	0:e8bfffbb3ab6	1564	* Clear the pending bit for the specified interrupt.
lynxeyed_atsu	0:e8bfffbb3ab6	1565	* The interrupt number cannot be a negative value.
lynxeyed_atsu	0:e8bfffbb3ab6	1566	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1567	static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
lynxeyed_atsu	0:e8bfffbb3ab6	1568	{
lynxeyed_atsu	0:e8bfffbb3ab6	1569	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
lynxeyed_atsu	0:e8bfffbb3ab6	1570	}
lynxeyed_atsu	0:e8bfffbb3ab6	1571
lynxeyed_atsu	0:e8bfffbb3ab6	1572	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1573	* @brief Read the active bit for an external interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1574	*
lynxeyed_atsu	0:e8bfffbb3ab6	1575	* @param IRQn The number of the interrupt for read active bit
lynxeyed_atsu	0:e8bfffbb3ab6	1576	* @return 1 = interrupt active, 0 = interrupt not active
lynxeyed_atsu	0:e8bfffbb3ab6	1577	*
lynxeyed_atsu	0:e8bfffbb3ab6	1578	* Read the active register in NVIC and returns 1 if its status is active,
lynxeyed_atsu	0:e8bfffbb3ab6	1579	* otherwise it returns 0.
lynxeyed_atsu	0:e8bfffbb3ab6	1580	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1581	static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
lynxeyed_atsu	0:e8bfffbb3ab6	1582	{
lynxeyed_atsu	0:e8bfffbb3ab6	1583	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
lynxeyed_atsu	0:e8bfffbb3ab6	1584	}
lynxeyed_atsu	0:e8bfffbb3ab6	1585
lynxeyed_atsu	0:e8bfffbb3ab6	1586	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1587	* @brief Set the priority for an interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1588	*
lynxeyed_atsu	0:e8bfffbb3ab6	1589	* @param IRQn The number of the interrupt for set priority
lynxeyed_atsu	0:e8bfffbb3ab6	1590	* @param priority The priority to set
lynxeyed_atsu	0:e8bfffbb3ab6	1591	*
lynxeyed_atsu	0:e8bfffbb3ab6	1592	* Set the priority for the specified interrupt. The interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1593	* number can be positive to specify an external (device specific)
lynxeyed_atsu	0:e8bfffbb3ab6	1594	* interrupt, or negative to specify an internal (core) interrupt.
lynxeyed_atsu	0:e8bfffbb3ab6	1595	*
lynxeyed_atsu	0:e8bfffbb3ab6	1596	* Note: The priority cannot be set for every core interrupt.
lynxeyed_atsu	0:e8bfffbb3ab6	1597	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1598	static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
lynxeyed_atsu	0:e8bfffbb3ab6	1599	{
lynxeyed_atsu	0:e8bfffbb3ab6	1600	if(IRQn < 0) {
lynxeyed_atsu	0:e8bfffbb3ab6	1601	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
lynxeyed_atsu	0:e8bfffbb3ab6	1602	else {
lynxeyed_atsu	0:e8bfffbb3ab6	1603	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
lynxeyed_atsu	0:e8bfffbb3ab6	1604	}
lynxeyed_atsu	0:e8bfffbb3ab6	1605
lynxeyed_atsu	0:e8bfffbb3ab6	1606	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1607	* @brief Read the priority for an interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1608	*
lynxeyed_atsu	0:e8bfffbb3ab6	1609	* @param IRQn The number of the interrupt for get priority
lynxeyed_atsu	0:e8bfffbb3ab6	1610	* @return The priority for the interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1611	*
lynxeyed_atsu	0:e8bfffbb3ab6	1612	* Read the priority for the specified interrupt. The interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1613	* number can be positive to specify an external (device specific)
lynxeyed_atsu	0:e8bfffbb3ab6	1614	* interrupt, or negative to specify an internal (core) interrupt.
lynxeyed_atsu	0:e8bfffbb3ab6	1615	*
lynxeyed_atsu	0:e8bfffbb3ab6	1616	* The returned priority value is automatically aligned to the implemented
lynxeyed_atsu	0:e8bfffbb3ab6	1617	* priority bits of the microcontroller.
lynxeyed_atsu	0:e8bfffbb3ab6	1618	*
lynxeyed_atsu	0:e8bfffbb3ab6	1619	* Note: The priority cannot be set for every core interrupt.
lynxeyed_atsu	0:e8bfffbb3ab6	1620	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1621	static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
lynxeyed_atsu	0:e8bfffbb3ab6	1622	{
lynxeyed_atsu	0:e8bfffbb3ab6	1623
lynxeyed_atsu	0:e8bfffbb3ab6	1624	if(IRQn < 0) {
lynxeyed_atsu	0:e8bfffbb3ab6	1625	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
lynxeyed_atsu	0:e8bfffbb3ab6	1626	else {
lynxeyed_atsu	0:e8bfffbb3ab6	1627	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
lynxeyed_atsu	0:e8bfffbb3ab6	1628	}
lynxeyed_atsu	0:e8bfffbb3ab6	1629
lynxeyed_atsu	0:e8bfffbb3ab6	1630
lynxeyed_atsu	0:e8bfffbb3ab6	1631	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1632	* @brief Encode the priority for an interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1633	*
lynxeyed_atsu	0:e8bfffbb3ab6	1634	* @param PriorityGroup The used priority group
lynxeyed_atsu	0:e8bfffbb3ab6	1635	* @param PreemptPriority The preemptive priority value (starting from 0)
lynxeyed_atsu	0:e8bfffbb3ab6	1636	* @param SubPriority The sub priority value (starting from 0)
lynxeyed_atsu	0:e8bfffbb3ab6	1637	* @return The encoded priority for the interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1638	*
lynxeyed_atsu	0:e8bfffbb3ab6	1639	* Encode the priority for an interrupt with the given priority group,
lynxeyed_atsu	0:e8bfffbb3ab6	1640	* preemptive priority value and sub priority value.
lynxeyed_atsu	0:e8bfffbb3ab6	1641	* In case of a conflict between priority grouping and available
lynxeyed_atsu	0:e8bfffbb3ab6	1642	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
lynxeyed_atsu	0:e8bfffbb3ab6	1643	*
lynxeyed_atsu	0:e8bfffbb3ab6	1644	* The returned priority value can be used for NVIC_SetPriority(...) function
lynxeyed_atsu	0:e8bfffbb3ab6	1645	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1646	static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
lynxeyed_atsu	0:e8bfffbb3ab6	1647	{
lynxeyed_atsu	0:e8bfffbb3ab6	1648	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
lynxeyed_atsu	0:e8bfffbb3ab6	1649	uint32_t PreemptPriorityBits;
lynxeyed_atsu	0:e8bfffbb3ab6	1650	uint32_t SubPriorityBits;
lynxeyed_atsu	0:e8bfffbb3ab6	1651
lynxeyed_atsu	0:e8bfffbb3ab6	1652	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
lynxeyed_atsu	0:e8bfffbb3ab6	1653	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
lynxeyed_atsu	0:e8bfffbb3ab6	1654
lynxeyed_atsu	0:e8bfffbb3ab6	1655	return (
lynxeyed_atsu	0:e8bfffbb3ab6	1656	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
lynxeyed_atsu	0:e8bfffbb3ab6	1657	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
lynxeyed_atsu	0:e8bfffbb3ab6	1658	);
lynxeyed_atsu	0:e8bfffbb3ab6	1659	}
lynxeyed_atsu	0:e8bfffbb3ab6	1660
lynxeyed_atsu	0:e8bfffbb3ab6	1661
lynxeyed_atsu	0:e8bfffbb3ab6	1662	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1663	* @brief Decode the priority of an interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1664	*
lynxeyed_atsu	0:e8bfffbb3ab6	1665	* @param Priority The priority for the interrupt
lynxeyed_atsu	0:e8bfffbb3ab6	1666	* @param PriorityGroup The used priority group
lynxeyed_atsu	0:e8bfffbb3ab6	1667	* @param pPreemptPriority The preemptive priority value (starting from 0)
lynxeyed_atsu	0:e8bfffbb3ab6	1668	* @param pSubPriority The sub priority value (starting from 0)
lynxeyed_atsu	0:e8bfffbb3ab6	1669	*
lynxeyed_atsu	0:e8bfffbb3ab6	1670	* Decode an interrupt priority value with the given priority group to
lynxeyed_atsu	0:e8bfffbb3ab6	1671	* preemptive priority value and sub priority value.
lynxeyed_atsu	0:e8bfffbb3ab6	1672	* In case of a conflict between priority grouping and available
lynxeyed_atsu	0:e8bfffbb3ab6	1673	* priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
lynxeyed_atsu	0:e8bfffbb3ab6	1674	*
lynxeyed_atsu	0:e8bfffbb3ab6	1675	* The priority value can be retrieved with NVIC_GetPriority(...) function
lynxeyed_atsu	0:e8bfffbb3ab6	1676	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1677	static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
lynxeyed_atsu	0:e8bfffbb3ab6	1678	{
lynxeyed_atsu	0:e8bfffbb3ab6	1679	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
lynxeyed_atsu	0:e8bfffbb3ab6	1680	uint32_t PreemptPriorityBits;
lynxeyed_atsu	0:e8bfffbb3ab6	1681	uint32_t SubPriorityBits;
lynxeyed_atsu	0:e8bfffbb3ab6	1682
lynxeyed_atsu	0:e8bfffbb3ab6	1683	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
lynxeyed_atsu	0:e8bfffbb3ab6	1684	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
lynxeyed_atsu	0:e8bfffbb3ab6	1685
lynxeyed_atsu	0:e8bfffbb3ab6	1686	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
lynxeyed_atsu	0:e8bfffbb3ab6	1687	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
lynxeyed_atsu	0:e8bfffbb3ab6	1688	}
lynxeyed_atsu	0:e8bfffbb3ab6	1689
lynxeyed_atsu	0:e8bfffbb3ab6	1690
lynxeyed_atsu	0:e8bfffbb3ab6	1691
lynxeyed_atsu	0:e8bfffbb3ab6	1692	/* ################################## SysTick function ############################################ */
lynxeyed_atsu	0:e8bfffbb3ab6	1693
lynxeyed_atsu	0:e8bfffbb3ab6	1694	#if (!defined (__Vendor_SysTickConfig)) \|\| (__Vendor_SysTickConfig == 0)
lynxeyed_atsu	0:e8bfffbb3ab6	1695
lynxeyed_atsu	0:e8bfffbb3ab6	1696	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1697	* @brief Initialize and start the SysTick counter and its interrupt.
lynxeyed_atsu	0:e8bfffbb3ab6	1698	*
lynxeyed_atsu	0:e8bfffbb3ab6	1699	* @param ticks number of ticks between two interrupts
lynxeyed_atsu	0:e8bfffbb3ab6	1700	* @return 1 = failed, 0 = successful
lynxeyed_atsu	0:e8bfffbb3ab6	1701	*
lynxeyed_atsu	0:e8bfffbb3ab6	1702	* Initialise the system tick timer and its interrupt and start the
lynxeyed_atsu	0:e8bfffbb3ab6	1703	* system tick timer / counter in free running mode to generate
lynxeyed_atsu	0:e8bfffbb3ab6	1704	* periodical interrupts.
lynxeyed_atsu	0:e8bfffbb3ab6	1705	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1706	static __INLINE uint32_t SysTick_Config(uint32_t ticks)
lynxeyed_atsu	0:e8bfffbb3ab6	1707	{
lynxeyed_atsu	0:e8bfffbb3ab6	1708	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
lynxeyed_atsu	0:e8bfffbb3ab6	1709
lynxeyed_atsu	0:e8bfffbb3ab6	1710	SysTick->RELOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
lynxeyed_atsu	0:e8bfffbb3ab6	1711	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
lynxeyed_atsu	0:e8bfffbb3ab6	1712	SysTick->CURR = 0; /* Load the SysTick Counter Value */
lynxeyed_atsu	0:e8bfffbb3ab6	1713	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
lynxeyed_atsu	0:e8bfffbb3ab6	1714	SysTick_CTRL_TICKINT_Msk \|
lynxeyed_atsu	0:e8bfffbb3ab6	1715	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
lynxeyed_atsu	0:e8bfffbb3ab6	1716	return (0); /* Function successful */
lynxeyed_atsu	0:e8bfffbb3ab6	1717	}
lynxeyed_atsu	0:e8bfffbb3ab6	1718
lynxeyed_atsu	0:e8bfffbb3ab6	1719	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	1720
lynxeyed_atsu	0:e8bfffbb3ab6	1721
lynxeyed_atsu	0:e8bfffbb3ab6	1722
lynxeyed_atsu	0:e8bfffbb3ab6	1723
lynxeyed_atsu	0:e8bfffbb3ab6	1724	/* ################################## Reset function ############################################ */
lynxeyed_atsu	0:e8bfffbb3ab6	1725
lynxeyed_atsu	0:e8bfffbb3ab6	1726	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1727	* @brief Initiate a system reset request.
lynxeyed_atsu	0:e8bfffbb3ab6	1728	*
lynxeyed_atsu	0:e8bfffbb3ab6	1729	* Initiate a system reset request to reset the MCU
lynxeyed_atsu	0:e8bfffbb3ab6	1730	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1731	static __INLINE void NVIC_SystemReset(void)
lynxeyed_atsu	0:e8bfffbb3ab6	1732	{
lynxeyed_atsu	0:e8bfffbb3ab6	1733	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
lynxeyed_atsu	0:e8bfffbb3ab6	1734	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
lynxeyed_atsu	0:e8bfffbb3ab6	1735	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
lynxeyed_atsu	0:e8bfffbb3ab6	1736	__DSB(); /* Ensure completion of memory access */
lynxeyed_atsu	0:e8bfffbb3ab6	1737	while(1); /* wait until reset */
lynxeyed_atsu	0:e8bfffbb3ab6	1738	}
lynxeyed_atsu	0:e8bfffbb3ab6	1739
lynxeyed_atsu	0:e8bfffbb3ab6	1740	/@}/ /* end of group CMSIS_CM3_Core_FunctionInterface */
lynxeyed_atsu	0:e8bfffbb3ab6	1741
lynxeyed_atsu	0:e8bfffbb3ab6	1742
lynxeyed_atsu	0:e8bfffbb3ab6	1743
lynxeyed_atsu	0:e8bfffbb3ab6	1744	/* ##################################### Debug In/Output function ########################################### */
lynxeyed_atsu	0:e8bfffbb3ab6	1745
lynxeyed_atsu	0:e8bfffbb3ab6	1746	/** @addtogroup CMSIS_CM3_CoreDebugInterface CMSIS CM3 Core Debug Interface
lynxeyed_atsu	0:e8bfffbb3ab6	1747	Core Debug Interface containing:
lynxeyed_atsu	0:e8bfffbb3ab6	1748	- Core Debug Receive / Transmit Functions
lynxeyed_atsu	0:e8bfffbb3ab6	1749	- Core Debug Defines
lynxeyed_atsu	0:e8bfffbb3ab6	1750	- Core Debug Variables
lynxeyed_atsu	0:e8bfffbb3ab6	1751	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1752	/@{/
lynxeyed_atsu	0:e8bfffbb3ab6	1753
lynxeyed_atsu	0:e8bfffbb3ab6	1754	extern volatile int ITM_RxBuffer; /!< variable to receive characters /
lynxeyed_atsu	0:e8bfffbb3ab6	1755	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< value identifying ITM_RxBuffer is ready for next character /
lynxeyed_atsu	0:e8bfffbb3ab6	1756
lynxeyed_atsu	0:e8bfffbb3ab6	1757
lynxeyed_atsu	0:e8bfffbb3ab6	1758	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1759	* @brief Outputs a character via the ITM channel 0
lynxeyed_atsu	0:e8bfffbb3ab6	1760	*
lynxeyed_atsu	0:e8bfffbb3ab6	1761	* @param ch character to output
lynxeyed_atsu	0:e8bfffbb3ab6	1762	* @return character to output
lynxeyed_atsu	0:e8bfffbb3ab6	1763	*
lynxeyed_atsu	0:e8bfffbb3ab6	1764	* The function outputs a character via the ITM channel 0.
lynxeyed_atsu	0:e8bfffbb3ab6	1765	* The function returns when no debugger is connected that has booked the output.
lynxeyed_atsu	0:e8bfffbb3ab6	1766	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
lynxeyed_atsu	0:e8bfffbb3ab6	1767	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1768	static __INLINE uint32_t ITM_SendChar (uint32_t ch)
lynxeyed_atsu	0:e8bfffbb3ab6	1769	{
lynxeyed_atsu	0:e8bfffbb3ab6	1770	if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
lynxeyed_atsu	0:e8bfffbb3ab6	1771	(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
lynxeyed_atsu	0:e8bfffbb3ab6	1772	(ITM->TER & (1ul << 0) ) ) /* ITM Port #0 enabled */
lynxeyed_atsu	0:e8bfffbb3ab6	1773	{
lynxeyed_atsu	0:e8bfffbb3ab6	1774	while (ITM->PORT[0].u32 == 0);
lynxeyed_atsu	0:e8bfffbb3ab6	1775	ITM->PORT[0].u8 = (uint8_t) ch;
lynxeyed_atsu	0:e8bfffbb3ab6	1776	}
lynxeyed_atsu	0:e8bfffbb3ab6	1777	return (ch);
lynxeyed_atsu	0:e8bfffbb3ab6	1778	}
lynxeyed_atsu	0:e8bfffbb3ab6	1779
lynxeyed_atsu	0:e8bfffbb3ab6	1780
lynxeyed_atsu	0:e8bfffbb3ab6	1781	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1782	* @brief Inputs a character via variable ITM_RxBuffer
lynxeyed_atsu	0:e8bfffbb3ab6	1783	*
lynxeyed_atsu	0:e8bfffbb3ab6	1784	* @return received character, -1 = no character received
lynxeyed_atsu	0:e8bfffbb3ab6	1785	*
lynxeyed_atsu	0:e8bfffbb3ab6	1786	* The function inputs a character via variable ITM_RxBuffer.
lynxeyed_atsu	0:e8bfffbb3ab6	1787	* The function returns when no debugger is connected that has booked the output.
lynxeyed_atsu	0:e8bfffbb3ab6	1788	* It is blocking when a debugger is connected, but the previous character send is not transmitted.
lynxeyed_atsu	0:e8bfffbb3ab6	1789	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1790	static __INLINE int ITM_ReceiveChar (void) {
lynxeyed_atsu	0:e8bfffbb3ab6	1791	int ch = -1; /* no character available */
lynxeyed_atsu	0:e8bfffbb3ab6	1792
lynxeyed_atsu	0:e8bfffbb3ab6	1793	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
lynxeyed_atsu	0:e8bfffbb3ab6	1794	ch = ITM_RxBuffer;
lynxeyed_atsu	0:e8bfffbb3ab6	1795	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
lynxeyed_atsu	0:e8bfffbb3ab6	1796	}
lynxeyed_atsu	0:e8bfffbb3ab6	1797
lynxeyed_atsu	0:e8bfffbb3ab6	1798	return (ch);
lynxeyed_atsu	0:e8bfffbb3ab6	1799	}
lynxeyed_atsu	0:e8bfffbb3ab6	1800
lynxeyed_atsu	0:e8bfffbb3ab6	1801
lynxeyed_atsu	0:e8bfffbb3ab6	1802	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1803	* @brief Check if a character via variable ITM_RxBuffer is available
lynxeyed_atsu	0:e8bfffbb3ab6	1804	*
lynxeyed_atsu	0:e8bfffbb3ab6	1805	* @return 1 = character available, 0 = no character available
lynxeyed_atsu	0:e8bfffbb3ab6	1806	*
lynxeyed_atsu	0:e8bfffbb3ab6	1807	* The function checks variable ITM_RxBuffer whether a character is available or not.
lynxeyed_atsu	0:e8bfffbb3ab6	1808	* The function returns '1' if a character is available and '0' if no character is available.
lynxeyed_atsu	0:e8bfffbb3ab6	1809	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1810	static __INLINE int ITM_CheckChar (void) {
lynxeyed_atsu	0:e8bfffbb3ab6	1811
lynxeyed_atsu	0:e8bfffbb3ab6	1812	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
lynxeyed_atsu	0:e8bfffbb3ab6	1813	return (0); /* no character available */
lynxeyed_atsu	0:e8bfffbb3ab6	1814	} else {
lynxeyed_atsu	0:e8bfffbb3ab6	1815	return (1); /* character available */
lynxeyed_atsu	0:e8bfffbb3ab6	1816	}
lynxeyed_atsu	0:e8bfffbb3ab6	1817	}
lynxeyed_atsu	0:e8bfffbb3ab6	1818
lynxeyed_atsu	0:e8bfffbb3ab6	1819	/@}/ /* end of group CMSIS_CM3_core_DebugInterface */
lynxeyed_atsu	0:e8bfffbb3ab6	1820
lynxeyed_atsu	0:e8bfffbb3ab6	1821
lynxeyed_atsu	0:e8bfffbb3ab6	1822	#ifdef __cplusplus
lynxeyed_atsu	0:e8bfffbb3ab6	1823	}
lynxeyed_atsu	0:e8bfffbb3ab6	1824	#endif
lynxeyed_atsu	0:e8bfffbb3ab6	1825
lynxeyed_atsu	0:e8bfffbb3ab6	1826	/@}/ /* end of group CMSIS_CM3_core_definitions */
lynxeyed_atsu	0:e8bfffbb3ab6	1827
lynxeyed_atsu	0:e8bfffbb3ab6	1828	#endif /* __CM3_CORE_H__ */
lynxeyed_atsu	0:e8bfffbb3ab6	1829
lynxeyed_atsu	0:e8bfffbb3ab6	1830	/**
lynxeyed_atsu	0:e8bfffbb3ab6	1831	* @}
lynxeyed_atsu	0:e8bfffbb3ab6	1832	*/
lynxeyed_atsu	0:e8bfffbb3ab6	1833
lynxeyed_atsu	0:e8bfffbb3ab6	1834	/lint -restore /

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Type:	Program
Mbed OS support:	Mbed 2 deprecated
Created:	26 Feb 2011
Imports:	12
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	1
Followers:	1

I2S_Example/core_cm3.h@0:e8bfffbb3ab6, 2011-02-26 (annotated)

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