Lucas Tai-MacArthur / Mbed 2 deprecated PMController

CIS441 Controller

Dependencies:   TextLCD mbed-rtos mbed

Fork of PacemakerController by Chad Nachiappan

PMTest.cpp@20:dc272bfaa276, 2015-11-30 (annotated)

Committer:
chadnach1
Date:
Mon Nov 30 21:38:54 2015 +0000
Revision:
20:dc272bfaa276
Parent:
8:5924b2048a27
Child:
23:08456978fb78
filled in pm_sense method, still need to figure out Sense stuff;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
lucastai 8:5924b2048a27 1 #include "mbed.h"
lucastai 8:5924b2048a27 2 #include "LPC17xx.h"
lucastai 8:5924b2048a27 3 #include "TextLCD.h"
lucastai 8:5924b2048a27 4 #include "rtos.h"
lucastai 8:5924b2048a27 5 #include "Thread.h"
lucastai 8:5924b2048a27 6
lucastai 8:5924b2048a27 7 DigitalOut vsense(p23);
lucastai 8:5924b2048a27 8 DigitalOut asense(p24);
chadnach1 20:dc272bfaa276 9 DigitalIn apace(p22);
chadnach1 20:dc272bfaa276 10 DigitalIn vpace(p21);
lucastai 8:5924b2048a27 11
lucastai 8:5924b2048a27 12 int timer_count;
lucastai 8:5924b2048a27 13 int curr_test;
lucastai 8:5924b2048a27 14
lucastai 8:5924b2048a27 15 int[][] testfunc;
lucastai 8:5924b2048a27 16
lucastai 8:5924b2048a27 17 // hardware interrupt handler, adapted from code in piazza post by Dagaen
lucastai 8:5924b2048a27 18 extern "C" void TIMER0_IRQHandler (void)
lucastai 8:5924b2048a27 19 {
lucastai 8:5924b2048a27 20 if((LPC_TIM0->IR & 0x01) == 0x01) // if MR0 interrupt, proceed
lucastai 8:5924b2048a27 21 {
lucastai 8:5924b2048a27 22 LPC_TIM0->IR |= 1 << 0; // Clear MR0 interrupt flag
lucastai 8:5924b2048a27 23 timer_count++; //increment timer_count
lucastai 8:5924b2048a27 24 }
lucastai 8:5924b2048a27 25 }
lucastai 8:5924b2048a27 26
lucastai 8:5924b2048a27 27 // init the hardware interrupt (timer0), adapted same as above
lucastai 8:5924b2048a27 28 void timer0_init(int n)
lucastai 8:5924b2048a27 29 {
lucastai 8:5924b2048a27 30 LPC_SC->PCONP |=1<1; //timer0 power on
lucastai 8:5924b2048a27 31 LPC_SC-> PCLKSEL0 |= 1 << 2; // set timer clock to CCLCK nondivided (1 clock cycle = 1 increment)
lucastai 8:5924b2048a27 32 LPC_TIM0->MR0 = n; //100mhz clock cycle, 1 cycle = 10ns, 10ms = 10 000 000 ns = 1M cycles
lucastai 8:5924b2048a27 33 LPC_TIM0->MCR = 3; //interrupt and reset control
lucastai 8:5924b2048a27 34 //3 = Interrupt & reset timer0 on match (111) sets all three bits
lucastai 8:5924b2048a27 35 NVIC_EnableIRQ(TIMER0_IRQn); //enable timer0 interrupt
lucastai 8:5924b2048a27 36 }
lucastai 8:5924b2048a27 37
lucastai 8:5924b2048a27 38 // interrupt function
lucastai 8:5924b2048a27 39 void interrupt_and_run_test(){
lucastai 8:5924b2048a27 40 // zero timer, set for 1ms interrupt
lucastai 8:5924b2048a27 41 timer0_init(100000)
lucastai 8:5924b2048a27 42
lucastai 8:5924b2048a27 43 // wait for atrial pulse
lucastai 8:5924b2048a27 44 while(apace != 1}{}
lucastai 8:5924b2048a27 45
lucastai 8:5924b2048a27 46 // check if timer was within event
lucastai 8:5924b2048a27 47
lucastai 8:5924b2048a27 48 if(timer_count < testfunc[curr_test][0]){
lucastai 8:5924b2048a27 49 printf("ATRIAL PULSE FOR TEST " + curr_test + " WAS WITHIN BOUNDS\n");
lucastai 8:5924b2048a27 50 }
lucastai 8:5924b2048a27 51
lucastai 8:5924b2048a27 52 // send vsense
lucastai 8:5924b2048a27 53
lucastai 8:5924b2048a27 54 while(timer_count < testfunc[curr_test][1]){};
lucastai 8:5924b2048a27 55 vpace = 1;
lucastai 8:5924b2048a27 56
lucastai 8:5924b2048a27 57 // send asense
lucastai 8:5924b2048a27 58 while(timer_count < testfunc[curr_test][2]){};
lucastai 8:5924b2048a27 59 apace = 1;
lucastai 8:5924b2048a27 60
lucastai 8:5924b2048a27 61 // check if timer was in event
lucastai 8:5924b2048a27 62
lucastai 8:5924b2048a27 63 // wait for vpace
lucastai 8:5924b2048a27 64
lucastai 8:5924b2048a27 65 // wait for atrial pulse
lucastai 8:5924b2048a27 66 while(vpace != 1}{}
lucastai 8:5924b2048a27 67
lucastai 8:5924b2048a27 68 // check if timer was within event
lucastai 8:5924b2048a27 69
lucastai 8:5924b2048a27 70 if(timer_count < testfunc[curr_test][0]){
lucastai 8:5924b2048a27 71 printf("VENT PULSE FOR TEST " + curr_test + " WAS WITHIN BOUNDS\n");
chadnach1 20:dc272bfaa276 72 }