Igor Levkov / levkov_ov7670

test

Dependencies:   zbar_010

Fork of ov7670 by Edoardo De Marchi

ov7670reg.h@5:a940d64a408b, 2017-09-25 (annotated)

Committer:
levkovigor
Date:
Mon Sep 25 12:38:33 2017 +0000
Revision:
5:a940d64a408b
Parent:
1:d82dbad9c06b 
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
edodm85 0:810d59d0b843 1 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
edodm85 0:810d59d0b843 2 #define REG_BLUE 0x01 /* blue gain */
edodm85 0:810d59d0b843 3 #define REG_RED 0x02 /* red gain */
edodm85 0:810d59d0b843 4 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
edodm85 0:810d59d0b843 5 #define REG_COM1 0x04 /* Control 1 */
edodm85 0:810d59d0b843 6 #define COM1_CCIR656 0x40 /* CCIR656 enable */
edodm85 0:810d59d0b843 7 #define REG_BAVE 0x05 /* U/B Average level */
edodm85 0:810d59d0b843 8 #define REG_GbAVE 0x06 /* Y/Gb Average level */
edodm85 0:810d59d0b843 9 #define REG_AECHH 0x07 /* AEC MS 5 bits */
edodm85 0:810d59d0b843 10 #define REG_RAVE 0x08 /* V/R Average level */
edodm85 0:810d59d0b843 11 #define REG_COM2 0x09 /* Control 2 */
edodm85 0:810d59d0b843 12 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
edodm85 0:810d59d0b843 13 #define REG_PID 0x0a /* Product ID MSB */
edodm85 0:810d59d0b843 14 #define REG_VER 0x0b /* Product ID LSB */
edodm85 0:810d59d0b843 15 #define REG_COM3 0x0c /* Control 3 */
edodm85 0:810d59d0b843 16 #define COM3_SWAP 0x40 /* Byte swap */
edodm85 0:810d59d0b843 17 #define COM3_SCALEEN 0x08 /* Enable scaling */
edodm85 0:810d59d0b843 18 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
edodm85 0:810d59d0b843 19 #define REG_COM4 0x0d /* Control 4 */
edodm85 0:810d59d0b843 20 #define REG_COM5 0x0e /* All "reserved" */
edodm85 0:810d59d0b843 21 #define REG_COM6 0x0f /* Control 6 */
edodm85 0:810d59d0b843 22 #define REG_AECH 0x10 /* More bits of AEC value */
edodm85 0:810d59d0b843 23 #define REG_CLKRC 0x11 /* Clocl control */
edodm85 0:810d59d0b843 24 #define CLK_EXT 0x40 /* Use external clock directly */
edodm85 0:810d59d0b843 25 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
edodm85 0:810d59d0b843 26 #define REG_COM7 0x12 /* Control 7 */
edodm85 0:810d59d0b843 27 #define COM7_RESET 0x80 /* Register reset */
edodm85 0:810d59d0b843 28 #define COM7_FMT_MASK 0x38
edodm85 0:810d59d0b843 29 #define COM7_FMT_VGA 0x00
edodm85 0:810d59d0b843 30 #define COM7_FMT_CIF 0x20 /* CIF format */
edodm85 0:810d59d0b843 31 #define COM7_FMT_QVGA 0x10 /* QVGA format */
edodm85 0:810d59d0b843 32 #define COM7_FMT_QCIF 0x08 /* QCIF format */
edodm85 0:810d59d0b843 33 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
edodm85 0:810d59d0b843 34 #define COM7_YUV 0x00 /* YUV */
edodm85 0:810d59d0b843 35 #define COM7_BAYER 0x01 /* Bayer format */
edodm85 0:810d59d0b843 36 #define COM7_PBAYER 0x05 /* "Processed bayer" */
edodm85 0:810d59d0b843 37 #define REG_COM8 0x13 /* Control 8 */
edodm85 0:810d59d0b843 38 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
edodm85 0:810d59d0b843 39 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
edodm85 0:810d59d0b843 40 #define COM8_BFILT 0x20 /* Band filter enable */
edodm85 0:810d59d0b843 41 #define COM8_AGC 0x04 /* Auto gain enable */
edodm85 0:810d59d0b843 42 #define COM8_AWB 0x02 /* White balance enable */
edodm85 0:810d59d0b843 43 #define COM8_AEC 0x01 /* Auto exposure enable */
edodm85 0:810d59d0b843 44 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
edodm85 0:810d59d0b843 45 #define REG_COM10 0x15 /* Control 10 */
edodm85 0:810d59d0b843 46 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
edodm85 0:810d59d0b843 47 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
edodm85 0:810d59d0b843 48 #define COM10_HREF_REV 0x08 /* Reverse HREF */
edodm85 0:810d59d0b843 49 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
edodm85 0:810d59d0b843 50 #define COM10_VS_NEG 0x02 /* VSYNC negative */
edodm85 0:810d59d0b843 51 #define COM10_HS_NEG 0x01 /* HSYNC negative */
edodm85 0:810d59d0b843 52 #define REG_HSTART 0x17 /* Horiz start high bits */
edodm85 0:810d59d0b843 53 #define REG_HSTOP 0x18 /* Horiz stop high bits */
edodm85 0:810d59d0b843 54 #define REG_VSTART 0x19 /* Vert start high bits */
edodm85 0:810d59d0b843 55 #define REG_VSTOP 0x1a /* Vert stop high bits */
edodm85 0:810d59d0b843 56 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
edodm85 0:810d59d0b843 57 #define REG_MIDH 0x1c /* Manuf. ID high */
edodm85 0:810d59d0b843 58 #define REG_MIDL 0x1d /* Manuf. ID low */
edodm85 0:810d59d0b843 59 #define REG_MVFP 0x1e /* Mirror / vflip */
edodm85 0:810d59d0b843 60 #define MVFP_MIRROR 0x20 /* Mirror image */
edodm85 0:810d59d0b843 61 #define MVFP_FLIP 0x10 /* Vertical flip */
edodm85 0:810d59d0b843 62 #define REG_AEW 0x24 /* AGC upper limit */
edodm85 0:810d59d0b843 63 #define REG_AEB 0x25 /* AGC lower limit */
edodm85 0:810d59d0b843 64 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
edodm85 0:810d59d0b843 65 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
edodm85 0:810d59d0b843 66 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
edodm85 0:810d59d0b843 67 #define REG_HREF 0x32 /* HREF pieces */
edodm85 0:810d59d0b843 68 #define REG_TSLB 0x3a /* lots of stuff */
edodm85 0:810d59d0b843 69 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
edodm85 0:810d59d0b843 70 #define REG_COM11 0x3b /* Control 11 */
edodm85 0:810d59d0b843 71 #define COM11_NIGHT 0x80 /* NIght mode enable */
edodm85 0:810d59d0b843 72 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
edodm85 0:810d59d0b843 73 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
edodm85 0:810d59d0b843 74 #define COM11_50HZ 0x08 /* Manual 50Hz select */
edodm85 0:810d59d0b843 75 #define COM11_EXP 0x02
edodm85 0:810d59d0b843 76 #define REG_COM12 0x3c /* Control 12 */
edodm85 0:810d59d0b843 77 #define COM12_HREF 0x80 /* HREF always */
edodm85 0:810d59d0b843 78 #define REG_COM13 0x3d /* Control 13 */
edodm85 0:810d59d0b843 79 #define COM13_GAMMA 0x80 /* Gamma enable */
edodm85 0:810d59d0b843 80 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
edodm85 0:810d59d0b843 81 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
edodm85 0:810d59d0b843 82 #define REG_COM14 0x3e /* Control 14 */
edodm85 0:810d59d0b843 83 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
edodm85 0:810d59d0b843 84 #define REG_EDGE 0x3f /* Edge enhancement factor */
edodm85 0:810d59d0b843 85 #define REG_COM15 0x40 /* Control 15 */
edodm85 0:810d59d0b843 86 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
edodm85 0:810d59d0b843 87 #define COM15_R01FE 0x80 /* 01 to FE */
edodm85 0:810d59d0b843 88 #define COM15_R00FF 0xc0 /* 00 to FF */
edodm85 0:810d59d0b843 89 #define COM15_RGB565 0x10 /* RGB565 output */
edodm85 0:810d59d0b843 90 #define COM15_RGB555 0x30 /* RGB555 output */
edodm85 0:810d59d0b843 91 #define REG_COM16 0x41 /* Control 16 */
edodm85 0:810d59d0b843 92 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
edodm85 0:810d59d0b843 93 #define REG_COM17 0x42 /* Control 17 */
edodm85 0:810d59d0b843 94 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
edodm85 0:810d59d0b843 95 #define COM17_CBAR 0x08 /* DSP Color bar */
edodm85 0:810d59d0b843 96
edodm85 0:810d59d0b843 97 #define REG_BRIGHT 0x55 /* Brightness */
edodm85 0:810d59d0b843 98 #define REG_REG76 0x76 /* OV's name */
edodm85 0:810d59d0b843 99 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
edodm85 0:810d59d0b843 100 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
edodm85 0:810d59d0b843 101 #define REG_RGB444 0x8c /* RGB 444 control */
edodm85 0:810d59d0b843 102 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
edodm85 0:810d59d0b843 103 #define R444_RGBX 0x01 /* Empty nibble at end */
edodm85 0:810d59d0b843 104 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
edodm85 0:810d59d0b843 105 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
edodm85 0:810d59d0b843 106 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
edodm85 0:810d59d0b843 107 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
edodm85 0:810d59d0b843 108 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
edodm85 0:810d59d0b843 109 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
edodm85 0:810d59d0b843 110 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
edodm85 0:810d59d0b843 111 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
edodm85 0:810d59d0b843 112 #define REG_BD60MAX 0xab /* 60hz banding step limit */
edodm85 0:810d59d0b843 113
edodm85 0:810d59d0b843 114 #define MTX1 0x4f /* Matrix Coefficient 1 */
edodm85 0:810d59d0b843 115 #define MTX2 0x50 /* Matrix Coefficient 2 */
edodm85 0:810d59d0b843 116 #define MTX3 0x51 /* Matrix Coefficient 3 */
edodm85 0:810d59d0b843 117 #define MTX4 0x52 /* Matrix Coefficient 4 */
edodm85 0:810d59d0b843 118 #define MTX5 0x53 /* Matrix Coefficient 5 */
edodm85 0:810d59d0b843 119 #define MTX6 0x54 /* Matrix Coefficient 6 */
edodm85 0:810d59d0b843 120 #define REG_CONTRAS 0x56 /* Contrast control */
edodm85 0:810d59d0b843 121 #define MTXS 0x58 /* Matrix Coefficient Sign */
edodm85 0:810d59d0b843 122 #define AWBC7 0x59 /* AWB Control 7 */
edodm85 0:810d59d0b843 123 #define AWBC8 0x5a /* AWB Control 8 */
edodm85 0:810d59d0b843 124 #define AWBC9 0x5b /* AWB Control 9 */
edodm85 0:810d59d0b843 125 #define AWBC10 0x5c /* AWB Control 10 */
edodm85 0:810d59d0b843 126 #define AWBC11 0x5d /* AWB Control 11 */
edodm85 0:810d59d0b843 127 #define AWBC12 0x5e /* AWB Control 12 */
edodm85 0:810d59d0b843 128 #define REG_GFIX 0x69 /* Fix gain control */
edodm85 0:810d59d0b843 129 #define GGAIN 0x6a /* G Channel AWB Gain */
edodm85 0:810d59d0b843 130 #define DBLV 0x6b
edodm85 0:810d59d0b843 131 #define AWBCTR3 0x6c /* AWB Control 3 */
edodm85 0:810d59d0b843 132 #define AWBCTR2 0x6d /* AWB Control 2 */
edodm85 0:810d59d0b843 133 #define AWBCTR1 0x6e /* AWB Control 1 */
edodm85 0:810d59d0b843 134 #define AWBCTR0 0x6f /* AWB Control 0 */