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projet_pololu_et5_ees

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Diff: Devices/FastIO_EFM32.h

Revision:
17:87872fcf8586
Parent:
16:a56c0e7ebf7f
--- a/Devices/FastIO_EFM32.h	Sat Jul 11 14:27:43 2015 +0000
+++ b/Devices/FastIO_EFM32.h	Sat Jul 11 14:38:29 2015 +0000
@@ -18,16 +18,16 @@
 #define MODE_REG        (*((&GPIO->P[PORT_INDEX].MODEL) + PIN_INDEX / 8))
 #define MODE_SHIFT      ((PIN_INDEX * 4) % 32)
 
-#define INIT_PIN        container.mask = PINMASK; container.input_mode = PullDefault; container.output_mode = PushPull; CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(cmuClock_GPIO, true)
+#define INIT_PIN        this->container.mask = PINMASK; this->container.input_mode = PullDefault; this->container.output_mode = PushPull; CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(cmuClock_GPIO, true)
 #define DESTROY_PIN     
 
-#define SET_DIR_INPUT   uint32_t temp = MODE_REG & ~(0xF << MODE_SHIFT); MODE_REG = temp + ((container.input_mode & 0xF) << MODE_SHIFT); if (container.input_mode > 0x10) WRITE_PIN_SET; else WRITE_PIN_CLR
+#define SET_DIR_INPUT   uint32_t temp = MODE_REG & ~(0xF << MODE_SHIFT); MODE_REG = temp + ((this->container.input_mode & 0xF) << MODE_SHIFT); if (this->container.input_mode > 0x10) WRITE_PIN_SET; else WRITE_PIN_CLR
 #define SET_DIR_OUTPUT  uint32_t temp = MODE_REG & ~(0xF << MODE_SHIFT); MODE_REG = temp + (container.output_mode << MODE_SHIFT)
-#define SET_MODE(pull)  if ((pull <= 3) || (pull > 0x10)) {container.input_mode = pull; SET_DIR_INPUT; } else {container.output_mode = pull; SET_DIR_OUTPUT;}
+#define SET_MODE(pull)  if ((pull <= 3) || (pull > 0x10)) {this->container.input_mode = pull; SET_DIR_INPUT; } else {this->container.output_mode = pull; SET_DIR_OUTPUT;}
 
 #define WRITE_PIN_SET   GPIO->P[PORT_INDEX].DOUTSET = PINMASK
 #define WRITE_PIN_CLR   GPIO->P[PORT_INDEX].DOUTCLR = PINMASK
 
-#define READ_PIN        ((GPIO->P[PORT_INDEX].DIN & PINMASK) ? 1 : 0)
+#define READ_PIN        ((GPIO->P[PORT_INDEX].DIN & this->container.mask) ? 1 : 0)
 
 #endif