Jindong Liu / ITG3200-forRM-G146

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Fork of ITG3200 by Aaron Berk

ITG3200.h@1:bd8398f25811, 2013-09-09 (annotated)

Committer:
kingwinter
Date:
Mon Sep 09 09:15:46 2013 +0000
Revision:
1:bd8398f25811
Parent:
0:b098d99dd81e 
RM-G146 board integrate ITG3200 and LSM303DLH into one chip. Here is a demo code for mbed reading when connect Pin 28 and 27 to I2C SDA and SDL.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
aberk 0:b098d99dd81e 1 /**
aberk 0:b098d99dd81e 2 * @author Aaron Berk
aberk 0:b098d99dd81e 3 *
aberk 0:b098d99dd81e 4 * @section LICENSE
aberk 0:b098d99dd81e 5 *
aberk 0:b098d99dd81e 6 * Copyright (c) 2010 ARM Limited
aberk 0:b098d99dd81e 7 *
aberk 0:b098d99dd81e 8 * Permission is hereby granted, free of charge, to any person obtaining a copy
aberk 0:b098d99dd81e 9 * of this software and associated documentation files (the "Software"), to deal
aberk 0:b098d99dd81e 10 * in the Software without restriction, including without limitation the rights
aberk 0:b098d99dd81e 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
aberk 0:b098d99dd81e 12 * copies of the Software, and to permit persons to whom the Software is
aberk 0:b098d99dd81e 13 * furnished to do so, subject to the following conditions:
aberk 0:b098d99dd81e 14 *
aberk 0:b098d99dd81e 15 * The above copyright notice and this permission notice shall be included in
aberk 0:b098d99dd81e 16 * all copies or substantial portions of the Software.
aberk 0:b098d99dd81e 17 *
aberk 0:b098d99dd81e 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
aberk 0:b098d99dd81e 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
aberk 0:b098d99dd81e 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
aberk 0:b098d99dd81e 21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
aberk 0:b098d99dd81e 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
aberk 0:b098d99dd81e 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
aberk 0:b098d99dd81e 24 * THE SOFTWARE.
aberk 0:b098d99dd81e 25 *
aberk 0:b098d99dd81e 26 * @section DESCRIPTION
aberk 0:b098d99dd81e 27 *
aberk 0:b098d99dd81e 28 * ITG-3200 triple axis, digital interface, gyroscope.
aberk 0:b098d99dd81e 29 *
aberk 0:b098d99dd81e 30 * Datasheet:
aberk 0:b098d99dd81e 31 *
aberk 0:b098d99dd81e 32 * http://invensense.com/mems/gyro/documents/PS-ITG-3200-00-01.4.pdf
aberk 0:b098d99dd81e 33 */
aberk 0:b098d99dd81e 34
aberk 0:b098d99dd81e 35 #ifndef ITG3200_H
aberk 0:b098d99dd81e 36 #define ITG3200_H
aberk 0:b098d99dd81e 37
aberk 0:b098d99dd81e 38 /**
aberk 0:b098d99dd81e 39 * Includes
aberk 0:b098d99dd81e 40 */
aberk 0:b098d99dd81e 41 #include "mbed.h"
aberk 0:b098d99dd81e 42
aberk 0:b098d99dd81e 43 /**
aberk 0:b098d99dd81e 44 * Defines
aberk 0:b098d99dd81e 45 */
kingwinter 1:bd8398f25811 46 #define ITG3200_I2C_ADDRESS 0x68 //7-bit address. option 2 address, corresponding to 0xd0
aberk 0:b098d99dd81e 47
aberk 0:b098d99dd81e 48 //-----------
aberk 0:b098d99dd81e 49 // Registers
aberk 0:b098d99dd81e 50 //-----------
aberk 0:b098d99dd81e 51 #define WHO_AM_I_REG 0x00
aberk 0:b098d99dd81e 52 #define SMPLRT_DIV_REG 0x15
aberk 0:b098d99dd81e 53 #define DLPF_FS_REG 0x16
aberk 0:b098d99dd81e 54 #define INT_CFG_REG 0x17
aberk 0:b098d99dd81e 55 #define INT_STATUS 0x1A
aberk 0:b098d99dd81e 56 #define TEMP_OUT_H_REG 0x1B
aberk 0:b098d99dd81e 57 #define TEMP_OUT_L_REG 0x1C
aberk 0:b098d99dd81e 58 #define GYRO_XOUT_H_REG 0x1D
aberk 0:b098d99dd81e 59 #define GYRO_XOUT_L_REG 0x1E
aberk 0:b098d99dd81e 60 #define GYRO_YOUT_H_REG 0x1F
aberk 0:b098d99dd81e 61 #define GYRO_YOUT_L_REG 0x20
aberk 0:b098d99dd81e 62 #define GYRO_ZOUT_H_REG 0x21
aberk 0:b098d99dd81e 63 #define GYRO_ZOUT_L_REG 0x22
aberk 0:b098d99dd81e 64 #define PWR_MGM_REG 0x3E
aberk 0:b098d99dd81e 65
aberk 0:b098d99dd81e 66 //----------------------------
aberk 0:b098d99dd81e 67 // Low Pass Filter Bandwidths
aberk 0:b098d99dd81e 68 //----------------------------
aberk 0:b098d99dd81e 69 #define LPFBW_256HZ 0x00
aberk 0:b098d99dd81e 70 #define LPFBW_188HZ 0x01
aberk 0:b098d99dd81e 71 #define LPFBW_98HZ 0x02
aberk 0:b098d99dd81e 72 #define LPFBW_42HZ 0x03
aberk 0:b098d99dd81e 73 #define LPFBW_20HZ 0x04
aberk 0:b098d99dd81e 74 #define LPFBW_10HZ 0x05
aberk 0:b098d99dd81e 75 #define LPFBW_5HZ 0x06
aberk 0:b098d99dd81e 76
aberk 0:b098d99dd81e 77 /**
aberk 0:b098d99dd81e 78 * ITG-3200 triple axis digital gyroscope.
aberk 0:b098d99dd81e 79 */
aberk 0:b098d99dd81e 80 class ITG3200 {
aberk 0:b098d99dd81e 81
aberk 0:b098d99dd81e 82 public:
aberk 0:b098d99dd81e 83
aberk 0:b098d99dd81e 84 /**
aberk 0:b098d99dd81e 85 * Constructor.
aberk 0:b098d99dd81e 86 *
aberk 0:b098d99dd81e 87 * Sets FS_SEL to 0x03 for proper opertaion.
aberk 0:b098d99dd81e 88 *
aberk 0:b098d99dd81e 89 * @param sda - mbed pin to use for the SDA I2C line.
aberk 0:b098d99dd81e 90 * @param scl - mbed pin to use for the SCL I2C line.
aberk 0:b098d99dd81e 91 */
aberk 0:b098d99dd81e 92 ITG3200(PinName sda, PinName scl);
aberk 0:b098d99dd81e 93
aberk 0:b098d99dd81e 94 /**
aberk 0:b098d99dd81e 95 * Get the identity of the device.
aberk 0:b098d99dd81e 96 *
aberk 0:b098d99dd81e 97 * @return The contents of the Who Am I register which contains the I2C
aberk 0:b098d99dd81e 98 * address of the device.
aberk 0:b098d99dd81e 99 */
aberk 0:b098d99dd81e 100 char getWhoAmI(void);
aberk 0:b098d99dd81e 101
aberk 0:b098d99dd81e 102 /**
aberk 0:b098d99dd81e 103 * Set the address of the device.
aberk 0:b098d99dd81e 104 *
aberk 0:b098d99dd81e 105 * @param address The I2C slave address to write to the Who Am I register
aberk 0:b098d99dd81e 106 * on the device.
aberk 0:b098d99dd81e 107 */
aberk 0:b098d99dd81e 108 void setWhoAmI(char address);
aberk 0:b098d99dd81e 109
aberk 0:b098d99dd81e 110 /**
aberk 0:b098d99dd81e 111 * Get the sample rate divider.
aberk 0:b098d99dd81e 112 *
aberk 0:b098d99dd81e 113 * @return The sample rate divider as a number from 0-255.
aberk 0:b098d99dd81e 114 */
aberk 0:b098d99dd81e 115 char getSampleRateDivider(void);
aberk 0:b098d99dd81e 116
aberk 0:b098d99dd81e 117 /**
aberk 0:b098d99dd81e 118 * Set the sample rate divider.
aberk 0:b098d99dd81e 119 *
aberk 0:b098d99dd81e 120 * Fsample = Finternal / (divider + 1), where Finternal = 1kHz or 8kHz,
aberk 0:b098d99dd81e 121 * as decidied by the DLPF_FS register.
aberk 0:b098d99dd81e 122 *
aberk 0:b098d99dd81e 123 * @param The sample rate divider as a number from 0-255.
aberk 0:b098d99dd81e 124 */
aberk 0:b098d99dd81e 125 void setSampleRateDivider(char divider);
aberk 0:b098d99dd81e 126
aberk 0:b098d99dd81e 127 /**
aberk 0:b098d99dd81e 128 * Get the internal sample rate.
aberk 0:b098d99dd81e 129 *
aberk 0:b098d99dd81e 130 * @return The internal sample rate in kHz - either 1 or 8.
aberk 0:b098d99dd81e 131 */
aberk 0:b098d99dd81e 132 int getInternalSampleRate(void);
aberk 0:b098d99dd81e 133
aberk 0:b098d99dd81e 134 /**
aberk 0:b098d99dd81e 135 * Set the low pass filter bandwidth.
aberk 0:b098d99dd81e 136 *
aberk 0:b098d99dd81e 137 * Also used to set the internal sample rate.
aberk 0:b098d99dd81e 138 * Pass the #define bandwidth codes as a parameter.
aberk 0:b098d99dd81e 139 *
aberk 0:b098d99dd81e 140 * 256Hz -> 8kHz internal sample rate.
aberk 0:b098d99dd81e 141 * Everything else -> 1kHz internal rate.
aberk 0:b098d99dd81e 142 *
aberk 0:b098d99dd81e 143 * @param bandwidth Low pass filter bandwidth code
aberk 0:b098d99dd81e 144 */
aberk 0:b098d99dd81e 145 void setLpBandwidth(char bandwidth);
aberk 0:b098d99dd81e 146
aberk 0:b098d99dd81e 147 /**
aberk 0:b098d99dd81e 148 * Get the interrupt configuration.
aberk 0:b098d99dd81e 149 *
aberk 0:b098d99dd81e 150 * See datasheet for register contents details.
aberk 0:b098d99dd81e 151 *
aberk 0:b098d99dd81e 152 * 7 6 5 4
aberk 0:b098d99dd81e 153 * +------+------+--------------+------------------+
aberk 0:b098d99dd81e 154 * | ACTL | OPEN | LATCH_INT_EN | INT_ANYRD_2CLEAR |
aberk 0:b098d99dd81e 155 * +------+------+--------------+------------------+
aberk 0:b098d99dd81e 156 *
aberk 0:b098d99dd81e 157 * 3 2 1 0
aberk 0:b098d99dd81e 158 * +---+------------+------------+---+
aberk 0:b098d99dd81e 159 * | 0 | ITG_RDY_EN | RAW_RDY_EN | 0 |
aberk 0:b098d99dd81e 160 * +---+------------+------------+---+
aberk 0:b098d99dd81e 161 *
aberk 0:b098d99dd81e 162 * ACTL Logic level for INT output pin; 1 = active low, 0 = active high.
aberk 0:b098d99dd81e 163 * OPEN Drive type for INT output pin; 1 = open drain, 0 = push-pull.
aberk 0:b098d99dd81e 164 * LATCH_INT_EN Latch mode; 1 = latch until interrupt is cleared,
aberk 0:b098d99dd81e 165 * 0 = 50us pulse.
aberk 0:b098d99dd81e 166 * INT_ANYRD_2CLEAR Latch clear method; 1 = any register read,
aberk 0:b098d99dd81e 167 * 0 = status register read only.
aberk 0:b098d99dd81e 168 * ITG_RDY_EN Enable interrupt when device is ready,
aberk 0:b098d99dd81e 169 * (PLL ready after changing clock source).
aberk 0:b098d99dd81e 170 * RAW_RDY_EN Enable interrupt when data is available.
aberk 0:b098d99dd81e 171 * 0 Bits 1 and 3 of the INT_CFG register should be zero.
aberk 0:b098d99dd81e 172 *
aberk 0:b098d99dd81e 173 * @return the contents of the INT_CFG register.
aberk 0:b098d99dd81e 174 */
aberk 0:b098d99dd81e 175 char getInterruptConfiguration(void);
aberk 0:b098d99dd81e 176
aberk 0:b098d99dd81e 177 /**
aberk 0:b098d99dd81e 178 * Set the interrupt configuration.
aberk 0:b098d99dd81e 179 *
aberk 0:b098d99dd81e 180 * See datasheet for configuration byte details.
aberk 0:b098d99dd81e 181 *
aberk 0:b098d99dd81e 182 * 7 6 5 4
aberk 0:b098d99dd81e 183 * +------+------+--------------+------------------+
aberk 0:b098d99dd81e 184 * | ACTL | OPEN | LATCH_INT_EN | INT_ANYRD_2CLEAR |
aberk 0:b098d99dd81e 185 * +------+------+--------------+------------------+
aberk 0:b098d99dd81e 186 *
aberk 0:b098d99dd81e 187 * 3 2 1 0
aberk 0:b098d99dd81e 188 * +---+------------+------------+---+
aberk 0:b098d99dd81e 189 * | 0 | ITG_RDY_EN | RAW_RDY_EN | 0 |
aberk 0:b098d99dd81e 190 * +---+------------+------------+---+
aberk 0:b098d99dd81e 191 *
aberk 0:b098d99dd81e 192 * ACTL Logic level for INT output pin; 1 = active low, 0 = active high.
aberk 0:b098d99dd81e 193 * OPEN Drive type for INT output pin; 1 = open drain, 0 = push-pull.
aberk 0:b098d99dd81e 194 * LATCH_INT_EN Latch mode; 1 = latch until interrupt is cleared,
aberk 0:b098d99dd81e 195 * 0 = 50us pulse.
aberk 0:b098d99dd81e 196 * INT_ANYRD_2CLEAR Latch clear method; 1 = any register read,
aberk 0:b098d99dd81e 197 * 0 = status register read only.
aberk 0:b098d99dd81e 198 * ITG_RDY_EN Enable interrupt when device is ready,
aberk 0:b098d99dd81e 199 * (PLL ready after changing clock source).
aberk 0:b098d99dd81e 200 * RAW_RDY_EN Enable interrupt when data is available.
aberk 0:b098d99dd81e 201 * 0 Bits 1 and 3 of the INT_CFG register should be zero.
aberk 0:b098d99dd81e 202 *
aberk 0:b098d99dd81e 203 * @param config Configuration byte to write to INT_CFG register.
aberk 0:b098d99dd81e 204 */
aberk 0:b098d99dd81e 205 void setInterruptConfiguration(char config);
aberk 0:b098d99dd81e 206
aberk 0:b098d99dd81e 207 /**
aberk 0:b098d99dd81e 208 * Check the ITG_RDY bit of the INT_STATUS register.
aberk 0:b098d99dd81e 209 *
aberk 0:b098d99dd81e 210 * @return True if the ITG_RDY bit is set, corresponding to PLL ready,
aberk 0:b098d99dd81e 211 * false if the ITG_RDY bit is not set, corresponding to PLL not
aberk 0:b098d99dd81e 212 * ready.
aberk 0:b098d99dd81e 213 */
aberk 0:b098d99dd81e 214 bool isPllReady(void);
aberk 0:b098d99dd81e 215
aberk 0:b098d99dd81e 216 /**
aberk 0:b098d99dd81e 217 * Check the RAW_DATA_RDY bit of the INT_STATUS register.
aberk 0:b098d99dd81e 218 *
aberk 0:b098d99dd81e 219 * @return True if the RAW_DATA_RDY bit is set, corresponding to new data
aberk 0:b098d99dd81e 220 * in the sensor registers, false if the RAW_DATA_RDY bit is not
aberk 0:b098d99dd81e 221 * set, corresponding to no new data yet in the sensor registers.
aberk 0:b098d99dd81e 222 */
aberk 0:b098d99dd81e 223 bool isRawDataReady(void);
aberk 0:b098d99dd81e 224
aberk 0:b098d99dd81e 225 /**
aberk 0:b098d99dd81e 226 * Get the temperature of the device.
aberk 0:b098d99dd81e 227 *
aberk 0:b098d99dd81e 228 * @return The temperature in degrees celsius.
aberk 0:b098d99dd81e 229 */
aberk 0:b098d99dd81e 230 float getTemperature(void);
aberk 0:b098d99dd81e 231
aberk 0:b098d99dd81e 232 /**
aberk 0:b098d99dd81e 233 * Get the output for the x-axis gyroscope.
aberk 0:b098d99dd81e 234 *
aberk 0:b098d99dd81e 235 * Typical sensitivity is 14.375 LSB/(degrees/sec).
aberk 0:b098d99dd81e 236 *
aberk 0:b098d99dd81e 237 * @return The output on the x-axis in raw ADC counts.
aberk 0:b098d99dd81e 238 */
aberk 0:b098d99dd81e 239 int getGyroX(void);
aberk 0:b098d99dd81e 240
aberk 0:b098d99dd81e 241 /**
aberk 0:b098d99dd81e 242 * Get the output for the y-axis gyroscope.
aberk 0:b098d99dd81e 243 *
aberk 0:b098d99dd81e 244 * Typical sensitivity is 14.375 LSB/(degrees/sec).
aberk 0:b098d99dd81e 245 *
aberk 0:b098d99dd81e 246 * @return The output on the y-axis in raw ADC counts.
aberk 0:b098d99dd81e 247 */
aberk 0:b098d99dd81e 248 int getGyroY(void);
aberk 0:b098d99dd81e 249
aberk 0:b098d99dd81e 250 /**
aberk 0:b098d99dd81e 251 * Get the output on the z-axis gyroscope.
aberk 0:b098d99dd81e 252 *
aberk 0:b098d99dd81e 253 * Typical sensitivity is 14.375 LSB/(degrees/sec).
aberk 0:b098d99dd81e 254 *
aberk 0:b098d99dd81e 255 * @return The output on the z-axis in raw ADC counts.
aberk 0:b098d99dd81e 256 */
aberk 0:b098d99dd81e 257 int getGyroZ(void);
aberk 0:b098d99dd81e 258
aberk 0:b098d99dd81e 259 /**
aberk 0:b098d99dd81e 260 * Get the power management configuration.
aberk 0:b098d99dd81e 261 *
aberk 0:b098d99dd81e 262 * See the datasheet for register contents details.
aberk 0:b098d99dd81e 263 *
aberk 0:b098d99dd81e 264 * 7 6 5 4
aberk 0:b098d99dd81e 265 * +---------+-------+---------+---------+
aberk 0:b098d99dd81e 266 * | H_RESET | SLEEP | STBY_XG | STBY_YG |
aberk 0:b098d99dd81e 267 * +---------+-------+---------+---------+
aberk 0:b098d99dd81e 268 *
aberk 0:b098d99dd81e 269 * 3 2 1 0
aberk 0:b098d99dd81e 270 * +---------+----------+----------+----------+
aberk 0:b098d99dd81e 271 * | STBY_ZG | CLK_SEL2 | CLK_SEL1 | CLK_SEL0 |
aberk 0:b098d99dd81e 272 * +---------+----------+----------+----------+
aberk 0:b098d99dd81e 273 *
aberk 0:b098d99dd81e 274 * H_RESET Reset device and internal registers to the power-up-default settings.
aberk 0:b098d99dd81e 275 * SLEEP Enable low power sleep mode.
aberk 0:b098d99dd81e 276 * STBY_XG Put gyro X in standby mode (1=standby, 0=normal).
aberk 0:b098d99dd81e 277 * STBY_YG Put gyro Y in standby mode (1=standby, 0=normal).
aberk 0:b098d99dd81e 278 * STBY_ZG Put gyro Z in standby mode (1=standby, 0=normal).
aberk 0:b098d99dd81e 279 * CLK_SEL Select device clock source:
aberk 0:b098d99dd81e 280 *
aberk 0:b098d99dd81e 281 * CLK_SEL | Clock Source
aberk 0:b098d99dd81e 282 * --------+--------------
aberk 0:b098d99dd81e 283 * 0 Internal oscillator
aberk 0:b098d99dd81e 284 * 1 PLL with X Gyro reference
aberk 0:b098d99dd81e 285 * 2 PLL with Y Gyro reference
aberk 0:b098d99dd81e 286 * 3 PLL with Z Gyro reference
aberk 0:b098d99dd81e 287 * 4 PLL with external 32.768kHz reference
aberk 0:b098d99dd81e 288 * 5 PLL with external 19.2MHz reference
aberk 0:b098d99dd81e 289 * 6 Reserved
aberk 0:b098d99dd81e 290 * 7 Reserved
aberk 0:b098d99dd81e 291 *
aberk 0:b098d99dd81e 292 * @return The contents of the PWR_MGM register.
aberk 0:b098d99dd81e 293 */
aberk 0:b098d99dd81e 294 char getPowerManagement(void);
aberk 0:b098d99dd81e 295
aberk 0:b098d99dd81e 296 /**
aberk 0:b098d99dd81e 297 * Set power management configuration.
aberk 0:b098d99dd81e 298 *
aberk 0:b098d99dd81e 299 * See the datasheet for configuration byte details
aberk 0:b098d99dd81e 300 *
aberk 0:b098d99dd81e 301 * 7 6 5 4
aberk 0:b098d99dd81e 302 * +---------+-------+---------+---------+
aberk 0:b098d99dd81e 303 * | H_RESET | SLEEP | STBY_XG | STBY_YG |
aberk 0:b098d99dd81e 304 * +---------+-------+---------+---------+
aberk 0:b098d99dd81e 305 *
aberk 0:b098d99dd81e 306 * 3 2 1 0
aberk 0:b098d99dd81e 307 * +---------+----------+----------+----------+
aberk 0:b098d99dd81e 308 * | STBY_ZG | CLK_SEL2 | CLK_SEL1 | CLK_SEL0 |
aberk 0:b098d99dd81e 309 * +---------+----------+----------+----------+
aberk 0:b098d99dd81e 310 *
aberk 0:b098d99dd81e 311 * H_RESET Reset device and internal registers to the power-up-default settings.
aberk 0:b098d99dd81e 312 * SLEEP Enable low power sleep mode.
aberk 0:b098d99dd81e 313 * STBY_XG Put gyro X in standby mode (1=standby, 0=normal).
aberk 0:b098d99dd81e 314 * STBY_YG Put gyro Y in standby mode (1=standby, 0=normal).
aberk 0:b098d99dd81e 315 * STBY_ZG Put gyro Z in standby mode (1=standby, 0=normal).
aberk 0:b098d99dd81e 316 * CLK_SEL Select device clock source:
aberk 0:b098d99dd81e 317 *
aberk 0:b098d99dd81e 318 * CLK_SEL | Clock Source
aberk 0:b098d99dd81e 319 * --------+--------------
aberk 0:b098d99dd81e 320 * 0 Internal oscillator
aberk 0:b098d99dd81e 321 * 1 PLL with X Gyro reference
aberk 0:b098d99dd81e 322 * 2 PLL with Y Gyro reference
aberk 0:b098d99dd81e 323 * 3 PLL with Z Gyro reference
aberk 0:b098d99dd81e 324 * 4 PLL with external 32.768kHz reference
aberk 0:b098d99dd81e 325 * 5 PLL with external 19.2MHz reference
aberk 0:b098d99dd81e 326 * 6 Reserved
aberk 0:b098d99dd81e 327 * 7 Reserved
aberk 0:b098d99dd81e 328 *
aberk 0:b098d99dd81e 329 * @param config The configuration byte to write to the PWR_MGM register.
aberk 0:b098d99dd81e 330 */
aberk 0:b098d99dd81e 331 void setPowerManagement(char config);
aberk 0:b098d99dd81e 332
aberk 0:b098d99dd81e 333 private:
aberk 0:b098d99dd81e 334
aberk 0:b098d99dd81e 335 I2C i2c_;
aberk 0:b098d99dd81e 336
aberk 0:b098d99dd81e 337 };
aberk 0:b098d99dd81e 338
aberk 0:b098d99dd81e 339 #endif /* ITG3200_H */