Kimberly Lie / Mbed 2 deprecated ECE4180_MasterCode

ECE 4180 Project for Spring 2020

Dependencies:   mbed mbed-rtos SDFileSystem PinDetect ESP8266NodeMCUInterface

PowerControl/EthernetPowerControl.cpp@1:5ae291085f75, 2020-05-01 (annotated)

Committer:
kimberlylie99
Date:
Fri May 01 18:43:13 2020 +0000
Revision:
1:5ae291085f75
Parent:
0:b97c07227845 
Edit Main.cpp;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kimberlylie99 0:b97c07227845 1 #include "EthernetPowerControl.h"
kimberlylie99 0:b97c07227845 2
kimberlylie99 0:b97c07227845 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
kimberlylie99 0:b97c07227845 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
kimberlylie99 0:b97c07227845 5 unsigned int tout;
kimberlylie99 0:b97c07227845 6 /* Hardware MII Management for LPC176x devices. */
kimberlylie99 0:b97c07227845 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
kimberlylie99 0:b97c07227845 8 LPC_EMAC->MWTD = Value;
kimberlylie99 0:b97c07227845 9
kimberlylie99 0:b97c07227845 10 /* Wait utill operation completed */
kimberlylie99 0:b97c07227845 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
kimberlylie99 0:b97c07227845 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
kimberlylie99 0:b97c07227845 13 break;
kimberlylie99 0:b97c07227845 14 }
kimberlylie99 0:b97c07227845 15 }
kimberlylie99 0:b97c07227845 16 }
kimberlylie99 0:b97c07227845 17
kimberlylie99 0:b97c07227845 18 static unsigned short read_PHY (unsigned int PhyReg) {
kimberlylie99 0:b97c07227845 19 /* Read a PHY register 'PhyReg'. */
kimberlylie99 0:b97c07227845 20 unsigned int tout, val;
kimberlylie99 0:b97c07227845 21
kimberlylie99 0:b97c07227845 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
kimberlylie99 0:b97c07227845 23 LPC_EMAC->MCMD = MCMD_READ;
kimberlylie99 0:b97c07227845 24
kimberlylie99 0:b97c07227845 25 /* Wait until operation completed */
kimberlylie99 0:b97c07227845 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
kimberlylie99 0:b97c07227845 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
kimberlylie99 0:b97c07227845 28 break;
kimberlylie99 0:b97c07227845 29 }
kimberlylie99 0:b97c07227845 30 }
kimberlylie99 0:b97c07227845 31 LPC_EMAC->MCMD = 0;
kimberlylie99 0:b97c07227845 32 val = LPC_EMAC->MRDD;
kimberlylie99 0:b97c07227845 33
kimberlylie99 0:b97c07227845 34 return (val);
kimberlylie99 0:b97c07227845 35 }
kimberlylie99 0:b97c07227845 36
kimberlylie99 0:b97c07227845 37 void EMAC_Init()
kimberlylie99 0:b97c07227845 38 {
kimberlylie99 0:b97c07227845 39 unsigned int tout,regv;
kimberlylie99 0:b97c07227845 40 /* Power Up the EMAC controller. */
kimberlylie99 0:b97c07227845 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
kimberlylie99 0:b97c07227845 42
kimberlylie99 0:b97c07227845 43 LPC_PINCON->PINSEL2 = 0x50150105;
kimberlylie99 0:b97c07227845 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
kimberlylie99 0:b97c07227845 45 LPC_PINCON->PINSEL3 |= 0x00000005;
kimberlylie99 0:b97c07227845 46
kimberlylie99 0:b97c07227845 47 /* Reset all EMAC internal modules. */
kimberlylie99 0:b97c07227845 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
kimberlylie99 0:b97c07227845 49 MAC1_SIM_RES | MAC1_SOFT_RES;
kimberlylie99 0:b97c07227845 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
kimberlylie99 0:b97c07227845 51
kimberlylie99 0:b97c07227845 52 /* A short delay after reset. */
kimberlylie99 0:b97c07227845 53 for (tout = 100; tout; tout--);
kimberlylie99 0:b97c07227845 54
kimberlylie99 0:b97c07227845 55 /* Initialize MAC control registers. */
kimberlylie99 0:b97c07227845 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
kimberlylie99 0:b97c07227845 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
kimberlylie99 0:b97c07227845 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
kimberlylie99 0:b97c07227845 59 LPC_EMAC->CLRT = CLRT_DEF;
kimberlylie99 0:b97c07227845 60 LPC_EMAC->IPGR = IPGR_DEF;
kimberlylie99 0:b97c07227845 61
kimberlylie99 0:b97c07227845 62 /* Enable Reduced MII interface. */
kimberlylie99 0:b97c07227845 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
kimberlylie99 0:b97c07227845 64
kimberlylie99 0:b97c07227845 65 /* Reset Reduced MII Logic. */
kimberlylie99 0:b97c07227845 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
kimberlylie99 0:b97c07227845 67 for (tout = 100; tout; tout--);
kimberlylie99 0:b97c07227845 68 LPC_EMAC->SUPP = 0;
kimberlylie99 0:b97c07227845 69
kimberlylie99 0:b97c07227845 70 /* Put the DP83848C in reset mode */
kimberlylie99 0:b97c07227845 71 write_PHY (PHY_REG_BMCR, 0x8000);
kimberlylie99 0:b97c07227845 72
kimberlylie99 0:b97c07227845 73 /* Wait for hardware reset to end. */
kimberlylie99 0:b97c07227845 74 for (tout = 0; tout < 0x100000; tout++) {
kimberlylie99 0:b97c07227845 75 regv = read_PHY (PHY_REG_BMCR);
kimberlylie99 0:b97c07227845 76 if (!(regv & 0x8000)) {
kimberlylie99 0:b97c07227845 77 /* Reset complete */
kimberlylie99 0:b97c07227845 78 break;
kimberlylie99 0:b97c07227845 79 }
kimberlylie99 0:b97c07227845 80 }
kimberlylie99 0:b97c07227845 81 }
kimberlylie99 0:b97c07227845 82
kimberlylie99 0:b97c07227845 83
kimberlylie99 0:b97c07227845 84 void PHY_PowerDown()
kimberlylie99 0:b97c07227845 85 {
kimberlylie99 0:b97c07227845 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kimberlylie99 0:b97c07227845 87 EMAC_Init(); //init EMAC if it is not already init'd
kimberlylie99 0:b97c07227845 88
kimberlylie99 0:b97c07227845 89 unsigned int regv;
kimberlylie99 0:b97c07227845 90 regv = read_PHY(PHY_REG_BMCR);
kimberlylie99 0:b97c07227845 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
kimberlylie99 0:b97c07227845 92 regv = read_PHY(PHY_REG_BMCR);
kimberlylie99 0:b97c07227845 93
kimberlylie99 0:b97c07227845 94 //shouldn't need the EMAC now.
kimberlylie99 0:b97c07227845 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
kimberlylie99 0:b97c07227845 96
kimberlylie99 0:b97c07227845 97 //and turn off the PHY OSC
kimberlylie99 0:b97c07227845 98 LPC_GPIO1->FIODIR |= 0x8000000;
kimberlylie99 0:b97c07227845 99 LPC_GPIO1->FIOCLR = 0x8000000;
kimberlylie99 0:b97c07227845 100 }
kimberlylie99 0:b97c07227845 101
kimberlylie99 0:b97c07227845 102 void PHY_PowerUp()
kimberlylie99 0:b97c07227845 103 {
kimberlylie99 0:b97c07227845 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kimberlylie99 0:b97c07227845 105 EMAC_Init(); //init EMAC if it is not already init'd
kimberlylie99 0:b97c07227845 106
kimberlylie99 0:b97c07227845 107 LPC_GPIO1->FIODIR |= 0x8000000;
kimberlylie99 0:b97c07227845 108 LPC_GPIO1->FIOSET = 0x8000000;
kimberlylie99 0:b97c07227845 109
kimberlylie99 0:b97c07227845 110 //wait for osc to be stable
kimberlylie99 0:b97c07227845 111 wait_ms(200);
kimberlylie99 0:b97c07227845 112
kimberlylie99 0:b97c07227845 113 unsigned int regv;
kimberlylie99 0:b97c07227845 114 regv = read_PHY(PHY_REG_BMCR);
kimberlylie99 0:b97c07227845 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
kimberlylie99 0:b97c07227845 116 regv = read_PHY(PHY_REG_BMCR);
kimberlylie99 0:b97c07227845 117 }
kimberlylie99 0:b97c07227845 118
kimberlylie99 0:b97c07227845 119 void PHY_EnergyDetect_Enable()
kimberlylie99 0:b97c07227845 120 {
kimberlylie99 0:b97c07227845 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kimberlylie99 0:b97c07227845 122 EMAC_Init(); //init EMAC if it is not already init'd
kimberlylie99 0:b97c07227845 123
kimberlylie99 0:b97c07227845 124 unsigned int regv;
kimberlylie99 0:b97c07227845 125 regv = read_PHY(PHY_REG_EDCR);
kimberlylie99 0:b97c07227845 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
kimberlylie99 0:b97c07227845 127 regv = read_PHY(PHY_REG_EDCR);
kimberlylie99 0:b97c07227845 128 }
kimberlylie99 0:b97c07227845 129
kimberlylie99 0:b97c07227845 130 void PHY_EnergyDetect_Disable()
kimberlylie99 0:b97c07227845 131 {
kimberlylie99 0:b97c07227845 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
kimberlylie99 0:b97c07227845 133 EMAC_Init(); //init EMAC if it is not already init'd
kimberlylie99 0:b97c07227845 134 unsigned int regv;
kimberlylie99 0:b97c07227845 135 regv = read_PHY(PHY_REG_EDCR);
kimberlylie99 0:b97c07227845 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
kimberlylie99 0:b97c07227845 137 regv = read_PHY(PHY_REG_EDCR);
kimberlylie99 0:b97c07227845 138 }