Kenji Arai / mbed-os_TYBLE16

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Dependents:   TYBLE16_simple_data_logger TYBLE16_MP3_Air

components/802.15.4_RF/stm-s2lp-rf-driver/source/s2lpReg.h@1:9db0e321a9f4, 2019-12-31 (annotated)

Committer:
kenjiArai
Date:
Tue Dec 31 06:02:27 2019 +0000
Revision:
1:9db0e321a9f4
Parent:
0:5b88d5760320 
updated based on mbed-os5.15.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 0:5b88d5760320 1 /*
kenjiArai 0:5b88d5760320 2 * Copyright (c) 2018 ARM Limited. All rights reserved.
kenjiArai 0:5b88d5760320 3 * SPDX-License-Identifier: Apache-2.0
kenjiArai 0:5b88d5760320 4 * Licensed under the Apache License, Version 2.0 (the License); you may
kenjiArai 0:5b88d5760320 5 * not use this file except in compliance with the License.
kenjiArai 0:5b88d5760320 6 * You may obtain a copy of the License at
kenjiArai 0:5b88d5760320 7 *
kenjiArai 0:5b88d5760320 8 * http://www.apache.org/licenses/LICENSE-2.0
kenjiArai 0:5b88d5760320 9 *
kenjiArai 0:5b88d5760320 10 * Unless required by applicable law or agreed to in writing, software
kenjiArai 0:5b88d5760320 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
kenjiArai 0:5b88d5760320 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kenjiArai 0:5b88d5760320 13 * See the License for the specific language governing permissions and
kenjiArai 0:5b88d5760320 14 * limitations under the License.
kenjiArai 0:5b88d5760320 15 */
kenjiArai 0:5b88d5760320 16
kenjiArai 0:5b88d5760320 17 #ifndef S2LPREG_H_
kenjiArai 0:5b88d5760320 18 #define S2LPREG_H_
kenjiArai 0:5b88d5760320 19 #ifdef __cplusplus
kenjiArai 0:5b88d5760320 20 extern "C" {
kenjiArai 0:5b88d5760320 21 #endif
kenjiArai 0:5b88d5760320 22
kenjiArai 0:5b88d5760320 23 #define RF_MTU 2047
kenjiArai 0:5b88d5760320 24 #define PARTNUM 0x03
kenjiArai 0:5b88d5760320 25 #define VERSION 0xC1
kenjiArai 0:5b88d5760320 26 #define FIFO_SIZE 128
kenjiArai 0:5b88d5760320 27 #define SPI_HEADER_LENGTH 2
kenjiArai 0:5b88d5760320 28 #define RSSI_SETTLING_TIME 250
kenjiArai 0:5b88d5760320 29
kenjiArai 0:5b88d5760320 30 #define S2LP_GPIO0 0
kenjiArai 0:5b88d5760320 31 #define S2LP_GPIO1 1
kenjiArai 0:5b88d5760320 32 #define S2LP_GPIO2 2
kenjiArai 0:5b88d5760320 33 #define S2LP_GPIO3 3
kenjiArai 0:5b88d5760320 34
kenjiArai 0:5b88d5760320 35 // GPIO modes
kenjiArai 0:5b88d5760320 36 #define DIG_IN 1
kenjiArai 0:5b88d5760320 37 #define DIG_OUT_LOW 2
kenjiArai 0:5b88d5760320 38 #define DIG_OUT_HIGH 3
kenjiArai 0:5b88d5760320 39
kenjiArai 0:5b88d5760320 40 // Interrupt events
kenjiArai 0:5b88d5760320 41 #define RX_DATA_READY 0
kenjiArai 0:5b88d5760320 42 #define RX_DATA_DISCARDED 1
kenjiArai 0:5b88d5760320 43 #define TX_DATA_SENT 2
kenjiArai 0:5b88d5760320 44 #define MAX_RE_TX 3
kenjiArai 0:5b88d5760320 45 #define CRC_ERROR 4
kenjiArai 0:5b88d5760320 46 #define TX_FIFO_UNF_OVF 5
kenjiArai 0:5b88d5760320 47 #define RX_FIFO_UNF_OVF 6
kenjiArai 0:5b88d5760320 48 #define TX_FIFO_ALMOST_FULL 7
kenjiArai 0:5b88d5760320 49 #define TX_FIFO_ALMOST_EMPTY 8
kenjiArai 0:5b88d5760320 50 #define RX_FIFO_ALMOST_FULL 9
kenjiArai 0:5b88d5760320 51 #define RX_FIFO_ALMOST_EMPTY 10
kenjiArai 0:5b88d5760320 52 #define MAX_CCA_BACKOFFS 11
kenjiArai 0:5b88d5760320 53 #define VALID_PREAMBLE 12
kenjiArai 0:5b88d5760320 54 #define SYNC_WORD 13
kenjiArai 0:5b88d5760320 55 #define RSSI_ABOVE_THR 14
kenjiArai 0:5b88d5760320 56 #define WAKE_UP_TIMEOUT 15
kenjiArai 0:5b88d5760320 57 #define READY 16
kenjiArai 0:5b88d5760320 58 #define STANDBY_SWITCHING 17
kenjiArai 0:5b88d5760320 59 #define LOW_BATTERY_LVL 18
kenjiArai 0:5b88d5760320 60 #define POWER_ON_RESET 19
kenjiArai 0:5b88d5760320 61 #define RX_TIMER_TIMEOUT 28
kenjiArai 0:5b88d5760320 62 #define SNIFF_TIMER_TIMEOUT 29
kenjiArai 0:5b88d5760320 63
kenjiArai 0:5b88d5760320 64 // GPIO signals
kenjiArai 0:5b88d5760320 65 #define NIRQ 0
kenjiArai 0:5b88d5760320 66 #define POR 1
kenjiArai 0:5b88d5760320 67 #define WUT_EXPIRE 2
kenjiArai 0:5b88d5760320 68 #define LOW_BATTERY 3
kenjiArai 0:5b88d5760320 69 #define TX_DATA_OUTPUT 4
kenjiArai 0:5b88d5760320 70 #define TX_STATE 5
kenjiArai 0:5b88d5760320 71 #define TXRX_FIFO_ALMOST_EMPTY 6
kenjiArai 0:5b88d5760320 72 #define TXRX_FIFO_ALMOST_FULL 7
kenjiArai 0:5b88d5760320 73 #define RX_DATA_OUTPUT 8
kenjiArai 0:5b88d5760320 74 #define RX_CLOCK_OUTPUT 9
kenjiArai 0:5b88d5760320 75 #define RX_STATE 10
kenjiArai 0:5b88d5760320 76 #define STATE_OTHER_THAN_SLEEP_OR_STANDBY 11
kenjiArai 0:5b88d5760320 77 #define STANDBY_STATE 12
kenjiArai 0:5b88d5760320 78 #define ANTENNA_SWITCH 13
kenjiArai 0:5b88d5760320 79 #define VALID_PREAMBLE_DETECTED 14
kenjiArai 0:5b88d5760320 80 #define SYNC_WORD_DETECTED 15
kenjiArai 0:5b88d5760320 81 #define RSSI_ABOVE_THRESHOLD 16
kenjiArai 0:5b88d5760320 82 #define TXRX_MODE_INDICATOR 18
kenjiArai 0:5b88d5760320 83 #define VDD 19
kenjiArai 0:5b88d5760320 84 #define GND 20
kenjiArai 0:5b88d5760320 85 #define SMPS_ENABLE 21
kenjiArai 0:5b88d5760320 86 #define SLEEP_STATE 22
kenjiArai 0:5b88d5760320 87 #define READY_STATE 23
kenjiArai 0:5b88d5760320 88 #define LOCK_STATE 24
kenjiArai 0:5b88d5760320 89 #define WAIT_LOCK_DETECTOR 25
kenjiArai 0:5b88d5760320 90 #define TX_DATA_OOK 26
kenjiArai 0:5b88d5760320 91 #define WAIT_READY 27
kenjiArai 0:5b88d5760320 92 #define WAIT_TIMER_EXPIRATION 28
kenjiArai 0:5b88d5760320 93 #define END_OF_CALIBRATION 29
kenjiArai 0:5b88d5760320 94 #define ENABLE_SYNTH_BLOCK 30
kenjiArai 0:5b88d5760320 95
kenjiArai 0:5b88d5760320 96 // RF registers
kenjiArai 0:5b88d5760320 97 #define GPIO0_CONF 0x00
kenjiArai 0:5b88d5760320 98 #define GPIO1_CONF 0x01
kenjiArai 0:5b88d5760320 99 #define GPIO2_CONF 0x02
kenjiArai 0:5b88d5760320 100 #define GPIO3_CONF 0x03
kenjiArai 0:5b88d5760320 101 #define SYNT3 0x05
kenjiArai 0:5b88d5760320 102 #define SYNT2 0x06
kenjiArai 0:5b88d5760320 103 #define SYNT1 0x07
kenjiArai 0:5b88d5760320 104 #define SYNT0 0x08
kenjiArai 0:5b88d5760320 105 #define IF_OFFSET_ANA 0x09
kenjiArai 0:5b88d5760320 106 #define IF_OFFSET_DIG 0x0A
kenjiArai 0:5b88d5760320 107 #define CHSPACE 0x0C
kenjiArai 0:5b88d5760320 108 #define CHNUM 0x0D
kenjiArai 0:5b88d5760320 109 #define MOD4 0x0E
kenjiArai 0:5b88d5760320 110 #define MOD3 0x0F
kenjiArai 0:5b88d5760320 111 #define MOD2 0x10
kenjiArai 0:5b88d5760320 112 #define MOD1 0x11
kenjiArai 0:5b88d5760320 113 #define MOD0 0x12
kenjiArai 0:5b88d5760320 114 #define CHFLT 0x13
kenjiArai 0:5b88d5760320 115 #define AFC2 0x14
kenjiArai 0:5b88d5760320 116 #define AFC1 0x15
kenjiArai 0:5b88d5760320 117 #define AFC0 0x16
kenjiArai 0:5b88d5760320 118 #define RSSI_FLT 0x17
kenjiArai 0:5b88d5760320 119 #define RSSI_TH 0x18
kenjiArai 0:5b88d5760320 120 #define AGCCTRL4 0x1A
kenjiArai 0:5b88d5760320 121 #define AGCCTRL3 0x1B
kenjiArai 0:5b88d5760320 122 #define AGCCTRL2 0x1C
kenjiArai 0:5b88d5760320 123 #define AGCCTRL1 0x1D
kenjiArai 0:5b88d5760320 124 #define AGCCTRL0 0x1E
kenjiArai 0:5b88d5760320 125 #define ANT_SELECT_CONF 0x1F
kenjiArai 0:5b88d5760320 126 #define CLOCKREC2 0x20
kenjiArai 0:5b88d5760320 127 #define CLOCKREC1 0x21
kenjiArai 0:5b88d5760320 128 #define PCKTCTRL6 0x2B
kenjiArai 0:5b88d5760320 129 #define PCKTCTRL5 0x2C
kenjiArai 0:5b88d5760320 130 #define PCKTCTRL4 0x2D
kenjiArai 0:5b88d5760320 131 #define PCKTCTRL3 0x2E
kenjiArai 0:5b88d5760320 132 #define PCKTCTRL2 0x2F
kenjiArai 0:5b88d5760320 133 #define PCKTCTRL1 0x30
kenjiArai 0:5b88d5760320 134 #define PCKTLEN1 0x31
kenjiArai 0:5b88d5760320 135 #define PCKTLEN0 0x32
kenjiArai 0:5b88d5760320 136 #define SYNC3 0x33
kenjiArai 0:5b88d5760320 137 #define SYNC2 0x34
kenjiArai 0:5b88d5760320 138 #define SYNC1 0x35
kenjiArai 0:5b88d5760320 139 #define SYNC0 0x36
kenjiArai 0:5b88d5760320 140 #define QI 0x37
kenjiArai 0:5b88d5760320 141 #define PCKT_PSTMBL 0x38
kenjiArai 0:5b88d5760320 142 #define PROTOCOL2 0x39
kenjiArai 0:5b88d5760320 143 #define PROTOCOL1 0x3A
kenjiArai 0:5b88d5760320 144 #define PROTOCOL0 0x3B
kenjiArai 0:5b88d5760320 145 #define FIFO_CONFIG3 0x3C
kenjiArai 0:5b88d5760320 146 #define FIFO_CONFIG2 0x3D
kenjiArai 0:5b88d5760320 147 #define FIFO_CONFIG1 0x3E
kenjiArai 0:5b88d5760320 148 #define FIFO_CONFIG0 0x3F
kenjiArai 0:5b88d5760320 149 #define PCKT_FLT_OPTIONS 0x40
kenjiArai 0:5b88d5760320 150 #define PCKT_FLT_GOALS4 0x41
kenjiArai 0:5b88d5760320 151 #define PCKT_FLT_GOALS3 0x42
kenjiArai 0:5b88d5760320 152 #define PCKT_FLT_GOALS2 0x43
kenjiArai 0:5b88d5760320 153 #define PCKT_FLT_GOALS1 0x44
kenjiArai 0:5b88d5760320 154 #define PCKT_FLT_GOALS0 0x45
kenjiArai 0:5b88d5760320 155 #define TIMERS5 0x46
kenjiArai 0:5b88d5760320 156 #define TIMERS4 0x47
kenjiArai 0:5b88d5760320 157 #define TIMERS3 0x48
kenjiArai 0:5b88d5760320 158 #define TIMERS2 0x49
kenjiArai 0:5b88d5760320 159 #define TIMERS1 0x4A
kenjiArai 0:5b88d5760320 160 #define TIMERS0 0x4B
kenjiArai 0:5b88d5760320 161 #define CSMA_CONF3 0x4C
kenjiArai 0:5b88d5760320 162 #define CSMA_CONF2 0x4D
kenjiArai 0:5b88d5760320 163 #define CSMA_CONF1 0x4E
kenjiArai 0:5b88d5760320 164 #define CSMA_CONF0 0x4F
kenjiArai 0:5b88d5760320 165 #define IRQ_MASK3 0x50
kenjiArai 0:5b88d5760320 166 #define IRQ_MASK2 0x51
kenjiArai 0:5b88d5760320 167 #define IRQ_MASK1 0x52
kenjiArai 0:5b88d5760320 168 #define IRQ_MASK0 0x53
kenjiArai 0:5b88d5760320 169 #define FAST_RX_TIMER 0x54
kenjiArai 0:5b88d5760320 170 #define PA_POWER8 0x5A
kenjiArai 0:5b88d5760320 171 #define PA_POWER7 0x5B
kenjiArai 0:5b88d5760320 172 #define PA_POWER6 0x5C
kenjiArai 0:5b88d5760320 173 #define PA_POWER5 0x5D
kenjiArai 0:5b88d5760320 174 #define PA_POWER4 0x5E
kenjiArai 0:5b88d5760320 175 #define PA_POWER3 0x5F
kenjiArai 0:5b88d5760320 176 #define PA_POWER2 0x60
kenjiArai 0:5b88d5760320 177 #define PA_POWER1 0x61
kenjiArai 0:5b88d5760320 178 #define PA_POWER0 0x62
kenjiArai 0:5b88d5760320 179 #define PA_CONFIG1 0x63
kenjiArai 0:5b88d5760320 180 #define PA_CONFIG0 0x64
kenjiArai 0:5b88d5760320 181 #define SYNTH_CONFIG2 0x65
kenjiArai 0:5b88d5760320 182 #define VCO_CONFIG 0x68
kenjiArai 0:5b88d5760320 183 #define VCO_CALIBR_IN2 0x69
kenjiArai 0:5b88d5760320 184 #define VCO_CALIBR_IN1 0x6A
kenjiArai 0:5b88d5760320 185 #define VCO_CALIBR_IN0 0x6B
kenjiArai 0:5b88d5760320 186 #define XO_RCO_CONF1 0x6C
kenjiArai 0:5b88d5760320 187 #define XO_RCO_CONF0 0x6D
kenjiArai 0:5b88d5760320 188 #define RCO_CALIBR_CONF3 0x6E
kenjiArai 0:5b88d5760320 189 #define RCO_CALIBR_CONF2 0x6F
kenjiArai 0:5b88d5760320 190 #define PM_CONF4 0x75
kenjiArai 0:5b88d5760320 191 #define PM_CONF3 0x76
kenjiArai 0:5b88d5760320 192 #define PM_CONF2 0x77
kenjiArai 0:5b88d5760320 193 #define PM_CONF1 0x78
kenjiArai 0:5b88d5760320 194 #define PM_CONF0 0x79
kenjiArai 0:5b88d5760320 195 #define MC_STATE1 0x8D
kenjiArai 0:5b88d5760320 196 #define MC_STATE0 0x8E
kenjiArai 0:5b88d5760320 197 #define TX_FIFO_STATUS 0x8F
kenjiArai 0:5b88d5760320 198 #define RX_FIFO_STATUS 0x90
kenjiArai 0:5b88d5760320 199 #define RCO_CALIBR_OUT4 0x94
kenjiArai 0:5b88d5760320 200 #define RCO_CALIBR_OUT3 0x95
kenjiArai 0:5b88d5760320 201 #define VCO_CALIBR_OUT1 0x99
kenjiArai 0:5b88d5760320 202 #define VCO_CALIBR_OUT0 0x9A
kenjiArai 0:5b88d5760320 203 #define TX_PCKT_INFO 0x9C
kenjiArai 0:5b88d5760320 204 #define RX_PCKT_INFO 0x9D
kenjiArai 0:5b88d5760320 205 #define AFC_CORR 0x9E
kenjiArai 0:5b88d5760320 206 #define LINK_QUALIF2 0x9F
kenjiArai 0:5b88d5760320 207 #define LINK_QUALIF1 0xA0
kenjiArai 0:5b88d5760320 208 #define RSSI_LEVEL 0xA2
kenjiArai 0:5b88d5760320 209 #define RX_PCKT_LEN1 0xA4
kenjiArai 0:5b88d5760320 210 #define RX_PCKT_LEN0 0xA5
kenjiArai 0:5b88d5760320 211 #define CRC_FIELD3 0xA6
kenjiArai 0:5b88d5760320 212 #define CRC_FIELD2 0xA7
kenjiArai 0:5b88d5760320 213 #define CRC_FIELD1 0xA8
kenjiArai 0:5b88d5760320 214 #define CRC_FIELD0 0xA9
kenjiArai 0:5b88d5760320 215 #define RX_ADDRE_FIELD1 0xAA
kenjiArai 0:5b88d5760320 216 #define RX_ADDRE_FIELD0 0xAB
kenjiArai 0:5b88d5760320 217 #define RSSI_LEVEL_RUN 0xEF
kenjiArai 0:5b88d5760320 218 #define DEVICE_INFO1 0xF0
kenjiArai 0:5b88d5760320 219 #define DEVICE_INFO0 0xF1
kenjiArai 0:5b88d5760320 220 #define IRQ_STATUS3 0xFA
kenjiArai 0:5b88d5760320 221 #define IRQ_STATUS2 0xFB
kenjiArai 0:5b88d5760320 222 #define IRQ_STATUS1 0xFC
kenjiArai 0:5b88d5760320 223 #define IRQ_STATUS0 0xFD
kenjiArai 0:5b88d5760320 224 #define TX_FIFO 0xFF
kenjiArai 0:5b88d5760320 225 #define RX_FIFO 0xFF
kenjiArai 0:5b88d5760320 226
kenjiArai 0:5b88d5760320 227 #define SFD0 0x90
kenjiArai 0:5b88d5760320 228 #define SFD1 0x4e
kenjiArai 0:5b88d5760320 229
kenjiArai 0:5b88d5760320 230 #define DEFAULT_DEVIATION 125000
kenjiArai 0:5b88d5760320 231 #define RX_FILTER_BANDWIDTH 540000
kenjiArai 1:9db0e321a9f4 232 #define RSSI_THRESHOLD -85
kenjiArai 0:5b88d5760320 233
kenjiArai 0:5b88d5760320 234 // PCKTCTRL6
kenjiArai 0:5b88d5760320 235 #define PCKT_SYNCLEN_FIELD 0xFC
kenjiArai 0:5b88d5760320 236 #define PCKT_SYNCLEN (16 << 2)
kenjiArai 0:5b88d5760320 237
kenjiArai 0:5b88d5760320 238 // PCKTCTRL5
kenjiArai 0:5b88d5760320 239 #define PCKT_PREAMBLE_LEN 32
kenjiArai 0:5b88d5760320 240
kenjiArai 0:5b88d5760320 241 // PCKTCTRL3
kenjiArai 0:5b88d5760320 242 #define PCKT_FORMAT_FIELD 0xC0
kenjiArai 0:5b88d5760320 243 #define PCKT_FORMAT_802_15_4 (1 << 6)
kenjiArai 0:5b88d5760320 244 #define PCKT_RXMODE_FIELD 0x30
kenjiArai 0:5b88d5760320 245 #define PCKT_RXMODE_NORMAL (0 << 4)
kenjiArai 0:5b88d5760320 246 #define PCKT_BYTE_SWAP_FIELD 0x04
kenjiArai 0:5b88d5760320 247 #define PCKT_BYTE_SWAP_LSB (1 << 2)
kenjiArai 0:5b88d5760320 248
kenjiArai 0:5b88d5760320 249 // PCKTCTRL2
kenjiArai 0:5b88d5760320 250 #define PCKT_FIXVARLEN_FIELD 0x01
kenjiArai 0:5b88d5760320 251 #define PCKT_VARIABLE_LEN (1 << 0)
kenjiArai 1:9db0e321a9f4 252 #define PCKT_FCS_TYPE_FIELD 0x20
kenjiArai 1:9db0e321a9f4 253 #define PCKT_FCS_TYPE_4_OCTET (0 << 5)
kenjiArai 1:9db0e321a9f4 254 #define PCKT_FCS_TYPE_2_OCTET (1 << 5)
kenjiArai 0:5b88d5760320 255
kenjiArai 0:5b88d5760320 256 // PCKTCTRL1
kenjiArai 0:5b88d5760320 257 #define PCKT_CRCMODE_FIELD 0xE0
kenjiArai 0:5b88d5760320 258 #define PCKT_CRCMODE_0X1021 (3 << 5)
kenjiArai 1:9db0e321a9f4 259 #define PCKT_CRCMODE_0x04C11DB7 (5 << 5)
kenjiArai 0:5b88d5760320 260 #define PCKT_TXSOURCE_FIELD 0x0C
kenjiArai 0:5b88d5760320 261 #define PCKT_TXSOURCE_NORMAL (0 << 2)
kenjiArai 0:5b88d5760320 262 #define PCKT_WHITENING_FIELD 0x10
kenjiArai 0:5b88d5760320 263 #define PCKT_WHITENING_ENABLED (1 << 4)
kenjiArai 0:5b88d5760320 264
kenjiArai 0:5b88d5760320 265 // MOD4
kenjiArai 0:5b88d5760320 266 #define DATARATE_M_MSB 0x47
kenjiArai 0:5b88d5760320 267 // MOD3
kenjiArai 0:5b88d5760320 268 #define DATARATE_M_LSB 0xAE
kenjiArai 0:5b88d5760320 269
kenjiArai 0:5b88d5760320 270 // MOD2
kenjiArai 0:5b88d5760320 271 #define MOD_TYPE_FIELD 0xF0
kenjiArai 0:5b88d5760320 272 #define MOD_2FSK (0 << 4)
kenjiArai 0:5b88d5760320 273 #define MOD_2GFSK (10 << 4)
kenjiArai 0:5b88d5760320 274 #define DATARATE_E_FIELD 0x0F
kenjiArai 0:5b88d5760320 275 #define DATARATE_E (10 << 0)
kenjiArai 0:5b88d5760320 276
kenjiArai 0:5b88d5760320 277 // MOD1
kenjiArai 0:5b88d5760320 278 #define FDEV_E_FIELD 0x0F
kenjiArai 0:5b88d5760320 279
kenjiArai 0:5b88d5760320 280 // QI
kenjiArai 0:5b88d5760320 281 #define PQI_TH_FIELD 0x1E
kenjiArai 0:5b88d5760320 282 #define PQI_TH (8 << 1)
kenjiArai 0:5b88d5760320 283 #define SQI_EN_FIELD 0x01
kenjiArai 0:5b88d5760320 284 #define SQI_EN (1 << 0)
kenjiArai 0:5b88d5760320 285
kenjiArai 0:5b88d5760320 286 // SYNT3
kenjiArai 0:5b88d5760320 287 #define SYNT_FIELD 0x0F
kenjiArai 0:5b88d5760320 288
kenjiArai 0:5b88d5760320 289 // CHFLT
kenjiArai 0:5b88d5760320 290 #define CHFLT_M_FIELD 0xF0
kenjiArai 0:5b88d5760320 291 #define CHFLT_E_FIELD 0x0F
kenjiArai 0:5b88d5760320 292
kenjiArai 0:5b88d5760320 293 // LINK_QUALIF1
kenjiArai 0:5b88d5760320 294 #define CARRIER_SENSE (1 << 7)
kenjiArai 0:5b88d5760320 295
kenjiArai 0:5b88d5760320 296 #define SPI_WR_REG 0x00
kenjiArai 0:5b88d5760320 297 #define SPI_RD_REG 0x01
kenjiArai 0:5b88d5760320 298 #define SPI_CMD 0x80
kenjiArai 0:5b88d5760320 299
kenjiArai 0:5b88d5760320 300 typedef enum {
kenjiArai 0:5b88d5760320 301 S2LP_STATE_STANDBY = 0x02,
kenjiArai 0:5b88d5760320 302 S2LP_STATE_SLEEPA = 0x01,
kenjiArai 0:5b88d5760320 303 S2LP_STATE_SLEEPB = 0x03,
kenjiArai 0:5b88d5760320 304 S2LP_STATE_READY = 0x00,
kenjiArai 0:5b88d5760320 305 S2LP_STATE_LOCK = 0x0C,
kenjiArai 0:5b88d5760320 306 S2LP_STATE_RX = 0x30,
kenjiArai 0:5b88d5760320 307 S2LP_STATE_TX = 0x5C,
kenjiArai 0:5b88d5760320 308 S2LP_STATE_SYNTH_SETUP = 0x50
kenjiArai 0:5b88d5760320 309 } s2lp_states_e;
kenjiArai 0:5b88d5760320 310
kenjiArai 0:5b88d5760320 311 #if defined __cplusplus && __cplusplus >= 201103
kenjiArai 0:5b88d5760320 312 typedef enum : uint8_t {
kenjiArai 0:5b88d5760320 313 #else
kenjiArai 0:5b88d5760320 314 typedef enum {
kenjiArai 0:5b88d5760320 315 #endif
kenjiArai 0:5b88d5760320 316 S2LP_CMD_TX = 0x60,
kenjiArai 0:5b88d5760320 317 S2LP_CMD_RX,
kenjiArai 0:5b88d5760320 318 S2LP_CMD_READY,
kenjiArai 0:5b88d5760320 319 S2LP_CMD_STANDBY,
kenjiArai 0:5b88d5760320 320 S2LP_CMD_SLEEP,
kenjiArai 0:5b88d5760320 321 S2LP_CMD_LOCKRX,
kenjiArai 0:5b88d5760320 322 S2LP_CMD_LOCKTX,
kenjiArai 0:5b88d5760320 323 S2LP_CMD_SABORT,
kenjiArai 0:5b88d5760320 324 S2LP_CMD_LDC_RELOAD,
kenjiArai 0:5b88d5760320 325 S2LP_CMD_SRES = 0x70,
kenjiArai 0:5b88d5760320 326 S2LP_CMD_FLUSHRXFIFO,
kenjiArai 0:5b88d5760320 327 S2LP_CMD_FLUSHTXFIFO,
kenjiArai 0:5b88d5760320 328 S2LP_CMD_SEQUPDATE
kenjiArai 0:5b88d5760320 329 } s2lp_commands_e;
kenjiArai 0:5b88d5760320 330
kenjiArai 0:5b88d5760320 331 typedef enum {
kenjiArai 0:5b88d5760320 332 RF_IDLE,
kenjiArai 0:5b88d5760320 333 RF_CSMA_STARTED,
kenjiArai 0:5b88d5760320 334 RF_TX_STARTED,
kenjiArai 0:5b88d5760320 335 RF_RX_STARTED,
kenjiArai 0:5b88d5760320 336 RF_TX_ACK
kenjiArai 0:5b88d5760320 337 } rf_states_e;
kenjiArai 0:5b88d5760320 338
kenjiArai 0:5b88d5760320 339 #ifdef __cplusplus
kenjiArai 0:5b88d5760320 340 }
kenjiArai 0:5b88d5760320 341 #endif
kenjiArai 0:5b88d5760320 342
kenjiArai 0:5b88d5760320 343 #endif /* S2LPREG_H_ */