Diff: hal/spi_api.h

Revision:

1:9db0e321a9f4

Parent:

0:5b88d5760320

--- a/hal/spi_api.h	Tue Dec 17 23:23:45 2019 +0000
+++ b/hal/spi_api.h	Tue Dec 31 06:02:27 2019 +0000
@@ -53,15 +53,106 @@
 
 #endif
 
+typedef struct {
+    int peripheral;
+    PinName mosi_pin;
+    int mosi_function;
+    PinName miso_pin;
+    int miso_function;
+    PinName sclk_pin;
+    int sclk_function;
+    PinName ssel_pin;
+    int ssel_function;
+} spi_pinmap_t;
+
+/**
+ * Describes the capabilities of a SPI peripherals
+ */
+typedef struct {
+    /** Minimum frequency supported must be set by target device and it will be assessed during
+     *  testing.
+     */
+    uint32_t    minimum_frequency;
+    /** Maximum frequency supported must be set by target device and it will be assessed during
+     *  testing.
+     */
+    uint32_t    maximum_frequency;
+    /** Each bit represents the corresponding word length. lsb => 1bit, msb => 32bit. */
+    uint32_t    word_length;
+    uint16_t    slave_delay_between_symbols_ns; /**< specifies required number of ns between transmission of successive symbols in slave mode. */
+    uint8_t     clk_modes; /**< specifies supported modes from spi_mode_t. Each bit represents the corresponding mode. */
+    bool        support_slave_mode; /**< If true, the device can handle SPI slave mode using hardware management on the specified ssel pin. */
+    bool        hw_cs_handle; /**< If true, in SPI master mode Chip Select can be handled by hardware. */
+    bool        async_mode; /**< If true, in async mode is supported. */
+
+} spi_capabilities_t;
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /**
  * \defgroup hal_GeneralSPI SPI Configuration Functions
+ *
+ * # Defined behavior
+ * * ::spi_init initializes the spi_t control structure
+ * * ::spi_init configures the pins used by SPI
+ * * ::spi_get_capabilities() fills the given `spi_capabilities_t` instance
+ * * ::spi_get_capabilities() should consider the `ssel` pin when evaluation the `support_slave_mode` and `hw_cs_handle` capability
+ * * ::spi_get_capabilities(): if the given `ssel` pin cannot be managed by hardware, `support_slave_mode` and `hw_cs_handle` should be false
+ * * At least a symbol width of 8bit must be supported
+ * * The supported frequency range must include the range [0.2..2] MHz
+ * * ::spi_free returns the pins owned by the SPI object to their reset state
+ * * ::spi_format sets the number of bits per frame
+ * * ::spi_format configures clock polarity and phase
+ * * ::spi_format configures master/slave mode
+ * * ::spi_frequency sets the SPI baud rate
+ * * ::spi_master_write writes a symbol out in master mode and receives a symbol
+ * * ::spi_master_block_write writes `tx_length` words to the bus
+ * * ::spi_master_block_write reads `rx_length` words from the bus
+ * * ::spi_master_block_write returns the maximum of tx_length and rx_length
+ * * ::spi_master_block_write specifies the write_fill which is default data transmitted while performing a read
+ * * ::spi_get_module returns non-zero if a value is available to read from SPI channel, 0 otherwise
+ * * ::spi_slave_read returns a received value out of the SPI receive buffer in slave mode
+ * * ::spi_slave_read blocks until a value is available
+ * * ::spi_slave_write writes a value to the SPI peripheral in slave mode
+ * * ::spi_slave_write blocks until the SPI peripheral can be written to
+ * * ::spi_busy returns non-zero if the peripheral is currently transmitting, 0 otherwise
+ * * ::spi_master_transfer starts the SPI asynchronous transfer
+ * * ::spi_master_transfer writes `tx_len` words to the bus
+ * * ::spi_master_transfer reads `rx_len` words from the bus
+ * * ::spi_master_transfer specifies the bit width of buffer words
+ * * The callback given to ::spi_master_transfer is invoked when the transfer completes (with a success or an error)
+ * * ::spi_master_transfer specifies the logical OR of events to be registered
+ * * The ::spi_master_transfer function may use the `DMAUsage` hint to select the appropriate async algorithm
+ * * ::spi_irq_handler_asynch reads the received values out of the RX FIFO
+ * * ::spi_irq_handler_asynch writes values into the TX FIFO
+ * * ::spi_irq_handler_asynch checks for transfer termination conditions, such as buffer overflows or transfer complete
+ * * ::spi_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise 0
+ * * ::spi_abort_asynch aborts an on-going async transfer
+ * * ::spi_active returns non-zero if the SPI port is active or zero if it is not
+ *
+ * # Undefined behavior
+ * * Calling ::spi_init multiple times on the same `spi_t` without ::spi_free
+ * * Calling any function other than ::spi_init on a non-initialized or freed `spi_t`
+ * * Passing pins that cannot be on the same peripheral
+ * * Passing an invalid pointer as `obj` to any function
+ * * Passing an invalid pointer as `handler` to ::spi_master_transfer
+ * * Calling ::spi_abort while no async transfer is being processed (no transfer or a synchronous transfer)
+ *
  * @{
  */
 
+/**
+ * \defgroup hal_GeneralSPI_tests SPI hal tests
+ * The SPI HAL tests ensure driver conformance to defined behaviour.
+ *
+ * To run the SPI hal tests use the command:
+ *
+ *     mbed test -t <toolchain> -m <target> -n tests-mbed_hal_fpga_ci_test_shield-spi
+ *
+ */
+
 #ifdef DEVICE_SPI_COUNT
 /**
  * Returns a variant of the SPIName enum uniquely identifying a SPI peripheral of the device.
@@ -73,6 +164,19 @@
 SPIName spi_get_peripheral_name(PinName mosi, PinName miso, PinName mclk);
 #endif
 
+/**
+ * Fills the given spi_capabilities_t structure with the capabilities of the given peripheral.
+ */
+void spi_get_capabilities(PinName ssel, bool slave, spi_capabilities_t *cap);
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj  The SPI object to initialize
+ * @param[in]  pinmap pointer to structure which holds static pinmap
+ */
+void spi_init_direct(spi_t *obj, const spi_pinmap_t *pinmap);
+
 /** Initialize the SPI peripheral
  *
  * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral