Kenji Arai / mbed-os_TYBLE16

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Dependents:   TYBLE16_simple_data_logger TYBLE16_MP3_Air

drivers/QSPI.h@0:5b88d5760320, 2019-12-17 (annotated)

Committer:
kenjiArai
Date:
Tue Dec 17 23:23:45 2019 +0000
Revision:
0:5b88d5760320
Child:
1:9db0e321a9f4
mbed-os5 only for TYBLE16

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kenjiArai 0:5b88d5760320 1 /* mbed Microcontroller Library
kenjiArai 0:5b88d5760320 2 * Copyright (c) 2006-2018 ARM Limited
kenjiArai 0:5b88d5760320 3 * SPDX-License-Identifier: Apache-2.0
kenjiArai 0:5b88d5760320 4 *
kenjiArai 0:5b88d5760320 5 * Licensed under the Apache License, Version 2.0 (the "License");
kenjiArai 0:5b88d5760320 6 * you may not use this file except in compliance with the License.
kenjiArai 0:5b88d5760320 7 * You may obtain a copy of the License at
kenjiArai 0:5b88d5760320 8 *
kenjiArai 0:5b88d5760320 9 * http://www.apache.org/licenses/LICENSE-2.0
kenjiArai 0:5b88d5760320 10 *
kenjiArai 0:5b88d5760320 11 * Unless required by applicable law or agreed to in writing, software
kenjiArai 0:5b88d5760320 12 * distributed under the License is distributed on an "AS IS" BASIS,
kenjiArai 0:5b88d5760320 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
kenjiArai 0:5b88d5760320 14 * See the License for the specific language governing permissions and
kenjiArai 0:5b88d5760320 15 * limitations under the License.
kenjiArai 0:5b88d5760320 16 */
kenjiArai 0:5b88d5760320 17 #ifndef MBED_QSPI_H
kenjiArai 0:5b88d5760320 18 #define MBED_QSPI_H
kenjiArai 0:5b88d5760320 19
kenjiArai 0:5b88d5760320 20 #include "platform/platform.h"
kenjiArai 0:5b88d5760320 21
kenjiArai 0:5b88d5760320 22 #if DEVICE_QSPI || defined(DOXYGEN_ONLY)
kenjiArai 0:5b88d5760320 23
kenjiArai 0:5b88d5760320 24 #include "hal/qspi_api.h"
kenjiArai 0:5b88d5760320 25 #include "platform/PlatformMutex.h"
kenjiArai 0:5b88d5760320 26 #include "platform/SingletonPtr.h"
kenjiArai 0:5b88d5760320 27 #include "platform/NonCopyable.h"
kenjiArai 0:5b88d5760320 28
kenjiArai 0:5b88d5760320 29 #define ONE_MHZ 1000000
kenjiArai 0:5b88d5760320 30
kenjiArai 0:5b88d5760320 31 namespace mbed {
kenjiArai 0:5b88d5760320 32
kenjiArai 0:5b88d5760320 33 /** \addtogroup drivers */
kenjiArai 0:5b88d5760320 34
kenjiArai 0:5b88d5760320 35 /** A QSPI Driver, used for communicating with QSPI slave devices
kenjiArai 0:5b88d5760320 36 *
kenjiArai 0:5b88d5760320 37 * The default format is set to Quad-SPI(1-1-1), and a clock frequency of 1MHz
kenjiArai 0:5b88d5760320 38 * Most QSPI devices will also require Chip Select which is indicated by ssel.
kenjiArai 0:5b88d5760320 39 *
kenjiArai 0:5b88d5760320 40 * @note Synchronization level: Thread safe
kenjiArai 0:5b88d5760320 41 *
kenjiArai 0:5b88d5760320 42 * Example:
kenjiArai 0:5b88d5760320 43 * @code
kenjiArai 0:5b88d5760320 44 * // Write 4 byte array to a QSPI slave, and read the response, note that each device will have its specific read/write/alt values defined
kenjiArai 0:5b88d5760320 45 *
kenjiArai 0:5b88d5760320 46 * #include "mbed.h"
kenjiArai 0:5b88d5760320 47 *
kenjiArai 0:5b88d5760320 48 * #define CMD_WRITE 0x02
kenjiArai 0:5b88d5760320 49 * #define CMD_READ 0x03
kenjiArai 0:5b88d5760320 50 * #define ADDRESS 0x1000
kenjiArai 0:5b88d5760320 51 *
kenjiArai 0:5b88d5760320 52 * // hardware ssel (where applicable)
kenjiArai 0:5b88d5760320 53 * QSPI qspi_device(QSPI_FLASH1_IO0, QSPI_FLASH1_IO1, QSPI_FLASH1_IO2, QSPI_FLASH1_IO3, QSPI_FLASH1_SCK, QSPI_FLASH1_CSN); // io0, io1, io2, io3, sclk, ssel
kenjiArai 0:5b88d5760320 54 *
kenjiArai 0:5b88d5760320 55 *
kenjiArai 0:5b88d5760320 56 * int main() {
kenjiArai 0:5b88d5760320 57 * char tx_buf[] = { 0x11, 0x22, 0x33, 0x44 };
kenjiArai 0:5b88d5760320 58 * char rx_buf[4];
kenjiArai 0:5b88d5760320 59 * int buf_len = sizeof(tx_buf);
kenjiArai 0:5b88d5760320 60 *
kenjiArai 0:5b88d5760320 61 * qspi_status_t result = qspi_device.write(CMD_WRITE, 0, ADDRESS, tx_buf, &buf_len);
kenjiArai 0:5b88d5760320 62 * if (result != QSPI_STATUS_OK) {
kenjiArai 0:5b88d5760320 63 * printf("Write failed");
kenjiArai 0:5b88d5760320 64 * }
kenjiArai 0:5b88d5760320 65 * result = qspi_device.read(CMD_READ, 0, ADDRESS, rx_buf, &buf_len);
kenjiArai 0:5b88d5760320 66 * if (result != QSPI_STATUS_OK) {
kenjiArai 0:5b88d5760320 67 * printf("Read failed");
kenjiArai 0:5b88d5760320 68 * }
kenjiArai 0:5b88d5760320 69 *
kenjiArai 0:5b88d5760320 70 * }
kenjiArai 0:5b88d5760320 71 * @endcode
kenjiArai 0:5b88d5760320 72 * @ingroup drivers
kenjiArai 0:5b88d5760320 73 */
kenjiArai 0:5b88d5760320 74 class QSPI : private NonCopyable<QSPI> {
kenjiArai 0:5b88d5760320 75
kenjiArai 0:5b88d5760320 76 public:
kenjiArai 0:5b88d5760320 77
kenjiArai 0:5b88d5760320 78 /** Create a QSPI master connected to the specified pins
kenjiArai 0:5b88d5760320 79 *
kenjiArai 0:5b88d5760320 80 * io0-io3 is used to specify the Pins used for Quad SPI mode
kenjiArai 0:5b88d5760320 81 *
kenjiArai 0:5b88d5760320 82 * @param io0 1st IO pin used for sending/receiving data during data phase of a transaction
kenjiArai 0:5b88d5760320 83 * @param io1 2nd IO pin used for sending/receiving data during data phase of a transaction
kenjiArai 0:5b88d5760320 84 * @param io2 3rd IO pin used for sending/receiving data during data phase of a transaction
kenjiArai 0:5b88d5760320 85 * @param io3 4th IO pin used for sending/receiving data during data phase of a transaction
kenjiArai 0:5b88d5760320 86 * @param sclk QSPI Clock pin
kenjiArai 0:5b88d5760320 87 * @param ssel QSPI chip select pin
kenjiArai 0:5b88d5760320 88 * @param mode Clock polarity and phase mode (0 - 3) of SPI
kenjiArai 0:5b88d5760320 89 * (Default: Mode=0 uses CPOL=0, CPHA=0, Mode=1 uses CPOL=1, CPHA=1)
kenjiArai 0:5b88d5760320 90 *
kenjiArai 0:5b88d5760320 91 */
kenjiArai 0:5b88d5760320 92 QSPI(PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel = NC, int mode = 0);
kenjiArai 0:5b88d5760320 93 virtual ~QSPI()
kenjiArai 0:5b88d5760320 94 {
kenjiArai 0:5b88d5760320 95 }
kenjiArai 0:5b88d5760320 96
kenjiArai 0:5b88d5760320 97 /** Configure the data transmission format
kenjiArai 0:5b88d5760320 98 *
kenjiArai 0:5b88d5760320 99 * @param inst_width Bus width used by instruction phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kenjiArai 0:5b88d5760320 100 * @param address_width Bus width used by address phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kenjiArai 0:5b88d5760320 101 * @param address_size Size in bits used by address phase(Valid values are QSPI_CFG_ADDR_SIZE_8, QSPI_CFG_ADDR_SIZE_16, QSPI_CFG_ADDR_SIZE_24, QSPI_CFG_ADDR_SIZE_32)
kenjiArai 0:5b88d5760320 102 * @param alt_width Bus width used by alt phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kenjiArai 0:5b88d5760320 103 * @param alt_size Size in bits used by alt phase(Valid values are QSPI_CFG_ALT_SIZE_8, QSPI_CFG_ALT_SIZE_16, QSPI_CFG_ALT_SIZE_24, QSPI_CFG_ALT_SIZE_32)
kenjiArai 0:5b88d5760320 104 * @param data_width Bus width used by data phase(Valid values are QSPI_CFG_BUS_SINGLE, QSPI_CFG_BUS_DUAL, QSPI_CFG_BUS_QUAD)
kenjiArai 0:5b88d5760320 105 * @param dummy_cycles Number of dummy clock cycles to be used after alt phase
kenjiArai 0:5b88d5760320 106 *
kenjiArai 0:5b88d5760320 107 */
kenjiArai 0:5b88d5760320 108 qspi_status_t configure_format(qspi_bus_width_t inst_width,
kenjiArai 0:5b88d5760320 109 qspi_bus_width_t address_width,
kenjiArai 0:5b88d5760320 110 qspi_address_size_t address_size,
kenjiArai 0:5b88d5760320 111 qspi_bus_width_t alt_width,
kenjiArai 0:5b88d5760320 112 qspi_alt_size_t alt_size,
kenjiArai 0:5b88d5760320 113 qspi_bus_width_t data_width,
kenjiArai 0:5b88d5760320 114 int dummy_cycles);
kenjiArai 0:5b88d5760320 115
kenjiArai 0:5b88d5760320 116 /** Set the qspi bus clock frequency
kenjiArai 0:5b88d5760320 117 *
kenjiArai 0:5b88d5760320 118 * @param hz SCLK frequency in hz (default = 1MHz)
kenjiArai 0:5b88d5760320 119 * @returns
kenjiArai 0:5b88d5760320 120 * Returns QSPI_STATUS_SUCCESS on successful, fails if the interface is already init-ed
kenjiArai 0:5b88d5760320 121 */
kenjiArai 0:5b88d5760320 122 qspi_status_t set_frequency(int hz = ONE_MHZ);
kenjiArai 0:5b88d5760320 123
kenjiArai 0:5b88d5760320 124 /** Read from QSPI peripheral with the preset read_instruction and alt_value
kenjiArai 0:5b88d5760320 125 *
kenjiArai 0:5b88d5760320 126 * @param address Address to be accessed in QSPI peripheral
kenjiArai 0:5b88d5760320 127 * @param rx_buffer Buffer for data to be read from the peripheral
kenjiArai 0:5b88d5760320 128 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
kenjiArai 0:5b88d5760320 129 *
kenjiArai 0:5b88d5760320 130 * @returns
kenjiArai 0:5b88d5760320 131 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kenjiArai 0:5b88d5760320 132 */
kenjiArai 0:5b88d5760320 133 qspi_status_t read(int address, char *rx_buffer, size_t *rx_length);
kenjiArai 0:5b88d5760320 134
kenjiArai 0:5b88d5760320 135 /** Write to QSPI peripheral using custom write instruction
kenjiArai 0:5b88d5760320 136 *
kenjiArai 0:5b88d5760320 137 * @param address Address to be accessed in QSPI peripheral
kenjiArai 0:5b88d5760320 138 * @param tx_buffer Buffer containing data to be sent to peripheral
kenjiArai 0:5b88d5760320 139 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
kenjiArai 0:5b88d5760320 140 *
kenjiArai 0:5b88d5760320 141 * @returns
kenjiArai 0:5b88d5760320 142 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kenjiArai 0:5b88d5760320 143 */
kenjiArai 0:5b88d5760320 144 qspi_status_t write(int address, const char *tx_buffer, size_t *tx_length);
kenjiArai 0:5b88d5760320 145
kenjiArai 0:5b88d5760320 146 /** Read from QSPI peripheral using custom read instruction, alt values
kenjiArai 0:5b88d5760320 147 *
kenjiArai 0:5b88d5760320 148 * @param instruction Instruction value to be used in instruction phase
kenjiArai 0:5b88d5760320 149 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
kenjiArai 0:5b88d5760320 150 * @param address Address to be accessed in QSPI peripheral
kenjiArai 0:5b88d5760320 151 * @param rx_buffer Buffer for data to be read from the peripheral
kenjiArai 0:5b88d5760320 152 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
kenjiArai 0:5b88d5760320 153 *
kenjiArai 0:5b88d5760320 154 * @returns
kenjiArai 0:5b88d5760320 155 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kenjiArai 0:5b88d5760320 156 */
kenjiArai 0:5b88d5760320 157 qspi_status_t read(int instruction, int alt, int address, char *rx_buffer, size_t *rx_length);
kenjiArai 0:5b88d5760320 158
kenjiArai 0:5b88d5760320 159 /** Write to QSPI peripheral using custom write instruction, alt values
kenjiArai 0:5b88d5760320 160 *
kenjiArai 0:5b88d5760320 161 * @param instruction Instruction value to be used in instruction phase
kenjiArai 0:5b88d5760320 162 * @param alt Alt value to be used in Alternate-byte phase. Use -1 for ignoring Alternate-byte phase
kenjiArai 0:5b88d5760320 163 * @param address Address to be accessed in QSPI peripheral
kenjiArai 0:5b88d5760320 164 * @param tx_buffer Buffer containing data to be sent to peripheral
kenjiArai 0:5b88d5760320 165 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
kenjiArai 0:5b88d5760320 166 *
kenjiArai 0:5b88d5760320 167 * @returns
kenjiArai 0:5b88d5760320 168 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kenjiArai 0:5b88d5760320 169 */
kenjiArai 0:5b88d5760320 170 qspi_status_t write(int instruction, int alt, int address, const char *tx_buffer, size_t *tx_length);
kenjiArai 0:5b88d5760320 171
kenjiArai 0:5b88d5760320 172 /** Perform a transaction to write to an address(a control register) and get the status results
kenjiArai 0:5b88d5760320 173 *
kenjiArai 0:5b88d5760320 174 * @param instruction Instruction value to be used in instruction phase
kenjiArai 0:5b88d5760320 175 * @param address Some instruction might require address. Use -1 if no address
kenjiArai 0:5b88d5760320 176 * @param tx_buffer Buffer containing data to be sent to peripheral
kenjiArai 0:5b88d5760320 177 * @param tx_length Pointer to a variable containing the length of data to be transmitted, and on return this variable will be updated with the actual number of bytes written
kenjiArai 0:5b88d5760320 178 * @param rx_buffer Buffer for data to be read from the peripheral
kenjiArai 0:5b88d5760320 179 * @param rx_length Pointer to a variable containing the length of rx_buffer, and on return this variable will be updated with the actual number of bytes read
kenjiArai 0:5b88d5760320 180 *
kenjiArai 0:5b88d5760320 181 * @returns
kenjiArai 0:5b88d5760320 182 * Returns QSPI_STATUS_SUCCESS on successful reads and QSPI_STATUS_ERROR on failed reads.
kenjiArai 0:5b88d5760320 183 */
kenjiArai 0:5b88d5760320 184 qspi_status_t command_transfer(int instruction, int address, const char *tx_buffer, size_t tx_length, const char *rx_buffer, size_t rx_length);
kenjiArai 0:5b88d5760320 185
kenjiArai 0:5b88d5760320 186 #if !defined(DOXYGEN_ONLY)
kenjiArai 0:5b88d5760320 187 protected:
kenjiArai 0:5b88d5760320 188 /** Acquire exclusive access to this SPI bus
kenjiArai 0:5b88d5760320 189 */
kenjiArai 0:5b88d5760320 190 virtual void lock(void);
kenjiArai 0:5b88d5760320 191
kenjiArai 0:5b88d5760320 192 /** Release exclusive access to this SPI bus
kenjiArai 0:5b88d5760320 193 */
kenjiArai 0:5b88d5760320 194 virtual void unlock(void);
kenjiArai 0:5b88d5760320 195
kenjiArai 0:5b88d5760320 196 qspi_t _qspi;
kenjiArai 0:5b88d5760320 197
kenjiArai 0:5b88d5760320 198 bool acquire(void);
kenjiArai 0:5b88d5760320 199 static QSPI *_owner;
kenjiArai 0:5b88d5760320 200 static SingletonPtr<PlatformMutex> _mutex;
kenjiArai 0:5b88d5760320 201 qspi_bus_width_t _inst_width; //Bus width for Instruction phase
kenjiArai 0:5b88d5760320 202 qspi_bus_width_t _address_width; //Bus width for Address phase
kenjiArai 0:5b88d5760320 203 qspi_address_size_t _address_size;
kenjiArai 0:5b88d5760320 204 qspi_bus_width_t _alt_width; //Bus width for Alt phase
kenjiArai 0:5b88d5760320 205 qspi_alt_size_t _alt_size;
kenjiArai 0:5b88d5760320 206 qspi_bus_width_t _data_width; //Bus width for Data phase
kenjiArai 0:5b88d5760320 207 qspi_command_t _qspi_command; //QSPI Hal command struct
kenjiArai 0:5b88d5760320 208 unsigned int _num_dummy_cycles; //Number of dummy cycles to be used
kenjiArai 0:5b88d5760320 209 int _hz; //Bus Frequency
kenjiArai 0:5b88d5760320 210 int _mode; //SPI mode
kenjiArai 0:5b88d5760320 211 bool _initialized;
kenjiArai 0:5b88d5760320 212 PinName _qspi_io0, _qspi_io1, _qspi_io2, _qspi_io3, _qspi_clk, _qspi_cs; //IO lines, clock and chip select
kenjiArai 0:5b88d5760320 213
kenjiArai 0:5b88d5760320 214 private:
kenjiArai 0:5b88d5760320 215 /* Private acquire function without locking/unlocking
kenjiArai 0:5b88d5760320 216 * Implemented in order to avoid duplicate locking and boost performance
kenjiArai 0:5b88d5760320 217 */
kenjiArai 0:5b88d5760320 218 bool _acquire(void);
kenjiArai 0:5b88d5760320 219 bool _initialize();
kenjiArai 0:5b88d5760320 220
kenjiArai 0:5b88d5760320 221 /*
kenjiArai 0:5b88d5760320 222 * This function builds the qspi command struct to be send to Hal
kenjiArai 0:5b88d5760320 223 */
kenjiArai 0:5b88d5760320 224 inline void _build_qspi_command(int instruction, int address, int alt);
kenjiArai 0:5b88d5760320 225 #endif
kenjiArai 0:5b88d5760320 226 };
kenjiArai 0:5b88d5760320 227
kenjiArai 0:5b88d5760320 228 } // namespace mbed
kenjiArai 0:5b88d5760320 229
kenjiArai 0:5b88d5760320 230 #endif
kenjiArai 0:5b88d5760320 231
kenjiArai 0:5b88d5760320 232 #endif