This is a RTC additional function. This is only for Nucleo F401RE & F411RE mbed(Added L152RE, F334R8, L476RG & F746xx). If you connected battery backup circuit for internal RTC, you can make a power-off and reset condition. RTC still has proper time and date.
Dependents: Nucleo_rtos_sample PB_Emma_Ethernet
Please refer following NOTE information.
/users/kenjiArai/notebook/nucleo-series-rtc-control-under-power-onoff-and-re/
Diff: SetRTC.cpp
- Revision:
- 14:78e453d7bb85
- Parent:
- 13:44e5327acb05
--- a/SetRTC.cpp Fri May 27 20:16:09 2016 +0000 +++ b/SetRTC.cpp Sat Jul 02 03:00:33 2016 +0000 @@ -7,7 +7,7 @@ * http://www.page.sannet.ne.jp/kenjia/index.html * http://mbed.org/users/kenjiArai/ * Created: October 24th, 2014 - * Revised: May 28th, 2016 + * Revised: July 2nd, 2016 * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE @@ -18,13 +18,17 @@ #if (defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) \ || defined(TARGET_STM32L152RE) || defined(TARGET_STM32F334R8) \ - || defined(TARGET_STM32L476RG) ) + || defined(TARGET_STM32L476RG) \ + || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) ) //#define DEBUG // use Communication with PC(UART) // Include --------------------------------------------------------------------------------------- #include "mbed.h" #include "SetRTC.h" +#if (defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) ) +#include "stm32f7xx_hal.h" +#endif // Definition ------------------------------------------------------------------------------------ #ifdef DEBUG @@ -79,7 +83,7 @@ // Enable Power Clock __PWR_CLK_ENABLE(); // Enable write access to Backup domain -#if defined(TARGET_STM32L476RG) +#if (defined(TARGET_STM32L476RG) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG)) PWR->CR1 |= PWR_CR1_DBP; #else PWR->CR |= PWR_CR_DBP; @@ -87,7 +91,7 @@ // Wait for Backup domain Write protection disable timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE; PRINTF("Time-Out %d\r\n", timeout); -#if defined(TARGET_STM32L476RG) +#if (defined(TARGET_STM32L476RG) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG)) while((PWR->CR1 & PWR_CR1_DBP) == RESET) { #else while((PWR->CR & PWR_CR_DBP) == RESET) { @@ -120,7 +124,8 @@ PRINTF("Time-Out %d\r\n", timeout); // Wait till LSE is ready #if (defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) \ - || defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) ) + || defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) \ + || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) ) while((RCC->BDCR & 0x02) != 2){ #elif defined(TARGET_STM32L152RE) while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { @@ -150,14 +155,14 @@ // Enable Power Clock __PWR_CLK_ENABLE(); // Enable write access to Backup domain -#if defined(TARGET_STM32L476RG) +#if (defined(TARGET_STM32L476RG) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG)) PWR->CR1 |= PWR_CR1_DBP; #else PWR->CR |= PWR_CR_DBP; #endif // Wait for Backup domain Write protection disable timeout = HAL_GetTick() + DBP_TIMEOUT_VALUE; -#if defined(TARGET_STM32L476RG) +#if (defined(TARGET_STM32L476RG) || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG)) while((PWR->CR1 & PWR_CR1_DBP) == RESET) { #else while((PWR->CR & PWR_CR_DBP) == RESET) { @@ -177,7 +182,8 @@ } } // Connect LSI to RTC -#if !(defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG)) +#if !(defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) \ + || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) ) __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI); #endif __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI); @@ -197,7 +203,8 @@ // Check backup condition if ( check_RTC_backup_reg() ) { #if (defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) \ - || defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) ) + || defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) \ + || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) ) if ((RCC->BDCR & 0x8307) == 0x8103){ #else if ((RCC->CSR & 0x430703) == 0x410300) { @@ -225,7 +232,9 @@ // Enable LSE Oscillator if (set_RTC_LSE() == 1) { // Connect LSE to RTC -#if !(defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG)) +#if !(defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) \ + || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) \ + || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) ) __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE); #endif __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE); @@ -291,7 +300,8 @@ ); pcr.printf( "Show RCC registers (only RTC Related reg.)\r\n" ); #if (defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) \ - || defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) ) + || defined(TARGET_STM32F334R8) || defined(TARGET_STM32L476RG) \ + || defined(TARGET_STM32F746NG) || defined(TARGET_STM32F746ZG) ) pcr.printf( " RCC_BDCR=0x...%05x\r\n", RCC->BDCR); #else pcr.printf( " RCC_CSR =0x%08x\r\n", RCC->CSR); @@ -568,7 +578,7 @@ ; // No implementation } #endif // defined(TARGET_STM32L152RE) +#else // defined(TARGET_STM32F401RE,_F411RE,_L152RE,_F334R8,_L476RG, _F746xx) +#error "No suport this mbed, only for Nucleo mbed" +#endif // defined(TARGET_STM32F401RE,_F411RE,_L152RE,_F334R8,_L476RG, _F746xx) -#else // defined(TARGET_STM32F401RE,_F411RE,_L152RE,_F334R8,_L476RG) -#error "No suport this mbed, only for Nucleo mbed" -#endif // defined(TARGET_STM32F401RE,_F411RE,_L152RE,_F334R8,_L476RG)