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TARGET_NRF51_DK/nrf51.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
97:433970e64889
Child:
123:b0220dba8be7
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /*
Kojto 122:f9eeca106725 2 * Copyright (c) Nordic Semiconductor ASA
Kojto 122:f9eeca106725 3 * All rights reserved.
Kojto 97:433970e64889 4 *
Kojto 122:f9eeca106725 5 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 6 * are permitted provided that the following conditions are met:
Kojto 97:433970e64889 7 *
Kojto 122:f9eeca106725 8 * 1. Redistributions of source code must retain the above copyright notice, this
Kojto 122:f9eeca106725 9 * list of conditions and the following disclaimer.
Kojto 91:031413cf7a89 10 *
Kojto 122:f9eeca106725 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
Kojto 122:f9eeca106725 12 * list of conditions and the following disclaimer in the documentation and/or
Kojto 122:f9eeca106725 13 * other materials provided with the distribution.
Kojto 122:f9eeca106725 14 *
Kojto 122:f9eeca106725 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
Kojto 122:f9eeca106725 16 * contributors to this software may be used to endorse or promote products
Kojto 122:f9eeca106725 17 * derived from this software without specific prior written permission.
Kojto 97:433970e64889 18 *
Kojto 97:433970e64889 19 *
Kojto 122:f9eeca106725 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 122:f9eeca106725 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 122:f9eeca106725 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 122:f9eeca106725 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 122:f9eeca106725 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 122:f9eeca106725 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 122:f9eeca106725 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 122:f9eeca106725 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 122:f9eeca106725 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 30 *
Kojto 122:f9eeca106725 31 */
Kojto 91:031413cf7a89 32
Kojto 91:031413cf7a89 33 #ifndef NRF51_H
Kojto 91:031413cf7a89 34 #define NRF51_H
Kojto 91:031413cf7a89 35
Kojto 91:031413cf7a89 36 #ifdef __cplusplus
Kojto 91:031413cf7a89 37 extern "C" {
Kojto 91:031413cf7a89 38 #endif
Kojto 91:031413cf7a89 39
Kojto 91:031413cf7a89 40
Kojto 91:031413cf7a89 41 /* ------------------------- Interrupt Number Definition ------------------------ */
Kojto 91:031413cf7a89 42
Kojto 91:031413cf7a89 43 typedef enum {
Kojto 91:031413cf7a89 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Kojto 91:031413cf7a89 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
Kojto 91:031413cf7a89 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
Kojto 91:031413cf7a89 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
Kojto 91:031413cf7a89 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
Kojto 91:031413cf7a89 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
Kojto 91:031413cf7a89 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
Kojto 91:031413cf7a89 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Kojto 122:f9eeca106725 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
Kojto 91:031413cf7a89 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
Kojto 91:031413cf7a89 54 RADIO_IRQn = 1, /*!< 1 RADIO */
Kojto 91:031413cf7a89 55 UART0_IRQn = 2, /*!< 2 UART0 */
Kojto 91:031413cf7a89 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
Kojto 91:031413cf7a89 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
Kojto 91:031413cf7a89 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
Kojto 91:031413cf7a89 59 ADC_IRQn = 7, /*!< 7 ADC */
Kojto 91:031413cf7a89 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
Kojto 91:031413cf7a89 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
Kojto 91:031413cf7a89 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
Kojto 91:031413cf7a89 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
Kojto 91:031413cf7a89 64 TEMP_IRQn = 12, /*!< 12 TEMP */
Kojto 91:031413cf7a89 65 RNG_IRQn = 13, /*!< 13 RNG */
Kojto 91:031413cf7a89 66 ECB_IRQn = 14, /*!< 14 ECB */
Kojto 91:031413cf7a89 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
Kojto 91:031413cf7a89 68 WDT_IRQn = 16, /*!< 16 WDT */
Kojto 91:031413cf7a89 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
Kojto 91:031413cf7a89 70 QDEC_IRQn = 18, /*!< 18 QDEC */
Kojto 97:433970e64889 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
Kojto 91:031413cf7a89 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
Kojto 91:031413cf7a89 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
Kojto 91:031413cf7a89 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
Kojto 91:031413cf7a89 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
Kojto 91:031413cf7a89 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
Kojto 91:031413cf7a89 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
Kojto 91:031413cf7a89 78 } IRQn_Type;
Kojto 91:031413cf7a89 79
Kojto 91:031413cf7a89 80
Kojto 91:031413cf7a89 81 /** @addtogroup Configuration_of_CMSIS
Kojto 91:031413cf7a89 82 * @{
Kojto 91:031413cf7a89 83 */
Kojto 91:031413cf7a89 84
Kojto 91:031413cf7a89 85
Kojto 91:031413cf7a89 86 /* ================================================================================ */
Kojto 91:031413cf7a89 87 /* ================ Processor and Core Peripheral Section ================ */
Kojto 91:031413cf7a89 88 /* ================================================================================ */
Kojto 91:031413cf7a89 89
Kojto 97:433970e64889 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
Kojto 91:031413cf7a89 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
Kojto 91:031413cf7a89 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
Kojto 91:031413cf7a89 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
Kojto 91:031413cf7a89 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 91:031413cf7a89 95 /** @} */ /* End of group Configuration_of_CMSIS */
Kojto 91:031413cf7a89 96
Kojto 97:433970e64889 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
Kojto 122:f9eeca106725 98 #include "system_nrf51.h" /*!< nrf51 System */
Kojto 122:f9eeca106725 99
Kojto 91:031413cf7a89 100
Kojto 91:031413cf7a89 101 /* ================================================================================ */
Kojto 91:031413cf7a89 102 /* ================ Device Specific Peripheral Section ================ */
Kojto 91:031413cf7a89 103 /* ================================================================================ */
Kojto 91:031413cf7a89 104
Kojto 91:031413cf7a89 105
Kojto 91:031413cf7a89 106 /** @addtogroup Device_Peripheral_Registers
Kojto 91:031413cf7a89 107 * @{
Kojto 91:031413cf7a89 108 */
Kojto 91:031413cf7a89 109
Kojto 91:031413cf7a89 110
Kojto 91:031413cf7a89 111 /* ------------------- Start of section using anonymous unions ------------------ */
Kojto 91:031413cf7a89 112 #if defined(__CC_ARM)
Kojto 91:031413cf7a89 113 #pragma push
Kojto 91:031413cf7a89 114 #pragma anon_unions
Kojto 91:031413cf7a89 115 #elif defined(__ICCARM__)
Kojto 91:031413cf7a89 116 #pragma language=extended
Kojto 91:031413cf7a89 117 #elif defined(__GNUC__)
Kojto 91:031413cf7a89 118 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 119 #elif defined(__TMS470__)
Kojto 91:031413cf7a89 120 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 121 #elif defined(__TASKING__)
Kojto 91:031413cf7a89 122 #pragma warning 586
Kojto 91:031413cf7a89 123 #else
Kojto 91:031413cf7a89 124 #warning Not supported compiler type
Kojto 91:031413cf7a89 125 #endif
Kojto 91:031413cf7a89 126
Kojto 91:031413cf7a89 127
Kojto 91:031413cf7a89 128 typedef struct {
Kojto 91:031413cf7a89 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
Kojto 91:031413cf7a89 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
Kojto 91:031413cf7a89 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
Kojto 91:031413cf7a89 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
Kojto 91:031413cf7a89 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
Kojto 91:031413cf7a89 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
Kojto 91:031413cf7a89 135 } AMLI_RAMPRI_Type;
Kojto 91:031413cf7a89 136
Kojto 91:031413cf7a89 137 typedef struct {
Kojto 97:433970e64889 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
Kojto 97:433970e64889 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
Kojto 97:433970e64889 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
Kojto 97:433970e64889 141 } SPIM_PSEL_Type;
Kojto 97:433970e64889 142
Kojto 97:433970e64889 143 typedef struct {
Kojto 97:433970e64889 144 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
Kojto 97:433970e64889 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
Kojto 97:433970e64889 147 } SPIM_RXD_Type;
Kojto 97:433970e64889 148
Kojto 97:433970e64889 149 typedef struct {
Kojto 97:433970e64889 150 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
Kojto 97:433970e64889 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
Kojto 97:433970e64889 153 } SPIM_TXD_Type;
Kojto 97:433970e64889 154
Kojto 97:433970e64889 155 typedef struct {
Kojto 91:031413cf7a89 156 __O uint32_t EN; /*!< Enable channel group. */
Kojto 91:031413cf7a89 157 __O uint32_t DIS; /*!< Disable channel group. */
Kojto 91:031413cf7a89 158 } PPI_TASKS_CHG_Type;
Kojto 91:031413cf7a89 159
Kojto 91:031413cf7a89 160 typedef struct {
Kojto 91:031413cf7a89 161 __IO uint32_t EEP; /*!< Channel event end-point. */
Kojto 91:031413cf7a89 162 __IO uint32_t TEP; /*!< Channel task end-point. */
Kojto 91:031413cf7a89 163 } PPI_CH_Type;
Kojto 91:031413cf7a89 164
Kojto 91:031413cf7a89 165
Kojto 91:031413cf7a89 166 /* ================================================================================ */
Kojto 91:031413cf7a89 167 /* ================ POWER ================ */
Kojto 91:031413cf7a89 168 /* ================================================================================ */
Kojto 91:031413cf7a89 169
Kojto 91:031413cf7a89 170
Kojto 91:031413cf7a89 171 /**
Kojto 91:031413cf7a89 172 * @brief Power Control. (POWER)
Kojto 91:031413cf7a89 173 */
Kojto 91:031413cf7a89 174
Kojto 91:031413cf7a89 175 typedef struct { /*!< POWER Structure */
Kojto 91:031413cf7a89 176 __I uint32_t RESERVED0[30];
Kojto 91:031413cf7a89 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
Kojto 91:031413cf7a89 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
Kojto 91:031413cf7a89 179 __I uint32_t RESERVED1[34];
Kojto 91:031413cf7a89 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
Kojto 91:031413cf7a89 181 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 184 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
Kojto 97:433970e64889 186 __I uint32_t RESERVED4[9];
Kojto 97:433970e64889 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
Kojto 97:433970e64889 188 __I uint32_t RESERVED5[53];
Kojto 91:031413cf7a89 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
Kojto 97:433970e64889 190 __I uint32_t RESERVED6[3];
Kojto 91:031413cf7a89 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
Kojto 97:433970e64889 192 __I uint32_t RESERVED7[2];
Kojto 91:031413cf7a89 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
Kojto 91:031413cf7a89 194 register. */
Kojto 97:433970e64889 195 __I uint32_t RESERVED8;
Kojto 91:031413cf7a89 196 __IO uint32_t RAMON; /*!< Ram on/off. */
Kojto 97:433970e64889 197 __I uint32_t RESERVED9[7];
Kojto 91:031413cf7a89 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
Kojto 91:031413cf7a89 199 is a retained register. */
Kojto 97:433970e64889 200 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
Kojto 97:433970e64889 202 __I uint32_t RESERVED11[8];
Kojto 91:031413cf7a89 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Kojto 97:433970e64889 204 __I uint32_t RESERVED12[291];
Kojto 97:433970e64889 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
Kojto 91:031413cf7a89 206 } NRF_POWER_Type;
Kojto 91:031413cf7a89 207
Kojto 91:031413cf7a89 208
Kojto 91:031413cf7a89 209 /* ================================================================================ */
Kojto 91:031413cf7a89 210 /* ================ CLOCK ================ */
Kojto 91:031413cf7a89 211 /* ================================================================================ */
Kojto 91:031413cf7a89 212
Kojto 91:031413cf7a89 213
Kojto 91:031413cf7a89 214 /**
Kojto 91:031413cf7a89 215 * @brief Clock control. (CLOCK)
Kojto 91:031413cf7a89 216 */
Kojto 91:031413cf7a89 217
Kojto 91:031413cf7a89 218 typedef struct { /*!< CLOCK Structure */
Kojto 91:031413cf7a89 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
Kojto 91:031413cf7a89 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
Kojto 91:031413cf7a89 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
Kojto 91:031413cf7a89 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
Kojto 91:031413cf7a89 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
Kojto 91:031413cf7a89 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
Kojto 91:031413cf7a89 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
Kojto 91:031413cf7a89 226 __I uint32_t RESERVED0[57];
Kojto 91:031413cf7a89 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
Kojto 91:031413cf7a89 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
Kojto 91:031413cf7a89 229 __I uint32_t RESERVED1;
Kojto 97:433970e64889 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
Kojto 97:433970e64889 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
Kojto 91:031413cf7a89 232 __I uint32_t RESERVED2[124];
Kojto 91:031413cf7a89 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 235 __I uint32_t RESERVED3[63];
Kojto 97:433970e64889 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
Kojto 91:031413cf7a89 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Kojto 97:433970e64889 238 __I uint32_t RESERVED4;
Kojto 97:433970e64889 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
Kojto 91:031413cf7a89 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Kojto 97:433970e64889 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto 97:433970e64889 242 triggered. */
Kojto 97:433970e64889 243 __I uint32_t RESERVED5[62];
Kojto 91:031413cf7a89 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
Kojto 91:031413cf7a89 245 __I uint32_t RESERVED6[7];
Kojto 91:031413cf7a89 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
Kojto 91:031413cf7a89 247 __I uint32_t RESERVED7[5];
Kojto 91:031413cf7a89 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
Kojto 91:031413cf7a89 249 } NRF_CLOCK_Type;
Kojto 91:031413cf7a89 250
Kojto 91:031413cf7a89 251
Kojto 91:031413cf7a89 252 /* ================================================================================ */
Kojto 91:031413cf7a89 253 /* ================ MPU ================ */
Kojto 91:031413cf7a89 254 /* ================================================================================ */
Kojto 91:031413cf7a89 255
Kojto 91:031413cf7a89 256
Kojto 91:031413cf7a89 257 /**
Kojto 91:031413cf7a89 258 * @brief Memory Protection Unit. (MPU)
Kojto 91:031413cf7a89 259 */
Kojto 91:031413cf7a89 260
Kojto 91:031413cf7a89 261 typedef struct { /*!< MPU Structure */
Kojto 91:031413cf7a89 262 __I uint32_t RESERVED0[330];
Kojto 91:031413cf7a89 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
Kojto 91:031413cf7a89 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
Kojto 91:031413cf7a89 265 __I uint32_t RESERVED1[52];
Kojto 97:433970e64889 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
Kojto 97:433970e64889 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
Kojto 91:031413cf7a89 270 } NRF_MPU_Type;
Kojto 91:031413cf7a89 271
Kojto 91:031413cf7a89 272
Kojto 91:031413cf7a89 273 /* ================================================================================ */
Kojto 91:031413cf7a89 274 /* ================ AMLI ================ */
Kojto 91:031413cf7a89 275 /* ================================================================================ */
Kojto 91:031413cf7a89 276
Kojto 91:031413cf7a89 277
Kojto 91:031413cf7a89 278 /**
Kojto 91:031413cf7a89 279 * @brief AHB Multi-Layer Interface. (AMLI)
Kojto 91:031413cf7a89 280 */
Kojto 91:031413cf7a89 281
Kojto 91:031413cf7a89 282 typedef struct { /*!< AMLI Structure */
Kojto 91:031413cf7a89 283 __I uint32_t RESERVED0[896];
Kojto 91:031413cf7a89 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
Kojto 91:031413cf7a89 285 } NRF_AMLI_Type;
Kojto 91:031413cf7a89 286
Kojto 91:031413cf7a89 287
Kojto 91:031413cf7a89 288 /* ================================================================================ */
Kojto 91:031413cf7a89 289 /* ================ RADIO ================ */
Kojto 91:031413cf7a89 290 /* ================================================================================ */
Kojto 91:031413cf7a89 291
Kojto 91:031413cf7a89 292
Kojto 91:031413cf7a89 293 /**
Kojto 91:031413cf7a89 294 * @brief The radio. (RADIO)
Kojto 91:031413cf7a89 295 */
Kojto 91:031413cf7a89 296
Kojto 91:031413cf7a89 297 typedef struct { /*!< RADIO Structure */
Kojto 91:031413cf7a89 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
Kojto 91:031413cf7a89 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
Kojto 91:031413cf7a89 300 __O uint32_t TASKS_START; /*!< Start radio. */
Kojto 91:031413cf7a89 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
Kojto 91:031413cf7a89 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
Kojto 91:031413cf7a89 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
Kojto 91:031413cf7a89 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
Kojto 91:031413cf7a89 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
Kojto 91:031413cf7a89 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
Kojto 91:031413cf7a89 307 __I uint32_t RESERVED0[55];
Kojto 91:031413cf7a89 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
Kojto 91:031413cf7a89 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
Kojto 91:031413cf7a89 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
Kojto 91:031413cf7a89 311 __IO uint32_t EVENTS_END; /*!< End event. */
Kojto 91:031413cf7a89 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
Kojto 91:031413cf7a89 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
Kojto 91:031413cf7a89 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
Kojto 91:031413cf7a89 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
Kojto 91:031413cf7a89 316 sample is ready for readout at the RSSISAMPLE register. */
Kojto 91:031413cf7a89 317 __I uint32_t RESERVED1[2];
Kojto 122:f9eeca106725 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
Kojto 91:031413cf7a89 319 __I uint32_t RESERVED2[53];
Kojto 97:433970e64889 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
Kojto 91:031413cf7a89 321 __I uint32_t RESERVED3[64];
Kojto 91:031413cf7a89 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 324 __I uint32_t RESERVED4[61];
Kojto 91:031413cf7a89 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Kojto 122:f9eeca106725 326 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 327 __I uint32_t RXMATCH; /*!< Received address. */
Kojto 91:031413cf7a89 328 __I uint32_t RXCRC; /*!< Received CRC. */
Kojto 97:433970e64889 329 __I uint32_t DAI; /*!< Device address match index. */
Kojto 122:f9eeca106725 330 __I uint32_t RESERVED6[60];
Kojto 91:031413cf7a89 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
Kojto 91:031413cf7a89 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
Kojto 91:031413cf7a89 333 __IO uint32_t TXPOWER; /*!< Output power. */
Kojto 91:031413cf7a89 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
Kojto 91:031413cf7a89 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
Kojto 91:031413cf7a89 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
Kojto 91:031413cf7a89 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
Kojto 91:031413cf7a89 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
Kojto 91:031413cf7a89 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
Kojto 91:031413cf7a89 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
Kojto 91:031413cf7a89 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
Kojto 91:031413cf7a89 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
Kojto 91:031413cf7a89 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
Kojto 91:031413cf7a89 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
Kojto 91:031413cf7a89 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
Kojto 91:031413cf7a89 346 __IO uint32_t TEST; /*!< Test features enable register. */
Kojto 91:031413cf7a89 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Kojto 97:433970e64889 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
Kojto 122:f9eeca106725 349 __I uint32_t RESERVED7;
Kojto 91:031413cf7a89 350 __I uint32_t STATE; /*!< Current radio state. */
Kojto 91:031413cf7a89 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Kojto 122:f9eeca106725 352 __I uint32_t RESERVED8[2];
Kojto 91:031413cf7a89 353 __IO uint32_t BCC; /*!< Bit counter compare. */
Kojto 122:f9eeca106725 354 __I uint32_t RESERVED9[39];
Kojto 91:031413cf7a89 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
Kojto 91:031413cf7a89 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
Kojto 91:031413cf7a89 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
Kojto 122:f9eeca106725 358 __I uint32_t RESERVED10[56];
Kojto 91:031413cf7a89 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
Kojto 91:031413cf7a89 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
Kojto 91:031413cf7a89 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
Kojto 91:031413cf7a89 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
Kojto 91:031413cf7a89 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Kojto 122:f9eeca106725 364 __I uint32_t RESERVED11[561];
Kojto 91:031413cf7a89 365 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 366 } NRF_RADIO_Type;
Kojto 91:031413cf7a89 367
Kojto 91:031413cf7a89 368
Kojto 91:031413cf7a89 369 /* ================================================================================ */
Kojto 91:031413cf7a89 370 /* ================ UART ================ */
Kojto 91:031413cf7a89 371 /* ================================================================================ */
Kojto 91:031413cf7a89 372
Kojto 91:031413cf7a89 373
Kojto 91:031413cf7a89 374 /**
Kojto 91:031413cf7a89 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
Kojto 91:031413cf7a89 376 */
Kojto 91:031413cf7a89 377
Kojto 91:031413cf7a89 378 typedef struct { /*!< UART Structure */
Kojto 91:031413cf7a89 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
Kojto 91:031413cf7a89 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
Kojto 91:031413cf7a89 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
Kojto 91:031413cf7a89 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
Kojto 91:031413cf7a89 383 __I uint32_t RESERVED0[3];
Kojto 91:031413cf7a89 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
Kojto 91:031413cf7a89 385 __I uint32_t RESERVED1[56];
Kojto 91:031413cf7a89 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
Kojto 91:031413cf7a89 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
Kojto 91:031413cf7a89 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
Kojto 91:031413cf7a89 389 __I uint32_t RESERVED2[4];
Kojto 91:031413cf7a89 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
Kojto 91:031413cf7a89 391 __I uint32_t RESERVED3;
Kojto 91:031413cf7a89 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
Kojto 91:031413cf7a89 393 __I uint32_t RESERVED4[7];
Kojto 91:031413cf7a89 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
Kojto 91:031413cf7a89 395 __I uint32_t RESERVED5[46];
Kojto 97:433970e64889 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
Kojto 97:433970e64889 397 __I uint32_t RESERVED6[64];
Kojto 91:031413cf7a89 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 400 __I uint32_t RESERVED7[93];
Kojto 91:031413cf7a89 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
Kojto 91:031413cf7a89 402 __I uint32_t RESERVED8[31];
Kojto 91:031413cf7a89 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
Kojto 91:031413cf7a89 404 __I uint32_t RESERVED9;
Kojto 91:031413cf7a89 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
Kojto 91:031413cf7a89 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
Kojto 91:031413cf7a89 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
Kojto 91:031413cf7a89 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
Kojto 91:031413cf7a89 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto 97:433970e64889 410 Once read the character is consumed. If read when no character
Kojto 91:031413cf7a89 411 available, the UART will stop working. */
Kojto 91:031413cf7a89 412 __O uint32_t TXD; /*!< TXD register. */
Kojto 91:031413cf7a89 413 __I uint32_t RESERVED10;
Kojto 91:031413cf7a89 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
Kojto 91:031413cf7a89 415 __I uint32_t RESERVED11[17];
Kojto 91:031413cf7a89 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
Kojto 91:031413cf7a89 417 __I uint32_t RESERVED12[675];
Kojto 91:031413cf7a89 418 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 419 } NRF_UART_Type;
Kojto 91:031413cf7a89 420
Kojto 91:031413cf7a89 421
Kojto 91:031413cf7a89 422 /* ================================================================================ */
Kojto 91:031413cf7a89 423 /* ================ SPI ================ */
Kojto 91:031413cf7a89 424 /* ================================================================================ */
Kojto 91:031413cf7a89 425
Kojto 91:031413cf7a89 426
Kojto 91:031413cf7a89 427 /**
Kojto 91:031413cf7a89 428 * @brief SPI master 0. (SPI)
Kojto 91:031413cf7a89 429 */
Kojto 91:031413cf7a89 430
Kojto 91:031413cf7a89 431 typedef struct { /*!< SPI Structure */
Kojto 91:031413cf7a89 432 __I uint32_t RESERVED0[66];
Kojto 91:031413cf7a89 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
Kojto 91:031413cf7a89 434 __I uint32_t RESERVED1[126];
Kojto 91:031413cf7a89 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 437 __I uint32_t RESERVED2[125];
Kojto 91:031413cf7a89 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
Kojto 91:031413cf7a89 439 __I uint32_t RESERVED3;
Kojto 91:031413cf7a89 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Kojto 91:031413cf7a89 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Kojto 91:031413cf7a89 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Kojto 91:031413cf7a89 443 __I uint32_t RESERVED4;
Kojto 97:433970e64889 444 __I uint32_t RXD; /*!< RX data. */
Kojto 91:031413cf7a89 445 __IO uint32_t TXD; /*!< TX data. */
Kojto 91:031413cf7a89 446 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
Kojto 91:031413cf7a89 448 __I uint32_t RESERVED6[11];
Kojto 91:031413cf7a89 449 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 450 __I uint32_t RESERVED7[681];
Kojto 91:031413cf7a89 451 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 452 } NRF_SPI_Type;
Kojto 91:031413cf7a89 453
Kojto 91:031413cf7a89 454
Kojto 91:031413cf7a89 455 /* ================================================================================ */
Kojto 91:031413cf7a89 456 /* ================ TWI ================ */
Kojto 91:031413cf7a89 457 /* ================================================================================ */
Kojto 91:031413cf7a89 458
Kojto 91:031413cf7a89 459
Kojto 91:031413cf7a89 460 /**
Kojto 91:031413cf7a89 461 * @brief Two-wire interface master 0. (TWI)
Kojto 91:031413cf7a89 462 */
Kojto 91:031413cf7a89 463
Kojto 91:031413cf7a89 464 typedef struct { /*!< TWI Structure */
Kojto 91:031413cf7a89 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
Kojto 91:031413cf7a89 466 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
Kojto 91:031413cf7a89 468 __I uint32_t RESERVED1[2];
Kojto 91:031413cf7a89 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
Kojto 91:031413cf7a89 470 __I uint32_t RESERVED2;
Kojto 91:031413cf7a89 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
Kojto 91:031413cf7a89 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
Kojto 91:031413cf7a89 473 __I uint32_t RESERVED3[56];
Kojto 91:031413cf7a89 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
Kojto 91:031413cf7a89 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
Kojto 91:031413cf7a89 476 __I uint32_t RESERVED4[4];
Kojto 91:031413cf7a89 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
Kojto 91:031413cf7a89 478 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
Kojto 91:031413cf7a89 480 __I uint32_t RESERVED6[4];
Kojto 91:031413cf7a89 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Kojto 97:433970e64889 482 __I uint32_t RESERVED7[3];
Kojto 97:433970e64889 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
Kojto 97:433970e64889 484 __I uint32_t RESERVED8[45];
Kojto 91:031413cf7a89 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Kojto 97:433970e64889 486 __I uint32_t RESERVED9[64];
Kojto 91:031413cf7a89 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 489 __I uint32_t RESERVED10[110];
Kojto 91:031413cf7a89 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Kojto 97:433970e64889 491 __I uint32_t RESERVED11[14];
Kojto 91:031413cf7a89 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Kojto 97:433970e64889 493 __I uint32_t RESERVED12;
Kojto 91:031413cf7a89 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
Kojto 91:031413cf7a89 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Kojto 97:433970e64889 496 __I uint32_t RESERVED13[2];
Kojto 97:433970e64889 497 __I uint32_t RXD; /*!< RX data register. */
Kojto 91:031413cf7a89 498 __IO uint32_t TXD; /*!< TX data register. */
Kojto 97:433970e64889 499 __I uint32_t RESERVED14;
Kojto 91:031413cf7a89 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Kojto 97:433970e64889 501 __I uint32_t RESERVED15[24];
Kojto 91:031413cf7a89 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Kojto 97:433970e64889 503 __I uint32_t RESERVED16[668];
Kojto 91:031413cf7a89 504 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 505 } NRF_TWI_Type;
Kojto 91:031413cf7a89 506
Kojto 91:031413cf7a89 507
Kojto 91:031413cf7a89 508 /* ================================================================================ */
Kojto 91:031413cf7a89 509 /* ================ SPIS ================ */
Kojto 91:031413cf7a89 510 /* ================================================================================ */
Kojto 91:031413cf7a89 511
Kojto 91:031413cf7a89 512
Kojto 91:031413cf7a89 513 /**
Kojto 91:031413cf7a89 514 * @brief SPI slave 1. (SPIS)
Kojto 91:031413cf7a89 515 */
Kojto 91:031413cf7a89 516
Kojto 91:031413cf7a89 517 typedef struct { /*!< SPIS Structure */
Kojto 91:031413cf7a89 518 __I uint32_t RESERVED0[9];
Kojto 91:031413cf7a89 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
Kojto 91:031413cf7a89 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
Kojto 91:031413cf7a89 521 __I uint32_t RESERVED1[54];
Kojto 91:031413cf7a89 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
Kojto 122:f9eeca106725 523 __I uint32_t RESERVED2[2];
Kojto 122:f9eeca106725 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
Kojto 122:f9eeca106725 525 __I uint32_t RESERVED3[5];
Kojto 91:031413cf7a89 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
Kojto 122:f9eeca106725 527 __I uint32_t RESERVED4[53];
Kojto 91:031413cf7a89 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
Kojto 122:f9eeca106725 529 __I uint32_t RESERVED5[64];
Kojto 91:031413cf7a89 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 532 __I uint32_t RESERVED6[61];
Kojto 91:031413cf7a89 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
Kojto 122:f9eeca106725 534 __I uint32_t RESERVED7[15];
Kojto 91:031413cf7a89 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
Kojto 122:f9eeca106725 536 __I uint32_t RESERVED8[47];
Kojto 91:031413cf7a89 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
Kojto 122:f9eeca106725 538 __I uint32_t RESERVED9;
Kojto 91:031413cf7a89 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Kojto 91:031413cf7a89 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Kojto 91:031413cf7a89 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Kojto 91:031413cf7a89 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
Kojto 122:f9eeca106725 543 __I uint32_t RESERVED10[7];
Kojto 91:031413cf7a89 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
Kojto 91:031413cf7a89 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Kojto 97:433970e64889 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
Kojto 122:f9eeca106725 547 __I uint32_t RESERVED11;
Kojto 91:031413cf7a89 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
Kojto 91:031413cf7a89 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Kojto 97:433970e64889 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
Kojto 122:f9eeca106725 551 __I uint32_t RESERVED12;
Kojto 91:031413cf7a89 552 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 553 __I uint32_t RESERVED13;
Kojto 91:031413cf7a89 554 __IO uint32_t DEF; /*!< Default character. */
Kojto 122:f9eeca106725 555 __I uint32_t RESERVED14[24];
Kojto 91:031413cf7a89 556 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 557 __I uint32_t RESERVED15[654];
Kojto 91:031413cf7a89 558 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 559 } NRF_SPIS_Type;
Kojto 91:031413cf7a89 560
Kojto 91:031413cf7a89 561
Kojto 91:031413cf7a89 562 /* ================================================================================ */
Kojto 97:433970e64889 563 /* ================ SPIM ================ */
Kojto 97:433970e64889 564 /* ================================================================================ */
Kojto 97:433970e64889 565
Kojto 97:433970e64889 566
Kojto 97:433970e64889 567 /**
Kojto 97:433970e64889 568 * @brief SPI master with easyDMA 1. (SPIM)
Kojto 97:433970e64889 569 */
Kojto 97:433970e64889 570
Kojto 97:433970e64889 571 typedef struct { /*!< SPIM Structure */
Kojto 97:433970e64889 572 __I uint32_t RESERVED0[4];
Kojto 97:433970e64889 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
Kojto 97:433970e64889 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
Kojto 97:433970e64889 575 __I uint32_t RESERVED1;
Kojto 97:433970e64889 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
Kojto 97:433970e64889 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
Kojto 97:433970e64889 578 __I uint32_t RESERVED2[56];
Kojto 97:433970e64889 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
Kojto 97:433970e64889 580 __I uint32_t RESERVED3[2];
Kojto 97:433970e64889 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
Kojto 122:f9eeca106725 582 __I uint32_t RESERVED4[3];
Kojto 97:433970e64889 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
Kojto 122:f9eeca106725 584 __I uint32_t RESERVED5[10];
Kojto 97:433970e64889 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
Kojto 122:f9eeca106725 586 __I uint32_t RESERVED6[109];
Kojto 97:433970e64889 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 97:433970e64889 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 589 __I uint32_t RESERVED7[125];
Kojto 97:433970e64889 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
Kojto 122:f9eeca106725 591 __I uint32_t RESERVED8;
Kojto 97:433970e64889 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
Kojto 122:f9eeca106725 593 __I uint32_t RESERVED9[4];
Kojto 97:433970e64889 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
Kojto 122:f9eeca106725 595 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 597 __I uint32_t RESERVED11;
Kojto 97:433970e64889 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 599 __I uint32_t RESERVED12;
Kojto 97:433970e64889 600 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 601 __I uint32_t RESERVED13[26];
Kojto 97:433970e64889 602 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 603 __I uint32_t RESERVED14[654];
Kojto 97:433970e64889 604 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 97:433970e64889 605 } NRF_SPIM_Type;
Kojto 97:433970e64889 606
Kojto 97:433970e64889 607
Kojto 97:433970e64889 608 /* ================================================================================ */
Kojto 91:031413cf7a89 609 /* ================ GPIOTE ================ */
Kojto 91:031413cf7a89 610 /* ================================================================================ */
Kojto 91:031413cf7a89 611
Kojto 91:031413cf7a89 612
Kojto 91:031413cf7a89 613 /**
Kojto 91:031413cf7a89 614 * @brief GPIO tasks and events. (GPIOTE)
Kojto 91:031413cf7a89 615 */
Kojto 91:031413cf7a89 616
Kojto 91:031413cf7a89 617 typedef struct { /*!< GPIOTE Structure */
Kojto 91:031413cf7a89 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
Kojto 91:031413cf7a89 619 __I uint32_t RESERVED0[60];
Kojto 91:031413cf7a89 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
Kojto 91:031413cf7a89 621 __I uint32_t RESERVED1[27];
Kojto 91:031413cf7a89 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
Kojto 91:031413cf7a89 623 __I uint32_t RESERVED2[97];
Kojto 91:031413cf7a89 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 626 __I uint32_t RESERVED3[129];
Kojto 91:031413cf7a89 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
Kojto 91:031413cf7a89 628 __I uint32_t RESERVED4[695];
Kojto 91:031413cf7a89 629 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 630 } NRF_GPIOTE_Type;
Kojto 91:031413cf7a89 631
Kojto 91:031413cf7a89 632
Kojto 91:031413cf7a89 633 /* ================================================================================ */
Kojto 91:031413cf7a89 634 /* ================ ADC ================ */
Kojto 91:031413cf7a89 635 /* ================================================================================ */
Kojto 91:031413cf7a89 636
Kojto 91:031413cf7a89 637
Kojto 91:031413cf7a89 638 /**
Kojto 91:031413cf7a89 639 * @brief Analog to digital converter. (ADC)
Kojto 91:031413cf7a89 640 */
Kojto 91:031413cf7a89 641
Kojto 91:031413cf7a89 642 typedef struct { /*!< ADC Structure */
Kojto 91:031413cf7a89 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
Kojto 91:031413cf7a89 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
Kojto 91:031413cf7a89 645 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
Kojto 91:031413cf7a89 647 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 650 __I uint32_t RESERVED2[61];
Kojto 91:031413cf7a89 651 __I uint32_t BUSY; /*!< ADC busy register. */
Kojto 91:031413cf7a89 652 __I uint32_t RESERVED3[63];
Kojto 91:031413cf7a89 653 __IO uint32_t ENABLE; /*!< ADC enable. */
Kojto 91:031413cf7a89 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
Kojto 91:031413cf7a89 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
Kojto 91:031413cf7a89 656 __I uint32_t RESERVED4[700];
Kojto 91:031413cf7a89 657 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 658 } NRF_ADC_Type;
Kojto 91:031413cf7a89 659
Kojto 91:031413cf7a89 660
Kojto 91:031413cf7a89 661 /* ================================================================================ */
Kojto 91:031413cf7a89 662 /* ================ TIMER ================ */
Kojto 91:031413cf7a89 663 /* ================================================================================ */
Kojto 91:031413cf7a89 664
Kojto 91:031413cf7a89 665
Kojto 91:031413cf7a89 666 /**
Kojto 91:031413cf7a89 667 * @brief Timer 0. (TIMER)
Kojto 91:031413cf7a89 668 */
Kojto 91:031413cf7a89 669
Kojto 91:031413cf7a89 670 typedef struct { /*!< TIMER Structure */
Kojto 91:031413cf7a89 671 __O uint32_t TASKS_START; /*!< Start Timer. */
Kojto 91:031413cf7a89 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
Kojto 91:031413cf7a89 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
Kojto 91:031413cf7a89 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Kojto 97:433970e64889 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
Kojto 97:433970e64889 676 __I uint32_t RESERVED0[11];
Kojto 91:031413cf7a89 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
Kojto 91:031413cf7a89 678 __I uint32_t RESERVED1[60];
Kojto 91:031413cf7a89 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Kojto 91:031413cf7a89 680 __I uint32_t RESERVED2[44];
Kojto 91:031413cf7a89 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
Kojto 91:031413cf7a89 682 __I uint32_t RESERVED3[64];
Kojto 91:031413cf7a89 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 685 __I uint32_t RESERVED4[126];
Kojto 91:031413cf7a89 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
Kojto 91:031413cf7a89 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
Kojto 91:031413cf7a89 688 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
Kojto 91:031413cf7a89 690 clock frequency is divided by 2^SCALE. */
Kojto 91:031413cf7a89 691 __I uint32_t RESERVED6[11];
Kojto 91:031413cf7a89 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Kojto 91:031413cf7a89 693 __I uint32_t RESERVED7[683];
Kojto 91:031413cf7a89 694 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 695 } NRF_TIMER_Type;
Kojto 91:031413cf7a89 696
Kojto 91:031413cf7a89 697
Kojto 91:031413cf7a89 698 /* ================================================================================ */
Kojto 91:031413cf7a89 699 /* ================ RTC ================ */
Kojto 91:031413cf7a89 700 /* ================================================================================ */
Kojto 91:031413cf7a89 701
Kojto 91:031413cf7a89 702
Kojto 91:031413cf7a89 703 /**
Kojto 91:031413cf7a89 704 * @brief Real time counter 0. (RTC)
Kojto 91:031413cf7a89 705 */
Kojto 91:031413cf7a89 706
Kojto 91:031413cf7a89 707 typedef struct { /*!< RTC Structure */
Kojto 91:031413cf7a89 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
Kojto 91:031413cf7a89 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
Kojto 91:031413cf7a89 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
Kojto 91:031413cf7a89 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
Kojto 91:031413cf7a89 712 __I uint32_t RESERVED0[60];
Kojto 91:031413cf7a89 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
Kojto 91:031413cf7a89 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
Kojto 91:031413cf7a89 715 __I uint32_t RESERVED1[14];
Kojto 91:031413cf7a89 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Kojto 91:031413cf7a89 717 __I uint32_t RESERVED2[109];
Kojto 91:031413cf7a89 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 720 __I uint32_t RESERVED3[13];
Kojto 91:031413cf7a89 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
Kojto 91:031413cf7a89 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
Kojto 91:031413cf7a89 723 the value of EVTEN. */
Kojto 91:031413cf7a89 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
Kojto 91:031413cf7a89 725 gives the value of EVTEN. */
Kojto 91:031413cf7a89 726 __I uint32_t RESERVED4[110];
Kojto 97:433970e64889 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
Kojto 91:031413cf7a89 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Kojto 91:031413cf7a89 729 Must be written when RTC is STOPed. */
Kojto 91:031413cf7a89 730 __I uint32_t RESERVED5[13];
Kojto 91:031413cf7a89 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Kojto 91:031413cf7a89 732 __I uint32_t RESERVED6[683];
Kojto 91:031413cf7a89 733 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 734 } NRF_RTC_Type;
Kojto 91:031413cf7a89 735
Kojto 91:031413cf7a89 736
Kojto 91:031413cf7a89 737 /* ================================================================================ */
Kojto 91:031413cf7a89 738 /* ================ TEMP ================ */
Kojto 91:031413cf7a89 739 /* ================================================================================ */
Kojto 91:031413cf7a89 740
Kojto 91:031413cf7a89 741
Kojto 91:031413cf7a89 742 /**
Kojto 91:031413cf7a89 743 * @brief Temperature Sensor. (TEMP)
Kojto 91:031413cf7a89 744 */
Kojto 91:031413cf7a89 745
Kojto 91:031413cf7a89 746 typedef struct { /*!< TEMP Structure */
Kojto 91:031413cf7a89 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
Kojto 91:031413cf7a89 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
Kojto 91:031413cf7a89 749 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
Kojto 91:031413cf7a89 751 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 754 __I uint32_t RESERVED2[127];
Kojto 91:031413cf7a89 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
Kojto 91:031413cf7a89 756 __I uint32_t RESERVED3[700];
Kojto 91:031413cf7a89 757 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 758 } NRF_TEMP_Type;
Kojto 91:031413cf7a89 759
Kojto 91:031413cf7a89 760
Kojto 91:031413cf7a89 761 /* ================================================================================ */
Kojto 91:031413cf7a89 762 /* ================ RNG ================ */
Kojto 91:031413cf7a89 763 /* ================================================================================ */
Kojto 91:031413cf7a89 764
Kojto 91:031413cf7a89 765
Kojto 91:031413cf7a89 766 /**
Kojto 91:031413cf7a89 767 * @brief Random Number Generator. (RNG)
Kojto 91:031413cf7a89 768 */
Kojto 91:031413cf7a89 769
Kojto 91:031413cf7a89 770 typedef struct { /*!< RNG Structure */
Kojto 91:031413cf7a89 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
Kojto 91:031413cf7a89 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
Kojto 91:031413cf7a89 773 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
Kojto 91:031413cf7a89 775 __I uint32_t RESERVED1[63];
Kojto 97:433970e64889 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
Kojto 91:031413cf7a89 777 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
Kojto 91:031413cf7a89 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
Kojto 91:031413cf7a89 780 __I uint32_t RESERVED3[126];
Kojto 91:031413cf7a89 781 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 782 __I uint32_t VALUE; /*!< RNG random number. */
Kojto 91:031413cf7a89 783 __I uint32_t RESERVED4[700];
Kojto 91:031413cf7a89 784 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 785 } NRF_RNG_Type;
Kojto 91:031413cf7a89 786
Kojto 91:031413cf7a89 787
Kojto 91:031413cf7a89 788 /* ================================================================================ */
Kojto 91:031413cf7a89 789 /* ================ ECB ================ */
Kojto 91:031413cf7a89 790 /* ================================================================================ */
Kojto 91:031413cf7a89 791
Kojto 91:031413cf7a89 792
Kojto 91:031413cf7a89 793 /**
Kojto 91:031413cf7a89 794 * @brief AES ECB Mode Encryption. (ECB)
Kojto 91:031413cf7a89 795 */
Kojto 91:031413cf7a89 796
Kojto 91:031413cf7a89 797 typedef struct { /*!< ECB Structure */
Kojto 91:031413cf7a89 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
Kojto 91:031413cf7a89 799 will not initiate a new encryption and the ERRORECB event will
Kojto 91:031413cf7a89 800 be triggered. */
Kojto 91:031413cf7a89 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
Kojto 91:031413cf7a89 802 this will will trigger the ERRORECB event. */
Kojto 91:031413cf7a89 803 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
Kojto 91:031413cf7a89 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
Kojto 91:031413cf7a89 806 error. */
Kojto 91:031413cf7a89 807 __I uint32_t RESERVED1[127];
Kojto 91:031413cf7a89 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 810 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
Kojto 91:031413cf7a89 812 __I uint32_t RESERVED3[701];
Kojto 91:031413cf7a89 813 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 814 } NRF_ECB_Type;
Kojto 91:031413cf7a89 815
Kojto 91:031413cf7a89 816
Kojto 91:031413cf7a89 817 /* ================================================================================ */
Kojto 91:031413cf7a89 818 /* ================ AAR ================ */
Kojto 91:031413cf7a89 819 /* ================================================================================ */
Kojto 91:031413cf7a89 820
Kojto 91:031413cf7a89 821
Kojto 91:031413cf7a89 822 /**
Kojto 91:031413cf7a89 823 * @brief Accelerated Address Resolver. (AAR)
Kojto 91:031413cf7a89 824 */
Kojto 91:031413cf7a89 825
Kojto 91:031413cf7a89 826 typedef struct { /*!< AAR Structure */
Kojto 91:031413cf7a89 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Kojto 91:031413cf7a89 828 data structure. */
Kojto 91:031413cf7a89 829 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
Kojto 91:031413cf7a89 831 __I uint32_t RESERVED1[61];
Kojto 91:031413cf7a89 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
Kojto 91:031413cf7a89 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
Kojto 91:031413cf7a89 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
Kojto 91:031413cf7a89 835 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 838 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 839 __I uint32_t STATUS; /*!< Resolution status. */
Kojto 91:031413cf7a89 840 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
Kojto 91:031413cf7a89 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
Kojto 91:031413cf7a89 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
Kojto 91:031413cf7a89 844 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Kojto 97:433970e64889 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 847 during resolution. A minimum of 3 bytes must be reserved. */
Kojto 91:031413cf7a89 848 __I uint32_t RESERVED6[697];
Kojto 91:031413cf7a89 849 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 850 } NRF_AAR_Type;
Kojto 91:031413cf7a89 851
Kojto 91:031413cf7a89 852
Kojto 91:031413cf7a89 853 /* ================================================================================ */
Kojto 91:031413cf7a89 854 /* ================ CCM ================ */
Kojto 91:031413cf7a89 855 /* ================================================================================ */
Kojto 91:031413cf7a89 856
Kojto 91:031413cf7a89 857
Kojto 91:031413cf7a89 858 /**
Kojto 91:031413cf7a89 859 * @brief AES CCM Mode Encryption. (CCM)
Kojto 91:031413cf7a89 860 */
Kojto 91:031413cf7a89 861
Kojto 91:031413cf7a89 862 typedef struct { /*!< CCM Structure */
Kojto 91:031413cf7a89 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Kojto 91:031413cf7a89 864 itself when completed. */
Kojto 91:031413cf7a89 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
Kojto 91:031413cf7a89 866 completed. */
Kojto 91:031413cf7a89 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
Kojto 91:031413cf7a89 868 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
Kojto 91:031413cf7a89 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
Kojto 91:031413cf7a89 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
Kojto 91:031413cf7a89 872 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
Kojto 91:031413cf7a89 874 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 877 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
Kojto 91:031413cf7a89 879 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 880 __IO uint32_t ENABLE; /*!< CCM enable. */
Kojto 91:031413cf7a89 881 __IO uint32_t MODE; /*!< Operation mode. */
Kojto 97:433970e64889 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
Kojto 97:433970e64889 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
Kojto 97:433970e64889 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
Kojto 97:433970e64889 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 886 during resolution. A minimum of 43 bytes must be reserved. */
Kojto 91:031413cf7a89 887 __I uint32_t RESERVED5[697];
Kojto 91:031413cf7a89 888 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 889 } NRF_CCM_Type;
Kojto 91:031413cf7a89 890
Kojto 91:031413cf7a89 891
Kojto 91:031413cf7a89 892 /* ================================================================================ */
Kojto 91:031413cf7a89 893 /* ================ WDT ================ */
Kojto 91:031413cf7a89 894 /* ================================================================================ */
Kojto 91:031413cf7a89 895
Kojto 91:031413cf7a89 896
Kojto 91:031413cf7a89 897 /**
Kojto 91:031413cf7a89 898 * @brief Watchdog Timer. (WDT)
Kojto 91:031413cf7a89 899 */
Kojto 91:031413cf7a89 900
Kojto 91:031413cf7a89 901 typedef struct { /*!< WDT Structure */
Kojto 91:031413cf7a89 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
Kojto 91:031413cf7a89 903 __I uint32_t RESERVED0[63];
Kojto 91:031413cf7a89 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
Kojto 91:031413cf7a89 905 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 908 __I uint32_t RESERVED2[61];
Kojto 91:031413cf7a89 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
Kojto 91:031413cf7a89 910 __I uint32_t REQSTATUS; /*!< Request status. */
Kojto 91:031413cf7a89 911 __I uint32_t RESERVED3[63];
Kojto 91:031413cf7a89 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
Kojto 91:031413cf7a89 913 __IO uint32_t RREN; /*!< Reload request enable. */
Kojto 91:031413cf7a89 914 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 915 __I uint32_t RESERVED4[60];
Kojto 91:031413cf7a89 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
Kojto 91:031413cf7a89 917 __I uint32_t RESERVED5[631];
Kojto 91:031413cf7a89 918 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 919 } NRF_WDT_Type;
Kojto 91:031413cf7a89 920
Kojto 91:031413cf7a89 921
Kojto 91:031413cf7a89 922 /* ================================================================================ */
Kojto 91:031413cf7a89 923 /* ================ QDEC ================ */
Kojto 91:031413cf7a89 924 /* ================================================================================ */
Kojto 91:031413cf7a89 925
Kojto 91:031413cf7a89 926
Kojto 91:031413cf7a89 927 /**
Kojto 91:031413cf7a89 928 * @brief Rotary decoder. (QDEC)
Kojto 91:031413cf7a89 929 */
Kojto 91:031413cf7a89 930
Kojto 91:031413cf7a89 931 typedef struct { /*!< QDEC Structure */
Kojto 91:031413cf7a89 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
Kojto 91:031413cf7a89 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
Kojto 91:031413cf7a89 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
Kojto 91:031413cf7a89 935 and clears the ACC registers. */
Kojto 91:031413cf7a89 936 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
Kojto 91:031413cf7a89 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
Kojto 91:031413cf7a89 939 ACC register different than zero. */
Kojto 91:031413cf7a89 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
Kojto 91:031413cf7a89 941 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
Kojto 91:031413cf7a89 943 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 946 __I uint32_t RESERVED3[125];
Kojto 91:031413cf7a89 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
Kojto 91:031413cf7a89 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
Kojto 91:031413cf7a89 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
Kojto 91:031413cf7a89 950 __I int32_t SAMPLE; /*!< Motion sample value. */
Kojto 91:031413cf7a89 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
Kojto 91:031413cf7a89 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
Kojto 91:031413cf7a89 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
Kojto 91:031413cf7a89 954 task. */
Kojto 91:031413cf7a89 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
Kojto 91:031413cf7a89 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
Kojto 91:031413cf7a89 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
Kojto 91:031413cf7a89 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
Kojto 91:031413cf7a89 959 __I uint32_t RESERVED4[5];
Kojto 91:031413cf7a89 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
Kojto 91:031413cf7a89 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
Kojto 91:031413cf7a89 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
Kojto 91:031413cf7a89 963 task. */
Kojto 91:031413cf7a89 964 __I uint32_t RESERVED5[684];
Kojto 91:031413cf7a89 965 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 966 } NRF_QDEC_Type;
Kojto 91:031413cf7a89 967
Kojto 91:031413cf7a89 968
Kojto 91:031413cf7a89 969 /* ================================================================================ */
Kojto 91:031413cf7a89 970 /* ================ LPCOMP ================ */
Kojto 91:031413cf7a89 971 /* ================================================================================ */
Kojto 91:031413cf7a89 972
Kojto 91:031413cf7a89 973
Kojto 91:031413cf7a89 974 /**
Kojto 97:433970e64889 975 * @brief Low power comparator. (LPCOMP)
Kojto 91:031413cf7a89 976 */
Kojto 91:031413cf7a89 977
Kojto 91:031413cf7a89 978 typedef struct { /*!< LPCOMP Structure */
Kojto 91:031413cf7a89 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
Kojto 91:031413cf7a89 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
Kojto 91:031413cf7a89 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
Kojto 91:031413cf7a89 982 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
Kojto 91:031413cf7a89 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
Kojto 91:031413cf7a89 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
Kojto 91:031413cf7a89 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
Kojto 91:031413cf7a89 987 __I uint32_t RESERVED1[60];
Kojto 97:433970e64889 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
Kojto 91:031413cf7a89 989 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 992 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 993 __I uint32_t RESULT; /*!< Result of last compare. */
Kojto 91:031413cf7a89 994 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
Kojto 91:031413cf7a89 996 __IO uint32_t PSEL; /*!< Input pin select. */
Kojto 91:031413cf7a89 997 __IO uint32_t REFSEL; /*!< Reference select. */
Kojto 91:031413cf7a89 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
Kojto 91:031413cf7a89 999 __I uint32_t RESERVED5[4];
Kojto 91:031413cf7a89 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
Kojto 91:031413cf7a89 1001 __I uint32_t RESERVED6[694];
Kojto 91:031413cf7a89 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 1003 } NRF_LPCOMP_Type;
Kojto 91:031413cf7a89 1004
Kojto 91:031413cf7a89 1005
Kojto 91:031413cf7a89 1006 /* ================================================================================ */
Kojto 91:031413cf7a89 1007 /* ================ SWI ================ */
Kojto 91:031413cf7a89 1008 /* ================================================================================ */
Kojto 91:031413cf7a89 1009
Kojto 91:031413cf7a89 1010
Kojto 91:031413cf7a89 1011 /**
Kojto 91:031413cf7a89 1012 * @brief SW Interrupts. (SWI)
Kojto 91:031413cf7a89 1013 */
Kojto 91:031413cf7a89 1014
Kojto 91:031413cf7a89 1015 typedef struct { /*!< SWI Structure */
Kojto 91:031413cf7a89 1016 __I uint32_t UNUSED; /*!< Unused. */
Kojto 91:031413cf7a89 1017 } NRF_SWI_Type;
Kojto 91:031413cf7a89 1018
Kojto 91:031413cf7a89 1019
Kojto 91:031413cf7a89 1020 /* ================================================================================ */
Kojto 91:031413cf7a89 1021 /* ================ NVMC ================ */
Kojto 91:031413cf7a89 1022 /* ================================================================================ */
Kojto 91:031413cf7a89 1023
Kojto 91:031413cf7a89 1024
Kojto 91:031413cf7a89 1025 /**
Kojto 91:031413cf7a89 1026 * @brief Non Volatile Memory Controller. (NVMC)
Kojto 91:031413cf7a89 1027 */
Kojto 91:031413cf7a89 1028
Kojto 91:031413cf7a89 1029 typedef struct { /*!< NVMC Structure */
Kojto 91:031413cf7a89 1030 __I uint32_t RESERVED0[256];
Kojto 91:031413cf7a89 1031 __I uint32_t READY; /*!< Ready flag. */
Kojto 91:031413cf7a89 1032 __I uint32_t RESERVED1[64];
Kojto 91:031413cf7a89 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 1034
Kojto 122:f9eeca106725 1035 union {
Kojto 122:f9eeca106725 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1038 };
Kojto 91:031413cf7a89 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
Kojto 122:f9eeca106725 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
Kojto 91:031413cf7a89 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
Kojto 91:031413cf7a89 1042 } NRF_NVMC_Type;
Kojto 91:031413cf7a89 1043
Kojto 91:031413cf7a89 1044
Kojto 91:031413cf7a89 1045 /* ================================================================================ */
Kojto 91:031413cf7a89 1046 /* ================ PPI ================ */
Kojto 91:031413cf7a89 1047 /* ================================================================================ */
Kojto 91:031413cf7a89 1048
Kojto 91:031413cf7a89 1049
Kojto 91:031413cf7a89 1050 /**
Kojto 91:031413cf7a89 1051 * @brief PPI controller. (PPI)
Kojto 91:031413cf7a89 1052 */
Kojto 91:031413cf7a89 1053
Kojto 91:031413cf7a89 1054 typedef struct { /*!< PPI Structure */
Kojto 91:031413cf7a89 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
Kojto 91:031413cf7a89 1056 __I uint32_t RESERVED0[312];
Kojto 91:031413cf7a89 1057 __IO uint32_t CHEN; /*!< Channel enable. */
Kojto 91:031413cf7a89 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
Kojto 91:031413cf7a89 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
Kojto 91:031413cf7a89 1060 __I uint32_t RESERVED1;
Kojto 91:031413cf7a89 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
Kojto 91:031413cf7a89 1062 __I uint32_t RESERVED2[156];
Kojto 91:031413cf7a89 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
Kojto 91:031413cf7a89 1064 } NRF_PPI_Type;
Kojto 91:031413cf7a89 1065
Kojto 91:031413cf7a89 1066
Kojto 91:031413cf7a89 1067 /* ================================================================================ */
Kojto 91:031413cf7a89 1068 /* ================ FICR ================ */
Kojto 91:031413cf7a89 1069 /* ================================================================================ */
Kojto 91:031413cf7a89 1070
Kojto 91:031413cf7a89 1071
Kojto 91:031413cf7a89 1072 /**
Kojto 91:031413cf7a89 1073 * @brief Factory Information Configuration. (FICR)
Kojto 91:031413cf7a89 1074 */
Kojto 91:031413cf7a89 1075
Kojto 91:031413cf7a89 1076 typedef struct { /*!< FICR Structure */
Kojto 91:031413cf7a89 1077 __I uint32_t RESERVED0[4];
Kojto 91:031413cf7a89 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
Kojto 91:031413cf7a89 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
Kojto 91:031413cf7a89 1080 __I uint32_t RESERVED1[4];
Kojto 91:031413cf7a89 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
Kojto 91:031413cf7a89 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
Kojto 91:031413cf7a89 1083 __I uint32_t RESERVED2;
Kojto 91:031413cf7a89 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Kojto 97:433970e64889 1085
Kojto 97:433970e64889 1086 union {
Kojto 97:433970e64889 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto 97:433970e64889 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto 97:433970e64889 1089 instead. */
Kojto 97:433970e64889 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
Kojto 97:433970e64889 1091 };
Kojto 91:031413cf7a89 1092 __I uint32_t RESERVED3[5];
Kojto 91:031413cf7a89 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
Kojto 91:031413cf7a89 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
Kojto 91:031413cf7a89 1095 __I uint32_t RESERVED4[6];
Kojto 91:031413cf7a89 1096 __I uint32_t ER[4]; /*!< Encryption root. */
Kojto 91:031413cf7a89 1097 __I uint32_t IR[4]; /*!< Identity root. */
Kojto 91:031413cf7a89 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
Kojto 91:031413cf7a89 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
Kojto 91:031413cf7a89 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Kojto 97:433970e64889 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto 97:433970e64889 1102 mode. */
Kojto 97:433970e64889 1103 __I uint32_t RESERVED5[10];
Kojto 91:031413cf7a89 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
Kojto 91:031413cf7a89 1105 mode. */
Kojto 91:031413cf7a89 1106 } NRF_FICR_Type;
Kojto 91:031413cf7a89 1107
Kojto 91:031413cf7a89 1108
Kojto 91:031413cf7a89 1109 /* ================================================================================ */
Kojto 91:031413cf7a89 1110 /* ================ UICR ================ */
Kojto 91:031413cf7a89 1111 /* ================================================================================ */
Kojto 91:031413cf7a89 1112
Kojto 91:031413cf7a89 1113
Kojto 91:031413cf7a89 1114 /**
Kojto 91:031413cf7a89 1115 * @brief User Information Configuration. (UICR)
Kojto 91:031413cf7a89 1116 */
Kojto 91:031413cf7a89 1117
Kojto 91:031413cf7a89 1118 typedef struct { /*!< UICR Structure */
Kojto 91:031413cf7a89 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
Kojto 91:031413cf7a89 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
Kojto 91:031413cf7a89 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
Kojto 91:031413cf7a89 1122 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 1123 __I uint32_t FWID; /*!< Firmware ID. */
Kojto 122:f9eeca106725 1124
Kojto 122:f9eeca106725 1125 union {
Kojto 122:f9eeca106725 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
Kojto 122:f9eeca106725 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
Kojto 122:f9eeca106725 1128 };
Kojto 122:f9eeca106725 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
Kojto 122:f9eeca106725 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
Kojto 91:031413cf7a89 1131 } NRF_UICR_Type;
Kojto 91:031413cf7a89 1132
Kojto 91:031413cf7a89 1133
Kojto 91:031413cf7a89 1134 /* ================================================================================ */
Kojto 91:031413cf7a89 1135 /* ================ GPIO ================ */
Kojto 91:031413cf7a89 1136 /* ================================================================================ */
Kojto 91:031413cf7a89 1137
Kojto 91:031413cf7a89 1138
Kojto 91:031413cf7a89 1139 /**
Kojto 91:031413cf7a89 1140 * @brief General purpose input and output. (GPIO)
Kojto 91:031413cf7a89 1141 */
Kojto 91:031413cf7a89 1142
Kojto 91:031413cf7a89 1143 typedef struct { /*!< GPIO Structure */
Kojto 91:031413cf7a89 1144 __I uint32_t RESERVED0[321];
Kojto 91:031413cf7a89 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
Kojto 91:031413cf7a89 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
Kojto 91:031413cf7a89 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
Kojto 91:031413cf7a89 1148 __I uint32_t IN; /*!< Read GPIO port. */
Kojto 91:031413cf7a89 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
Kojto 91:031413cf7a89 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
Kojto 91:031413cf7a89 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
Kojto 91:031413cf7a89 1152 __I uint32_t RESERVED1[120];
Kojto 91:031413cf7a89 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
Kojto 91:031413cf7a89 1154 } NRF_GPIO_Type;
Kojto 91:031413cf7a89 1155
Kojto 91:031413cf7a89 1156
Kojto 91:031413cf7a89 1157 /* -------------------- End of section using anonymous unions ------------------- */
Kojto 91:031413cf7a89 1158 #if defined(__CC_ARM)
Kojto 91:031413cf7a89 1159 #pragma pop
Kojto 91:031413cf7a89 1160 #elif defined(__ICCARM__)
Kojto 91:031413cf7a89 1161 /* leave anonymous unions enabled */
Kojto 91:031413cf7a89 1162 #elif defined(__GNUC__)
Kojto 91:031413cf7a89 1163 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 1164 #elif defined(__TMS470__)
Kojto 91:031413cf7a89 1165 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 1166 #elif defined(__TASKING__)
Kojto 91:031413cf7a89 1167 #pragma warning restore
Kojto 91:031413cf7a89 1168 #else
Kojto 91:031413cf7a89 1169 #warning Not supported compiler type
Kojto 91:031413cf7a89 1170 #endif
Kojto 91:031413cf7a89 1171
Kojto 91:031413cf7a89 1172
Kojto 91:031413cf7a89 1173
Kojto 91:031413cf7a89 1174
Kojto 91:031413cf7a89 1175 /* ================================================================================ */
Kojto 91:031413cf7a89 1176 /* ================ Peripheral memory map ================ */
Kojto 91:031413cf7a89 1177 /* ================================================================================ */
Kojto 91:031413cf7a89 1178
Kojto 91:031413cf7a89 1179 #define NRF_POWER_BASE 0x40000000UL
Kojto 91:031413cf7a89 1180 #define NRF_CLOCK_BASE 0x40000000UL
Kojto 91:031413cf7a89 1181 #define NRF_MPU_BASE 0x40000000UL
Kojto 91:031413cf7a89 1182 #define NRF_AMLI_BASE 0x40000000UL
Kojto 91:031413cf7a89 1183 #define NRF_RADIO_BASE 0x40001000UL
Kojto 91:031413cf7a89 1184 #define NRF_UART0_BASE 0x40002000UL
Kojto 91:031413cf7a89 1185 #define NRF_SPI0_BASE 0x40003000UL
Kojto 91:031413cf7a89 1186 #define NRF_TWI0_BASE 0x40003000UL
Kojto 91:031413cf7a89 1187 #define NRF_SPI1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1188 #define NRF_TWI1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1189 #define NRF_SPIS1_BASE 0x40004000UL
Kojto 97:433970e64889 1190 #define NRF_SPIM1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1191 #define NRF_GPIOTE_BASE 0x40006000UL
Kojto 91:031413cf7a89 1192 #define NRF_ADC_BASE 0x40007000UL
Kojto 91:031413cf7a89 1193 #define NRF_TIMER0_BASE 0x40008000UL
Kojto 91:031413cf7a89 1194 #define NRF_TIMER1_BASE 0x40009000UL
Kojto 91:031413cf7a89 1195 #define NRF_TIMER2_BASE 0x4000A000UL
Kojto 91:031413cf7a89 1196 #define NRF_RTC0_BASE 0x4000B000UL
Kojto 91:031413cf7a89 1197 #define NRF_TEMP_BASE 0x4000C000UL
Kojto 91:031413cf7a89 1198 #define NRF_RNG_BASE 0x4000D000UL
Kojto 91:031413cf7a89 1199 #define NRF_ECB_BASE 0x4000E000UL
Kojto 91:031413cf7a89 1200 #define NRF_AAR_BASE 0x4000F000UL
Kojto 91:031413cf7a89 1201 #define NRF_CCM_BASE 0x4000F000UL
Kojto 91:031413cf7a89 1202 #define NRF_WDT_BASE 0x40010000UL
Kojto 91:031413cf7a89 1203 #define NRF_RTC1_BASE 0x40011000UL
Kojto 91:031413cf7a89 1204 #define NRF_QDEC_BASE 0x40012000UL
Kojto 91:031413cf7a89 1205 #define NRF_LPCOMP_BASE 0x40013000UL
Kojto 91:031413cf7a89 1206 #define NRF_SWI_BASE 0x40014000UL
Kojto 91:031413cf7a89 1207 #define NRF_NVMC_BASE 0x4001E000UL
Kojto 91:031413cf7a89 1208 #define NRF_PPI_BASE 0x4001F000UL
Kojto 91:031413cf7a89 1209 #define NRF_FICR_BASE 0x10000000UL
Kojto 91:031413cf7a89 1210 #define NRF_UICR_BASE 0x10001000UL
Kojto 91:031413cf7a89 1211 #define NRF_GPIO_BASE 0x50000000UL
Kojto 91:031413cf7a89 1212
Kojto 91:031413cf7a89 1213
Kojto 91:031413cf7a89 1214 /* ================================================================================ */
Kojto 91:031413cf7a89 1215 /* ================ Peripheral declaration ================ */
Kojto 91:031413cf7a89 1216 /* ================================================================================ */
Kojto 91:031413cf7a89 1217
Kojto 91:031413cf7a89 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Kojto 91:031413cf7a89 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Kojto 91:031413cf7a89 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
Kojto 91:031413cf7a89 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Kojto 91:031413cf7a89 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Kojto 91:031413cf7a89 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Kojto 91:031413cf7a89 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Kojto 91:031413cf7a89 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Kojto 91:031413cf7a89 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Kojto 91:031413cf7a89 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Kojto 91:031413cf7a89 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto 97:433970e64889 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
Kojto 91:031413cf7a89 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Kojto 91:031413cf7a89 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
Kojto 91:031413cf7a89 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Kojto 91:031413cf7a89 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Kojto 91:031413cf7a89 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Kojto 91:031413cf7a89 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Kojto 91:031413cf7a89 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Kojto 91:031413cf7a89 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Kojto 91:031413cf7a89 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Kojto 91:031413cf7a89 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Kojto 91:031413cf7a89 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Kojto 91:031413cf7a89 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Kojto 91:031413cf7a89 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Kojto 91:031413cf7a89 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Kojto 91:031413cf7a89 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Kojto 91:031413cf7a89 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
Kojto 91:031413cf7a89 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Kojto 91:031413cf7a89 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Kojto 91:031413cf7a89 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Kojto 91:031413cf7a89 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Kojto 91:031413cf7a89 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
Kojto 91:031413cf7a89 1251
Kojto 91:031413cf7a89 1252
Kojto 91:031413cf7a89 1253 /** @} */ /* End of group Device_Peripheral_Registers */
Kojto 122:f9eeca106725 1254 /** @} */ /* End of group nrf51 */
Kojto 91:031413cf7a89 1255 /** @} */ /* End of group Nordic Semiconductor */
Kojto 91:031413cf7a89 1256
Kojto 91:031413cf7a89 1257 #ifdef __cplusplus
Kojto 91:031413cf7a89 1258 }
Kojto 91:031413cf7a89 1259 #endif
Kojto 91:031413cf7a89 1260
Kojto 91:031413cf7a89 1261
Kojto 122:f9eeca106725 1262 #endif /* nrf51_H */