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TARGET_NRF51_DK/nrf51.h@123:b0220dba8be7, 2016-08-12 (annotated)

Committer:
Kojto
Date:
Fri Aug 12 13:04:35 2016 +0200
Revision:
123:b0220dba8be7
Parent:
122:f9eeca106725 
Release 123 of the mbed library



Changes:

- new targets: nucleo_f207zg, beetle, nrf51_dk, hexiwear,

 nuvoton nuc472, vk rz a1h

- ST - fix timer interrupt handler, sleep api fix

- NXP - lpc15xx us ticker fix

- Nordic - analogin fixes, LF clock init addition, enable i2c async

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 123:b0220dba8be7 1
Kojto 123:b0220dba8be7 2 /****************************************************************************************************//**
Kojto 123:b0220dba8be7 3 * @file nrf51.h
Kojto 97:433970e64889 4 *
Kojto 123:b0220dba8be7 5 * @brief CMSIS Cortex-M0 Peripheral Access Layer Header File for
Kojto 123:b0220dba8be7 6 * nrf51 from Nordic Semiconductor.
Kojto 91:031413cf7a89 7 *
Kojto 123:b0220dba8be7 8 * @version V522
Kojto 123:b0220dba8be7 9 * @date 23. February 2016
Kojto 123:b0220dba8be7 10 *
Kojto 123:b0220dba8be7 11 * @note Generated with SVDConv V2.81d
Kojto 123:b0220dba8be7 12 * from CMSIS SVD File 'nrf51.svd' Version 522,
Kojto 122:f9eeca106725 13 *
Kojto 123:b0220dba8be7 14 * @par Copyright (c) 2013, Nordic Semiconductor ASA
Kojto 123:b0220dba8be7 15 * All rights reserved.
Kojto 123:b0220dba8be7 16 *
Kojto 123:b0220dba8be7 17 * Redistribution and use in source and binary forms, with or without
Kojto 123:b0220dba8be7 18 * modification, are permitted provided that the following conditions are met:
Kojto 123:b0220dba8be7 19 *
Kojto 123:b0220dba8be7 20 * * Redistributions of source code must retain the above copyright notice, this
Kojto 123:b0220dba8be7 21 * list of conditions and the following disclaimer.
Kojto 123:b0220dba8be7 22 *
Kojto 123:b0220dba8be7 23 * * Redistributions in binary form must reproduce the above copyright notice,
Kojto 123:b0220dba8be7 24 * this list of conditions and the following disclaimer in the documentation
Kojto 123:b0220dba8be7 25 * and/or other materials provided with the distribution.
Kojto 123:b0220dba8be7 26 *
Kojto 123:b0220dba8be7 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto 123:b0220dba8be7 28 * contributors may be used to endorse or promote products derived from
Kojto 123:b0220dba8be7 29 * this software without specific prior written permission.
Kojto 123:b0220dba8be7 30 *
Kojto 123:b0220dba8be7 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 123:b0220dba8be7 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 123:b0220dba8be7 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 123:b0220dba8be7 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 123:b0220dba8be7 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 123:b0220dba8be7 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 123:b0220dba8be7 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 123:b0220dba8be7 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 123:b0220dba8be7 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 123:b0220dba8be7 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 123:b0220dba8be7 41 *
Kojto 97:433970e64889 42 *
Kojto 123:b0220dba8be7 43 *******************************************************************************************************/
Kojto 123:b0220dba8be7 44
Kojto 123:b0220dba8be7 45
Kojto 123:b0220dba8be7 46
Kojto 123:b0220dba8be7 47 /** @addtogroup Nordic Semiconductor
Kojto 123:b0220dba8be7 48 * @{
Kojto 123:b0220dba8be7 49 */
Kojto 123:b0220dba8be7 50
Kojto 123:b0220dba8be7 51 /** @addtogroup nrf51
Kojto 123:b0220dba8be7 52 * @{
Kojto 123:b0220dba8be7 53 */
Kojto 91:031413cf7a89 54
Kojto 91:031413cf7a89 55 #ifndef NRF51_H
Kojto 91:031413cf7a89 56 #define NRF51_H
Kojto 91:031413cf7a89 57
Kojto 91:031413cf7a89 58 #ifdef __cplusplus
Kojto 91:031413cf7a89 59 extern "C" {
Kojto 91:031413cf7a89 60 #endif
Kojto 91:031413cf7a89 61
Kojto 91:031413cf7a89 62
Kojto 91:031413cf7a89 63 /* ------------------------- Interrupt Number Definition ------------------------ */
Kojto 91:031413cf7a89 64
Kojto 91:031413cf7a89 65 typedef enum {
Kojto 91:031413cf7a89 66 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
Kojto 91:031413cf7a89 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
Kojto 91:031413cf7a89 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
Kojto 91:031413cf7a89 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
Kojto 91:031413cf7a89 70 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
Kojto 91:031413cf7a89 71 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
Kojto 91:031413cf7a89 72 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
Kojto 91:031413cf7a89 73 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Kojto 122:f9eeca106725 74 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
Kojto 91:031413cf7a89 75 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
Kojto 91:031413cf7a89 76 RADIO_IRQn = 1, /*!< 1 RADIO */
Kojto 91:031413cf7a89 77 UART0_IRQn = 2, /*!< 2 UART0 */
Kojto 91:031413cf7a89 78 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
Kojto 91:031413cf7a89 79 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
Kojto 91:031413cf7a89 80 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
Kojto 91:031413cf7a89 81 ADC_IRQn = 7, /*!< 7 ADC */
Kojto 91:031413cf7a89 82 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
Kojto 91:031413cf7a89 83 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
Kojto 91:031413cf7a89 84 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
Kojto 91:031413cf7a89 85 RTC0_IRQn = 11, /*!< 11 RTC0 */
Kojto 91:031413cf7a89 86 TEMP_IRQn = 12, /*!< 12 TEMP */
Kojto 91:031413cf7a89 87 RNG_IRQn = 13, /*!< 13 RNG */
Kojto 91:031413cf7a89 88 ECB_IRQn = 14, /*!< 14 ECB */
Kojto 91:031413cf7a89 89 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
Kojto 91:031413cf7a89 90 WDT_IRQn = 16, /*!< 16 WDT */
Kojto 91:031413cf7a89 91 RTC1_IRQn = 17, /*!< 17 RTC1 */
Kojto 91:031413cf7a89 92 QDEC_IRQn = 18, /*!< 18 QDEC */
Kojto 97:433970e64889 93 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
Kojto 91:031413cf7a89 94 SWI0_IRQn = 20, /*!< 20 SWI0 */
Kojto 91:031413cf7a89 95 SWI1_IRQn = 21, /*!< 21 SWI1 */
Kojto 91:031413cf7a89 96 SWI2_IRQn = 22, /*!< 22 SWI2 */
Kojto 91:031413cf7a89 97 SWI3_IRQn = 23, /*!< 23 SWI3 */
Kojto 91:031413cf7a89 98 SWI4_IRQn = 24, /*!< 24 SWI4 */
Kojto 91:031413cf7a89 99 SWI5_IRQn = 25 /*!< 25 SWI5 */
Kojto 91:031413cf7a89 100 } IRQn_Type;
Kojto 91:031413cf7a89 101
Kojto 91:031413cf7a89 102
Kojto 91:031413cf7a89 103 /** @addtogroup Configuration_of_CMSIS
Kojto 91:031413cf7a89 104 * @{
Kojto 91:031413cf7a89 105 */
Kojto 91:031413cf7a89 106
Kojto 91:031413cf7a89 107
Kojto 91:031413cf7a89 108 /* ================================================================================ */
Kojto 91:031413cf7a89 109 /* ================ Processor and Core Peripheral Section ================ */
Kojto 91:031413cf7a89 110 /* ================================================================================ */
Kojto 91:031413cf7a89 111
Kojto 97:433970e64889 112 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
Kojto 91:031413cf7a89 113 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
Kojto 91:031413cf7a89 114 #define __MPU_PRESENT 0 /*!< MPU present or not */
Kojto 91:031413cf7a89 115 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
Kojto 91:031413cf7a89 116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 91:031413cf7a89 117 /** @} */ /* End of group Configuration_of_CMSIS */
Kojto 91:031413cf7a89 118
Kojto 97:433970e64889 119 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
Kojto 122:f9eeca106725 120 #include "system_nrf51.h" /*!< nrf51 System */
Kojto 122:f9eeca106725 121
Kojto 91:031413cf7a89 122
Kojto 91:031413cf7a89 123 /* ================================================================================ */
Kojto 91:031413cf7a89 124 /* ================ Device Specific Peripheral Section ================ */
Kojto 91:031413cf7a89 125 /* ================================================================================ */
Kojto 91:031413cf7a89 126
Kojto 91:031413cf7a89 127
Kojto 91:031413cf7a89 128 /** @addtogroup Device_Peripheral_Registers
Kojto 91:031413cf7a89 129 * @{
Kojto 91:031413cf7a89 130 */
Kojto 91:031413cf7a89 131
Kojto 91:031413cf7a89 132
Kojto 91:031413cf7a89 133 /* ------------------- Start of section using anonymous unions ------------------ */
Kojto 91:031413cf7a89 134 #if defined(__CC_ARM)
Kojto 91:031413cf7a89 135 #pragma push
Kojto 91:031413cf7a89 136 #pragma anon_unions
Kojto 91:031413cf7a89 137 #elif defined(__ICCARM__)
Kojto 91:031413cf7a89 138 #pragma language=extended
Kojto 91:031413cf7a89 139 #elif defined(__GNUC__)
Kojto 91:031413cf7a89 140 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 141 #elif defined(__TMS470__)
Kojto 91:031413cf7a89 142 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 143 #elif defined(__TASKING__)
Kojto 91:031413cf7a89 144 #pragma warning 586
Kojto 91:031413cf7a89 145 #else
Kojto 91:031413cf7a89 146 #warning Not supported compiler type
Kojto 91:031413cf7a89 147 #endif
Kojto 91:031413cf7a89 148
Kojto 91:031413cf7a89 149
Kojto 91:031413cf7a89 150 typedef struct {
Kojto 91:031413cf7a89 151 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
Kojto 91:031413cf7a89 152 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
Kojto 91:031413cf7a89 153 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
Kojto 91:031413cf7a89 154 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
Kojto 91:031413cf7a89 155 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
Kojto 91:031413cf7a89 156 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
Kojto 91:031413cf7a89 157 } AMLI_RAMPRI_Type;
Kojto 91:031413cf7a89 158
Kojto 91:031413cf7a89 159 typedef struct {
Kojto 97:433970e64889 160 __IO uint32_t SCK; /*!< Pin select for SCK. */
Kojto 97:433970e64889 161 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
Kojto 97:433970e64889 162 __IO uint32_t MISO; /*!< Pin select for MISO. */
Kojto 97:433970e64889 163 } SPIM_PSEL_Type;
Kojto 97:433970e64889 164
Kojto 97:433970e64889 165 typedef struct {
Kojto 97:433970e64889 166 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 167 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
Kojto 97:433970e64889 168 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
Kojto 97:433970e64889 169 } SPIM_RXD_Type;
Kojto 97:433970e64889 170
Kojto 97:433970e64889 171 typedef struct {
Kojto 97:433970e64889 172 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 173 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
Kojto 97:433970e64889 174 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
Kojto 97:433970e64889 175 } SPIM_TXD_Type;
Kojto 97:433970e64889 176
Kojto 97:433970e64889 177 typedef struct {
Kojto 91:031413cf7a89 178 __O uint32_t EN; /*!< Enable channel group. */
Kojto 91:031413cf7a89 179 __O uint32_t DIS; /*!< Disable channel group. */
Kojto 91:031413cf7a89 180 } PPI_TASKS_CHG_Type;
Kojto 91:031413cf7a89 181
Kojto 91:031413cf7a89 182 typedef struct {
Kojto 91:031413cf7a89 183 __IO uint32_t EEP; /*!< Channel event end-point. */
Kojto 91:031413cf7a89 184 __IO uint32_t TEP; /*!< Channel task end-point. */
Kojto 91:031413cf7a89 185 } PPI_CH_Type;
Kojto 91:031413cf7a89 186
Kojto 91:031413cf7a89 187
Kojto 91:031413cf7a89 188 /* ================================================================================ */
Kojto 91:031413cf7a89 189 /* ================ POWER ================ */
Kojto 91:031413cf7a89 190 /* ================================================================================ */
Kojto 91:031413cf7a89 191
Kojto 91:031413cf7a89 192
Kojto 91:031413cf7a89 193 /**
Kojto 91:031413cf7a89 194 * @brief Power Control. (POWER)
Kojto 91:031413cf7a89 195 */
Kojto 91:031413cf7a89 196
Kojto 91:031413cf7a89 197 typedef struct { /*!< POWER Structure */
Kojto 91:031413cf7a89 198 __I uint32_t RESERVED0[30];
Kojto 91:031413cf7a89 199 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
Kojto 91:031413cf7a89 200 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
Kojto 91:031413cf7a89 201 __I uint32_t RESERVED1[34];
Kojto 91:031413cf7a89 202 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
Kojto 91:031413cf7a89 203 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 204 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 205 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 206 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 207 __IO uint32_t RESETREAS; /*!< Reset reason. */
Kojto 97:433970e64889 208 __I uint32_t RESERVED4[9];
Kojto 97:433970e64889 209 __I uint32_t RAMSTATUS; /*!< Ram status register. */
Kojto 97:433970e64889 210 __I uint32_t RESERVED5[53];
Kojto 91:031413cf7a89 211 __O uint32_t SYSTEMOFF; /*!< System off register. */
Kojto 97:433970e64889 212 __I uint32_t RESERVED6[3];
Kojto 91:031413cf7a89 213 __IO uint32_t POFCON; /*!< Power failure configuration. */
Kojto 97:433970e64889 214 __I uint32_t RESERVED7[2];
Kojto 91:031413cf7a89 215 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
Kojto 91:031413cf7a89 216 register. */
Kojto 97:433970e64889 217 __I uint32_t RESERVED8;
Kojto 91:031413cf7a89 218 __IO uint32_t RAMON; /*!< Ram on/off. */
Kojto 97:433970e64889 219 __I uint32_t RESERVED9[7];
Kojto 91:031413cf7a89 220 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
Kojto 91:031413cf7a89 221 is a retained register. */
Kojto 97:433970e64889 222 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 223 __IO uint32_t RAMONB; /*!< Ram on/off. */
Kojto 97:433970e64889 224 __I uint32_t RESERVED11[8];
Kojto 91:031413cf7a89 225 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Kojto 97:433970e64889 226 __I uint32_t RESERVED12[291];
Kojto 97:433970e64889 227 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
Kojto 91:031413cf7a89 228 } NRF_POWER_Type;
Kojto 91:031413cf7a89 229
Kojto 91:031413cf7a89 230
Kojto 91:031413cf7a89 231 /* ================================================================================ */
Kojto 91:031413cf7a89 232 /* ================ CLOCK ================ */
Kojto 91:031413cf7a89 233 /* ================================================================================ */
Kojto 91:031413cf7a89 234
Kojto 91:031413cf7a89 235
Kojto 91:031413cf7a89 236 /**
Kojto 91:031413cf7a89 237 * @brief Clock control. (CLOCK)
Kojto 91:031413cf7a89 238 */
Kojto 91:031413cf7a89 239
Kojto 91:031413cf7a89 240 typedef struct { /*!< CLOCK Structure */
Kojto 91:031413cf7a89 241 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
Kojto 91:031413cf7a89 242 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
Kojto 91:031413cf7a89 243 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
Kojto 91:031413cf7a89 244 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
Kojto 91:031413cf7a89 245 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
Kojto 91:031413cf7a89 246 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
Kojto 91:031413cf7a89 247 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
Kojto 91:031413cf7a89 248 __I uint32_t RESERVED0[57];
Kojto 91:031413cf7a89 249 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
Kojto 91:031413cf7a89 250 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
Kojto 91:031413cf7a89 251 __I uint32_t RESERVED1;
Kojto 97:433970e64889 252 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
Kojto 97:433970e64889 253 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
Kojto 91:031413cf7a89 254 __I uint32_t RESERVED2[124];
Kojto 91:031413cf7a89 255 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 256 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 257 __I uint32_t RESERVED3[63];
Kojto 97:433970e64889 258 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
Kojto 91:031413cf7a89 259 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Kojto 97:433970e64889 260 __I uint32_t RESERVED4;
Kojto 97:433970e64889 261 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
Kojto 91:031413cf7a89 262 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Kojto 97:433970e64889 263 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto 97:433970e64889 264 triggered. */
Kojto 97:433970e64889 265 __I uint32_t RESERVED5[62];
Kojto 91:031413cf7a89 266 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
Kojto 91:031413cf7a89 267 __I uint32_t RESERVED6[7];
Kojto 91:031413cf7a89 268 __IO uint32_t CTIV; /*!< Calibration timer interval. */
Kojto 91:031413cf7a89 269 __I uint32_t RESERVED7[5];
Kojto 91:031413cf7a89 270 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
Kojto 91:031413cf7a89 271 } NRF_CLOCK_Type;
Kojto 91:031413cf7a89 272
Kojto 91:031413cf7a89 273
Kojto 91:031413cf7a89 274 /* ================================================================================ */
Kojto 91:031413cf7a89 275 /* ================ MPU ================ */
Kojto 91:031413cf7a89 276 /* ================================================================================ */
Kojto 91:031413cf7a89 277
Kojto 91:031413cf7a89 278
Kojto 91:031413cf7a89 279 /**
Kojto 91:031413cf7a89 280 * @brief Memory Protection Unit. (MPU)
Kojto 91:031413cf7a89 281 */
Kojto 91:031413cf7a89 282
Kojto 91:031413cf7a89 283 typedef struct { /*!< MPU Structure */
Kojto 91:031413cf7a89 284 __I uint32_t RESERVED0[330];
Kojto 91:031413cf7a89 285 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
Kojto 91:031413cf7a89 286 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
Kojto 91:031413cf7a89 287 __I uint32_t RESERVED1[52];
Kojto 97:433970e64889 288 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 289 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 290 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
Kojto 97:433970e64889 291 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
Kojto 91:031413cf7a89 292 } NRF_MPU_Type;
Kojto 91:031413cf7a89 293
Kojto 91:031413cf7a89 294
Kojto 91:031413cf7a89 295 /* ================================================================================ */
Kojto 91:031413cf7a89 296 /* ================ AMLI ================ */
Kojto 91:031413cf7a89 297 /* ================================================================================ */
Kojto 91:031413cf7a89 298
Kojto 91:031413cf7a89 299
Kojto 91:031413cf7a89 300 /**
Kojto 91:031413cf7a89 301 * @brief AHB Multi-Layer Interface. (AMLI)
Kojto 91:031413cf7a89 302 */
Kojto 91:031413cf7a89 303
Kojto 91:031413cf7a89 304 typedef struct { /*!< AMLI Structure */
Kojto 91:031413cf7a89 305 __I uint32_t RESERVED0[896];
Kojto 91:031413cf7a89 306 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
Kojto 91:031413cf7a89 307 } NRF_AMLI_Type;
Kojto 91:031413cf7a89 308
Kojto 91:031413cf7a89 309
Kojto 91:031413cf7a89 310 /* ================================================================================ */
Kojto 91:031413cf7a89 311 /* ================ RADIO ================ */
Kojto 91:031413cf7a89 312 /* ================================================================================ */
Kojto 91:031413cf7a89 313
Kojto 91:031413cf7a89 314
Kojto 91:031413cf7a89 315 /**
Kojto 91:031413cf7a89 316 * @brief The radio. (RADIO)
Kojto 91:031413cf7a89 317 */
Kojto 91:031413cf7a89 318
Kojto 91:031413cf7a89 319 typedef struct { /*!< RADIO Structure */
Kojto 91:031413cf7a89 320 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
Kojto 91:031413cf7a89 321 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
Kojto 91:031413cf7a89 322 __O uint32_t TASKS_START; /*!< Start radio. */
Kojto 91:031413cf7a89 323 __O uint32_t TASKS_STOP; /*!< Stop radio. */
Kojto 91:031413cf7a89 324 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
Kojto 91:031413cf7a89 325 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
Kojto 91:031413cf7a89 326 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
Kojto 91:031413cf7a89 327 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
Kojto 91:031413cf7a89 328 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
Kojto 91:031413cf7a89 329 __I uint32_t RESERVED0[55];
Kojto 91:031413cf7a89 330 __IO uint32_t EVENTS_READY; /*!< Ready event. */
Kojto 91:031413cf7a89 331 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
Kojto 91:031413cf7a89 332 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
Kojto 91:031413cf7a89 333 __IO uint32_t EVENTS_END; /*!< End event. */
Kojto 91:031413cf7a89 334 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
Kojto 91:031413cf7a89 335 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
Kojto 91:031413cf7a89 336 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
Kojto 91:031413cf7a89 337 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
Kojto 91:031413cf7a89 338 sample is ready for readout at the RSSISAMPLE register. */
Kojto 91:031413cf7a89 339 __I uint32_t RESERVED1[2];
Kojto 122:f9eeca106725 340 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
Kojto 91:031413cf7a89 341 __I uint32_t RESERVED2[53];
Kojto 97:433970e64889 342 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
Kojto 91:031413cf7a89 343 __I uint32_t RESERVED3[64];
Kojto 91:031413cf7a89 344 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 345 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 346 __I uint32_t RESERVED4[61];
Kojto 91:031413cf7a89 347 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Kojto 122:f9eeca106725 348 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 349 __I uint32_t RXMATCH; /*!< Received address. */
Kojto 91:031413cf7a89 350 __I uint32_t RXCRC; /*!< Received CRC. */
Kojto 97:433970e64889 351 __I uint32_t DAI; /*!< Device address match index. */
Kojto 122:f9eeca106725 352 __I uint32_t RESERVED6[60];
Kojto 91:031413cf7a89 353 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
Kojto 91:031413cf7a89 354 __IO uint32_t FREQUENCY; /*!< Frequency. */
Kojto 91:031413cf7a89 355 __IO uint32_t TXPOWER; /*!< Output power. */
Kojto 91:031413cf7a89 356 __IO uint32_t MODE; /*!< Data rate and modulation. */
Kojto 91:031413cf7a89 357 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
Kojto 91:031413cf7a89 358 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
Kojto 91:031413cf7a89 359 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
Kojto 91:031413cf7a89 360 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
Kojto 91:031413cf7a89 361 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
Kojto 91:031413cf7a89 362 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
Kojto 91:031413cf7a89 363 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
Kojto 91:031413cf7a89 364 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
Kojto 91:031413cf7a89 365 __IO uint32_t CRCCNF; /*!< CRC configuration. */
Kojto 91:031413cf7a89 366 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
Kojto 91:031413cf7a89 367 __IO uint32_t CRCINIT; /*!< CRC initial value. */
Kojto 91:031413cf7a89 368 __IO uint32_t TEST; /*!< Test features enable register. */
Kojto 91:031413cf7a89 369 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Kojto 97:433970e64889 370 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
Kojto 122:f9eeca106725 371 __I uint32_t RESERVED7;
Kojto 91:031413cf7a89 372 __I uint32_t STATE; /*!< Current radio state. */
Kojto 91:031413cf7a89 373 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Kojto 122:f9eeca106725 374 __I uint32_t RESERVED8[2];
Kojto 91:031413cf7a89 375 __IO uint32_t BCC; /*!< Bit counter compare. */
Kojto 122:f9eeca106725 376 __I uint32_t RESERVED9[39];
Kojto 91:031413cf7a89 377 __IO uint32_t DAB[8]; /*!< Device address base segment. */
Kojto 91:031413cf7a89 378 __IO uint32_t DAP[8]; /*!< Device address prefix. */
Kojto 91:031413cf7a89 379 __IO uint32_t DACNF; /*!< Device address match configuration. */
Kojto 122:f9eeca106725 380 __I uint32_t RESERVED10[56];
Kojto 91:031413cf7a89 381 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
Kojto 91:031413cf7a89 382 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
Kojto 91:031413cf7a89 383 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
Kojto 91:031413cf7a89 384 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
Kojto 91:031413cf7a89 385 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Kojto 122:f9eeca106725 386 __I uint32_t RESERVED11[561];
Kojto 91:031413cf7a89 387 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 388 } NRF_RADIO_Type;
Kojto 91:031413cf7a89 389
Kojto 91:031413cf7a89 390
Kojto 91:031413cf7a89 391 /* ================================================================================ */
Kojto 91:031413cf7a89 392 /* ================ UART ================ */
Kojto 91:031413cf7a89 393 /* ================================================================================ */
Kojto 91:031413cf7a89 394
Kojto 91:031413cf7a89 395
Kojto 91:031413cf7a89 396 /**
Kojto 91:031413cf7a89 397 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
Kojto 91:031413cf7a89 398 */
Kojto 91:031413cf7a89 399
Kojto 91:031413cf7a89 400 typedef struct { /*!< UART Structure */
Kojto 91:031413cf7a89 401 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
Kojto 91:031413cf7a89 402 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
Kojto 91:031413cf7a89 403 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
Kojto 91:031413cf7a89 404 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
Kojto 91:031413cf7a89 405 __I uint32_t RESERVED0[3];
Kojto 91:031413cf7a89 406 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
Kojto 91:031413cf7a89 407 __I uint32_t RESERVED1[56];
Kojto 91:031413cf7a89 408 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
Kojto 91:031413cf7a89 409 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
Kojto 91:031413cf7a89 410 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
Kojto 91:031413cf7a89 411 __I uint32_t RESERVED2[4];
Kojto 91:031413cf7a89 412 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
Kojto 91:031413cf7a89 413 __I uint32_t RESERVED3;
Kojto 91:031413cf7a89 414 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
Kojto 91:031413cf7a89 415 __I uint32_t RESERVED4[7];
Kojto 91:031413cf7a89 416 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
Kojto 91:031413cf7a89 417 __I uint32_t RESERVED5[46];
Kojto 97:433970e64889 418 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
Kojto 97:433970e64889 419 __I uint32_t RESERVED6[64];
Kojto 91:031413cf7a89 420 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 421 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 422 __I uint32_t RESERVED7[93];
Kojto 91:031413cf7a89 423 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
Kojto 91:031413cf7a89 424 __I uint32_t RESERVED8[31];
Kojto 91:031413cf7a89 425 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
Kojto 91:031413cf7a89 426 __I uint32_t RESERVED9;
Kojto 91:031413cf7a89 427 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
Kojto 91:031413cf7a89 428 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
Kojto 91:031413cf7a89 429 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
Kojto 91:031413cf7a89 430 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
Kojto 91:031413cf7a89 431 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto 97:433970e64889 432 Once read the character is consumed. If read when no character
Kojto 91:031413cf7a89 433 available, the UART will stop working. */
Kojto 91:031413cf7a89 434 __O uint32_t TXD; /*!< TXD register. */
Kojto 91:031413cf7a89 435 __I uint32_t RESERVED10;
Kojto 91:031413cf7a89 436 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
Kojto 91:031413cf7a89 437 __I uint32_t RESERVED11[17];
Kojto 91:031413cf7a89 438 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
Kojto 91:031413cf7a89 439 __I uint32_t RESERVED12[675];
Kojto 91:031413cf7a89 440 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 441 } NRF_UART_Type;
Kojto 91:031413cf7a89 442
Kojto 91:031413cf7a89 443
Kojto 91:031413cf7a89 444 /* ================================================================================ */
Kojto 91:031413cf7a89 445 /* ================ SPI ================ */
Kojto 91:031413cf7a89 446 /* ================================================================================ */
Kojto 91:031413cf7a89 447
Kojto 91:031413cf7a89 448
Kojto 91:031413cf7a89 449 /**
Kojto 91:031413cf7a89 450 * @brief SPI master 0. (SPI)
Kojto 91:031413cf7a89 451 */
Kojto 91:031413cf7a89 452
Kojto 91:031413cf7a89 453 typedef struct { /*!< SPI Structure */
Kojto 91:031413cf7a89 454 __I uint32_t RESERVED0[66];
Kojto 91:031413cf7a89 455 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
Kojto 91:031413cf7a89 456 __I uint32_t RESERVED1[126];
Kojto 91:031413cf7a89 457 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 458 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 459 __I uint32_t RESERVED2[125];
Kojto 91:031413cf7a89 460 __IO uint32_t ENABLE; /*!< Enable SPI. */
Kojto 91:031413cf7a89 461 __I uint32_t RESERVED3;
Kojto 91:031413cf7a89 462 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Kojto 91:031413cf7a89 463 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Kojto 91:031413cf7a89 464 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Kojto 91:031413cf7a89 465 __I uint32_t RESERVED4;
Kojto 97:433970e64889 466 __I uint32_t RXD; /*!< RX data. */
Kojto 91:031413cf7a89 467 __IO uint32_t TXD; /*!< TX data. */
Kojto 91:031413cf7a89 468 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 469 __IO uint32_t FREQUENCY; /*!< SPI frequency */
Kojto 91:031413cf7a89 470 __I uint32_t RESERVED6[11];
Kojto 91:031413cf7a89 471 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 472 __I uint32_t RESERVED7[681];
Kojto 91:031413cf7a89 473 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 474 } NRF_SPI_Type;
Kojto 91:031413cf7a89 475
Kojto 91:031413cf7a89 476
Kojto 91:031413cf7a89 477 /* ================================================================================ */
Kojto 91:031413cf7a89 478 /* ================ TWI ================ */
Kojto 91:031413cf7a89 479 /* ================================================================================ */
Kojto 91:031413cf7a89 480
Kojto 91:031413cf7a89 481
Kojto 91:031413cf7a89 482 /**
Kojto 91:031413cf7a89 483 * @brief Two-wire interface master 0. (TWI)
Kojto 91:031413cf7a89 484 */
Kojto 91:031413cf7a89 485
Kojto 91:031413cf7a89 486 typedef struct { /*!< TWI Structure */
Kojto 91:031413cf7a89 487 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
Kojto 91:031413cf7a89 488 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 489 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
Kojto 91:031413cf7a89 490 __I uint32_t RESERVED1[2];
Kojto 91:031413cf7a89 491 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
Kojto 91:031413cf7a89 492 __I uint32_t RESERVED2;
Kojto 91:031413cf7a89 493 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
Kojto 91:031413cf7a89 494 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
Kojto 91:031413cf7a89 495 __I uint32_t RESERVED3[56];
Kojto 91:031413cf7a89 496 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
Kojto 91:031413cf7a89 497 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
Kojto 91:031413cf7a89 498 __I uint32_t RESERVED4[4];
Kojto 91:031413cf7a89 499 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
Kojto 91:031413cf7a89 500 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 501 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
Kojto 91:031413cf7a89 502 __I uint32_t RESERVED6[4];
Kojto 91:031413cf7a89 503 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Kojto 97:433970e64889 504 __I uint32_t RESERVED7[3];
Kojto 97:433970e64889 505 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
Kojto 97:433970e64889 506 __I uint32_t RESERVED8[45];
Kojto 91:031413cf7a89 507 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Kojto 97:433970e64889 508 __I uint32_t RESERVED9[64];
Kojto 91:031413cf7a89 509 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 510 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 511 __I uint32_t RESERVED10[110];
Kojto 91:031413cf7a89 512 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Kojto 97:433970e64889 513 __I uint32_t RESERVED11[14];
Kojto 91:031413cf7a89 514 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Kojto 97:433970e64889 515 __I uint32_t RESERVED12;
Kojto 91:031413cf7a89 516 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
Kojto 91:031413cf7a89 517 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Kojto 97:433970e64889 518 __I uint32_t RESERVED13[2];
Kojto 97:433970e64889 519 __I uint32_t RXD; /*!< RX data register. */
Kojto 91:031413cf7a89 520 __IO uint32_t TXD; /*!< TX data register. */
Kojto 97:433970e64889 521 __I uint32_t RESERVED14;
Kojto 91:031413cf7a89 522 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Kojto 97:433970e64889 523 __I uint32_t RESERVED15[24];
Kojto 91:031413cf7a89 524 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Kojto 97:433970e64889 525 __I uint32_t RESERVED16[668];
Kojto 91:031413cf7a89 526 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 527 } NRF_TWI_Type;
Kojto 91:031413cf7a89 528
Kojto 91:031413cf7a89 529
Kojto 91:031413cf7a89 530 /* ================================================================================ */
Kojto 91:031413cf7a89 531 /* ================ SPIS ================ */
Kojto 91:031413cf7a89 532 /* ================================================================================ */
Kojto 91:031413cf7a89 533
Kojto 91:031413cf7a89 534
Kojto 91:031413cf7a89 535 /**
Kojto 91:031413cf7a89 536 * @brief SPI slave 1. (SPIS)
Kojto 91:031413cf7a89 537 */
Kojto 91:031413cf7a89 538
Kojto 91:031413cf7a89 539 typedef struct { /*!< SPIS Structure */
Kojto 91:031413cf7a89 540 __I uint32_t RESERVED0[9];
Kojto 91:031413cf7a89 541 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
Kojto 91:031413cf7a89 542 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
Kojto 91:031413cf7a89 543 __I uint32_t RESERVED1[54];
Kojto 91:031413cf7a89 544 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
Kojto 122:f9eeca106725 545 __I uint32_t RESERVED2[2];
Kojto 122:f9eeca106725 546 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
Kojto 122:f9eeca106725 547 __I uint32_t RESERVED3[5];
Kojto 91:031413cf7a89 548 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
Kojto 122:f9eeca106725 549 __I uint32_t RESERVED4[53];
Kojto 91:031413cf7a89 550 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
Kojto 122:f9eeca106725 551 __I uint32_t RESERVED5[64];
Kojto 91:031413cf7a89 552 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 553 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 554 __I uint32_t RESERVED6[61];
Kojto 91:031413cf7a89 555 __I uint32_t SEMSTAT; /*!< Semaphore status. */
Kojto 122:f9eeca106725 556 __I uint32_t RESERVED7[15];
Kojto 91:031413cf7a89 557 __IO uint32_t STATUS; /*!< Status from last transaction. */
Kojto 122:f9eeca106725 558 __I uint32_t RESERVED8[47];
Kojto 91:031413cf7a89 559 __IO uint32_t ENABLE; /*!< Enable SPIS. */
Kojto 122:f9eeca106725 560 __I uint32_t RESERVED9;
Kojto 91:031413cf7a89 561 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
Kojto 91:031413cf7a89 562 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
Kojto 91:031413cf7a89 563 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
Kojto 91:031413cf7a89 564 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
Kojto 122:f9eeca106725 565 __I uint32_t RESERVED10[7];
Kojto 91:031413cf7a89 566 __IO uint32_t RXDPTR; /*!< RX data pointer. */
Kojto 91:031413cf7a89 567 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Kojto 97:433970e64889 568 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
Kojto 122:f9eeca106725 569 __I uint32_t RESERVED11;
Kojto 91:031413cf7a89 570 __IO uint32_t TXDPTR; /*!< TX data pointer. */
Kojto 91:031413cf7a89 571 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Kojto 97:433970e64889 572 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
Kojto 122:f9eeca106725 573 __I uint32_t RESERVED12;
Kojto 91:031413cf7a89 574 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 575 __I uint32_t RESERVED13;
Kojto 91:031413cf7a89 576 __IO uint32_t DEF; /*!< Default character. */
Kojto 122:f9eeca106725 577 __I uint32_t RESERVED14[24];
Kojto 91:031413cf7a89 578 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 579 __I uint32_t RESERVED15[654];
Kojto 91:031413cf7a89 580 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 581 } NRF_SPIS_Type;
Kojto 91:031413cf7a89 582
Kojto 91:031413cf7a89 583
Kojto 91:031413cf7a89 584 /* ================================================================================ */
Kojto 97:433970e64889 585 /* ================ SPIM ================ */
Kojto 97:433970e64889 586 /* ================================================================================ */
Kojto 97:433970e64889 587
Kojto 97:433970e64889 588
Kojto 97:433970e64889 589 /**
Kojto 97:433970e64889 590 * @brief SPI master with easyDMA 1. (SPIM)
Kojto 97:433970e64889 591 */
Kojto 97:433970e64889 592
Kojto 97:433970e64889 593 typedef struct { /*!< SPIM Structure */
Kojto 97:433970e64889 594 __I uint32_t RESERVED0[4];
Kojto 97:433970e64889 595 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
Kojto 97:433970e64889 596 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
Kojto 97:433970e64889 597 __I uint32_t RESERVED1;
Kojto 97:433970e64889 598 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
Kojto 97:433970e64889 599 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
Kojto 97:433970e64889 600 __I uint32_t RESERVED2[56];
Kojto 97:433970e64889 601 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
Kojto 97:433970e64889 602 __I uint32_t RESERVED3[2];
Kojto 97:433970e64889 603 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
Kojto 122:f9eeca106725 604 __I uint32_t RESERVED4[3];
Kojto 97:433970e64889 605 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
Kojto 122:f9eeca106725 606 __I uint32_t RESERVED5[10];
Kojto 97:433970e64889 607 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
Kojto 122:f9eeca106725 608 __I uint32_t RESERVED6[109];
Kojto 97:433970e64889 609 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 97:433970e64889 610 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 611 __I uint32_t RESERVED7[125];
Kojto 97:433970e64889 612 __IO uint32_t ENABLE; /*!< Enable SPIM. */
Kojto 122:f9eeca106725 613 __I uint32_t RESERVED8;
Kojto 97:433970e64889 614 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
Kojto 122:f9eeca106725 615 __I uint32_t RESERVED9[4];
Kojto 97:433970e64889 616 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
Kojto 122:f9eeca106725 617 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 618 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 619 __I uint32_t RESERVED11;
Kojto 97:433970e64889 620 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 621 __I uint32_t RESERVED12;
Kojto 97:433970e64889 622 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 623 __I uint32_t RESERVED13[26];
Kojto 97:433970e64889 624 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 625 __I uint32_t RESERVED14[654];
Kojto 97:433970e64889 626 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 97:433970e64889 627 } NRF_SPIM_Type;
Kojto 97:433970e64889 628
Kojto 97:433970e64889 629
Kojto 97:433970e64889 630 /* ================================================================================ */
Kojto 91:031413cf7a89 631 /* ================ GPIOTE ================ */
Kojto 91:031413cf7a89 632 /* ================================================================================ */
Kojto 91:031413cf7a89 633
Kojto 91:031413cf7a89 634
Kojto 91:031413cf7a89 635 /**
Kojto 91:031413cf7a89 636 * @brief GPIO tasks and events. (GPIOTE)
Kojto 91:031413cf7a89 637 */
Kojto 91:031413cf7a89 638
Kojto 91:031413cf7a89 639 typedef struct { /*!< GPIOTE Structure */
Kojto 91:031413cf7a89 640 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
Kojto 91:031413cf7a89 641 __I uint32_t RESERVED0[60];
Kojto 91:031413cf7a89 642 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
Kojto 91:031413cf7a89 643 __I uint32_t RESERVED1[27];
Kojto 91:031413cf7a89 644 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
Kojto 91:031413cf7a89 645 __I uint32_t RESERVED2[97];
Kojto 91:031413cf7a89 646 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 647 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 648 __I uint32_t RESERVED3[129];
Kojto 91:031413cf7a89 649 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
Kojto 91:031413cf7a89 650 __I uint32_t RESERVED4[695];
Kojto 91:031413cf7a89 651 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 652 } NRF_GPIOTE_Type;
Kojto 91:031413cf7a89 653
Kojto 91:031413cf7a89 654
Kojto 91:031413cf7a89 655 /* ================================================================================ */
Kojto 91:031413cf7a89 656 /* ================ ADC ================ */
Kojto 91:031413cf7a89 657 /* ================================================================================ */
Kojto 91:031413cf7a89 658
Kojto 91:031413cf7a89 659
Kojto 91:031413cf7a89 660 /**
Kojto 91:031413cf7a89 661 * @brief Analog to digital converter. (ADC)
Kojto 91:031413cf7a89 662 */
Kojto 91:031413cf7a89 663
Kojto 91:031413cf7a89 664 typedef struct { /*!< ADC Structure */
Kojto 91:031413cf7a89 665 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
Kojto 91:031413cf7a89 666 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
Kojto 91:031413cf7a89 667 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 668 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
Kojto 91:031413cf7a89 669 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 670 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 671 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 672 __I uint32_t RESERVED2[61];
Kojto 91:031413cf7a89 673 __I uint32_t BUSY; /*!< ADC busy register. */
Kojto 91:031413cf7a89 674 __I uint32_t RESERVED3[63];
Kojto 91:031413cf7a89 675 __IO uint32_t ENABLE; /*!< ADC enable. */
Kojto 91:031413cf7a89 676 __IO uint32_t CONFIG; /*!< ADC configuration register. */
Kojto 91:031413cf7a89 677 __I uint32_t RESULT; /*!< Result of ADC conversion. */
Kojto 91:031413cf7a89 678 __I uint32_t RESERVED4[700];
Kojto 91:031413cf7a89 679 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 680 } NRF_ADC_Type;
Kojto 91:031413cf7a89 681
Kojto 91:031413cf7a89 682
Kojto 91:031413cf7a89 683 /* ================================================================================ */
Kojto 91:031413cf7a89 684 /* ================ TIMER ================ */
Kojto 91:031413cf7a89 685 /* ================================================================================ */
Kojto 91:031413cf7a89 686
Kojto 91:031413cf7a89 687
Kojto 91:031413cf7a89 688 /**
Kojto 91:031413cf7a89 689 * @brief Timer 0. (TIMER)
Kojto 91:031413cf7a89 690 */
Kojto 91:031413cf7a89 691
Kojto 91:031413cf7a89 692 typedef struct { /*!< TIMER Structure */
Kojto 91:031413cf7a89 693 __O uint32_t TASKS_START; /*!< Start Timer. */
Kojto 91:031413cf7a89 694 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
Kojto 91:031413cf7a89 695 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
Kojto 91:031413cf7a89 696 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Kojto 97:433970e64889 697 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
Kojto 97:433970e64889 698 __I uint32_t RESERVED0[11];
Kojto 91:031413cf7a89 699 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
Kojto 91:031413cf7a89 700 __I uint32_t RESERVED1[60];
Kojto 91:031413cf7a89 701 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Kojto 91:031413cf7a89 702 __I uint32_t RESERVED2[44];
Kojto 91:031413cf7a89 703 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
Kojto 91:031413cf7a89 704 __I uint32_t RESERVED3[64];
Kojto 91:031413cf7a89 705 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 706 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 707 __I uint32_t RESERVED4[126];
Kojto 91:031413cf7a89 708 __IO uint32_t MODE; /*!< Timer Mode selection. */
Kojto 91:031413cf7a89 709 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
Kojto 91:031413cf7a89 710 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 711 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
Kojto 91:031413cf7a89 712 clock frequency is divided by 2^SCALE. */
Kojto 91:031413cf7a89 713 __I uint32_t RESERVED6[11];
Kojto 91:031413cf7a89 714 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Kojto 91:031413cf7a89 715 __I uint32_t RESERVED7[683];
Kojto 91:031413cf7a89 716 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 717 } NRF_TIMER_Type;
Kojto 91:031413cf7a89 718
Kojto 91:031413cf7a89 719
Kojto 91:031413cf7a89 720 /* ================================================================================ */
Kojto 91:031413cf7a89 721 /* ================ RTC ================ */
Kojto 91:031413cf7a89 722 /* ================================================================================ */
Kojto 91:031413cf7a89 723
Kojto 91:031413cf7a89 724
Kojto 91:031413cf7a89 725 /**
Kojto 91:031413cf7a89 726 * @brief Real time counter 0. (RTC)
Kojto 91:031413cf7a89 727 */
Kojto 91:031413cf7a89 728
Kojto 91:031413cf7a89 729 typedef struct { /*!< RTC Structure */
Kojto 91:031413cf7a89 730 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
Kojto 91:031413cf7a89 731 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
Kojto 91:031413cf7a89 732 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
Kojto 91:031413cf7a89 733 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
Kojto 91:031413cf7a89 734 __I uint32_t RESERVED0[60];
Kojto 91:031413cf7a89 735 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
Kojto 91:031413cf7a89 736 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
Kojto 91:031413cf7a89 737 __I uint32_t RESERVED1[14];
Kojto 91:031413cf7a89 738 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
Kojto 91:031413cf7a89 739 __I uint32_t RESERVED2[109];
Kojto 91:031413cf7a89 740 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 741 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 742 __I uint32_t RESERVED3[13];
Kojto 91:031413cf7a89 743 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
Kojto 91:031413cf7a89 744 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
Kojto 91:031413cf7a89 745 the value of EVTEN. */
Kojto 91:031413cf7a89 746 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
Kojto 91:031413cf7a89 747 gives the value of EVTEN. */
Kojto 91:031413cf7a89 748 __I uint32_t RESERVED4[110];
Kojto 97:433970e64889 749 __I uint32_t COUNTER; /*!< Current COUNTER value. */
Kojto 91:031413cf7a89 750 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
Kojto 91:031413cf7a89 751 Must be written when RTC is STOPed. */
Kojto 91:031413cf7a89 752 __I uint32_t RESERVED5[13];
Kojto 91:031413cf7a89 753 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
Kojto 91:031413cf7a89 754 __I uint32_t RESERVED6[683];
Kojto 91:031413cf7a89 755 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 756 } NRF_RTC_Type;
Kojto 91:031413cf7a89 757
Kojto 91:031413cf7a89 758
Kojto 91:031413cf7a89 759 /* ================================================================================ */
Kojto 91:031413cf7a89 760 /* ================ TEMP ================ */
Kojto 91:031413cf7a89 761 /* ================================================================================ */
Kojto 91:031413cf7a89 762
Kojto 91:031413cf7a89 763
Kojto 91:031413cf7a89 764 /**
Kojto 91:031413cf7a89 765 * @brief Temperature Sensor. (TEMP)
Kojto 91:031413cf7a89 766 */
Kojto 91:031413cf7a89 767
Kojto 91:031413cf7a89 768 typedef struct { /*!< TEMP Structure */
Kojto 91:031413cf7a89 769 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
Kojto 91:031413cf7a89 770 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
Kojto 91:031413cf7a89 771 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 772 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
Kojto 91:031413cf7a89 773 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 774 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 775 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 776 __I uint32_t RESERVED2[127];
Kojto 91:031413cf7a89 777 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
Kojto 91:031413cf7a89 778 __I uint32_t RESERVED3[700];
Kojto 91:031413cf7a89 779 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 780 } NRF_TEMP_Type;
Kojto 91:031413cf7a89 781
Kojto 91:031413cf7a89 782
Kojto 91:031413cf7a89 783 /* ================================================================================ */
Kojto 91:031413cf7a89 784 /* ================ RNG ================ */
Kojto 91:031413cf7a89 785 /* ================================================================================ */
Kojto 91:031413cf7a89 786
Kojto 91:031413cf7a89 787
Kojto 91:031413cf7a89 788 /**
Kojto 91:031413cf7a89 789 * @brief Random Number Generator. (RNG)
Kojto 91:031413cf7a89 790 */
Kojto 91:031413cf7a89 791
Kojto 91:031413cf7a89 792 typedef struct { /*!< RNG Structure */
Kojto 91:031413cf7a89 793 __O uint32_t TASKS_START; /*!< Start the random number generator. */
Kojto 91:031413cf7a89 794 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
Kojto 91:031413cf7a89 795 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 796 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
Kojto 91:031413cf7a89 797 __I uint32_t RESERVED1[63];
Kojto 97:433970e64889 798 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
Kojto 91:031413cf7a89 799 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 800 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
Kojto 91:031413cf7a89 801 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
Kojto 91:031413cf7a89 802 __I uint32_t RESERVED3[126];
Kojto 91:031413cf7a89 803 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 804 __I uint32_t VALUE; /*!< RNG random number. */
Kojto 91:031413cf7a89 805 __I uint32_t RESERVED4[700];
Kojto 91:031413cf7a89 806 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 807 } NRF_RNG_Type;
Kojto 91:031413cf7a89 808
Kojto 91:031413cf7a89 809
Kojto 91:031413cf7a89 810 /* ================================================================================ */
Kojto 91:031413cf7a89 811 /* ================ ECB ================ */
Kojto 91:031413cf7a89 812 /* ================================================================================ */
Kojto 91:031413cf7a89 813
Kojto 91:031413cf7a89 814
Kojto 91:031413cf7a89 815 /**
Kojto 91:031413cf7a89 816 * @brief AES ECB Mode Encryption. (ECB)
Kojto 91:031413cf7a89 817 */
Kojto 91:031413cf7a89 818
Kojto 91:031413cf7a89 819 typedef struct { /*!< ECB Structure */
Kojto 91:031413cf7a89 820 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
Kojto 91:031413cf7a89 821 will not initiate a new encryption and the ERRORECB event will
Kojto 91:031413cf7a89 822 be triggered. */
Kojto 91:031413cf7a89 823 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
Kojto 91:031413cf7a89 824 this will will trigger the ERRORECB event. */
Kojto 91:031413cf7a89 825 __I uint32_t RESERVED0[62];
Kojto 91:031413cf7a89 826 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
Kojto 91:031413cf7a89 827 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
Kojto 91:031413cf7a89 828 error. */
Kojto 91:031413cf7a89 829 __I uint32_t RESERVED1[127];
Kojto 91:031413cf7a89 830 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 831 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 832 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 833 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
Kojto 91:031413cf7a89 834 __I uint32_t RESERVED3[701];
Kojto 91:031413cf7a89 835 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 836 } NRF_ECB_Type;
Kojto 91:031413cf7a89 837
Kojto 91:031413cf7a89 838
Kojto 91:031413cf7a89 839 /* ================================================================================ */
Kojto 91:031413cf7a89 840 /* ================ AAR ================ */
Kojto 91:031413cf7a89 841 /* ================================================================================ */
Kojto 91:031413cf7a89 842
Kojto 91:031413cf7a89 843
Kojto 91:031413cf7a89 844 /**
Kojto 91:031413cf7a89 845 * @brief Accelerated Address Resolver. (AAR)
Kojto 91:031413cf7a89 846 */
Kojto 91:031413cf7a89 847
Kojto 91:031413cf7a89 848 typedef struct { /*!< AAR Structure */
Kojto 91:031413cf7a89 849 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Kojto 91:031413cf7a89 850 data structure. */
Kojto 91:031413cf7a89 851 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 852 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
Kojto 91:031413cf7a89 853 __I uint32_t RESERVED1[61];
Kojto 91:031413cf7a89 854 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
Kojto 91:031413cf7a89 855 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
Kojto 91:031413cf7a89 856 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
Kojto 91:031413cf7a89 857 __I uint32_t RESERVED2[126];
Kojto 91:031413cf7a89 858 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 859 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 860 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 861 __I uint32_t STATUS; /*!< Resolution status. */
Kojto 91:031413cf7a89 862 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 863 __IO uint32_t ENABLE; /*!< Enable AAR. */
Kojto 91:031413cf7a89 864 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
Kojto 91:031413cf7a89 865 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
Kojto 91:031413cf7a89 866 __I uint32_t RESERVED5;
Kojto 91:031413cf7a89 867 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Kojto 123:b0220dba8be7 868 __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
Kojto 123:b0220dba8be7 869 resolution. A minimum of 3 bytes must be reserved. */
Kojto 91:031413cf7a89 870 __I uint32_t RESERVED6[697];
Kojto 91:031413cf7a89 871 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 872 } NRF_AAR_Type;
Kojto 91:031413cf7a89 873
Kojto 91:031413cf7a89 874
Kojto 91:031413cf7a89 875 /* ================================================================================ */
Kojto 91:031413cf7a89 876 /* ================ CCM ================ */
Kojto 91:031413cf7a89 877 /* ================================================================================ */
Kojto 91:031413cf7a89 878
Kojto 91:031413cf7a89 879
Kojto 91:031413cf7a89 880 /**
Kojto 91:031413cf7a89 881 * @brief AES CCM Mode Encryption. (CCM)
Kojto 91:031413cf7a89 882 */
Kojto 91:031413cf7a89 883
Kojto 91:031413cf7a89 884 typedef struct { /*!< CCM Structure */
Kojto 91:031413cf7a89 885 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Kojto 91:031413cf7a89 886 itself when completed. */
Kojto 91:031413cf7a89 887 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
Kojto 91:031413cf7a89 888 completed. */
Kojto 91:031413cf7a89 889 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
Kojto 91:031413cf7a89 890 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 891 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
Kojto 91:031413cf7a89 892 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
Kojto 91:031413cf7a89 893 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
Kojto 91:031413cf7a89 894 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 895 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
Kojto 91:031413cf7a89 896 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 897 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 898 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 899 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 900 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
Kojto 91:031413cf7a89 901 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 902 __IO uint32_t ENABLE; /*!< CCM enable. */
Kojto 91:031413cf7a89 903 __IO uint32_t MODE; /*!< Operation mode. */
Kojto 97:433970e64889 904 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
Kojto 97:433970e64889 905 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
Kojto 97:433970e64889 906 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
Kojto 123:b0220dba8be7 907 __IO uint32_t SCRATCHPTR; /*!< Pointer to a scratch data area used for temporary storage during
Kojto 123:b0220dba8be7 908 resolution. A minimum of 43 bytes must be reserved. */
Kojto 91:031413cf7a89 909 __I uint32_t RESERVED5[697];
Kojto 91:031413cf7a89 910 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 911 } NRF_CCM_Type;
Kojto 91:031413cf7a89 912
Kojto 91:031413cf7a89 913
Kojto 91:031413cf7a89 914 /* ================================================================================ */
Kojto 91:031413cf7a89 915 /* ================ WDT ================ */
Kojto 91:031413cf7a89 916 /* ================================================================================ */
Kojto 91:031413cf7a89 917
Kojto 91:031413cf7a89 918
Kojto 91:031413cf7a89 919 /**
Kojto 91:031413cf7a89 920 * @brief Watchdog Timer. (WDT)
Kojto 91:031413cf7a89 921 */
Kojto 91:031413cf7a89 922
Kojto 91:031413cf7a89 923 typedef struct { /*!< WDT Structure */
Kojto 91:031413cf7a89 924 __O uint32_t TASKS_START; /*!< Start the watchdog. */
Kojto 91:031413cf7a89 925 __I uint32_t RESERVED0[63];
Kojto 91:031413cf7a89 926 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
Kojto 91:031413cf7a89 927 __I uint32_t RESERVED1[128];
Kojto 91:031413cf7a89 928 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 929 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 930 __I uint32_t RESERVED2[61];
Kojto 91:031413cf7a89 931 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
Kojto 91:031413cf7a89 932 __I uint32_t REQSTATUS; /*!< Request status. */
Kojto 91:031413cf7a89 933 __I uint32_t RESERVED3[63];
Kojto 91:031413cf7a89 934 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
Kojto 91:031413cf7a89 935 __IO uint32_t RREN; /*!< Reload request enable. */
Kojto 91:031413cf7a89 936 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 91:031413cf7a89 937 __I uint32_t RESERVED4[60];
Kojto 91:031413cf7a89 938 __O uint32_t RR[8]; /*!< Reload requests registers. */
Kojto 91:031413cf7a89 939 __I uint32_t RESERVED5[631];
Kojto 91:031413cf7a89 940 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 941 } NRF_WDT_Type;
Kojto 91:031413cf7a89 942
Kojto 91:031413cf7a89 943
Kojto 91:031413cf7a89 944 /* ================================================================================ */
Kojto 91:031413cf7a89 945 /* ================ QDEC ================ */
Kojto 91:031413cf7a89 946 /* ================================================================================ */
Kojto 91:031413cf7a89 947
Kojto 91:031413cf7a89 948
Kojto 91:031413cf7a89 949 /**
Kojto 91:031413cf7a89 950 * @brief Rotary decoder. (QDEC)
Kojto 91:031413cf7a89 951 */
Kojto 91:031413cf7a89 952
Kojto 91:031413cf7a89 953 typedef struct { /*!< QDEC Structure */
Kojto 91:031413cf7a89 954 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
Kojto 91:031413cf7a89 955 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
Kojto 91:031413cf7a89 956 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
Kojto 91:031413cf7a89 957 and clears the ACC registers. */
Kojto 91:031413cf7a89 958 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 959 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
Kojto 91:031413cf7a89 960 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
Kojto 91:031413cf7a89 961 ACC register different than zero. */
Kojto 91:031413cf7a89 962 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
Kojto 91:031413cf7a89 963 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 964 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
Kojto 91:031413cf7a89 965 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 966 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 967 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 968 __I uint32_t RESERVED3[125];
Kojto 91:031413cf7a89 969 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
Kojto 91:031413cf7a89 970 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
Kojto 91:031413cf7a89 971 __IO uint32_t SAMPLEPER; /*!< Sample period. */
Kojto 91:031413cf7a89 972 __I int32_t SAMPLE; /*!< Motion sample value. */
Kojto 91:031413cf7a89 973 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
Kojto 91:031413cf7a89 974 __I int32_t ACC; /*!< Accumulated valid transitions register. */
Kojto 91:031413cf7a89 975 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
Kojto 91:031413cf7a89 976 task. */
Kojto 91:031413cf7a89 977 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
Kojto 91:031413cf7a89 978 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
Kojto 91:031413cf7a89 979 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
Kojto 91:031413cf7a89 980 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
Kojto 91:031413cf7a89 981 __I uint32_t RESERVED4[5];
Kojto 91:031413cf7a89 982 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
Kojto 91:031413cf7a89 983 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
Kojto 91:031413cf7a89 984 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
Kojto 91:031413cf7a89 985 task. */
Kojto 91:031413cf7a89 986 __I uint32_t RESERVED5[684];
Kojto 91:031413cf7a89 987 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 988 } NRF_QDEC_Type;
Kojto 91:031413cf7a89 989
Kojto 91:031413cf7a89 990
Kojto 91:031413cf7a89 991 /* ================================================================================ */
Kojto 91:031413cf7a89 992 /* ================ LPCOMP ================ */
Kojto 91:031413cf7a89 993 /* ================================================================================ */
Kojto 91:031413cf7a89 994
Kojto 91:031413cf7a89 995
Kojto 91:031413cf7a89 996 /**
Kojto 97:433970e64889 997 * @brief Low power comparator. (LPCOMP)
Kojto 91:031413cf7a89 998 */
Kojto 91:031413cf7a89 999
Kojto 91:031413cf7a89 1000 typedef struct { /*!< LPCOMP Structure */
Kojto 91:031413cf7a89 1001 __O uint32_t TASKS_START; /*!< Start the comparator. */
Kojto 91:031413cf7a89 1002 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
Kojto 91:031413cf7a89 1003 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
Kojto 91:031413cf7a89 1004 __I uint32_t RESERVED0[61];
Kojto 91:031413cf7a89 1005 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
Kojto 91:031413cf7a89 1006 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
Kojto 91:031413cf7a89 1007 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
Kojto 91:031413cf7a89 1008 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
Kojto 91:031413cf7a89 1009 __I uint32_t RESERVED1[60];
Kojto 97:433970e64889 1010 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
Kojto 91:031413cf7a89 1011 __I uint32_t RESERVED2[64];
Kojto 91:031413cf7a89 1012 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 91:031413cf7a89 1013 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 91:031413cf7a89 1014 __I uint32_t RESERVED3[61];
Kojto 91:031413cf7a89 1015 __I uint32_t RESULT; /*!< Result of last compare. */
Kojto 91:031413cf7a89 1016 __I uint32_t RESERVED4[63];
Kojto 91:031413cf7a89 1017 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
Kojto 91:031413cf7a89 1018 __IO uint32_t PSEL; /*!< Input pin select. */
Kojto 91:031413cf7a89 1019 __IO uint32_t REFSEL; /*!< Reference select. */
Kojto 91:031413cf7a89 1020 __IO uint32_t EXTREFSEL; /*!< External reference select. */
Kojto 91:031413cf7a89 1021 __I uint32_t RESERVED5[4];
Kojto 91:031413cf7a89 1022 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
Kojto 91:031413cf7a89 1023 __I uint32_t RESERVED6[694];
Kojto 91:031413cf7a89 1024 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 91:031413cf7a89 1025 } NRF_LPCOMP_Type;
Kojto 91:031413cf7a89 1026
Kojto 91:031413cf7a89 1027
Kojto 91:031413cf7a89 1028 /* ================================================================================ */
Kojto 91:031413cf7a89 1029 /* ================ SWI ================ */
Kojto 91:031413cf7a89 1030 /* ================================================================================ */
Kojto 91:031413cf7a89 1031
Kojto 91:031413cf7a89 1032
Kojto 91:031413cf7a89 1033 /**
Kojto 91:031413cf7a89 1034 * @brief SW Interrupts. (SWI)
Kojto 91:031413cf7a89 1035 */
Kojto 91:031413cf7a89 1036
Kojto 91:031413cf7a89 1037 typedef struct { /*!< SWI Structure */
Kojto 91:031413cf7a89 1038 __I uint32_t UNUSED; /*!< Unused. */
Kojto 91:031413cf7a89 1039 } NRF_SWI_Type;
Kojto 91:031413cf7a89 1040
Kojto 91:031413cf7a89 1041
Kojto 91:031413cf7a89 1042 /* ================================================================================ */
Kojto 91:031413cf7a89 1043 /* ================ NVMC ================ */
Kojto 91:031413cf7a89 1044 /* ================================================================================ */
Kojto 91:031413cf7a89 1045
Kojto 91:031413cf7a89 1046
Kojto 91:031413cf7a89 1047 /**
Kojto 91:031413cf7a89 1048 * @brief Non Volatile Memory Controller. (NVMC)
Kojto 91:031413cf7a89 1049 */
Kojto 91:031413cf7a89 1050
Kojto 91:031413cf7a89 1051 typedef struct { /*!< NVMC Structure */
Kojto 91:031413cf7a89 1052 __I uint32_t RESERVED0[256];
Kojto 91:031413cf7a89 1053 __I uint32_t READY; /*!< Ready flag. */
Kojto 91:031413cf7a89 1054 __I uint32_t RESERVED1[64];
Kojto 91:031413cf7a89 1055 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 123:b0220dba8be7 1056
Kojto 122:f9eeca106725 1057 union {
Kojto 122:f9eeca106725 1058 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1059 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1060 };
Kojto 91:031413cf7a89 1061 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
Kojto 122:f9eeca106725 1062 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
Kojto 91:031413cf7a89 1063 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
Kojto 91:031413cf7a89 1064 } NRF_NVMC_Type;
Kojto 91:031413cf7a89 1065
Kojto 91:031413cf7a89 1066
Kojto 91:031413cf7a89 1067 /* ================================================================================ */
Kojto 91:031413cf7a89 1068 /* ================ PPI ================ */
Kojto 91:031413cf7a89 1069 /* ================================================================================ */
Kojto 91:031413cf7a89 1070
Kojto 91:031413cf7a89 1071
Kojto 91:031413cf7a89 1072 /**
Kojto 91:031413cf7a89 1073 * @brief PPI controller. (PPI)
Kojto 91:031413cf7a89 1074 */
Kojto 91:031413cf7a89 1075
Kojto 91:031413cf7a89 1076 typedef struct { /*!< PPI Structure */
Kojto 91:031413cf7a89 1077 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
Kojto 91:031413cf7a89 1078 __I uint32_t RESERVED0[312];
Kojto 91:031413cf7a89 1079 __IO uint32_t CHEN; /*!< Channel enable. */
Kojto 91:031413cf7a89 1080 __IO uint32_t CHENSET; /*!< Channel enable set. */
Kojto 91:031413cf7a89 1081 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
Kojto 91:031413cf7a89 1082 __I uint32_t RESERVED1;
Kojto 91:031413cf7a89 1083 PPI_CH_Type CH[16]; /*!< PPI Channel. */
Kojto 91:031413cf7a89 1084 __I uint32_t RESERVED2[156];
Kojto 91:031413cf7a89 1085 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
Kojto 91:031413cf7a89 1086 } NRF_PPI_Type;
Kojto 91:031413cf7a89 1087
Kojto 91:031413cf7a89 1088
Kojto 91:031413cf7a89 1089 /* ================================================================================ */
Kojto 91:031413cf7a89 1090 /* ================ FICR ================ */
Kojto 91:031413cf7a89 1091 /* ================================================================================ */
Kojto 91:031413cf7a89 1092
Kojto 91:031413cf7a89 1093
Kojto 91:031413cf7a89 1094 /**
Kojto 91:031413cf7a89 1095 * @brief Factory Information Configuration. (FICR)
Kojto 91:031413cf7a89 1096 */
Kojto 91:031413cf7a89 1097
Kojto 91:031413cf7a89 1098 typedef struct { /*!< FICR Structure */
Kojto 91:031413cf7a89 1099 __I uint32_t RESERVED0[4];
Kojto 91:031413cf7a89 1100 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
Kojto 91:031413cf7a89 1101 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
Kojto 91:031413cf7a89 1102 __I uint32_t RESERVED1[4];
Kojto 91:031413cf7a89 1103 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
Kojto 91:031413cf7a89 1104 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
Kojto 91:031413cf7a89 1105 __I uint32_t RESERVED2;
Kojto 91:031413cf7a89 1106 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Kojto 123:b0220dba8be7 1107
Kojto 97:433970e64889 1108 union {
Kojto 97:433970e64889 1109 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto 97:433970e64889 1110 kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto 97:433970e64889 1111 instead. */
Kojto 97:433970e64889 1112 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
Kojto 97:433970e64889 1113 };
Kojto 91:031413cf7a89 1114 __I uint32_t RESERVED3[5];
Kojto 91:031413cf7a89 1115 __I uint32_t CONFIGID; /*!< Configuration identifier. */
Kojto 91:031413cf7a89 1116 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
Kojto 91:031413cf7a89 1117 __I uint32_t RESERVED4[6];
Kojto 91:031413cf7a89 1118 __I uint32_t ER[4]; /*!< Encryption root. */
Kojto 91:031413cf7a89 1119 __I uint32_t IR[4]; /*!< Identity root. */
Kojto 91:031413cf7a89 1120 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
Kojto 91:031413cf7a89 1121 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
Kojto 91:031413cf7a89 1122 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Kojto 97:433970e64889 1123 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto 97:433970e64889 1124 mode. */
Kojto 97:433970e64889 1125 __I uint32_t RESERVED5[10];
Kojto 91:031413cf7a89 1126 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
Kojto 91:031413cf7a89 1127 mode. */
Kojto 91:031413cf7a89 1128 } NRF_FICR_Type;
Kojto 91:031413cf7a89 1129
Kojto 91:031413cf7a89 1130
Kojto 91:031413cf7a89 1131 /* ================================================================================ */
Kojto 91:031413cf7a89 1132 /* ================ UICR ================ */
Kojto 91:031413cf7a89 1133 /* ================================================================================ */
Kojto 91:031413cf7a89 1134
Kojto 91:031413cf7a89 1135
Kojto 91:031413cf7a89 1136 /**
Kojto 91:031413cf7a89 1137 * @brief User Information Configuration. (UICR)
Kojto 91:031413cf7a89 1138 */
Kojto 91:031413cf7a89 1139
Kojto 91:031413cf7a89 1140 typedef struct { /*!< UICR Structure */
Kojto 91:031413cf7a89 1141 __IO uint32_t CLENR0; /*!< Length of code region 0. */
Kojto 91:031413cf7a89 1142 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
Kojto 91:031413cf7a89 1143 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
Kojto 91:031413cf7a89 1144 __I uint32_t RESERVED0;
Kojto 91:031413cf7a89 1145 __I uint32_t FWID; /*!< Firmware ID. */
Kojto 123:b0220dba8be7 1146
Kojto 122:f9eeca106725 1147 union {
Kojto 122:f9eeca106725 1148 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
Kojto 122:f9eeca106725 1149 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
Kojto 122:f9eeca106725 1150 };
Kojto 122:f9eeca106725 1151 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
Kojto 122:f9eeca106725 1152 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
Kojto 91:031413cf7a89 1153 } NRF_UICR_Type;
Kojto 91:031413cf7a89 1154
Kojto 91:031413cf7a89 1155
Kojto 91:031413cf7a89 1156 /* ================================================================================ */
Kojto 91:031413cf7a89 1157 /* ================ GPIO ================ */
Kojto 91:031413cf7a89 1158 /* ================================================================================ */
Kojto 91:031413cf7a89 1159
Kojto 91:031413cf7a89 1160
Kojto 91:031413cf7a89 1161 /**
Kojto 91:031413cf7a89 1162 * @brief General purpose input and output. (GPIO)
Kojto 91:031413cf7a89 1163 */
Kojto 91:031413cf7a89 1164
Kojto 91:031413cf7a89 1165 typedef struct { /*!< GPIO Structure */
Kojto 91:031413cf7a89 1166 __I uint32_t RESERVED0[321];
Kojto 91:031413cf7a89 1167 __IO uint32_t OUT; /*!< Write GPIO port. */
Kojto 91:031413cf7a89 1168 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
Kojto 91:031413cf7a89 1169 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
Kojto 91:031413cf7a89 1170 __I uint32_t IN; /*!< Read GPIO port. */
Kojto 91:031413cf7a89 1171 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
Kojto 91:031413cf7a89 1172 __IO uint32_t DIRSET; /*!< DIR set register. */
Kojto 91:031413cf7a89 1173 __IO uint32_t DIRCLR; /*!< DIR clear register. */
Kojto 91:031413cf7a89 1174 __I uint32_t RESERVED1[120];
Kojto 91:031413cf7a89 1175 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
Kojto 91:031413cf7a89 1176 } NRF_GPIO_Type;
Kojto 91:031413cf7a89 1177
Kojto 91:031413cf7a89 1178
Kojto 91:031413cf7a89 1179 /* -------------------- End of section using anonymous unions ------------------- */
Kojto 91:031413cf7a89 1180 #if defined(__CC_ARM)
Kojto 91:031413cf7a89 1181 #pragma pop
Kojto 91:031413cf7a89 1182 #elif defined(__ICCARM__)
Kojto 91:031413cf7a89 1183 /* leave anonymous unions enabled */
Kojto 91:031413cf7a89 1184 #elif defined(__GNUC__)
Kojto 91:031413cf7a89 1185 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 1186 #elif defined(__TMS470__)
Kojto 91:031413cf7a89 1187 /* anonymous unions are enabled by default */
Kojto 91:031413cf7a89 1188 #elif defined(__TASKING__)
Kojto 91:031413cf7a89 1189 #pragma warning restore
Kojto 91:031413cf7a89 1190 #else
Kojto 91:031413cf7a89 1191 #warning Not supported compiler type
Kojto 91:031413cf7a89 1192 #endif
Kojto 91:031413cf7a89 1193
Kojto 91:031413cf7a89 1194
Kojto 91:031413cf7a89 1195
Kojto 91:031413cf7a89 1196
Kojto 91:031413cf7a89 1197 /* ================================================================================ */
Kojto 91:031413cf7a89 1198 /* ================ Peripheral memory map ================ */
Kojto 91:031413cf7a89 1199 /* ================================================================================ */
Kojto 91:031413cf7a89 1200
Kojto 91:031413cf7a89 1201 #define NRF_POWER_BASE 0x40000000UL
Kojto 91:031413cf7a89 1202 #define NRF_CLOCK_BASE 0x40000000UL
Kojto 91:031413cf7a89 1203 #define NRF_MPU_BASE 0x40000000UL
Kojto 91:031413cf7a89 1204 #define NRF_AMLI_BASE 0x40000000UL
Kojto 91:031413cf7a89 1205 #define NRF_RADIO_BASE 0x40001000UL
Kojto 91:031413cf7a89 1206 #define NRF_UART0_BASE 0x40002000UL
Kojto 91:031413cf7a89 1207 #define NRF_SPI0_BASE 0x40003000UL
Kojto 91:031413cf7a89 1208 #define NRF_TWI0_BASE 0x40003000UL
Kojto 91:031413cf7a89 1209 #define NRF_SPI1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1210 #define NRF_TWI1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1211 #define NRF_SPIS1_BASE 0x40004000UL
Kojto 97:433970e64889 1212 #define NRF_SPIM1_BASE 0x40004000UL
Kojto 91:031413cf7a89 1213 #define NRF_GPIOTE_BASE 0x40006000UL
Kojto 91:031413cf7a89 1214 #define NRF_ADC_BASE 0x40007000UL
Kojto 91:031413cf7a89 1215 #define NRF_TIMER0_BASE 0x40008000UL
Kojto 91:031413cf7a89 1216 #define NRF_TIMER1_BASE 0x40009000UL
Kojto 91:031413cf7a89 1217 #define NRF_TIMER2_BASE 0x4000A000UL
Kojto 91:031413cf7a89 1218 #define NRF_RTC0_BASE 0x4000B000UL
Kojto 91:031413cf7a89 1219 #define NRF_TEMP_BASE 0x4000C000UL
Kojto 91:031413cf7a89 1220 #define NRF_RNG_BASE 0x4000D000UL
Kojto 91:031413cf7a89 1221 #define NRF_ECB_BASE 0x4000E000UL
Kojto 91:031413cf7a89 1222 #define NRF_AAR_BASE 0x4000F000UL
Kojto 91:031413cf7a89 1223 #define NRF_CCM_BASE 0x4000F000UL
Kojto 91:031413cf7a89 1224 #define NRF_WDT_BASE 0x40010000UL
Kojto 91:031413cf7a89 1225 #define NRF_RTC1_BASE 0x40011000UL
Kojto 91:031413cf7a89 1226 #define NRF_QDEC_BASE 0x40012000UL
Kojto 91:031413cf7a89 1227 #define NRF_LPCOMP_BASE 0x40013000UL
Kojto 91:031413cf7a89 1228 #define NRF_SWI_BASE 0x40014000UL
Kojto 91:031413cf7a89 1229 #define NRF_NVMC_BASE 0x4001E000UL
Kojto 91:031413cf7a89 1230 #define NRF_PPI_BASE 0x4001F000UL
Kojto 91:031413cf7a89 1231 #define NRF_FICR_BASE 0x10000000UL
Kojto 91:031413cf7a89 1232 #define NRF_UICR_BASE 0x10001000UL
Kojto 91:031413cf7a89 1233 #define NRF_GPIO_BASE 0x50000000UL
Kojto 91:031413cf7a89 1234
Kojto 91:031413cf7a89 1235
Kojto 91:031413cf7a89 1236 /* ================================================================================ */
Kojto 91:031413cf7a89 1237 /* ================ Peripheral declaration ================ */
Kojto 91:031413cf7a89 1238 /* ================================================================================ */
Kojto 91:031413cf7a89 1239
Kojto 91:031413cf7a89 1240 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Kojto 91:031413cf7a89 1241 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Kojto 91:031413cf7a89 1242 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
Kojto 91:031413cf7a89 1243 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Kojto 91:031413cf7a89 1244 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Kojto 91:031413cf7a89 1245 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Kojto 91:031413cf7a89 1246 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Kojto 91:031413cf7a89 1247 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Kojto 91:031413cf7a89 1248 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Kojto 91:031413cf7a89 1249 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Kojto 91:031413cf7a89 1250 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto 97:433970e64889 1251 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
Kojto 91:031413cf7a89 1252 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Kojto 91:031413cf7a89 1253 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
Kojto 91:031413cf7a89 1254 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Kojto 91:031413cf7a89 1255 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Kojto 91:031413cf7a89 1256 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Kojto 91:031413cf7a89 1257 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Kojto 91:031413cf7a89 1258 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Kojto 91:031413cf7a89 1259 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Kojto 91:031413cf7a89 1260 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Kojto 91:031413cf7a89 1261 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Kojto 91:031413cf7a89 1262 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Kojto 91:031413cf7a89 1263 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Kojto 91:031413cf7a89 1264 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Kojto 91:031413cf7a89 1265 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Kojto 91:031413cf7a89 1266 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Kojto 91:031413cf7a89 1267 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
Kojto 91:031413cf7a89 1268 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Kojto 91:031413cf7a89 1269 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Kojto 91:031413cf7a89 1270 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Kojto 91:031413cf7a89 1271 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Kojto 91:031413cf7a89 1272 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
Kojto 91:031413cf7a89 1273
Kojto 91:031413cf7a89 1274
Kojto 91:031413cf7a89 1275 /** @} */ /* End of group Device_Peripheral_Registers */
Kojto 122:f9eeca106725 1276 /** @} */ /* End of group nrf51 */
Kojto 91:031413cf7a89 1277 /** @} */ /* End of group Nordic Semiconductor */
Kojto 91:031413cf7a89 1278
Kojto 91:031413cf7a89 1279 #ifdef __cplusplus
Kojto 91:031413cf7a89 1280 }
Kojto 91:031413cf7a89 1281 #endif
Kojto 91:031413cf7a89 1282
Kojto 91:031413cf7a89 1283
Kojto 122:f9eeca106725 1284 #endif /* nrf51_H */
Kojto 123:b0220dba8be7 1285