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TARGET_KL46Z/TARGET_Freescale/TARGET_KLXX/clk_freqs.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Parent:
82:6473597d706e
Child:
93:e188a91d3eaa
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 76:824293ae5e43 1 /* mbed Microcontroller Library
bogdanm 76:824293ae5e43 2 * Copyright (c) 2006-2013 ARM Limited
bogdanm 76:824293ae5e43 3 *
bogdanm 76:824293ae5e43 4 * Licensed under the Apache License, Version 2.0 (the "License");
bogdanm 76:824293ae5e43 5 * you may not use this file except in compliance with the License.
bogdanm 76:824293ae5e43 6 * You may obtain a copy of the License at
bogdanm 76:824293ae5e43 7 *
bogdanm 76:824293ae5e43 8 * http://www.apache.org/licenses/LICENSE-2.0
bogdanm 76:824293ae5e43 9 *
bogdanm 76:824293ae5e43 10 * Unless required by applicable law or agreed to in writing, software
bogdanm 76:824293ae5e43 11 * distributed under the License is distributed on an "AS IS" BASIS,
bogdanm 76:824293ae5e43 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
bogdanm 76:824293ae5e43 13 * See the License for the specific language governing permissions and
bogdanm 76:824293ae5e43 14 * limitations under the License.
bogdanm 76:824293ae5e43 15 */
bogdanm 76:824293ae5e43 16 #ifndef MBED_CLK_FREQS_H
bogdanm 76:824293ae5e43 17 #define MBED_CLK_FREQS_H
bogdanm 76:824293ae5e43 18
bogdanm 76:824293ae5e43 19 #ifdef __cplusplus
bogdanm 76:824293ae5e43 20 extern "C" {
bogdanm 76:824293ae5e43 21 #endif
bogdanm 76:824293ae5e43 22
emilmont 77:869cf507173a 23 #include "PeripheralPins.h"
emilmont 77:869cf507173a 24
bogdanm 76:824293ae5e43 25 //Get the peripheral bus clock frequency
bogdanm 76:824293ae5e43 26 static inline uint32_t bus_frequency(void) {
Kojto 90:cb3d968589d8 27 return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
Kojto 90:cb3d968589d8 28 }
Kojto 90:cb3d968589d8 29
Kojto 90:cb3d968589d8 30 #if defined(TARGET_KL43Z)
Kojto 90:cb3d968589d8 31
Kojto 90:cb3d968589d8 32 static inline uint32_t extosc_frequency(void) {
Kojto 90:cb3d968589d8 33 return CPU_XTAL_CLK_HZ;
bogdanm 76:824293ae5e43 34 }
bogdanm 76:824293ae5e43 35
Kojto 90:cb3d968589d8 36 static inline uint32_t mcgirc_frequency(void) {
Kojto 90:cb3d968589d8 37 uint32_t mcgirc_clock = 0;
Kojto 90:cb3d968589d8 38
Kojto 90:cb3d968589d8 39 if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
Kojto 90:cb3d968589d8 40 mcgirc_clock = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
Kojto 90:cb3d968589d8 41 mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
Kojto 90:cb3d968589d8 42 mcgirc_clock /= 1u + (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
Kojto 90:cb3d968589d8 43 }
Kojto 90:cb3d968589d8 44
Kojto 90:cb3d968589d8 45 return mcgirc_clock;
Kojto 90:cb3d968589d8 46 }
Kojto 90:cb3d968589d8 47
Kojto 90:cb3d968589d8 48 #else
Kojto 90:cb3d968589d8 49
bogdanm 76:824293ae5e43 50 //Get external oscillator (crystal) frequency
bogdanm 76:824293ae5e43 51 static uint32_t extosc_frequency(void) {
bogdanm 76:824293ae5e43 52 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
bogdanm 76:824293ae5e43 53
bogdanm 76:824293ae5e43 54 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
bogdanm 76:824293ae5e43 55 return MCGClock;
bogdanm 76:824293ae5e43 56
emilmont 77:869cf507173a 57 uint32_t divider, multiplier;
Kojto 90:cb3d968589d8 58 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
bogdanm 76:824293ae5e43 59 if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
bogdanm 76:824293ae5e43 60 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
emilmont 77:869cf507173a 61 #endif
bogdanm 76:824293ae5e43 62 if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
bogdanm 76:824293ae5e43 63 divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
bogdanm 76:824293ae5e43 64 if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
bogdanm 76:824293ae5e43 65 divider <<= 5u;
bogdanm 76:824293ae5e43 66 /* Select correct multiplier to calculate the MCG output clock */
bogdanm 76:824293ae5e43 67 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
bogdanm 76:824293ae5e43 68 case 0x0u:
bogdanm 76:824293ae5e43 69 multiplier = 640u;
bogdanm 76:824293ae5e43 70 break;
bogdanm 76:824293ae5e43 71 case 0x20u:
bogdanm 76:824293ae5e43 72 multiplier = 1280u;
bogdanm 76:824293ae5e43 73 break;
bogdanm 76:824293ae5e43 74 case 0x40u:
bogdanm 76:824293ae5e43 75 multiplier = 1920u;
bogdanm 76:824293ae5e43 76 break;
bogdanm 76:824293ae5e43 77 case 0x60u:
bogdanm 76:824293ae5e43 78 multiplier = 2560u;
bogdanm 76:824293ae5e43 79 break;
bogdanm 76:824293ae5e43 80 case 0x80u:
bogdanm 76:824293ae5e43 81 multiplier = 732u;
bogdanm 76:824293ae5e43 82 break;
bogdanm 76:824293ae5e43 83 case 0xA0u:
bogdanm 76:824293ae5e43 84 multiplier = 1464u;
bogdanm 76:824293ae5e43 85 break;
bogdanm 76:824293ae5e43 86 case 0xC0u:
bogdanm 76:824293ae5e43 87 multiplier = 2197u;
bogdanm 76:824293ae5e43 88 break;
bogdanm 76:824293ae5e43 89 case 0xE0u:
bogdanm 76:824293ae5e43 90 default:
bogdanm 76:824293ae5e43 91 multiplier = 2929u;
bogdanm 76:824293ae5e43 92 break;
bogdanm 76:824293ae5e43 93 }
bogdanm 76:824293ae5e43 94
bogdanm 76:824293ae5e43 95 return MCGClock * divider / multiplier;
bogdanm 76:824293ae5e43 96 }
emilmont 77:869cf507173a 97 #ifdef MCG_C5_PLLCLKEN0_MASK
bogdanm 76:824293ae5e43 98 } else { //PLL is selected
bogdanm 76:824293ae5e43 99 divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
emilmont 77:869cf507173a 100 multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
emilmont 77:869cf507173a 101 return MCGClock * divider / multiplier;
bogdanm 76:824293ae5e43 102 }
bogdanm 76:824293ae5e43 103 }
emilmont 77:869cf507173a 104 #endif
bogdanm 76:824293ae5e43 105
bogdanm 76:824293ae5e43 106 //In all other cases either there is no crystal or we cannot determine it
bogdanm 76:824293ae5e43 107 //For example when the FLL is running on the internal reference, and there is also an
bogdanm 76:824293ae5e43 108 //external crystal. However these are unlikely situations
bogdanm 76:824293ae5e43 109 return 0;
bogdanm 76:824293ae5e43 110 }
bogdanm 76:824293ae5e43 111
emilmont 77:869cf507173a 112 //Get MCG PLL/2 or FLL frequency, depending on which one is active, sets PLLFLLSEL bit
emilmont 77:869cf507173a 113 static uint32_t mcgpllfll_frequency(void) {
emilmont 77:869cf507173a 114 if ((MCG->C1 & MCG_C1_CLKS_MASK) != MCG_C1_CLKS(0)) //PLL/FLL is not selected
emilmont 77:869cf507173a 115 return 0;
emilmont 77:869cf507173a 116
emilmont 77:869cf507173a 117 uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
emilmont 77:869cf507173a 118 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 77:869cf507173a 119 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
emilmont 77:869cf507173a 120 SIM->SOPT2 &= ~SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is FLL output
emilmont 77:869cf507173a 121 #endif
emilmont 77:869cf507173a 122 return MCGClock;
emilmont 77:869cf507173a 123 #ifdef MCG_C5_PLLCLKEN0_MASK
emilmont 77:869cf507173a 124 } else { //PLL is selected
emilmont 77:869cf507173a 125 SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //MCG peripheral clock is PLL output
emilmont 77:869cf507173a 126 return (MCGClock >> 1);
emilmont 77:869cf507173a 127 }
emilmont 77:869cf507173a 128 #endif
emilmont 77:869cf507173a 129
emilmont 77:869cf507173a 130 //It is possible the SystemCoreClock isn't running on the PLL, and the PLL is still active
emilmont 77:869cf507173a 131 //for the peripherals, this is however an unlikely setup
emilmont 77:869cf507173a 132 }
bogdanm 76:824293ae5e43 133
Kojto 90:cb3d968589d8 134 #endif
Kojto 90:cb3d968589d8 135
bogdanm 76:824293ae5e43 136 #ifdef __cplusplus
bogdanm 76:824293ae5e43 137 }
bogdanm 76:824293ae5e43 138 #endif
bogdanm 76:824293ae5e43 139
bogdanm 76:824293ae5e43 140 #endif