Diff: TARGET_KL46Z/TARGET_Freescale/TARGET_KLXX/clk_freqs.h

Revision:

90:cb3d968589d8

Parent:

82:6473597d706e

Child:

93:e188a91d3eaa

--- a/TARGET_KL46Z/TARGET_Freescale/TARGET_KLXX/clk_freqs.h	Fri Sep 12 16:41:52 2014 +0100
+++ b/TARGET_KL46Z/TARGET_Freescale/TARGET_KLXX/clk_freqs.h	Tue Oct 28 16:40:41 2014 +0000
@@ -24,9 +24,29 @@
 
 //Get the peripheral bus clock frequency
 static inline uint32_t bus_frequency(void) {
-    return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
+    return (SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1));
+}
+
+#if defined(TARGET_KL43Z)
+
+static inline uint32_t extosc_frequency(void) {
+    return CPU_XTAL_CLK_HZ;
 }
 
+static inline uint32_t mcgirc_frequency(void) {
+    uint32_t mcgirc_clock = 0;
+
+    if (MCG->C1 & MCG_C1_IREFSTEN_MASK) {
+        mcgirc_clock  = (MCG->C2 & MCG_C2_IRCS_MASK) ? 8000000u : 2000000u;
+        mcgirc_clock /= 1u + ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT);
+        mcgirc_clock /= 1u +  (MCG->MC & MCG_MC_LIRC_DIV2_MASK);
+    }
+
+    return mcgirc_clock;
+}
+
+#else
+
 //Get external oscillator (crystal) frequency
 static uint32_t extosc_frequency(void) {
     uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
@@ -35,7 +55,7 @@
         return MCGClock;
     
     uint32_t divider, multiplier;
-    #ifdef MCG_C5_PLLCLKEN0_MASK                             //PLL available
+    #ifdef MCG_C5_PLLCLKEN0_MASK                            //PLL available
     if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) {   //PLL/FLL is selected
         if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {         //FLL is selected
     #endif
@@ -111,6 +131,8 @@
     //for the peripherals, this is however an unlikely setup
 }
 
+#endif
+
 #ifdef __cplusplus
 }
 #endif