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TARGET_NUCLEO_F746ZG/stm32f7xx_hal_rcc_ex.h@116:c0f6e94411f5, 2016-03-15 (annotated)

Committer:: Kojto
Date:: Tue Mar 15 14:34:00 2016 +0000
Revision:: 116:c0f6e94411f5
Parent:: 115:87f2f5183dfb
Child:: 122:f9eeca106725

Release 116 of the mbed library



Changes:

- new targets - NUCLEO_L073RZ

- fixes to IOTSS BEID platform

- LPC824, LPC1549 and LPC11U68 - fix PWMOut SCT bugs

- STM32F7 - Cube driver

- STM32F4 - add RTC LSI macro, defined as 0

- STM32F3 - fix multiple ADC clock initialization

- retarget - binary mode fix for GCC

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	115:87f2f5183dfb	1	/**
Kojto	115:87f2f5183dfb	2	******************************************************************************
Kojto	115:87f2f5183dfb	3	* @file stm32f7xx_hal_rcc_ex.h
Kojto	116:c0f6e94411f5	4	* @author MCD Application Team
Kojto	116:c0f6e94411f5	5	* @version V1.0.4
Kojto	116:c0f6e94411f5	6	* @date 09-December-2015
Kojto	115:87f2f5183dfb	7	* @brief Header file of RCC HAL Extension module.
Kojto	115:87f2f5183dfb	8	******************************************************************************
Kojto	115:87f2f5183dfb	9	* @attention
Kojto	115:87f2f5183dfb	10	*
Kojto	115:87f2f5183dfb	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto	115:87f2f5183dfb	12	*
Kojto	115:87f2f5183dfb	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	115:87f2f5183dfb	14	* are permitted provided that the following conditions are met:
Kojto	115:87f2f5183dfb	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	115:87f2f5183dfb	16	* this list of conditions and the following disclaimer.
Kojto	115:87f2f5183dfb	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	115:87f2f5183dfb	18	* this list of conditions and the following disclaimer in the documentation
Kojto	115:87f2f5183dfb	19	* and/or other materials provided with the distribution.
Kojto	115:87f2f5183dfb	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	115:87f2f5183dfb	21	* may be used to endorse or promote products derived from this software
Kojto	115:87f2f5183dfb	22	* without specific prior written permission.
Kojto	115:87f2f5183dfb	23	*
Kojto	115:87f2f5183dfb	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	115:87f2f5183dfb	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	115:87f2f5183dfb	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	115:87f2f5183dfb	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	115:87f2f5183dfb	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	115:87f2f5183dfb	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	115:87f2f5183dfb	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	115:87f2f5183dfb	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	115:87f2f5183dfb	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	115:87f2f5183dfb	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	115:87f2f5183dfb	34	*
Kojto	115:87f2f5183dfb	35	******************************************************************************
Kojto	115:87f2f5183dfb	36	*/
Kojto	115:87f2f5183dfb	37
Kojto	115:87f2f5183dfb	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	115:87f2f5183dfb	39	#ifndef __STM32F7xx_HAL_RCC_EX_H
Kojto	115:87f2f5183dfb	40	#define __STM32F7xx_HAL_RCC_EX_H
Kojto	115:87f2f5183dfb	41
Kojto	115:87f2f5183dfb	42	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	43	extern "C" {
Kojto	115:87f2f5183dfb	44	#endif
Kojto	115:87f2f5183dfb	45
Kojto	115:87f2f5183dfb	46	/* Includes ------------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	47	#include "stm32f7xx_hal_def.h"
Kojto	115:87f2f5183dfb	48
Kojto	115:87f2f5183dfb	49	/** @addtogroup STM32F7xx_HAL_Driver
Kojto	115:87f2f5183dfb	50	* @{
Kojto	115:87f2f5183dfb	51	*/
Kojto	115:87f2f5183dfb	52
Kojto	115:87f2f5183dfb	53	/** @addtogroup RCCEx
Kojto	115:87f2f5183dfb	54	* @{
Kojto	115:87f2f5183dfb	55	*/
Kojto	115:87f2f5183dfb	56
Kojto	115:87f2f5183dfb	57	/* Exported types ------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	58	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto	115:87f2f5183dfb	59	* @{
Kojto	115:87f2f5183dfb	60	*/
Kojto	115:87f2f5183dfb	61
Kojto	115:87f2f5183dfb	62	/**
Kojto	115:87f2f5183dfb	63	* @brief PLLI2S Clock structure definition
Kojto	115:87f2f5183dfb	64	*/
Kojto	115:87f2f5183dfb	65	typedef struct
Kojto	115:87f2f5183dfb	66	{
Kojto	115:87f2f5183dfb	67	uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	116:c0f6e94411f5	68	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	115:87f2f5183dfb	69	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	115:87f2f5183dfb	70
Kojto	115:87f2f5183dfb	71	uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto	115:87f2f5183dfb	72	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	115:87f2f5183dfb	73	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	115:87f2f5183dfb	74
Kojto	115:87f2f5183dfb	75	uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
Kojto	115:87f2f5183dfb	76	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	115:87f2f5183dfb	77	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	115:87f2f5183dfb	78
Kojto	115:87f2f5183dfb	79	uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
Kojto	116:c0f6e94411f5	80	This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
Kojto	116:c0f6e94411f5	81	This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
Kojto	115:87f2f5183dfb	82	}RCC_PLLI2SInitTypeDef;
Kojto	115:87f2f5183dfb	83
Kojto	115:87f2f5183dfb	84	/**
Kojto	115:87f2f5183dfb	85	* @brief PLLSAI Clock structure definition
Kojto	115:87f2f5183dfb	86	*/
Kojto	115:87f2f5183dfb	87	typedef struct
Kojto	115:87f2f5183dfb	88	{
Kojto	115:87f2f5183dfb	89	uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	116:c0f6e94411f5	90	This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	115:87f2f5183dfb	91	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	115:87f2f5183dfb	92
Kojto	115:87f2f5183dfb	93	uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
Kojto	115:87f2f5183dfb	94	This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	115:87f2f5183dfb	95	This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto	115:87f2f5183dfb	96
Kojto	115:87f2f5183dfb	97	uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
Kojto	115:87f2f5183dfb	98	This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	115:87f2f5183dfb	99	This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
Kojto	115:87f2f5183dfb	100
Kojto	115:87f2f5183dfb	101	uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
Kojto	116:c0f6e94411f5	102	This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
Kojto	115:87f2f5183dfb	103	This parameter will be used only when PLLSAI is disabled */
Kojto	115:87f2f5183dfb	104	}RCC_PLLSAIInitTypeDef;
Kojto	115:87f2f5183dfb	105
Kojto	115:87f2f5183dfb	106	/**
Kojto	115:87f2f5183dfb	107	* @brief RCC extended clocks structure definition
Kojto	115:87f2f5183dfb	108	*/
Kojto	115:87f2f5183dfb	109	typedef struct
Kojto	115:87f2f5183dfb	110	{
Kojto	115:87f2f5183dfb	111	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	115:87f2f5183dfb	112	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	115:87f2f5183dfb	113
Kojto	115:87f2f5183dfb	114	RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto	115:87f2f5183dfb	115	This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto	115:87f2f5183dfb	116
Kojto	115:87f2f5183dfb	117	RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto	115:87f2f5183dfb	118	This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto	115:87f2f5183dfb	119
Kojto	115:87f2f5183dfb	120	uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	115:87f2f5183dfb	121	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	115:87f2f5183dfb	122	This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto	115:87f2f5183dfb	123
Kojto	115:87f2f5183dfb	124	uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto	115:87f2f5183dfb	125	This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto	115:87f2f5183dfb	126	This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto	115:87f2f5183dfb	127
Kojto	115:87f2f5183dfb	128	uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
Kojto	115:87f2f5183dfb	129	This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
Kojto	115:87f2f5183dfb	130
Kojto	115:87f2f5183dfb	131	uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
Kojto	115:87f2f5183dfb	132	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	115:87f2f5183dfb	133
Kojto	115:87f2f5183dfb	134	uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
Kojto	115:87f2f5183dfb	135	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	115:87f2f5183dfb	136
Kojto	115:87f2f5183dfb	137	uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
Kojto	115:87f2f5183dfb	138	This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
Kojto	115:87f2f5183dfb	139
Kojto	115:87f2f5183dfb	140	uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
Kojto	115:87f2f5183dfb	141	This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto	115:87f2f5183dfb	142
Kojto	115:87f2f5183dfb	143	uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
Kojto	115:87f2f5183dfb	144	This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto	115:87f2f5183dfb	145
Kojto	115:87f2f5183dfb	146	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	115:87f2f5183dfb	147	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	115:87f2f5183dfb	148
Kojto	115:87f2f5183dfb	149	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	115:87f2f5183dfb	150	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto	115:87f2f5183dfb	151
Kojto	115:87f2f5183dfb	152	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	115:87f2f5183dfb	153	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto	115:87f2f5183dfb	154
Kojto	115:87f2f5183dfb	155	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	115:87f2f5183dfb	156	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	115:87f2f5183dfb	157
Kojto	115:87f2f5183dfb	158	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	115:87f2f5183dfb	159	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	115:87f2f5183dfb	160
Kojto	115:87f2f5183dfb	161	uint32_t Usart6ClockSelection; /*!< USART6 clock source
Kojto	115:87f2f5183dfb	162	This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
Kojto	115:87f2f5183dfb	163
Kojto	115:87f2f5183dfb	164	uint32_t Uart7ClockSelection; /*!< UART7 clock source
Kojto	115:87f2f5183dfb	165	This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
Kojto	115:87f2f5183dfb	166
Kojto	115:87f2f5183dfb	167	uint32_t Uart8ClockSelection; /*!< UART8 clock source
Kojto	115:87f2f5183dfb	168	This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
Kojto	115:87f2f5183dfb	169
Kojto	115:87f2f5183dfb	170	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	115:87f2f5183dfb	171	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto	115:87f2f5183dfb	172
Kojto	115:87f2f5183dfb	173	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	115:87f2f5183dfb	174	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	115:87f2f5183dfb	175
Kojto	115:87f2f5183dfb	176	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	115:87f2f5183dfb	177	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	115:87f2f5183dfb	178
Kojto	115:87f2f5183dfb	179	uint32_t I2c4ClockSelection; /*!< I2C4 clock source
Kojto	115:87f2f5183dfb	180	This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
Kojto	115:87f2f5183dfb	181
Kojto	115:87f2f5183dfb	182	uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
Kojto	115:87f2f5183dfb	183	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto	115:87f2f5183dfb	184
Kojto	115:87f2f5183dfb	185	uint32_t CecClockSelection; /*!< CEC clock source
Kojto	115:87f2f5183dfb	186	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	115:87f2f5183dfb	187
Kojto	115:87f2f5183dfb	188	uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
Kojto	115:87f2f5183dfb	189	This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto	115:87f2f5183dfb	190
Kojto	115:87f2f5183dfb	191	uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
Kojto	115:87f2f5183dfb	192	This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
Kojto	115:87f2f5183dfb	193	}RCC_PeriphCLKInitTypeDef;
Kojto	115:87f2f5183dfb	194	/**
Kojto	115:87f2f5183dfb	195	* @}
Kojto	115:87f2f5183dfb	196	*/
Kojto	115:87f2f5183dfb	197
Kojto	115:87f2f5183dfb	198	/* Exported constants --------------------------------------------------------*/
Kojto	115:87f2f5183dfb	199	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto	115:87f2f5183dfb	200	* @{
Kojto	115:87f2f5183dfb	201	*/
Kojto	115:87f2f5183dfb	202
Kojto	115:87f2f5183dfb	203	/** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
Kojto	115:87f2f5183dfb	204	* @{
Kojto	115:87f2f5183dfb	205	*/
Kojto	115:87f2f5183dfb	206	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto	116:c0f6e94411f5	207	#if defined(STM32F746xx) \|\| defined(STM32F756xx)
Kojto	115:87f2f5183dfb	208	#define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto	116:c0f6e94411f5	209	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	115:87f2f5183dfb	210	#define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto	115:87f2f5183dfb	211	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto	115:87f2f5183dfb	212	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
Kojto	115:87f2f5183dfb	213	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
Kojto	115:87f2f5183dfb	214	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
Kojto	115:87f2f5183dfb	215	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
Kojto	115:87f2f5183dfb	216	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
Kojto	115:87f2f5183dfb	217	#define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
Kojto	115:87f2f5183dfb	218	#define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
Kojto	115:87f2f5183dfb	219	#define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
Kojto	115:87f2f5183dfb	220	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
Kojto	115:87f2f5183dfb	221	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
Kojto	115:87f2f5183dfb	222	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
Kojto	115:87f2f5183dfb	223	#define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
Kojto	115:87f2f5183dfb	224	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
Kojto	115:87f2f5183dfb	225	#define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
Kojto	115:87f2f5183dfb	226	#define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
Kojto	115:87f2f5183dfb	227	#define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
Kojto	115:87f2f5183dfb	228	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
Kojto	115:87f2f5183dfb	229	#define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
Kojto	115:87f2f5183dfb	230	#define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
Kojto	115:87f2f5183dfb	231	#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)
Kojto	115:87f2f5183dfb	232
Kojto	116:c0f6e94411f5	233	/**
Kojto	116:c0f6e94411f5	234	* @}
Kojto	116:c0f6e94411f5	235	*/
Kojto	115:87f2f5183dfb	236
Kojto	116:c0f6e94411f5	237	/** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
Kojto	116:c0f6e94411f5	238	* @{
Kojto	116:c0f6e94411f5	239	*/
Kojto	116:c0f6e94411f5	240	#define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000)
Kojto	116:c0f6e94411f5	241	#define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001)
Kojto	116:c0f6e94411f5	242	#define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002)
Kojto	116:c0f6e94411f5	243	#define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	244	/**
Kojto	115:87f2f5183dfb	245	* @}
Kojto	115:87f2f5183dfb	246	*/
Kojto	115:87f2f5183dfb	247
Kojto	115:87f2f5183dfb	248	/** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
Kojto	115:87f2f5183dfb	249	* @{
Kojto	115:87f2f5183dfb	250	*/
Kojto	115:87f2f5183dfb	251	#define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	252	#define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
Kojto	115:87f2f5183dfb	253	#define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
Kojto	115:87f2f5183dfb	254	#define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)
Kojto	115:87f2f5183dfb	255	/**
Kojto	115:87f2f5183dfb	256	* @}
Kojto	115:87f2f5183dfb	257	*/
Kojto	115:87f2f5183dfb	258
Kojto	115:87f2f5183dfb	259	/** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
Kojto	115:87f2f5183dfb	260	* @{
Kojto	115:87f2f5183dfb	261	*/
Kojto	115:87f2f5183dfb	262	#define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	263	#define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
Kojto	115:87f2f5183dfb	264	#define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
Kojto	115:87f2f5183dfb	265	#define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
Kojto	115:87f2f5183dfb	266	/**
Kojto	115:87f2f5183dfb	267	* @}
Kojto	115:87f2f5183dfb	268	*/
Kojto	115:87f2f5183dfb	269
Kojto	115:87f2f5183dfb	270	/** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
Kojto	115:87f2f5183dfb	271	* @{
Kojto	115:87f2f5183dfb	272	*/
Kojto	115:87f2f5183dfb	273	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	274	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
Kojto	115:87f2f5183dfb	275
Kojto	115:87f2f5183dfb	276	/**
Kojto	115:87f2f5183dfb	277	* @}
Kojto	115:87f2f5183dfb	278	*/
Kojto	115:87f2f5183dfb	279
Kojto	115:87f2f5183dfb	280
Kojto	115:87f2f5183dfb	281	/** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
Kojto	115:87f2f5183dfb	282	* @{
Kojto	115:87f2f5183dfb	283	*/
Kojto	115:87f2f5183dfb	284	#define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	285	#define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
Kojto	115:87f2f5183dfb	286	#define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
Kojto	115:87f2f5183dfb	287
Kojto	115:87f2f5183dfb	288	/**
Kojto	115:87f2f5183dfb	289	* @}
Kojto	115:87f2f5183dfb	290	*/
Kojto	115:87f2f5183dfb	291
Kojto	115:87f2f5183dfb	292	/** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
Kojto	115:87f2f5183dfb	293	* @{
Kojto	115:87f2f5183dfb	294	*/
Kojto	115:87f2f5183dfb	295	#define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	296	#define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
Kojto	115:87f2f5183dfb	297	#define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
Kojto	115:87f2f5183dfb	298	/**
Kojto	115:87f2f5183dfb	299	* @}
Kojto	115:87f2f5183dfb	300	*/
Kojto	115:87f2f5183dfb	301
Kojto	115:87f2f5183dfb	302	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
Kojto	115:87f2f5183dfb	303	* @{
Kojto	115:87f2f5183dfb	304	*/
Kojto	115:87f2f5183dfb	305	#define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	306	#define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
Kojto	115:87f2f5183dfb	307	/**
Kojto	115:87f2f5183dfb	308	* @}
Kojto	115:87f2f5183dfb	309	*/
Kojto	115:87f2f5183dfb	310
Kojto	115:87f2f5183dfb	311	/** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
Kojto	115:87f2f5183dfb	312	* @{
Kojto	115:87f2f5183dfb	313	*/
Kojto	115:87f2f5183dfb	314	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	315	#define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
Kojto	115:87f2f5183dfb	316	#define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
Kojto	115:87f2f5183dfb	317	#define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
Kojto	115:87f2f5183dfb	318	/**
Kojto	115:87f2f5183dfb	319	* @}
Kojto	115:87f2f5183dfb	320	*/
Kojto	115:87f2f5183dfb	321
Kojto	115:87f2f5183dfb	322	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
Kojto	115:87f2f5183dfb	323	* @{
Kojto	115:87f2f5183dfb	324	*/
Kojto	115:87f2f5183dfb	325	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	326	#define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
Kojto	115:87f2f5183dfb	327	#define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
Kojto	115:87f2f5183dfb	328	#define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
Kojto	115:87f2f5183dfb	329	/**
Kojto	115:87f2f5183dfb	330	* @}
Kojto	115:87f2f5183dfb	331	*/
Kojto	115:87f2f5183dfb	332
Kojto	115:87f2f5183dfb	333	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
Kojto	115:87f2f5183dfb	334	* @{
Kojto	115:87f2f5183dfb	335	*/
Kojto	115:87f2f5183dfb	336	#define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	337	#define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
Kojto	115:87f2f5183dfb	338	#define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
Kojto	115:87f2f5183dfb	339	#define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
Kojto	115:87f2f5183dfb	340	/**
Kojto	115:87f2f5183dfb	341	* @}
Kojto	115:87f2f5183dfb	342	*/
Kojto	115:87f2f5183dfb	343
Kojto	115:87f2f5183dfb	344	/** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
Kojto	115:87f2f5183dfb	345	* @{
Kojto	115:87f2f5183dfb	346	*/
Kojto	115:87f2f5183dfb	347	#define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	348	#define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
Kojto	115:87f2f5183dfb	349	#define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
Kojto	115:87f2f5183dfb	350	#define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
Kojto	115:87f2f5183dfb	351	/**
Kojto	115:87f2f5183dfb	352	* @}
Kojto	115:87f2f5183dfb	353	*/
Kojto	115:87f2f5183dfb	354
Kojto	115:87f2f5183dfb	355	/** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
Kojto	115:87f2f5183dfb	356	* @{
Kojto	115:87f2f5183dfb	357	*/
Kojto	115:87f2f5183dfb	358	#define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	359	#define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
Kojto	115:87f2f5183dfb	360	#define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
Kojto	115:87f2f5183dfb	361	#define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
Kojto	115:87f2f5183dfb	362	/**
Kojto	115:87f2f5183dfb	363	* @}
Kojto	115:87f2f5183dfb	364	*/
Kojto	115:87f2f5183dfb	365
Kojto	115:87f2f5183dfb	366	/** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
Kojto	115:87f2f5183dfb	367	* @{
Kojto	115:87f2f5183dfb	368	*/
Kojto	115:87f2f5183dfb	369	#define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	370	#define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
Kojto	115:87f2f5183dfb	371	#define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
Kojto	115:87f2f5183dfb	372	#define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
Kojto	115:87f2f5183dfb	373	/**
Kojto	115:87f2f5183dfb	374	* @}
Kojto	115:87f2f5183dfb	375	*/
Kojto	115:87f2f5183dfb	376
Kojto	115:87f2f5183dfb	377	/** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
Kojto	115:87f2f5183dfb	378	* @{
Kojto	115:87f2f5183dfb	379	*/
Kojto	115:87f2f5183dfb	380	#define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	381	#define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
Kojto	115:87f2f5183dfb	382	#define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
Kojto	115:87f2f5183dfb	383	#define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
Kojto	115:87f2f5183dfb	384	/**
Kojto	115:87f2f5183dfb	385	* @}
Kojto	115:87f2f5183dfb	386	*/
Kojto	115:87f2f5183dfb	387
Kojto	115:87f2f5183dfb	388	/** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
Kojto	115:87f2f5183dfb	389	* @{
Kojto	115:87f2f5183dfb	390	*/
Kojto	115:87f2f5183dfb	391	#define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	392	#define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
Kojto	115:87f2f5183dfb	393	#define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
Kojto	115:87f2f5183dfb	394	#define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
Kojto	115:87f2f5183dfb	395	/**
Kojto	115:87f2f5183dfb	396	* @}
Kojto	115:87f2f5183dfb	397	*/
Kojto	115:87f2f5183dfb	398
Kojto	115:87f2f5183dfb	399	/** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
Kojto	115:87f2f5183dfb	400	* @{
Kojto	115:87f2f5183dfb	401	*/
Kojto	115:87f2f5183dfb	402	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	403	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
Kojto	115:87f2f5183dfb	404	#define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
Kojto	115:87f2f5183dfb	405	/**
Kojto	115:87f2f5183dfb	406	* @}
Kojto	115:87f2f5183dfb	407	*/
Kojto	115:87f2f5183dfb	408
Kojto	115:87f2f5183dfb	409	/** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
Kojto	115:87f2f5183dfb	410	* @{
Kojto	115:87f2f5183dfb	411	*/
Kojto	115:87f2f5183dfb	412	#define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	413	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
Kojto	115:87f2f5183dfb	414	#define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
Kojto	115:87f2f5183dfb	415
Kojto	115:87f2f5183dfb	416	/**
Kojto	115:87f2f5183dfb	417	* @}
Kojto	115:87f2f5183dfb	418	*/
Kojto	115:87f2f5183dfb	419
Kojto	115:87f2f5183dfb	420	/** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
Kojto	115:87f2f5183dfb	421	* @{
Kojto	115:87f2f5183dfb	422	*/
Kojto	115:87f2f5183dfb	423	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	424	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
Kojto	115:87f2f5183dfb	425	#define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
Kojto	115:87f2f5183dfb	426	/**
Kojto	115:87f2f5183dfb	427	* @}
Kojto	115:87f2f5183dfb	428	*/
Kojto	115:87f2f5183dfb	429
Kojto	115:87f2f5183dfb	430	/** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
Kojto	115:87f2f5183dfb	431	* @{
Kojto	115:87f2f5183dfb	432	*/
Kojto	115:87f2f5183dfb	433	#define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	434	#define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
Kojto	115:87f2f5183dfb	435	#define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
Kojto	115:87f2f5183dfb	436	/**
Kojto	115:87f2f5183dfb	437	* @}
Kojto	115:87f2f5183dfb	438	*/
Kojto	115:87f2f5183dfb	439
Kojto	115:87f2f5183dfb	440	/** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
Kojto	115:87f2f5183dfb	441	* @{
Kojto	115:87f2f5183dfb	442	*/
Kojto	115:87f2f5183dfb	443	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	444	#define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
Kojto	115:87f2f5183dfb	445	#define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
Kojto	115:87f2f5183dfb	446	#define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
Kojto	115:87f2f5183dfb	447
Kojto	115:87f2f5183dfb	448	/**
Kojto	115:87f2f5183dfb	449	* @}
Kojto	115:87f2f5183dfb	450	*/
Kojto	115:87f2f5183dfb	451
Kojto	115:87f2f5183dfb	452	/** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
Kojto	115:87f2f5183dfb	453	* @{
Kojto	115:87f2f5183dfb	454	*/
Kojto	115:87f2f5183dfb	455	#define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	456	#define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
Kojto	115:87f2f5183dfb	457	/**
Kojto	115:87f2f5183dfb	458	* @}
Kojto	115:87f2f5183dfb	459	*/
Kojto	115:87f2f5183dfb	460
Kojto	115:87f2f5183dfb	461	/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
Kojto	115:87f2f5183dfb	462	* @{
Kojto	115:87f2f5183dfb	463	*/
Kojto	115:87f2f5183dfb	464	#define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
Kojto	115:87f2f5183dfb	465	#define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
Kojto	116:c0f6e94411f5	466	/**
Kojto	116:c0f6e94411f5	467	* @}
Kojto	116:c0f6e94411f5	468	*/
Kojto	115:87f2f5183dfb	469
Kojto	116:c0f6e94411f5	470	/** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
Kojto	116:c0f6e94411f5	471	* @{
Kojto	116:c0f6e94411f5	472	*/
Kojto	116:c0f6e94411f5	473	#define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
Kojto	116:c0f6e94411f5	474	#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
Kojto	115:87f2f5183dfb	475	/**
Kojto	115:87f2f5183dfb	476	* @}
Kojto	115:87f2f5183dfb	477	*/
Kojto	115:87f2f5183dfb	478
Kojto	115:87f2f5183dfb	479	/**
Kojto	115:87f2f5183dfb	480	* @}
Kojto	115:87f2f5183dfb	481	*/
Kojto	115:87f2f5183dfb	482
Kojto	115:87f2f5183dfb	483	/* Exported macro ------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	484	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto	115:87f2f5183dfb	485	* @{
Kojto	115:87f2f5183dfb	486	*/
Kojto	115:87f2f5183dfb	487	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto	115:87f2f5183dfb	488	* @brief Enables or disables the AHB/APB peripheral clock.
Kojto	115:87f2f5183dfb	489	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	490	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	491	* using it.
Kojto	115:87f2f5183dfb	492	* @{
Kojto	115:87f2f5183dfb	493	*/
Kojto	115:87f2f5183dfb	494
Kojto	115:87f2f5183dfb	495	/** @brief Enables or disables the AHB1 peripheral clock.
Kojto	115:87f2f5183dfb	496	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	497	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	498	* using it.
Kojto	115:87f2f5183dfb	499	*/
Kojto	115:87f2f5183dfb	500	#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	501	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	502	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	115:87f2f5183dfb	503	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	504	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto	115:87f2f5183dfb	505	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	506	} while(0)
Kojto	115:87f2f5183dfb	507
Kojto	115:87f2f5183dfb	508	#define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	509	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	510	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
Kojto	115:87f2f5183dfb	511	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	512	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
Kojto	115:87f2f5183dfb	513	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	514	} while(0)
Kojto	115:87f2f5183dfb	515
Kojto	115:87f2f5183dfb	516	#define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	517	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	518	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto	115:87f2f5183dfb	519	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	520	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto	115:87f2f5183dfb	521	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	522	} while(0)
Kojto	115:87f2f5183dfb	523
Kojto	115:87f2f5183dfb	524	#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	525	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	526	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	115:87f2f5183dfb	527	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	528	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto	115:87f2f5183dfb	529	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	530	} while(0)
Kojto	115:87f2f5183dfb	531
Kojto	115:87f2f5183dfb	532	#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	533	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	534	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	115:87f2f5183dfb	535	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	536	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto	115:87f2f5183dfb	537	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	538	} while(0)
Kojto	115:87f2f5183dfb	539
Kojto	115:87f2f5183dfb	540	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	541	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	542	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	115:87f2f5183dfb	543	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	544	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto	115:87f2f5183dfb	545	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	546	} while(0)
Kojto	115:87f2f5183dfb	547
Kojto	115:87f2f5183dfb	548	#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	549	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	550	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto	115:87f2f5183dfb	551	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	552	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto	115:87f2f5183dfb	553	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	554	} while(0)
Kojto	115:87f2f5183dfb	555
Kojto	115:87f2f5183dfb	556	#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	557	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	558	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto	115:87f2f5183dfb	559	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	560	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto	115:87f2f5183dfb	561	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	562	} while(0)
Kojto	115:87f2f5183dfb	563
Kojto	115:87f2f5183dfb	564	#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	565	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	566	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto	115:87f2f5183dfb	567	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	568	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto	115:87f2f5183dfb	569	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	570	} while(0)
Kojto	115:87f2f5183dfb	571
Kojto	115:87f2f5183dfb	572	#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	573	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	574	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	115:87f2f5183dfb	575	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	576	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto	115:87f2f5183dfb	577	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	578	} while(0)
Kojto	115:87f2f5183dfb	579
Kojto	115:87f2f5183dfb	580	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	581	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	582	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	115:87f2f5183dfb	583	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	584	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto	115:87f2f5183dfb	585	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	586	} while(0)
Kojto	115:87f2f5183dfb	587
Kojto	115:87f2f5183dfb	588	#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	589	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	590	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	115:87f2f5183dfb	591	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	592	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto	115:87f2f5183dfb	593	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	594	} while(0)
Kojto	115:87f2f5183dfb	595
Kojto	115:87f2f5183dfb	596	#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	597	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	598	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	115:87f2f5183dfb	599	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	600	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto	115:87f2f5183dfb	601	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	602	} while(0)
Kojto	115:87f2f5183dfb	603
Kojto	115:87f2f5183dfb	604	#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	605	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	606	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto	115:87f2f5183dfb	607	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	608	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto	115:87f2f5183dfb	609	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	610	} while(0)
Kojto	115:87f2f5183dfb	611
Kojto	115:87f2f5183dfb	612	#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	613	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	614	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	115:87f2f5183dfb	615	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	616	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto	115:87f2f5183dfb	617	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	618	} while(0)
Kojto	115:87f2f5183dfb	619
Kojto	115:87f2f5183dfb	620	#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	621	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	622	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	115:87f2f5183dfb	623	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	624	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto	115:87f2f5183dfb	625	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	626	} while(0)
Kojto	115:87f2f5183dfb	627
Kojto	115:87f2f5183dfb	628	#define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	629	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	630	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	115:87f2f5183dfb	631	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	632	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto	115:87f2f5183dfb	633	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	634	} while(0)
Kojto	115:87f2f5183dfb	635
Kojto	115:87f2f5183dfb	636	#define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto	115:87f2f5183dfb	637	#define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
Kojto	115:87f2f5183dfb	638	#define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto	115:87f2f5183dfb	639	#define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto	115:87f2f5183dfb	640	#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto	115:87f2f5183dfb	641	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto	115:87f2f5183dfb	642	#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto	115:87f2f5183dfb	643	#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto	115:87f2f5183dfb	644	#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto	115:87f2f5183dfb	645	#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto	115:87f2f5183dfb	646	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto	115:87f2f5183dfb	647	#define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto	115:87f2f5183dfb	648	#define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto	115:87f2f5183dfb	649	#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto	115:87f2f5183dfb	650	#define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto	115:87f2f5183dfb	651	#define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto	115:87f2f5183dfb	652	#define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto	115:87f2f5183dfb	653	/**
Kojto	115:87f2f5183dfb	654	* @brief Enable ETHERNET clock.
Kojto	115:87f2f5183dfb	655	*/
Kojto	115:87f2f5183dfb	656	#define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	657	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	658	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	115:87f2f5183dfb	659	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	660	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto	115:87f2f5183dfb	661	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	662	} while(0)
Kojto	115:87f2f5183dfb	663
Kojto	115:87f2f5183dfb	664	#define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	665	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	666	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	115:87f2f5183dfb	667	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	668	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto	115:87f2f5183dfb	669	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	670	} while(0)
Kojto	115:87f2f5183dfb	671
Kojto	115:87f2f5183dfb	672	#define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	673	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	674	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	115:87f2f5183dfb	675	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	676	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto	115:87f2f5183dfb	677	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	678	} while(0)
Kojto	115:87f2f5183dfb	679
Kojto	115:87f2f5183dfb	680	#define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	681	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	682	SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	115:87f2f5183dfb	683	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	684	tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto	115:87f2f5183dfb	685	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	686	} while(0)
Kojto	115:87f2f5183dfb	687
Kojto	115:87f2f5183dfb	688	#define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto	115:87f2f5183dfb	689	__HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto	115:87f2f5183dfb	690	__HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto	115:87f2f5183dfb	691	__HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto	115:87f2f5183dfb	692	} while(0)
Kojto	115:87f2f5183dfb	693	/**
Kojto	115:87f2f5183dfb	694	* @brief Disable ETHERNET clock.
Kojto	115:87f2f5183dfb	695	*/
Kojto	115:87f2f5183dfb	696	#define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto	115:87f2f5183dfb	697	#define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto	115:87f2f5183dfb	698	#define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto	115:87f2f5183dfb	699	#define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto	115:87f2f5183dfb	700	#define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto	115:87f2f5183dfb	701	__HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto	115:87f2f5183dfb	702	__HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto	115:87f2f5183dfb	703	__HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto	115:87f2f5183dfb	704	} while(0)
Kojto	115:87f2f5183dfb	705
Kojto	115:87f2f5183dfb	706	/** @brief Enable or disable the AHB2 peripheral clock.
Kojto	115:87f2f5183dfb	707	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	708	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	709	* using it.
Kojto	115:87f2f5183dfb	710	*/
Kojto	115:87f2f5183dfb	711	#define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	712	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	713	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	115:87f2f5183dfb	714	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	715	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto	115:87f2f5183dfb	716	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	717	} while(0)
Kojto	115:87f2f5183dfb	718
Kojto	115:87f2f5183dfb	719	#define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	720	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	721	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	115:87f2f5183dfb	722	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	723	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto	115:87f2f5183dfb	724	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	725	} while(0)
Kojto	115:87f2f5183dfb	726
Kojto	115:87f2f5183dfb	727	#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	728	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	729	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
Kojto	115:87f2f5183dfb	730	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	731	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
Kojto	115:87f2f5183dfb	732	UNUSED(tmpreg); \
Kojto	116:c0f6e94411f5	733	__HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto	115:87f2f5183dfb	734	} while(0)
Kojto	115:87f2f5183dfb	735
Kojto	116:c0f6e94411f5	736	#define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto	115:87f2f5183dfb	737	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto	115:87f2f5183dfb	738
Kojto	116:c0f6e94411f5	739	#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto	115:87f2f5183dfb	740	#if defined(STM32F756xx)
Kojto	115:87f2f5183dfb	741	#define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	742	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	743	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	115:87f2f5183dfb	744	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	745	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto	115:87f2f5183dfb	746	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	747	} while(0)
Kojto	115:87f2f5183dfb	748
Kojto	115:87f2f5183dfb	749	#define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	750	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	751	SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	115:87f2f5183dfb	752	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	753	tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto	115:87f2f5183dfb	754	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	755	} while(0)
Kojto	115:87f2f5183dfb	756
Kojto	115:87f2f5183dfb	757	#define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto	115:87f2f5183dfb	758	#define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto	115:87f2f5183dfb	759	#endif /* STM32F756x */
Kojto	116:c0f6e94411f5	760
Kojto	115:87f2f5183dfb	761	/** @brief Enables or disables the AHB3 peripheral clock.
Kojto	115:87f2f5183dfb	762	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	763	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	764	* using it.
Kojto	115:87f2f5183dfb	765	*/
Kojto	115:87f2f5183dfb	766	#define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	767	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	768	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	115:87f2f5183dfb	769	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	770	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto	115:87f2f5183dfb	771	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	772	} while(0)
Kojto	115:87f2f5183dfb	773
Kojto	115:87f2f5183dfb	774	#define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	775	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	776	SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	115:87f2f5183dfb	777	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	778	tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto	115:87f2f5183dfb	779	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	780	} while(0)
Kojto	115:87f2f5183dfb	781
Kojto	115:87f2f5183dfb	782	#define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto	115:87f2f5183dfb	783	#define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto	115:87f2f5183dfb	784
Kojto	115:87f2f5183dfb	785	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	115:87f2f5183dfb	786	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	787	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	788	* using it.
Kojto	115:87f2f5183dfb	789	*/
Kojto	115:87f2f5183dfb	790	#define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	791	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	792	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	115:87f2f5183dfb	793	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	794	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto	115:87f2f5183dfb	795	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	796	} while(0)
Kojto	115:87f2f5183dfb	797
Kojto	115:87f2f5183dfb	798	#define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	799	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	800	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	115:87f2f5183dfb	801	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	802	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto	115:87f2f5183dfb	803	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	804	} while(0)
Kojto	115:87f2f5183dfb	805
Kojto	115:87f2f5183dfb	806	#define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	807	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	808	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	115:87f2f5183dfb	809	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	810	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto	115:87f2f5183dfb	811	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	812	} while(0)
Kojto	115:87f2f5183dfb	813
Kojto	115:87f2f5183dfb	814	#define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	815	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	816	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto	115:87f2f5183dfb	817	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	818	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto	115:87f2f5183dfb	819	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	820	} while(0)
Kojto	115:87f2f5183dfb	821
Kojto	115:87f2f5183dfb	822	#define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	823	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	824	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	115:87f2f5183dfb	825	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	826	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto	115:87f2f5183dfb	827	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	828	} while(0)
Kojto	115:87f2f5183dfb	829
Kojto	115:87f2f5183dfb	830	#define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	831	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	832	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	115:87f2f5183dfb	833	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	834	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto	115:87f2f5183dfb	835	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	836	} while(0)
Kojto	115:87f2f5183dfb	837
Kojto	115:87f2f5183dfb	838	#define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	839	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	840	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	115:87f2f5183dfb	841	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	842	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto	115:87f2f5183dfb	843	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	844	} while(0)
Kojto	115:87f2f5183dfb	845
Kojto	115:87f2f5183dfb	846	#define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	847	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	848	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	115:87f2f5183dfb	849	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	850	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto	115:87f2f5183dfb	851	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	852	} while(0)
Kojto	115:87f2f5183dfb	853
Kojto	115:87f2f5183dfb	854	#define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	855	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	856	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	115:87f2f5183dfb	857	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	858	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto	115:87f2f5183dfb	859	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	860	} while(0)
Kojto	115:87f2f5183dfb	861
Kojto	115:87f2f5183dfb	862	#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	863	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	864	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	115:87f2f5183dfb	865	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	866	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto	115:87f2f5183dfb	867	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	868	} while(0)
Kojto	115:87f2f5183dfb	869
Kojto	115:87f2f5183dfb	870	#define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	871	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	872	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	115:87f2f5183dfb	873	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	874	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto	115:87f2f5183dfb	875	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	876	} while(0)
Kojto	115:87f2f5183dfb	877
Kojto	115:87f2f5183dfb	878	#define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	879	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	880	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	115:87f2f5183dfb	881	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	882	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto	115:87f2f5183dfb	883	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	884	} while(0)
Kojto	115:87f2f5183dfb	885
Kojto	115:87f2f5183dfb	886	#define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	887	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	888	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	115:87f2f5183dfb	889	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	890	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto	115:87f2f5183dfb	891	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	892	} while(0)
Kojto	115:87f2f5183dfb	893
Kojto	115:87f2f5183dfb	894	#define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	895	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	896	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	115:87f2f5183dfb	897	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	898	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto	115:87f2f5183dfb	899	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	900	} while(0)
Kojto	115:87f2f5183dfb	901
Kojto	115:87f2f5183dfb	902	#define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	903	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	904	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	115:87f2f5183dfb	905	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	906	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto	115:87f2f5183dfb	907	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	908	} while(0)
Kojto	115:87f2f5183dfb	909
Kojto	115:87f2f5183dfb	910	#define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	911	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	912	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	115:87f2f5183dfb	913	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	914	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto	115:87f2f5183dfb	915	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	916	} while(0)
Kojto	115:87f2f5183dfb	917
Kojto	115:87f2f5183dfb	918	#define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	919	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	920	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	115:87f2f5183dfb	921	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	922	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto	115:87f2f5183dfb	923	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	924	} while(0)
Kojto	115:87f2f5183dfb	925
Kojto	115:87f2f5183dfb	926	#define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	927	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	928	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	115:87f2f5183dfb	929	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	930	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto	115:87f2f5183dfb	931	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	932	} while(0)
Kojto	115:87f2f5183dfb	933
Kojto	115:87f2f5183dfb	934	#define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	935	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	936	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	115:87f2f5183dfb	937	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	938	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto	115:87f2f5183dfb	939	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	940	} while(0)
Kojto	115:87f2f5183dfb	941
Kojto	115:87f2f5183dfb	942	#define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	943	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	944	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	115:87f2f5183dfb	945	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	946	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto	115:87f2f5183dfb	947	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	948	} while(0)
Kojto	115:87f2f5183dfb	949
Kojto	115:87f2f5183dfb	950	#define __HAL_RCC_I2C4_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	951	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	952	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
Kojto	115:87f2f5183dfb	953	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	954	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
Kojto	115:87f2f5183dfb	955	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	956	} while(0)
Kojto	115:87f2f5183dfb	957
Kojto	115:87f2f5183dfb	958	#define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	959	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	960	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	115:87f2f5183dfb	961	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	962	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto	115:87f2f5183dfb	963	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	964	} while(0)
Kojto	115:87f2f5183dfb	965
Kojto	115:87f2f5183dfb	966	#define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	967	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	968	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	115:87f2f5183dfb	969	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	970	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto	115:87f2f5183dfb	971	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	972	} while(0)
Kojto	115:87f2f5183dfb	973
Kojto	115:87f2f5183dfb	974	#define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	975	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	976	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	115:87f2f5183dfb	977	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	978	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto	115:87f2f5183dfb	979	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	980	} while(0)
Kojto	115:87f2f5183dfb	981
Kojto	115:87f2f5183dfb	982	#define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	983	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	984	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	115:87f2f5183dfb	985	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	986	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto	115:87f2f5183dfb	987	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	988	} while(0)
Kojto	115:87f2f5183dfb	989
Kojto	115:87f2f5183dfb	990	#define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	991	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	992	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	115:87f2f5183dfb	993	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	994	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto	115:87f2f5183dfb	995	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	996	} while(0)
Kojto	115:87f2f5183dfb	997
Kojto	115:87f2f5183dfb	998	#define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	999	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1000	SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	115:87f2f5183dfb	1001	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1002	tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto	115:87f2f5183dfb	1003	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1004	} while(0)
Kojto	115:87f2f5183dfb	1005
Kojto	115:87f2f5183dfb	1006	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	115:87f2f5183dfb	1007	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	115:87f2f5183dfb	1008	#define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	115:87f2f5183dfb	1009	#define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto	115:87f2f5183dfb	1010	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	115:87f2f5183dfb	1011	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	115:87f2f5183dfb	1012	#define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	115:87f2f5183dfb	1013	#define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	115:87f2f5183dfb	1014	#define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	115:87f2f5183dfb	1015	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
Kojto	115:87f2f5183dfb	1016	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	115:87f2f5183dfb	1017	#define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	115:87f2f5183dfb	1018	#define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto	115:87f2f5183dfb	1019	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	115:87f2f5183dfb	1020	#define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	115:87f2f5183dfb	1021	#define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	115:87f2f5183dfb	1022	#define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	115:87f2f5183dfb	1023	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	115:87f2f5183dfb	1024	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	115:87f2f5183dfb	1025	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	115:87f2f5183dfb	1026	#define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
Kojto	115:87f2f5183dfb	1027	#define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto	115:87f2f5183dfb	1028	#define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto	115:87f2f5183dfb	1029	#define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	115:87f2f5183dfb	1030	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	115:87f2f5183dfb	1031	#define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto	115:87f2f5183dfb	1032	#define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto	115:87f2f5183dfb	1033
Kojto	115:87f2f5183dfb	1034	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	115:87f2f5183dfb	1035	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	1036	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	1037	* using it.
Kojto	115:87f2f5183dfb	1038	*/
Kojto	115:87f2f5183dfb	1039	#define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1040	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1041	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	115:87f2f5183dfb	1042	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1043	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto	115:87f2f5183dfb	1044	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1045	} while(0)
Kojto	115:87f2f5183dfb	1046
Kojto	115:87f2f5183dfb	1047	#define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1048	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1049	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	115:87f2f5183dfb	1050	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1051	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto	115:87f2f5183dfb	1052	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1053	} while(0)
Kojto	115:87f2f5183dfb	1054
Kojto	115:87f2f5183dfb	1055	#define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1056	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1057	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	115:87f2f5183dfb	1058	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1059	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto	115:87f2f5183dfb	1060	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1061	} while(0)
Kojto	115:87f2f5183dfb	1062
Kojto	115:87f2f5183dfb	1063	#define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1064	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1065	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	115:87f2f5183dfb	1066	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1067	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto	115:87f2f5183dfb	1068	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1069	} while(0)
Kojto	115:87f2f5183dfb	1070
Kojto	115:87f2f5183dfb	1071	#define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1072	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1073	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	115:87f2f5183dfb	1074	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1075	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto	115:87f2f5183dfb	1076	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1077	} while(0)
Kojto	115:87f2f5183dfb	1078
Kojto	115:87f2f5183dfb	1079	#define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1080	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1081	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	115:87f2f5183dfb	1082	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1083	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto	115:87f2f5183dfb	1084	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1085	} while(0)
Kojto	115:87f2f5183dfb	1086
Kojto	115:87f2f5183dfb	1087	#define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1088	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1089	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	115:87f2f5183dfb	1090	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1091	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto	115:87f2f5183dfb	1092	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1093	} while(0)
Kojto	115:87f2f5183dfb	1094
Kojto	115:87f2f5183dfb	1095	#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1096	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1097	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
Kojto	115:87f2f5183dfb	1098	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1099	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
Kojto	115:87f2f5183dfb	1100	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1101	} while(0)
Kojto	115:87f2f5183dfb	1102
Kojto	115:87f2f5183dfb	1103	#define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1104	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1105	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	115:87f2f5183dfb	1106	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1107	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto	115:87f2f5183dfb	1108	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1109	} while(0)
Kojto	115:87f2f5183dfb	1110
Kojto	115:87f2f5183dfb	1111	#define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1112	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1113	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	115:87f2f5183dfb	1114	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1115	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto	115:87f2f5183dfb	1116	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1117	} while(0)
Kojto	115:87f2f5183dfb	1118
Kojto	115:87f2f5183dfb	1119	#define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1120	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1121	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto	115:87f2f5183dfb	1122	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1123	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto	115:87f2f5183dfb	1124	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1125	} while(0)
Kojto	115:87f2f5183dfb	1126
Kojto	115:87f2f5183dfb	1127	#define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1128	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1129	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	115:87f2f5183dfb	1130	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1131	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto	115:87f2f5183dfb	1132	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1133	} while(0)
Kojto	115:87f2f5183dfb	1134
Kojto	115:87f2f5183dfb	1135	#define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1136	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1137	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto	115:87f2f5183dfb	1138	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1139	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto	115:87f2f5183dfb	1140	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1141	} while(0)
Kojto	115:87f2f5183dfb	1142
Kojto	115:87f2f5183dfb	1143	#define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1144	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1145	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	115:87f2f5183dfb	1146	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1147	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto	115:87f2f5183dfb	1148	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1149	} while(0)
Kojto	115:87f2f5183dfb	1150
Kojto	115:87f2f5183dfb	1151	#define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1152	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1153	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	115:87f2f5183dfb	1154	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1155	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto	115:87f2f5183dfb	1156	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1157	} while(0)
Kojto	115:87f2f5183dfb	1158
Kojto	115:87f2f5183dfb	1159	#define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1160	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1161	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	115:87f2f5183dfb	1162	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1163	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto	115:87f2f5183dfb	1164	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1165	} while(0)
Kojto	115:87f2f5183dfb	1166
Kojto	115:87f2f5183dfb	1167	#define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1168	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1169	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	115:87f2f5183dfb	1170	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1171	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto	115:87f2f5183dfb	1172	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1173	} while(0)
Kojto	115:87f2f5183dfb	1174
Kojto	116:c0f6e94411f5	1175	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1176	#define __HAL_RCC_LTDC_CLK_ENABLE() do { \
Kojto	116:c0f6e94411f5	1177	__IO uint32_t tmpreg = 0x00; \
Kojto	115:87f2f5183dfb	1178	SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	115:87f2f5183dfb	1179	/* Delay after an RCC peripheral clock enabling */ \
Kojto	115:87f2f5183dfb	1180	tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto	115:87f2f5183dfb	1181	UNUSED(tmpreg); \
Kojto	115:87f2f5183dfb	1182	} while(0)
Kojto	116:c0f6e94411f5	1183	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	116:c0f6e94411f5	1184
Kojto	115:87f2f5183dfb	1185	#define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	115:87f2f5183dfb	1186	#define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	115:87f2f5183dfb	1187	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	115:87f2f5183dfb	1188	#define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	115:87f2f5183dfb	1189	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	115:87f2f5183dfb	1190	#define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto	115:87f2f5183dfb	1191	#define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto	116:c0f6e94411f5	1192	#define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
Kojto	115:87f2f5183dfb	1193	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	115:87f2f5183dfb	1194	#define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	115:87f2f5183dfb	1195	#define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto	115:87f2f5183dfb	1196	#define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	115:87f2f5183dfb	1197	#define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto	115:87f2f5183dfb	1198	#define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto	115:87f2f5183dfb	1199	#define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto	115:87f2f5183dfb	1200	#define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto	115:87f2f5183dfb	1201	#define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto	116:c0f6e94411f5	1202	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1203	#define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto	116:c0f6e94411f5	1204	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	115:87f2f5183dfb	1205	/**
Kojto	115:87f2f5183dfb	1206	* @}
Kojto	115:87f2f5183dfb	1207	*/
Kojto	115:87f2f5183dfb	1208
Kojto	115:87f2f5183dfb	1209
Kojto	115:87f2f5183dfb	1210	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
Kojto	115:87f2f5183dfb	1211	* @brief Get the enable or disable status of the AHB/APB peripheral clock.
Kojto	115:87f2f5183dfb	1212	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	1213	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	1214	* using it.
Kojto	115:87f2f5183dfb	1215	* @{
Kojto	115:87f2f5183dfb	1216	*/
Kojto	115:87f2f5183dfb	1217
Kojto	115:87f2f5183dfb	1218	/** @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto	115:87f2f5183dfb	1219	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	1220	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	1221	* using it.
Kojto	115:87f2f5183dfb	1222	*/
Kojto	115:87f2f5183dfb	1223	#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto	115:87f2f5183dfb	1224	#define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
Kojto	115:87f2f5183dfb	1225	#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
Kojto	115:87f2f5183dfb	1226	#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
Kojto	115:87f2f5183dfb	1227	#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto	115:87f2f5183dfb	1228	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto	115:87f2f5183dfb	1229	#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
Kojto	115:87f2f5183dfb	1230	#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
Kojto	115:87f2f5183dfb	1231	#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
Kojto	115:87f2f5183dfb	1232	#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto	115:87f2f5183dfb	1233	#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto	115:87f2f5183dfb	1234	#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto	115:87f2f5183dfb	1235	#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto	115:87f2f5183dfb	1236	#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
Kojto	115:87f2f5183dfb	1237	#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
Kojto	115:87f2f5183dfb	1238	#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
Kojto	115:87f2f5183dfb	1239	#define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
Kojto	115:87f2f5183dfb	1240
Kojto	115:87f2f5183dfb	1241	#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto	115:87f2f5183dfb	1242	#define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
Kojto	115:87f2f5183dfb	1243	#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
Kojto	115:87f2f5183dfb	1244	#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
Kojto	115:87f2f5183dfb	1245	#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto	115:87f2f5183dfb	1246	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
Kojto	115:87f2f5183dfb	1247	#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
Kojto	115:87f2f5183dfb	1248	#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
Kojto	115:87f2f5183dfb	1249	#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
Kojto	115:87f2f5183dfb	1250	#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto	115:87f2f5183dfb	1251	#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto	115:87f2f5183dfb	1252	#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto	115:87f2f5183dfb	1253	#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto	115:87f2f5183dfb	1254	#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
Kojto	115:87f2f5183dfb	1255	#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
Kojto	115:87f2f5183dfb	1256	#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
Kojto	115:87f2f5183dfb	1257	#define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
Kojto	115:87f2f5183dfb	1258	/**
Kojto	115:87f2f5183dfb	1259	* @brief Enable ETHERNET clock.
Kojto	115:87f2f5183dfb	1260	*/
Kojto	115:87f2f5183dfb	1261	#define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Kojto	115:87f2f5183dfb	1262	#define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
Kojto	115:87f2f5183dfb	1263	#define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
Kojto	115:87f2f5183dfb	1264	#define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
Kojto	115:87f2f5183dfb	1265	#define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
Kojto	115:87f2f5183dfb	1266	__HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
Kojto	115:87f2f5183dfb	1267	__HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
Kojto	115:87f2f5183dfb	1268
Kojto	115:87f2f5183dfb	1269	/**
Kojto	115:87f2f5183dfb	1270	* @brief Disable ETHERNET clock.
Kojto	115:87f2f5183dfb	1271	*/
Kojto	115:87f2f5183dfb	1272	#define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Kojto	115:87f2f5183dfb	1273	#define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
Kojto	115:87f2f5183dfb	1274	#define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
Kojto	115:87f2f5183dfb	1275	#define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
Kojto	115:87f2f5183dfb	1276	#define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
Kojto	115:87f2f5183dfb	1277	__HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
Kojto	115:87f2f5183dfb	1278	__HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
Kojto	115:87f2f5183dfb	1279
Kojto	115:87f2f5183dfb	1280	/** @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto	115:87f2f5183dfb	1281	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	1282	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	1283	* using it.
Kojto	115:87f2f5183dfb	1284	*/
Kojto	115:87f2f5183dfb	1285	#define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto	115:87f2f5183dfb	1286	#define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto	115:87f2f5183dfb	1287	#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto	116:c0f6e94411f5	1288
Kojto	115:87f2f5183dfb	1289	#define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto	115:87f2f5183dfb	1290	#define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto	115:87f2f5183dfb	1291	#define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto	115:87f2f5183dfb	1292
Kojto	115:87f2f5183dfb	1293	#if defined(STM32F756xx)
Kojto	115:87f2f5183dfb	1294	#define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
Kojto	115:87f2f5183dfb	1295	#define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
Kojto	115:87f2f5183dfb	1296	#define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
Kojto	115:87f2f5183dfb	1297	#define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
Kojto	116:c0f6e94411f5	1298	#endif /* STM32F756xx */
Kojto	115:87f2f5183dfb	1299
Kojto	115:87f2f5183dfb	1300	/** @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto	115:87f2f5183dfb	1301	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	1302	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	1303	* using it.
Kojto	115:87f2f5183dfb	1304	*/
Kojto	115:87f2f5183dfb	1305	#define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Kojto	115:87f2f5183dfb	1306	#define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto	115:87f2f5183dfb	1307
Kojto	115:87f2f5183dfb	1308	#define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Kojto	115:87f2f5183dfb	1309	#define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto	115:87f2f5183dfb	1310
Kojto	115:87f2f5183dfb	1311	/** @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto	115:87f2f5183dfb	1312	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	1313	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	1314	* using it.
Kojto	115:87f2f5183dfb	1315	*/
Kojto	115:87f2f5183dfb	1316	#define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto	115:87f2f5183dfb	1317	#define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto	115:87f2f5183dfb	1318	#define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto	115:87f2f5183dfb	1319	#define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto	115:87f2f5183dfb	1320	#define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto	115:87f2f5183dfb	1321	#define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto	115:87f2f5183dfb	1322	#define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto	115:87f2f5183dfb	1323	#define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto	115:87f2f5183dfb	1324	#define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto	115:87f2f5183dfb	1325	#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
Kojto	115:87f2f5183dfb	1326	#define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto	115:87f2f5183dfb	1327	#define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto	115:87f2f5183dfb	1328	#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
Kojto	115:87f2f5183dfb	1329	#define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto	115:87f2f5183dfb	1330	#define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto	115:87f2f5183dfb	1331	#define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto	115:87f2f5183dfb	1332	#define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto	115:87f2f5183dfb	1333	#define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto	115:87f2f5183dfb	1334	#define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto	115:87f2f5183dfb	1335	#define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto	115:87f2f5183dfb	1336	#define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
Kojto	115:87f2f5183dfb	1337	#define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto	115:87f2f5183dfb	1338	#define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto	115:87f2f5183dfb	1339	#define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto	115:87f2f5183dfb	1340	#define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto	115:87f2f5183dfb	1341	#define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
Kojto	115:87f2f5183dfb	1342	#define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
Kojto	115:87f2f5183dfb	1343
Kojto	115:87f2f5183dfb	1344	#define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto	115:87f2f5183dfb	1345	#define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto	115:87f2f5183dfb	1346	#define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto	115:87f2f5183dfb	1347	#define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto	115:87f2f5183dfb	1348	#define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto	115:87f2f5183dfb	1349	#define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto	115:87f2f5183dfb	1350	#define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto	115:87f2f5183dfb	1351	#define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto	115:87f2f5183dfb	1352	#define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto	115:87f2f5183dfb	1353	#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
Kojto	115:87f2f5183dfb	1354	#define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto	115:87f2f5183dfb	1355	#define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto	115:87f2f5183dfb	1356	#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
Kojto	115:87f2f5183dfb	1357	#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto	115:87f2f5183dfb	1358	#define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto	115:87f2f5183dfb	1359	#define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto	115:87f2f5183dfb	1360	#define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto	115:87f2f5183dfb	1361	#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto	115:87f2f5183dfb	1362	#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto	115:87f2f5183dfb	1363	#define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto	115:87f2f5183dfb	1364	#define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
Kojto	115:87f2f5183dfb	1365	#define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto	115:87f2f5183dfb	1366	#define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto	115:87f2f5183dfb	1367	#define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto	115:87f2f5183dfb	1368	#define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto	115:87f2f5183dfb	1369	#define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
Kojto	115:87f2f5183dfb	1370	#define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
Kojto	115:87f2f5183dfb	1371
Kojto	115:87f2f5183dfb	1372	/** @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto	115:87f2f5183dfb	1373	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	115:87f2f5183dfb	1374	* is disabled and the application software has to enable this clock before
Kojto	115:87f2f5183dfb	1375	* using it.
Kojto	115:87f2f5183dfb	1376	*/
Kojto	115:87f2f5183dfb	1377	#define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto	115:87f2f5183dfb	1378	#define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto	115:87f2f5183dfb	1379	#define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto	115:87f2f5183dfb	1380	#define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto	115:87f2f5183dfb	1381	#define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto	115:87f2f5183dfb	1382	#define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto	115:87f2f5183dfb	1383	#define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto	115:87f2f5183dfb	1384	#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
Kojto	115:87f2f5183dfb	1385	#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto	115:87f2f5183dfb	1386	#define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto	115:87f2f5183dfb	1387	#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Kojto	115:87f2f5183dfb	1388	#define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto	115:87f2f5183dfb	1389	#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Kojto	115:87f2f5183dfb	1390	#define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto	115:87f2f5183dfb	1391	#define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
Kojto	115:87f2f5183dfb	1392	#define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
Kojto	115:87f2f5183dfb	1393	#define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
Kojto	116:c0f6e94411f5	1394	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1395	#define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
Kojto	116:c0f6e94411f5	1396	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	115:87f2f5183dfb	1397	#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto	115:87f2f5183dfb	1398	#define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto	115:87f2f5183dfb	1399	#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto	115:87f2f5183dfb	1400	#define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto	115:87f2f5183dfb	1401	#define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto	115:87f2f5183dfb	1402	#define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto	115:87f2f5183dfb	1403	#define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto	115:87f2f5183dfb	1404	#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
Kojto	115:87f2f5183dfb	1405	#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto	115:87f2f5183dfb	1406	#define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto	115:87f2f5183dfb	1407	#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Kojto	115:87f2f5183dfb	1408	#define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto	115:87f2f5183dfb	1409	#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Kojto	115:87f2f5183dfb	1410	#define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto	115:87f2f5183dfb	1411	#define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
Kojto	115:87f2f5183dfb	1412	#define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
Kojto	115:87f2f5183dfb	1413	#define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
Kojto	116:c0f6e94411f5	1414	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1415	#define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
Kojto	116:c0f6e94411f5	1416	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	115:87f2f5183dfb	1417	/**
Kojto	115:87f2f5183dfb	1418	* @}
Kojto	115:87f2f5183dfb	1419	*/
Kojto	115:87f2f5183dfb	1420
Kojto	115:87f2f5183dfb	1421	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto	115:87f2f5183dfb	1422	* @brief Forces or releases AHB/APB peripheral reset.
Kojto	115:87f2f5183dfb	1423	* @{
Kojto	115:87f2f5183dfb	1424	*/
Kojto	115:87f2f5183dfb	1425
Kojto	115:87f2f5183dfb	1426	/** @brief Force or release AHB1 peripheral reset.
Kojto	115:87f2f5183dfb	1427	*/
Kojto	115:87f2f5183dfb	1428	#define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
Kojto	115:87f2f5183dfb	1429	#define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2DRST))
Kojto	115:87f2f5183dfb	1430	#define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ETHMACRST))
Kojto	115:87f2f5183dfb	1431	#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_OTGHRST))
Kojto	115:87f2f5183dfb	1432	#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
Kojto	115:87f2f5183dfb	1433	#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
Kojto	115:87f2f5183dfb	1434	#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
Kojto	115:87f2f5183dfb	1435	#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
Kojto	115:87f2f5183dfb	1436	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
Kojto	115:87f2f5183dfb	1437	#define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOFRST))
Kojto	115:87f2f5183dfb	1438	#define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOGRST))
Kojto	115:87f2f5183dfb	1439	#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
Kojto	115:87f2f5183dfb	1440	#define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOIRST))
Kojto	115:87f2f5183dfb	1441	#define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOJRST))
Kojto	115:87f2f5183dfb	1442	#define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOKRST))
Kojto	115:87f2f5183dfb	1443
Kojto	115:87f2f5183dfb	1444	#define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto	115:87f2f5183dfb	1445	#define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto	115:87f2f5183dfb	1446	#define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto	115:87f2f5183dfb	1447	#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto	115:87f2f5183dfb	1448	#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto	115:87f2f5183dfb	1449	#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto	115:87f2f5183dfb	1450	#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto	115:87f2f5183dfb	1451	#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto	115:87f2f5183dfb	1452	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto	115:87f2f5183dfb	1453	#define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto	115:87f2f5183dfb	1454	#define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto	115:87f2f5183dfb	1455	#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto	115:87f2f5183dfb	1456	#define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto	115:87f2f5183dfb	1457	#define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto	115:87f2f5183dfb	1458	#define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto	115:87f2f5183dfb	1459
Kojto	115:87f2f5183dfb	1460	/** @brief Force or release AHB2 peripheral reset.
Kojto	115:87f2f5183dfb	1461	*/
Kojto	115:87f2f5183dfb	1462	#define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto	115:87f2f5183dfb	1463	#define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))
Kojto	115:87f2f5183dfb	1464	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
Kojto	115:87f2f5183dfb	1465	#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
Kojto	115:87f2f5183dfb	1466
Kojto	115:87f2f5183dfb	1467	#define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto	115:87f2f5183dfb	1468	#define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto	115:87f2f5183dfb	1469	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto	115:87f2f5183dfb	1470	#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto	115:87f2f5183dfb	1471
Kojto	115:87f2f5183dfb	1472	#if defined(STM32F756xx)
Kojto	115:87f2f5183dfb	1473	#define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_CRYPRST))
Kojto	115:87f2f5183dfb	1474	#define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_HASHRST))
Kojto	115:87f2f5183dfb	1475	#define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto	115:87f2f5183dfb	1476	#define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto	115:87f2f5183dfb	1477	#endif /* STM32F756xx */
Kojto	115:87f2f5183dfb	1478
Kojto	115:87f2f5183dfb	1479	/** @brief Force or release AHB3 peripheral reset
Kojto	115:87f2f5183dfb	1480	*/
Kojto	115:87f2f5183dfb	1481	#define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto	115:87f2f5183dfb	1482	#define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))
Kojto	115:87f2f5183dfb	1483	#define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_QSPIRST))
Kojto	115:87f2f5183dfb	1484
Kojto	115:87f2f5183dfb	1485	#define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto	115:87f2f5183dfb	1486	#define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto	115:87f2f5183dfb	1487	#define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto	115:87f2f5183dfb	1488
Kojto	115:87f2f5183dfb	1489	/** @brief Force or release APB1 peripheral reset.
Kojto	115:87f2f5183dfb	1490	*/
Kojto	115:87f2f5183dfb	1491	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	115:87f2f5183dfb	1492	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	115:87f2f5183dfb	1493	#define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	115:87f2f5183dfb	1494	#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
Kojto	115:87f2f5183dfb	1495	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	115:87f2f5183dfb	1496	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	115:87f2f5183dfb	1497	#define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	115:87f2f5183dfb	1498	#define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	115:87f2f5183dfb	1499	#define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	115:87f2f5183dfb	1500	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	115:87f2f5183dfb	1501	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	115:87f2f5183dfb	1502	#define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	115:87f2f5183dfb	1503	#define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPDIFRXRST))
Kojto	115:87f2f5183dfb	1504	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	115:87f2f5183dfb	1505	#define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	115:87f2f5183dfb	1506	#define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	115:87f2f5183dfb	1507	#define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	115:87f2f5183dfb	1508	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	115:87f2f5183dfb	1509	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	115:87f2f5183dfb	1510	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	115:87f2f5183dfb	1511	#define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C4RST))
Kojto	115:87f2f5183dfb	1512	#define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN1RST))
Kojto	115:87f2f5183dfb	1513	#define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CAN2RST))
Kojto	115:87f2f5183dfb	1514	#define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	115:87f2f5183dfb	1515	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	115:87f2f5183dfb	1516	#define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART7RST))
Kojto	115:87f2f5183dfb	1517	#define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART8RST))
Kojto	115:87f2f5183dfb	1518
Kojto	115:87f2f5183dfb	1519	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	115:87f2f5183dfb	1520	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	115:87f2f5183dfb	1521	#define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	115:87f2f5183dfb	1522	#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto	115:87f2f5183dfb	1523	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	115:87f2f5183dfb	1524	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	115:87f2f5183dfb	1525	#define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	115:87f2f5183dfb	1526	#define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	115:87f2f5183dfb	1527	#define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	115:87f2f5183dfb	1528	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
Kojto	115:87f2f5183dfb	1529	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	115:87f2f5183dfb	1530	#define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	115:87f2f5183dfb	1531	#define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto	115:87f2f5183dfb	1532	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	115:87f2f5183dfb	1533	#define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	115:87f2f5183dfb	1534	#define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	115:87f2f5183dfb	1535	#define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	115:87f2f5183dfb	1536	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	115:87f2f5183dfb	1537	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	115:87f2f5183dfb	1538	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	115:87f2f5183dfb	1539	#define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
Kojto	115:87f2f5183dfb	1540	#define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto	115:87f2f5183dfb	1541	#define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto	115:87f2f5183dfb	1542	#define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	115:87f2f5183dfb	1543	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	115:87f2f5183dfb	1544	#define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto	115:87f2f5183dfb	1545	#define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto	115:87f2f5183dfb	1546
Kojto	115:87f2f5183dfb	1547	/** @brief Force or release APB2 peripheral reset.
Kojto	115:87f2f5183dfb	1548	*/
Kojto	115:87f2f5183dfb	1549	#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	115:87f2f5183dfb	1550	#define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	115:87f2f5183dfb	1551	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	115:87f2f5183dfb	1552	#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	115:87f2f5183dfb	1553	#define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
Kojto	115:87f2f5183dfb	1554	#define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDMMC1RST))
Kojto	115:87f2f5183dfb	1555	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	115:87f2f5183dfb	1556	#define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	115:87f2f5183dfb	1557	#define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
Kojto	115:87f2f5183dfb	1558	#define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	115:87f2f5183dfb	1559	#define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
Kojto	115:87f2f5183dfb	1560	#define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI5RST))
Kojto	115:87f2f5183dfb	1561	#define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI6RST))
Kojto	115:87f2f5183dfb	1562	#define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI1RST))
Kojto	115:87f2f5183dfb	1563	#define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SAI2RST))
Kojto	116:c0f6e94411f5	1564	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1565	#define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_LTDCRST))
Kojto	116:c0f6e94411f5	1566	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	115:87f2f5183dfb	1567
Kojto	115:87f2f5183dfb	1568	#define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	115:87f2f5183dfb	1569	#define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	115:87f2f5183dfb	1570	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	115:87f2f5183dfb	1571	#define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	115:87f2f5183dfb	1572	#define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto	115:87f2f5183dfb	1573	#define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
Kojto	115:87f2f5183dfb	1574	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	115:87f2f5183dfb	1575	#define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	115:87f2f5183dfb	1576	#define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto	115:87f2f5183dfb	1577	#define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	115:87f2f5183dfb	1578	#define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto	115:87f2f5183dfb	1579	#define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto	115:87f2f5183dfb	1580	#define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto	115:87f2f5183dfb	1581	#define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto	115:87f2f5183dfb	1582	#define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto	116:c0f6e94411f5	1583	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1584	#define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto	116:c0f6e94411f5	1585	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	116:c0f6e94411f5	1586
Kojto	115:87f2f5183dfb	1587	/**
Kojto	115:87f2f5183dfb	1588	* @}
Kojto	115:87f2f5183dfb	1589	*/
Kojto	115:87f2f5183dfb	1590
Kojto	115:87f2f5183dfb	1591	/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
Kojto	115:87f2f5183dfb	1592	* @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1593	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1594	* power consumption.
Kojto	115:87f2f5183dfb	1595	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1596	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1597	* @{
Kojto	115:87f2f5183dfb	1598	*/
Kojto	115:87f2f5183dfb	1599
Kojto	115:87f2f5183dfb	1600	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1601	*/
Kojto	115:87f2f5183dfb	1602	#define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
Kojto	115:87f2f5183dfb	1603	#define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_AXILPEN))
Kojto	115:87f2f5183dfb	1604	#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto	115:87f2f5183dfb	1605	#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto	115:87f2f5183dfb	1606	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	115:87f2f5183dfb	1607	#define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DTCMLPEN))
Kojto	115:87f2f5183dfb	1608	#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
Kojto	115:87f2f5183dfb	1609	#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto	115:87f2f5183dfb	1610	#define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto	115:87f2f5183dfb	1611	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	115:87f2f5183dfb	1612	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	115:87f2f5183dfb	1613	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	115:87f2f5183dfb	1614	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto	115:87f2f5183dfb	1615	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	115:87f2f5183dfb	1616	#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
Kojto	115:87f2f5183dfb	1617	#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto	115:87f2f5183dfb	1618	#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto	115:87f2f5183dfb	1619	#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
Kojto	115:87f2f5183dfb	1620	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
Kojto	115:87f2f5183dfb	1621	#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto	115:87f2f5183dfb	1622	#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto	115:87f2f5183dfb	1623	#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto	115:87f2f5183dfb	1624	#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOILPEN))
Kojto	115:87f2f5183dfb	1625	#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto	115:87f2f5183dfb	1626	#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto	115:87f2f5183dfb	1627
Kojto	115:87f2f5183dfb	1628	#define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto	115:87f2f5183dfb	1629	#define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
Kojto	115:87f2f5183dfb	1630	#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto	115:87f2f5183dfb	1631	#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto	115:87f2f5183dfb	1632	#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto	115:87f2f5183dfb	1633	#define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
Kojto	115:87f2f5183dfb	1634	#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto	115:87f2f5183dfb	1635	#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto	115:87f2f5183dfb	1636	#define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto	115:87f2f5183dfb	1637	#define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto	115:87f2f5183dfb	1638	#define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto	115:87f2f5183dfb	1639	#define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto	115:87f2f5183dfb	1640	#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto	115:87f2f5183dfb	1641	#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto	115:87f2f5183dfb	1642	#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto	115:87f2f5183dfb	1643	#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto	115:87f2f5183dfb	1644	#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto	115:87f2f5183dfb	1645	#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto	115:87f2f5183dfb	1646	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto	115:87f2f5183dfb	1647	#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto	115:87f2f5183dfb	1648	#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto	115:87f2f5183dfb	1649	#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto	115:87f2f5183dfb	1650	#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto	115:87f2f5183dfb	1651	#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto	115:87f2f5183dfb	1652	#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto	115:87f2f5183dfb	1653
Kojto	115:87f2f5183dfb	1654	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1655	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1656	* power consumption.
Kojto	115:87f2f5183dfb	1657	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1658	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1659	*/
Kojto	115:87f2f5183dfb	1660	#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
Kojto	115:87f2f5183dfb	1661	#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto	116:c0f6e94411f5	1662
Kojto	115:87f2f5183dfb	1663	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
Kojto	115:87f2f5183dfb	1664	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto	115:87f2f5183dfb	1665
Kojto	115:87f2f5183dfb	1666	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto	115:87f2f5183dfb	1667	#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto	115:87f2f5183dfb	1668
Kojto	115:87f2f5183dfb	1669	#if defined(STM32F756xx)
Kojto	115:87f2f5183dfb	1670	#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_CRYPLPEN))
Kojto	115:87f2f5183dfb	1671	#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_HASHLPEN))
Kojto	115:87f2f5183dfb	1672
Kojto	115:87f2f5183dfb	1673	#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto	115:87f2f5183dfb	1674	#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto	115:87f2f5183dfb	1675	#endif /* STM32F756xx */
Kojto	115:87f2f5183dfb	1676
Kojto	115:87f2f5183dfb	1677	/** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1678	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1679	* power consumption.
Kojto	115:87f2f5183dfb	1680	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1681	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1682	*/
Kojto	115:87f2f5183dfb	1683	#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))
Kojto	115:87f2f5183dfb	1684	#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto	115:87f2f5183dfb	1685
Kojto	115:87f2f5183dfb	1686	#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_QSPILPEN))
Kojto	115:87f2f5183dfb	1687	#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto	115:87f2f5183dfb	1688
Kojto	115:87f2f5183dfb	1689	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1690	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1691	* power consumption.
Kojto	115:87f2f5183dfb	1692	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1693	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1694	*/
Kojto	115:87f2f5183dfb	1695	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	115:87f2f5183dfb	1696	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	115:87f2f5183dfb	1697	#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	115:87f2f5183dfb	1698	#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
Kojto	115:87f2f5183dfb	1699	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	115:87f2f5183dfb	1700	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	115:87f2f5183dfb	1701	#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM12LPEN))
Kojto	115:87f2f5183dfb	1702	#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM13LPEN))
Kojto	115:87f2f5183dfb	1703	#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM14LPEN))
Kojto	115:87f2f5183dfb	1704	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_LPTIM1LPEN))
Kojto	115:87f2f5183dfb	1705	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
Kojto	115:87f2f5183dfb	1706	#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
Kojto	115:87f2f5183dfb	1707	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	115:87f2f5183dfb	1708	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
Kojto	115:87f2f5183dfb	1709	#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	115:87f2f5183dfb	1710	#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART4LPEN))
Kojto	115:87f2f5183dfb	1711	#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART5LPEN))
Kojto	115:87f2f5183dfb	1712	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
Kojto	115:87f2f5183dfb	1713	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
Kojto	115:87f2f5183dfb	1714	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
Kojto	115:87f2f5183dfb	1715	#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C4LPEN))
Kojto	115:87f2f5183dfb	1716	#define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN1LPEN))
Kojto	115:87f2f5183dfb	1717	#define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CAN2LPEN))
Kojto	115:87f2f5183dfb	1718	#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_CECLPEN))
Kojto	115:87f2f5183dfb	1719	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	115:87f2f5183dfb	1720	#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART7LPEN))
Kojto	115:87f2f5183dfb	1721	#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_UART8LPEN))
Kojto	115:87f2f5183dfb	1722
Kojto	115:87f2f5183dfb	1723	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	115:87f2f5183dfb	1724	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	115:87f2f5183dfb	1725	#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	115:87f2f5183dfb	1726	#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto	115:87f2f5183dfb	1727	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	115:87f2f5183dfb	1728	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	115:87f2f5183dfb	1729	#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto	115:87f2f5183dfb	1730	#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto	115:87f2f5183dfb	1731	#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto	115:87f2f5183dfb	1732	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
Kojto	115:87f2f5183dfb	1733	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto	115:87f2f5183dfb	1734	#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto	115:87f2f5183dfb	1735	#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto	115:87f2f5183dfb	1736	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto	115:87f2f5183dfb	1737	#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	115:87f2f5183dfb	1738	#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto	115:87f2f5183dfb	1739	#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto	115:87f2f5183dfb	1740	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto	115:87f2f5183dfb	1741	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto	115:87f2f5183dfb	1742	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto	115:87f2f5183dfb	1743	#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
Kojto	115:87f2f5183dfb	1744	#define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto	115:87f2f5183dfb	1745	#define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto	115:87f2f5183dfb	1746	#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto	115:87f2f5183dfb	1747	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	116:c0f6e94411f5	1748	#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto	116:c0f6e94411f5	1749	#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto	115:87f2f5183dfb	1750
Kojto	115:87f2f5183dfb	1751	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1752	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1753	* power consumption.
Kojto	115:87f2f5183dfb	1754	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1755	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1756	*/
Kojto	115:87f2f5183dfb	1757	#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
Kojto	115:87f2f5183dfb	1758	#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM8LPEN))
Kojto	115:87f2f5183dfb	1759	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
Kojto	115:87f2f5183dfb	1760	#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
Kojto	115:87f2f5183dfb	1761	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
Kojto	115:87f2f5183dfb	1762	#define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC2LPEN))
Kojto	115:87f2f5183dfb	1763	#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC3LPEN))
Kojto	115:87f2f5183dfb	1764	#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDMMC1LPEN))
Kojto	115:87f2f5183dfb	1765	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
Kojto	115:87f2f5183dfb	1766	#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
Kojto	115:87f2f5183dfb	1767	#define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
Kojto	115:87f2f5183dfb	1768	#define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	115:87f2f5183dfb	1769	#define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
Kojto	115:87f2f5183dfb	1770	#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI5LPEN))
Kojto	115:87f2f5183dfb	1771	#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI6LPEN))
Kojto	115:87f2f5183dfb	1772	#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI1LPEN))
Kojto	115:87f2f5183dfb	1773	#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SAI2LPEN))
Kojto	116:c0f6e94411f5	1774	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1775	#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_LTDCLPEN))
Kojto	116:c0f6e94411f5	1776	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	115:87f2f5183dfb	1777
Kojto	115:87f2f5183dfb	1778	#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto	115:87f2f5183dfb	1779	#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto	115:87f2f5183dfb	1780	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto	115:87f2f5183dfb	1781	#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto	115:87f2f5183dfb	1782	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto	115:87f2f5183dfb	1783	#define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto	115:87f2f5183dfb	1784	#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto	115:87f2f5183dfb	1785	#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
Kojto	115:87f2f5183dfb	1786	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto	115:87f2f5183dfb	1787	#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto	115:87f2f5183dfb	1788	#define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto	115:87f2f5183dfb	1789	#define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	115:87f2f5183dfb	1790	#define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto	115:87f2f5183dfb	1791	#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto	115:87f2f5183dfb	1792	#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto	115:87f2f5183dfb	1793	#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto	115:87f2f5183dfb	1794	#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto	116:c0f6e94411f5	1795	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1796	#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto	116:c0f6e94411f5	1797	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	116:c0f6e94411f5	1798
Kojto	115:87f2f5183dfb	1799	/**
Kojto	115:87f2f5183dfb	1800	* @}
Kojto	115:87f2f5183dfb	1801	*/
Kojto	115:87f2f5183dfb	1802
Kojto	115:87f2f5183dfb	1803	/** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
Kojto	115:87f2f5183dfb	1804	* @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1805	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1806	* power consumption.
Kojto	115:87f2f5183dfb	1807	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1808	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1809	* @{
Kojto	115:87f2f5183dfb	1810	*/
Kojto	115:87f2f5183dfb	1811
Kojto	115:87f2f5183dfb	1812	/** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1813	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1814	* power consumption.
Kojto	115:87f2f5183dfb	1815	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1816	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1817	*/
Kojto	115:87f2f5183dfb	1818	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1819	#define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
Kojto	115:87f2f5183dfb	1820	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1821	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1822	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1823	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1824	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1825	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1826	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1827	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1828	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1829	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1830	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1831	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
Kojto	115:87f2f5183dfb	1832	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
Kojto	115:87f2f5183dfb	1833	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1834	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1835	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1836	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
Kojto	115:87f2f5183dfb	1837	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1838	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1839	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1840	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
Kojto	115:87f2f5183dfb	1841	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1842	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1843
Kojto	115:87f2f5183dfb	1844	#define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1845	#define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
Kojto	115:87f2f5183dfb	1846	#define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1847	#define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1848	#define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1849	#define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1850	#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1851	#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1852	#define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1853	#define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1854	#define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1855	#define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1856	#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1857	#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
Kojto	115:87f2f5183dfb	1858	#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
Kojto	115:87f2f5183dfb	1859	#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1860	#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1861	#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1862	#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
Kojto	115:87f2f5183dfb	1863	#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1864	#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1865	#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1866	#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
Kojto	115:87f2f5183dfb	1867	#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1868	#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1869
Kojto	115:87f2f5183dfb	1870	/** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1871	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1872	* power consumption.
Kojto	115:87f2f5183dfb	1873	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1874	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1875	*/
Kojto	115:87f2f5183dfb	1876	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
Kojto	115:87f2f5183dfb	1877	#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
Kojto	116:c0f6e94411f5	1878
Kojto	115:87f2f5183dfb	1879	#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1880	#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1881
Kojto	115:87f2f5183dfb	1882	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1883	#define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1884
Kojto	115:87f2f5183dfb	1885	#if defined(STM32F756xx)
Kojto	115:87f2f5183dfb	1886	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1887	#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1888
Kojto	115:87f2f5183dfb	1889	#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1890	#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1891	#endif /* STM32F756xx */
Kojto	115:87f2f5183dfb	1892
Kojto	115:87f2f5183dfb	1893	/** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1894	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1895	* power consumption.
Kojto	115:87f2f5183dfb	1896	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1897	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1898	*/
Kojto	115:87f2f5183dfb	1899	#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1900	#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1901
Kojto	115:87f2f5183dfb	1902	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
Kojto	115:87f2f5183dfb	1903	#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
Kojto	115:87f2f5183dfb	1904
Kojto	115:87f2f5183dfb	1905	/** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1906	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1907	* power consumption.
Kojto	115:87f2f5183dfb	1908	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1909	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1910	*/
Kojto	115:87f2f5183dfb	1911	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1912	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1913	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1914	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1915	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1916	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1917	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1918	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1919	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1920	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1921	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1922	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1923	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1924	#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1925	#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1926	#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1927	#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1928	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1929	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1930	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1931	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1932	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1933	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1934	#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1935	#define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
Kojto	115:87f2f5183dfb	1936	#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1937	#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1938
Kojto	115:87f2f5183dfb	1939	#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1940	#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1941	#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1942	#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1943	#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1944	#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1945	#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1946	#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1947	#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1948	#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1949	#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1950	#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1951	#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1952	#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1953	#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1954	#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1955	#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1956	#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1957	#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1958	#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1959	#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1960	#define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1961	#define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1962	#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1963	#define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
Kojto	115:87f2f5183dfb	1964	#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1965	#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1966
Kojto	115:87f2f5183dfb	1967	/** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	115:87f2f5183dfb	1968	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	115:87f2f5183dfb	1969	* power consumption.
Kojto	115:87f2f5183dfb	1970	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	115:87f2f5183dfb	1971	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	115:87f2f5183dfb	1972	*/
Kojto	115:87f2f5183dfb	1973	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1974	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1975	#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1976	#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1977	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1978	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1979	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1980	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1981	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1982	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1983	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1984	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1985	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1986	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1987	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1988	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
Kojto	115:87f2f5183dfb	1989	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
Kojto	116:c0f6e94411f5	1990	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	1991	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
Kojto	116:c0f6e94411f5	1992	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	115:87f2f5183dfb	1993
Kojto	115:87f2f5183dfb	1994	#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1995	#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1996	#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1997	#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1998	#define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	1999	#define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2000	#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2001	#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2002	#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2003	#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2004	#define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2005	#define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2006	#define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2007	#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2008	#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2009	#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
Kojto	115:87f2f5183dfb	2010	#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
Kojto	116:c0f6e94411f5	2011	#if defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	115:87f2f5183dfb	2012	#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
Kojto	116:c0f6e94411f5	2013	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	116:c0f6e94411f5	2014
Kojto	115:87f2f5183dfb	2015	/**
Kojto	115:87f2f5183dfb	2016	* @}
Kojto	115:87f2f5183dfb	2017	*/
Kojto	116:c0f6e94411f5	2018
Kojto	115:87f2f5183dfb	2019	/---------------------------------------------------------------------------------------------/
Kojto	115:87f2f5183dfb	2020
Kojto	115:87f2f5183dfb	2021	/** @brief Macro to configure the Timers clocks prescalers
Kojto	115:87f2f5183dfb	2022	* @param __PRESC__ : specifies the Timers clocks prescalers selection
Kojto	115:87f2f5183dfb	2023	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2024	* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
Kojto	115:87f2f5183dfb	2025	* equal to HPRE if PPREx is corresponding to division by 1 or 2,
Kojto	115:87f2f5183dfb	2026	* else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
Kojto	115:87f2f5183dfb	2027	* division by 4 or more.
Kojto	115:87f2f5183dfb	2028	* @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
Kojto	115:87f2f5183dfb	2029	* equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
Kojto	115:87f2f5183dfb	2030	* else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
Kojto	115:87f2f5183dfb	2031	* to division by 8 or more.
Kojto	115:87f2f5183dfb	2032	*/
Kojto	115:87f2f5183dfb	2033	#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
Kojto	116:c0f6e94411f5	2034	RCC->DCKCFGR1 \|= (__PRESC__); \
Kojto	116:c0f6e94411f5	2035	}while(0)
Kojto	115:87f2f5183dfb	2036
Kojto	115:87f2f5183dfb	2037	/** @brief Macros to Enable or Disable the PLLISAI.
Kojto	115:87f2f5183dfb	2038	* @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto	115:87f2f5183dfb	2039	*/
Kojto	115:87f2f5183dfb	2040	#define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR \|= (RCC_CR_PLLSAION))
Kojto	115:87f2f5183dfb	2041	#define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
Kojto	115:87f2f5183dfb	2042
Kojto	115:87f2f5183dfb	2043	/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto	115:87f2f5183dfb	2044	* @note This function must be used only when the PLLSAI is disabled.
Kojto	115:87f2f5183dfb	2045	* @note PLLSAI clock source is common with the main PLL (configured in
Kojto	115:87f2f5183dfb	2046	* RCC_PLLConfig function )
Kojto	115:87f2f5183dfb	2047	* @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto	116:c0f6e94411f5	2048	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	115:87f2f5183dfb	2049	* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto	116:c0f6e94411f5	2050	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	116:c0f6e94411f5	2051	* @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
Kojto	116:c0f6e94411f5	2052	* This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
Kojto	115:87f2f5183dfb	2053	* @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto	115:87f2f5183dfb	2054	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	115:87f2f5183dfb	2055	* @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto	115:87f2f5183dfb	2056	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	115:87f2f5183dfb	2057	*/
Kojto	116:c0f6e94411f5	2058	#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto	116:c0f6e94411f5	2059	(RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) \|\
Kojto	116:c0f6e94411f5	2060	((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) \|\
Kojto	116:c0f6e94411f5	2061	((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) \|\
Kojto	116:c0f6e94411f5	2062	((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
Kojto	115:87f2f5183dfb	2063
Kojto	116:c0f6e94411f5	2064	/** @brief Macro to configure the PLLI2S clock multiplication and division factors.
Kojto	115:87f2f5183dfb	2065	* @note This macro must be used only when the PLLI2S is disabled.
Kojto	115:87f2f5183dfb	2066	* @note PLLI2S clock source is common with the main PLL (configured in
Kojto	115:87f2f5183dfb	2067	* HAL_RCC_ClockConfig() API)
Kojto	115:87f2f5183dfb	2068	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto	116:c0f6e94411f5	2069	* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto	115:87f2f5183dfb	2070	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto	116:c0f6e94411f5	2071	* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto	116:c0f6e94411f5	2072	* @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
Kojto	116:c0f6e94411f5	2073	* This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
Kojto	115:87f2f5183dfb	2074	* @param __PLLI2SQ__: specifies the division factor for SAI clock.
Kojto	115:87f2f5183dfb	2075	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto	115:87f2f5183dfb	2076	* @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto	115:87f2f5183dfb	2077	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto	115:87f2f5183dfb	2078	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto	116:c0f6e94411f5	2079	* on the I2S clock frequency.
Kojto	115:87f2f5183dfb	2080	*/
Kojto	116:c0f6e94411f5	2081	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto	116:c0f6e94411f5	2082	(RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \|\
Kojto	116:c0f6e94411f5	2083	((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) \|\
Kojto	116:c0f6e94411f5	2084	((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) \|\
Kojto	116:c0f6e94411f5	2085	((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
Kojto	115:87f2f5183dfb	2086
Kojto	115:87f2f5183dfb	2087	/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto	115:87f2f5183dfb	2088	* @note This function must be called before enabling the PLLI2S.
Kojto	115:87f2f5183dfb	2089	* @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
Kojto	115:87f2f5183dfb	2090	* This parameter must be a number between 1 and 32.
Kojto	115:87f2f5183dfb	2091	* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto	115:87f2f5183dfb	2092	*/
Kojto	115:87f2f5183dfb	2093	#define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto	115:87f2f5183dfb	2094
Kojto	115:87f2f5183dfb	2095	/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto	115:87f2f5183dfb	2096	* @note This function must be called before enabling the PLLSAI.
Kojto	115:87f2f5183dfb	2097	* @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto	115:87f2f5183dfb	2098	* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto	115:87f2f5183dfb	2099	* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto	115:87f2f5183dfb	2100	*/
Kojto	115:87f2f5183dfb	2101	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto	115:87f2f5183dfb	2102
Kojto	115:87f2f5183dfb	2103	/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto	115:87f2f5183dfb	2104	*
Kojto	115:87f2f5183dfb	2105	* @note This function must be called before enabling the PLLSAI.
Kojto	115:87f2f5183dfb	2106	* @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto	116:c0f6e94411f5	2107	* This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
Kojto	115:87f2f5183dfb	2108	* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto	115:87f2f5183dfb	2109	*/
Kojto	115:87f2f5183dfb	2110	#define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
Kojto	115:87f2f5183dfb	2111	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
Kojto	115:87f2f5183dfb	2112
Kojto	115:87f2f5183dfb	2113	/** @brief Macro to configure SAI1 clock source selection.
Kojto	115:87f2f5183dfb	2114	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	115:87f2f5183dfb	2115	* the SAI clock.
Kojto	115:87f2f5183dfb	2116	* @param __SOURCE__: specifies the SAI1 clock source.
Kojto	115:87f2f5183dfb	2117	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2118	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	115:87f2f5183dfb	2119	* as SAI1 clock.
Kojto	115:87f2f5183dfb	2120	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	115:87f2f5183dfb	2121	* as SAI1 clock.
Kojto	115:87f2f5183dfb	2122	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto	115:87f2f5183dfb	2123	* used as SAI1 clock.
Kojto	115:87f2f5183dfb	2124	*/
Kojto	115:87f2f5183dfb	2125	#define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
Kojto	115:87f2f5183dfb	2126	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
Kojto	115:87f2f5183dfb	2127
Kojto	115:87f2f5183dfb	2128	/** @brief Macro to get the SAI1 clock source.
Kojto	115:87f2f5183dfb	2129	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2130	* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	115:87f2f5183dfb	2131	* as SAI1 clock.
Kojto	115:87f2f5183dfb	2132	* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	115:87f2f5183dfb	2133	* as SAI1 clock.
Kojto	115:87f2f5183dfb	2134	* @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto	115:87f2f5183dfb	2135	* used as SAI1 clock.
Kojto	115:87f2f5183dfb	2136	*/
Kojto	115:87f2f5183dfb	2137	#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
Kojto	115:87f2f5183dfb	2138
Kojto	115:87f2f5183dfb	2139
Kojto	115:87f2f5183dfb	2140	/** @brief Macro to configure SAI2 clock source selection.
Kojto	115:87f2f5183dfb	2141	* @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto	115:87f2f5183dfb	2142	* the SAI clock.
Kojto	115:87f2f5183dfb	2143	* @param __SOURCE__: specifies the SAI2 clock source.
Kojto	115:87f2f5183dfb	2144	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2145	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	115:87f2f5183dfb	2146	* as SAI2 clock.
Kojto	115:87f2f5183dfb	2147	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	115:87f2f5183dfb	2148	* as SAI2 clock.
Kojto	115:87f2f5183dfb	2149	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto	115:87f2f5183dfb	2150	* used as SAI2 clock.
Kojto	115:87f2f5183dfb	2151	*/
Kojto	115:87f2f5183dfb	2152	#define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
Kojto	115:87f2f5183dfb	2153	MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
Kojto	115:87f2f5183dfb	2154
Kojto	115:87f2f5183dfb	2155
Kojto	115:87f2f5183dfb	2156	/** @brief Macro to get the SAI2 clock source.
Kojto	115:87f2f5183dfb	2157	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2158	* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto	115:87f2f5183dfb	2159	* as SAI2 clock.
Kojto	115:87f2f5183dfb	2160	* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto	115:87f2f5183dfb	2161	* as SAI2 clock.
Kojto	115:87f2f5183dfb	2162	* @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto	115:87f2f5183dfb	2163	* used as SAI2 clock.
Kojto	115:87f2f5183dfb	2164	*/
Kojto	115:87f2f5183dfb	2165	#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
Kojto	115:87f2f5183dfb	2166
Kojto	115:87f2f5183dfb	2167
Kojto	115:87f2f5183dfb	2168	/** @brief Enable PLLSAI_RDY interrupt.
Kojto	115:87f2f5183dfb	2169	*/
Kojto	115:87f2f5183dfb	2170	#define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYIE))
Kojto	115:87f2f5183dfb	2171
Kojto	115:87f2f5183dfb	2172	/** @brief Disable PLLSAI_RDY interrupt.
Kojto	115:87f2f5183dfb	2173	*/
Kojto	115:87f2f5183dfb	2174	#define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Kojto	115:87f2f5183dfb	2175
Kojto	115:87f2f5183dfb	2176	/** @brief Clear the PLLSAI RDY interrupt pending bits.
Kojto	115:87f2f5183dfb	2177	*/
Kojto	115:87f2f5183dfb	2178	#define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR \|= (RCC_CIR_PLLSAIRDYF))
Kojto	115:87f2f5183dfb	2179
Kojto	115:87f2f5183dfb	2180	/** @brief Check the PLLSAI RDY interrupt has occurred or not.
Kojto	115:87f2f5183dfb	2181	* @retval The new state (TRUE or FALSE).
Kojto	115:87f2f5183dfb	2182	*/
Kojto	115:87f2f5183dfb	2183	#define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Kojto	115:87f2f5183dfb	2184
Kojto	115:87f2f5183dfb	2185	/** @brief Check PLLSAI RDY flag is set or not.
Kojto	115:87f2f5183dfb	2186	* @retval The new state (TRUE or FALSE).
Kojto	115:87f2f5183dfb	2187	*/
Kojto	115:87f2f5183dfb	2188	#define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Kojto	115:87f2f5183dfb	2189
Kojto	115:87f2f5183dfb	2190	/** @brief Macro to Get I2S clock source selection.
Kojto	115:87f2f5183dfb	2191	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2192	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto	115:87f2f5183dfb	2193	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
Kojto	115:87f2f5183dfb	2194	*/
Kojto	115:87f2f5183dfb	2195	#define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
Kojto	115:87f2f5183dfb	2196
Kojto	115:87f2f5183dfb	2197	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto	115:87f2f5183dfb	2198	*
Kojto	115:87f2f5183dfb	2199	* @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
Kojto	115:87f2f5183dfb	2200	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2201	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto	115:87f2f5183dfb	2202	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto	115:87f2f5183dfb	2203	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto	115:87f2f5183dfb	2204	*/
Kojto	115:87f2f5183dfb	2205	#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2206	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2207
Kojto	115:87f2f5183dfb	2208	/** @brief Macro to get the I2C1 clock source.
Kojto	115:87f2f5183dfb	2209	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2210	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto	115:87f2f5183dfb	2211	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto	115:87f2f5183dfb	2212	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto	115:87f2f5183dfb	2213	*/
Kojto	115:87f2f5183dfb	2214	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
Kojto	115:87f2f5183dfb	2215
Kojto	115:87f2f5183dfb	2216	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto	115:87f2f5183dfb	2217	*
Kojto	115:87f2f5183dfb	2218	* @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
Kojto	115:87f2f5183dfb	2219	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2220	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto	115:87f2f5183dfb	2221	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	115:87f2f5183dfb	2222	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	115:87f2f5183dfb	2223	*/
Kojto	115:87f2f5183dfb	2224	#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2225	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2226
Kojto	115:87f2f5183dfb	2227	/** @brief Macro to get the I2C2 clock source.
Kojto	115:87f2f5183dfb	2228	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2229	* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto	115:87f2f5183dfb	2230	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	115:87f2f5183dfb	2231	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	115:87f2f5183dfb	2232	*/
Kojto	115:87f2f5183dfb	2233	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
Kojto	115:87f2f5183dfb	2234
Kojto	115:87f2f5183dfb	2235	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto	115:87f2f5183dfb	2236	*
Kojto	115:87f2f5183dfb	2237	* @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
Kojto	115:87f2f5183dfb	2238	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2239	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto	115:87f2f5183dfb	2240	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	115:87f2f5183dfb	2241	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	115:87f2f5183dfb	2242	*/
Kojto	115:87f2f5183dfb	2243	#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2244	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2245
Kojto	115:87f2f5183dfb	2246	/** @brief macro to get the I2C3 clock source.
Kojto	115:87f2f5183dfb	2247	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2248	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto	115:87f2f5183dfb	2249	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	115:87f2f5183dfb	2250	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	115:87f2f5183dfb	2251	*/
Kojto	115:87f2f5183dfb	2252	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
Kojto	115:87f2f5183dfb	2253
Kojto	115:87f2f5183dfb	2254	/** @brief Macro to configure the I2C4 clock (I2C4CLK).
Kojto	115:87f2f5183dfb	2255	*
Kojto	115:87f2f5183dfb	2256	* @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
Kojto	115:87f2f5183dfb	2257	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2258	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
Kojto	115:87f2f5183dfb	2259	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
Kojto	115:87f2f5183dfb	2260	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Kojto	115:87f2f5183dfb	2261	*/
Kojto	115:87f2f5183dfb	2262	#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2263	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2264
Kojto	115:87f2f5183dfb	2265	/** @brief macro to get the I2C4 clock source.
Kojto	115:87f2f5183dfb	2266	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2267	* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
Kojto	115:87f2f5183dfb	2268	* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
Kojto	115:87f2f5183dfb	2269	* @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Kojto	115:87f2f5183dfb	2270	*/
Kojto	115:87f2f5183dfb	2271	#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
Kojto	115:87f2f5183dfb	2272
Kojto	115:87f2f5183dfb	2273	/** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto	115:87f2f5183dfb	2274	*
Kojto	115:87f2f5183dfb	2275	* @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
Kojto	115:87f2f5183dfb	2276	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2277	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto	115:87f2f5183dfb	2278	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto	115:87f2f5183dfb	2279	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto	115:87f2f5183dfb	2280	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto	115:87f2f5183dfb	2281	*/
Kojto	115:87f2f5183dfb	2282	#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2283	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2284
Kojto	115:87f2f5183dfb	2285	/** @brief macro to get the USART1 clock source.
Kojto	115:87f2f5183dfb	2286	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2287	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto	115:87f2f5183dfb	2288	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto	115:87f2f5183dfb	2289	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto	115:87f2f5183dfb	2290	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto	115:87f2f5183dfb	2291	*/
Kojto	115:87f2f5183dfb	2292	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
Kojto	115:87f2f5183dfb	2293
Kojto	115:87f2f5183dfb	2294	/** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto	115:87f2f5183dfb	2295	*
Kojto	115:87f2f5183dfb	2296	* @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
Kojto	115:87f2f5183dfb	2297	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2298	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	115:87f2f5183dfb	2299	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	115:87f2f5183dfb	2300	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	115:87f2f5183dfb	2301	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	115:87f2f5183dfb	2302	*/
Kojto	115:87f2f5183dfb	2303	#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2304	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2305
Kojto	115:87f2f5183dfb	2306	/** @brief macro to get the USART2 clock source.
Kojto	115:87f2f5183dfb	2307	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2308	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	115:87f2f5183dfb	2309	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	115:87f2f5183dfb	2310	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	115:87f2f5183dfb	2311	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	115:87f2f5183dfb	2312	*/
Kojto	115:87f2f5183dfb	2313	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
Kojto	115:87f2f5183dfb	2314
Kojto	115:87f2f5183dfb	2315	/** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto	115:87f2f5183dfb	2316	*
Kojto	115:87f2f5183dfb	2317	* @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
Kojto	115:87f2f5183dfb	2318	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2319	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	115:87f2f5183dfb	2320	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	115:87f2f5183dfb	2321	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	115:87f2f5183dfb	2322	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	115:87f2f5183dfb	2323	*/
Kojto	115:87f2f5183dfb	2324	#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2325	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2326
Kojto	115:87f2f5183dfb	2327	/** @brief macro to get the USART3 clock source.
Kojto	115:87f2f5183dfb	2328	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2329	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto	115:87f2f5183dfb	2330	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto	115:87f2f5183dfb	2331	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto	115:87f2f5183dfb	2332	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto	115:87f2f5183dfb	2333	*/
Kojto	115:87f2f5183dfb	2334	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
Kojto	115:87f2f5183dfb	2335
Kojto	115:87f2f5183dfb	2336	/** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto	115:87f2f5183dfb	2337	*
Kojto	115:87f2f5183dfb	2338	* @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
Kojto	115:87f2f5183dfb	2339	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2340	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto	115:87f2f5183dfb	2341	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto	115:87f2f5183dfb	2342	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto	115:87f2f5183dfb	2343	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto	115:87f2f5183dfb	2344	*/
Kojto	115:87f2f5183dfb	2345	#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2346	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2347
Kojto	115:87f2f5183dfb	2348	/** @brief macro to get the UART4 clock source.
Kojto	115:87f2f5183dfb	2349	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2350	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto	115:87f2f5183dfb	2351	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto	115:87f2f5183dfb	2352	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto	115:87f2f5183dfb	2353	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto	115:87f2f5183dfb	2354	*/
Kojto	115:87f2f5183dfb	2355	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
Kojto	115:87f2f5183dfb	2356
Kojto	115:87f2f5183dfb	2357	/** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto	115:87f2f5183dfb	2358	*
Kojto	115:87f2f5183dfb	2359	* @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
Kojto	115:87f2f5183dfb	2360	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2361	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto	115:87f2f5183dfb	2362	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto	115:87f2f5183dfb	2363	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto	115:87f2f5183dfb	2364	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto	115:87f2f5183dfb	2365	*/
Kojto	115:87f2f5183dfb	2366	#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2367	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2368
Kojto	115:87f2f5183dfb	2369	/** @brief macro to get the UART5 clock source.
Kojto	115:87f2f5183dfb	2370	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2371	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto	115:87f2f5183dfb	2372	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto	115:87f2f5183dfb	2373	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto	115:87f2f5183dfb	2374	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto	115:87f2f5183dfb	2375	*/
Kojto	115:87f2f5183dfb	2376	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
Kojto	115:87f2f5183dfb	2377
Kojto	115:87f2f5183dfb	2378	/** @brief Macro to configure the USART6 clock (USART6CLK).
Kojto	115:87f2f5183dfb	2379	*
Kojto	115:87f2f5183dfb	2380	* @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
Kojto	115:87f2f5183dfb	2381	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2382	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
Kojto	115:87f2f5183dfb	2383	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
Kojto	115:87f2f5183dfb	2384	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
Kojto	115:87f2f5183dfb	2385	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Kojto	115:87f2f5183dfb	2386	*/
Kojto	115:87f2f5183dfb	2387	#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2388	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2389
Kojto	115:87f2f5183dfb	2390	/** @brief macro to get the USART6 clock source.
Kojto	115:87f2f5183dfb	2391	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2392	* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
Kojto	115:87f2f5183dfb	2393	* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
Kojto	115:87f2f5183dfb	2394	* @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
Kojto	115:87f2f5183dfb	2395	* @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Kojto	115:87f2f5183dfb	2396	*/
Kojto	115:87f2f5183dfb	2397	#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
Kojto	115:87f2f5183dfb	2398
Kojto	115:87f2f5183dfb	2399	/** @brief Macro to configure the UART7 clock (UART7CLK).
Kojto	115:87f2f5183dfb	2400	*
Kojto	115:87f2f5183dfb	2401	* @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
Kojto	115:87f2f5183dfb	2402	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2403	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
Kojto	115:87f2f5183dfb	2404	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
Kojto	115:87f2f5183dfb	2405	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
Kojto	115:87f2f5183dfb	2406	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Kojto	115:87f2f5183dfb	2407	*/
Kojto	115:87f2f5183dfb	2408	#define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2409	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2410
Kojto	115:87f2f5183dfb	2411	/** @brief macro to get the UART7 clock source.
Kojto	115:87f2f5183dfb	2412	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2413	* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
Kojto	115:87f2f5183dfb	2414	* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
Kojto	115:87f2f5183dfb	2415	* @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
Kojto	115:87f2f5183dfb	2416	* @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Kojto	115:87f2f5183dfb	2417	*/
Kojto	115:87f2f5183dfb	2418	#define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
Kojto	115:87f2f5183dfb	2419
Kojto	115:87f2f5183dfb	2420	/** @brief Macro to configure the UART8 clock (UART8CLK).
Kojto	115:87f2f5183dfb	2421	*
Kojto	115:87f2f5183dfb	2422	* @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
Kojto	115:87f2f5183dfb	2423	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2424	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
Kojto	115:87f2f5183dfb	2425	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
Kojto	115:87f2f5183dfb	2426	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
Kojto	115:87f2f5183dfb	2427	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Kojto	115:87f2f5183dfb	2428	*/
Kojto	115:87f2f5183dfb	2429	#define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2430	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2431
Kojto	115:87f2f5183dfb	2432	/** @brief macro to get the UART8 clock source.
Kojto	115:87f2f5183dfb	2433	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2434	* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
Kojto	115:87f2f5183dfb	2435	* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
Kojto	115:87f2f5183dfb	2436	* @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
Kojto	115:87f2f5183dfb	2437	* @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Kojto	115:87f2f5183dfb	2438	*/
Kojto	115:87f2f5183dfb	2439	#define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
Kojto	115:87f2f5183dfb	2440
Kojto	115:87f2f5183dfb	2441	/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
Kojto	115:87f2f5183dfb	2442	*
Kojto	115:87f2f5183dfb	2443	* @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
Kojto	115:87f2f5183dfb	2444	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2445	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2446	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2447	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2448	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2449	*/
Kojto	115:87f2f5183dfb	2450	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2451	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2452
Kojto	115:87f2f5183dfb	2453	/** @brief macro to get the LPTIM1 clock source.
Kojto	115:87f2f5183dfb	2454	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2455	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2456	* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2457	* @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2458	* @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto	115:87f2f5183dfb	2459	*/
Kojto	115:87f2f5183dfb	2460	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
Kojto	115:87f2f5183dfb	2461
Kojto	115:87f2f5183dfb	2462	/** @brief Macro to configure the CEC clock (CECCLK).
Kojto	115:87f2f5183dfb	2463	*
Kojto	115:87f2f5183dfb	2464	* @param __CEC_CLKSOURCE__: specifies the CEC clock source.
Kojto	115:87f2f5183dfb	2465	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2466	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	116:c0f6e94411f5	2467	* @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
Kojto	115:87f2f5183dfb	2468	*/
Kojto	115:87f2f5183dfb	2469	#define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2470	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2471
Kojto	115:87f2f5183dfb	2472	/** @brief macro to get the CEC clock source.
Kojto	115:87f2f5183dfb	2473	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2474	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	115:87f2f5183dfb	2475	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	115:87f2f5183dfb	2476	*/
Kojto	115:87f2f5183dfb	2477	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
Kojto	115:87f2f5183dfb	2478
Kojto	115:87f2f5183dfb	2479	/** @brief Macro to configure the CLK48 source (CLK48CLK).
Kojto	115:87f2f5183dfb	2480	*
Kojto	115:87f2f5183dfb	2481	* @param __CLK48_SOURCE__: specifies the CLK48 clock source.
Kojto	115:87f2f5183dfb	2482	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2483	* @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
Kojto	116:c0f6e94411f5	2484	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
Kojto	115:87f2f5183dfb	2485	*/
Kojto	115:87f2f5183dfb	2486	#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
Kojto	115:87f2f5183dfb	2487	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
Kojto	115:87f2f5183dfb	2488
Kojto	115:87f2f5183dfb	2489	/** @brief macro to get the CLK48 source.
Kojto	115:87f2f5183dfb	2490	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2491	* @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
Kojto	116:c0f6e94411f5	2492	* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
Kojto	115:87f2f5183dfb	2493	*/
Kojto	115:87f2f5183dfb	2494	#define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
Kojto	115:87f2f5183dfb	2495
Kojto	115:87f2f5183dfb	2496	/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
Kojto	115:87f2f5183dfb	2497	*
Kojto	115:87f2f5183dfb	2498	* @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
Kojto	115:87f2f5183dfb	2499	* This parameter can be one of the following values:
Kojto	115:87f2f5183dfb	2500	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
Kojto	115:87f2f5183dfb	2501	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
Kojto	115:87f2f5183dfb	2502	*/
Kojto	115:87f2f5183dfb	2503	#define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
Kojto	115:87f2f5183dfb	2504	MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Kojto	115:87f2f5183dfb	2505
Kojto	115:87f2f5183dfb	2506	/** @brief macro to get the SDMMC1 clock source.
Kojto	115:87f2f5183dfb	2507	* @retval The clock source can be one of the following values:
Kojto	115:87f2f5183dfb	2508	* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
Kojto	115:87f2f5183dfb	2509	* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
Kojto	115:87f2f5183dfb	2510	*/
Kojto	115:87f2f5183dfb	2511	#define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
Kojto	115:87f2f5183dfb	2512
Kojto	115:87f2f5183dfb	2513	/**
Kojto	115:87f2f5183dfb	2514	* @}
Kojto	115:87f2f5183dfb	2515	*/
Kojto	116:c0f6e94411f5	2516
Kojto	115:87f2f5183dfb	2517	/* Exported functions --------------------------------------------------------*/
Kojto	115:87f2f5183dfb	2518	/** @addtogroup RCCEx_Exported_Functions_Group1
Kojto	115:87f2f5183dfb	2519	* @{
Kojto	115:87f2f5183dfb	2520	*/
Kojto	115:87f2f5183dfb	2521	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	115:87f2f5183dfb	2522	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	115:87f2f5183dfb	2523	uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto	115:87f2f5183dfb	2524
Kojto	115:87f2f5183dfb	2525	/**
Kojto	115:87f2f5183dfb	2526	* @}
Kojto	115:87f2f5183dfb	2527	*/
Kojto	115:87f2f5183dfb	2528	/* Private macros ------------------------------------------------------------*/
Kojto	115:87f2f5183dfb	2529	/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto	115:87f2f5183dfb	2530	* @{
Kojto	115:87f2f5183dfb	2531	*/
Kojto	115:87f2f5183dfb	2532	/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto	115:87f2f5183dfb	2533	* @{
Kojto	115:87f2f5183dfb	2534	*/
Kojto	115:87f2f5183dfb	2535	#if defined(STM32F756xx) \|\| defined(STM32F746xx)
Kojto	115:87f2f5183dfb	2536	#define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto	116:c0f6e94411f5	2537	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
Kojto	115:87f2f5183dfb	2538	(((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) \|\| \
Kojto	115:87f2f5183dfb	2539	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
Kojto	115:87f2f5183dfb	2540	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
Kojto	115:87f2f5183dfb	2541	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
Kojto	115:87f2f5183dfb	2542	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
Kojto	115:87f2f5183dfb	2543	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
Kojto	115:87f2f5183dfb	2544	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
Kojto	115:87f2f5183dfb	2545	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
Kojto	115:87f2f5183dfb	2546	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
Kojto	115:87f2f5183dfb	2547	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
Kojto	115:87f2f5183dfb	2548	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
Kojto	115:87f2f5183dfb	2549	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
Kojto	115:87f2f5183dfb	2550	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
Kojto	115:87f2f5183dfb	2551	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
Kojto	115:87f2f5183dfb	2552	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
Kojto	115:87f2f5183dfb	2553	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
Kojto	115:87f2f5183dfb	2554	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
Kojto	115:87f2f5183dfb	2555	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
Kojto	115:87f2f5183dfb	2556	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
Kojto	116:c0f6e94411f5	2557	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
Kojto	116:c0f6e94411f5	2558	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
Kojto	115:87f2f5183dfb	2559	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto	115:87f2f5183dfb	2560	#elif defined(STM32F745xx)
Kojto	115:87f2f5183dfb	2561	#define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto	116:c0f6e94411f5	2562	((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) \|\| \
Kojto	115:87f2f5183dfb	2563	(((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) \|\| \
Kojto	115:87f2f5183dfb	2564	(((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) \|\| \
Kojto	115:87f2f5183dfb	2565	(((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) \|\| \
Kojto	115:87f2f5183dfb	2566	(((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) \|\| \
Kojto	115:87f2f5183dfb	2567	(((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) \|\| \
Kojto	115:87f2f5183dfb	2568	(((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) \|\| \
Kojto	115:87f2f5183dfb	2569	(((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) \|\| \
Kojto	115:87f2f5183dfb	2570	(((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) \|\| \
Kojto	115:87f2f5183dfb	2571	(((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) \|\| \
Kojto	115:87f2f5183dfb	2572	(((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) \|\| \
Kojto	115:87f2f5183dfb	2573	(((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) \|\| \
Kojto	115:87f2f5183dfb	2574	(((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) \|\| \
Kojto	115:87f2f5183dfb	2575	(((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) \|\| \
Kojto	115:87f2f5183dfb	2576	(((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) \|\| \
Kojto	115:87f2f5183dfb	2577	(((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) \|\| \
Kojto	115:87f2f5183dfb	2578	(((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) \|\| \
Kojto	115:87f2f5183dfb	2579	(((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) \|\| \
Kojto	115:87f2f5183dfb	2580	(((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) \|\| \
Kojto	116:c0f6e94411f5	2581	(((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) \|\| \
Kojto	116:c0f6e94411f5	2582	(((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) \|\| \
Kojto	115:87f2f5183dfb	2583	(((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto	116:c0f6e94411f5	2584	#endif /* STM32F746xx \|\| STM32F756xx */
Kojto	116:c0f6e94411f5	2585	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
Kojto	116:c0f6e94411f5	2586	#define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) \|\|\
Kojto	116:c0f6e94411f5	2587	((VALUE) == RCC_PLLI2SP_DIV4) \|\|\
Kojto	116:c0f6e94411f5	2588	((VALUE) == RCC_PLLI2SP_DIV6) \|\|\
Kojto	116:c0f6e94411f5	2589	((VALUE) == RCC_PLLI2SP_DIV8))
Kojto	115:87f2f5183dfb	2590	#define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	115:87f2f5183dfb	2591	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	115:87f2f5183dfb	2592
Kojto	116:c0f6e94411f5	2593	#define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
Kojto	116:c0f6e94411f5	2594	#define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) \|\|\
Kojto	116:c0f6e94411f5	2595	((VALUE) == RCC_PLLSAIP_DIV4) \|\|\
Kojto	116:c0f6e94411f5	2596	((VALUE) == RCC_PLLSAIP_DIV6) \|\|\
Kojto	116:c0f6e94411f5	2597	((VALUE) == RCC_PLLSAIP_DIV8))
Kojto	115:87f2f5183dfb	2598	#define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto	115:87f2f5183dfb	2599	#define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto	115:87f2f5183dfb	2600
Kojto	115:87f2f5183dfb	2601	#define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	115:87f2f5183dfb	2602
Kojto	115:87f2f5183dfb	2603	#define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto	115:87f2f5183dfb	2604
Kojto	115:87f2f5183dfb	2605	#define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) \|\|\
Kojto	116:c0f6e94411f5	2606	((VALUE) == RCC_PLLSAIDIVR_4) \|\|\
Kojto	116:c0f6e94411f5	2607	((VALUE) == RCC_PLLSAIDIVR_8) \|\|\
Kojto	115:87f2f5183dfb	2608	((VALUE) == RCC_PLLSAIDIVR_16))
Kojto	115:87f2f5183dfb	2609	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) \|\| \
Kojto	116:c0f6e94411f5	2610	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto	115:87f2f5183dfb	2611
Kojto	116:c0f6e94411f5	2612	#define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) \|\| \
Kojto	116:c0f6e94411f5	2613	((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
Kojto	115:87f2f5183dfb	2614
Kojto	115:87f2f5183dfb	2615	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
Kojto	115:87f2f5183dfb	2616	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	115:87f2f5183dfb	2617	#define IS_RCC_USART1CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2618	(((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	115:87f2f5183dfb	2619	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2620	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2621	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2622
Kojto	115:87f2f5183dfb	2623	#define IS_RCC_USART2CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2624	(((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2625	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2626	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2627	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2628	#define IS_RCC_USART3CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2629	(((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2630	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2631	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2632	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2633
Kojto	115:87f2f5183dfb	2634	#define IS_RCC_UART4CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2635	(((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2636	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2637	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2638	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2639
Kojto	115:87f2f5183dfb	2640	#define IS_RCC_UART5CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2641	(((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2642	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2643	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2644	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2645
Kojto	115:87f2f5183dfb	2646	#define IS_RCC_USART6CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2647	(((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) \|\| \
Kojto	115:87f2f5183dfb	2648	((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2649	((SOURCE) == RCC_USART6CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2650	((SOURCE) == RCC_USART6CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2651
Kojto	115:87f2f5183dfb	2652	#define IS_RCC_UART7CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2653	(((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2654	((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2655	((SOURCE) == RCC_UART7CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2656	((SOURCE) == RCC_UART7CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2657
Kojto	115:87f2f5183dfb	2658	#define IS_RCC_UART8CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2659	(((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2660	((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) \|\| \
Kojto	115:87f2f5183dfb	2661	((SOURCE) == RCC_UART8CLKSOURCE_LSE) \|\| \
Kojto	115:87f2f5183dfb	2662	((SOURCE) == RCC_UART8CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2663	#define IS_RCC_I2C1CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2664	(((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2665	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
Kojto	115:87f2f5183dfb	2666	((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2667	#define IS_RCC_I2C2CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2668	(((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2669	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)\|\| \
Kojto	115:87f2f5183dfb	2670	((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2671
Kojto	115:87f2f5183dfb	2672	#define IS_RCC_I2C3CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2673	(((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2674	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
Kojto	115:87f2f5183dfb	2675	((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2676	#define IS_RCC_I2C4CLKSOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2677	(((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) \|\| \
Kojto	115:87f2f5183dfb	2678	((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)\|\| \
Kojto	115:87f2f5183dfb	2679	((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
Kojto	115:87f2f5183dfb	2680	#define IS_RCC_LPTIM1CLK(SOURCE) \
Kojto	115:87f2f5183dfb	2681	(((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
Kojto	115:87f2f5183dfb	2682	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
Kojto	115:87f2f5183dfb	2683	((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
Kojto	115:87f2f5183dfb	2684	((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto	115:87f2f5183dfb	2685	#define IS_RCC_CLK48SOURCE(SOURCE) \
Kojto	115:87f2f5183dfb	2686	(((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) \|\| \
Kojto	115:87f2f5183dfb	2687	((SOURCE) == RCC_CLK48SOURCE_PLL))
Kojto	115:87f2f5183dfb	2688	#define IS_RCC_TIMPRES(VALUE) \
Kojto	115:87f2f5183dfb	2689	(((VALUE) == RCC_TIMPRES_DESACTIVATED) \|\| \
Kojto	115:87f2f5183dfb	2690	((VALUE) == RCC_TIMPRES_ACTIVATED))
Kojto	116:c0f6e94411f5	2691
Kojto	116:c0f6e94411f5	2692	#if defined (STM32F745xx) \|\| defined (STM32F746xx) \|\| defined (STM32F756xx)
Kojto	116:c0f6e94411f5	2693	#define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) \|\| \
Kojto	116:c0f6e94411f5	2694	((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) \|\| \
Kojto	116:c0f6e94411f5	2695	((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
Kojto	116:c0f6e94411f5	2696	#define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) \|\| \
Kojto	116:c0f6e94411f5	2697	((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) \|\| \
Kojto	116:c0f6e94411f5	2698	((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
Kojto	116:c0f6e94411f5	2699	#endif /* STM32F745xx \|\| STM32F746xx \|\| STM32F756xx */
Kojto	116:c0f6e94411f5	2700
Kojto	115:87f2f5183dfb	2701	/**
Kojto	115:87f2f5183dfb	2702	* @}
Kojto	115:87f2f5183dfb	2703	*/
Kojto	115:87f2f5183dfb	2704
Kojto	115:87f2f5183dfb	2705	/**
Kojto	115:87f2f5183dfb	2706	* @}
Kojto	115:87f2f5183dfb	2707	*/
Kojto	115:87f2f5183dfb	2708
Kojto	115:87f2f5183dfb	2709	/**
Kojto	115:87f2f5183dfb	2710	* @}
Kojto	115:87f2f5183dfb	2711	*/
Kojto	115:87f2f5183dfb	2712
Kojto	115:87f2f5183dfb	2713	/**
Kojto	115:87f2f5183dfb	2714	* @}
Kojto	115:87f2f5183dfb	2715	*/
Kojto	116:c0f6e94411f5	2716
Kojto	115:87f2f5183dfb	2717	#ifdef __cplusplus
Kojto	115:87f2f5183dfb	2718	}
Kojto	115:87f2f5183dfb	2719	#endif
Kojto	115:87f2f5183dfb	2720
Kojto	115:87f2f5183dfb	2721	#endif /* __STM32F7xx_HAL_RCC_EX_H */
Kojto	115:87f2f5183dfb	2722
Kojto	115:87f2f5183dfb	2723	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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