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TARGET_NUCLEO_F746ZG/stm32f7xx_hal_rcc_ex.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
116:c0f6e94411f5 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 115:87f2f5183dfb 1 /**
Kojto 115:87f2f5183dfb 2 ******************************************************************************
Kojto 115:87f2f5183dfb 3 * @file stm32f7xx_hal_rcc_ex.h
Kojto 116:c0f6e94411f5 4 * @author MCD Application Team
Kojto 122:f9eeca106725 5 * @version V1.1.0
Kojto 122:f9eeca106725 6 * @date 22-April-2016
Kojto 115:87f2f5183dfb 7 * @brief Header file of RCC HAL Extension module.
Kojto 115:87f2f5183dfb 8 ******************************************************************************
Kojto 115:87f2f5183dfb 9 * @attention
Kojto 115:87f2f5183dfb 10 *
Kojto 122:f9eeca106725 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 115:87f2f5183dfb 12 *
Kojto 115:87f2f5183dfb 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 115:87f2f5183dfb 14 * are permitted provided that the following conditions are met:
Kojto 115:87f2f5183dfb 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 115:87f2f5183dfb 16 * this list of conditions and the following disclaimer.
Kojto 115:87f2f5183dfb 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 115:87f2f5183dfb 18 * this list of conditions and the following disclaimer in the documentation
Kojto 115:87f2f5183dfb 19 * and/or other materials provided with the distribution.
Kojto 115:87f2f5183dfb 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 115:87f2f5183dfb 21 * may be used to endorse or promote products derived from this software
Kojto 115:87f2f5183dfb 22 * without specific prior written permission.
Kojto 115:87f2f5183dfb 23 *
Kojto 115:87f2f5183dfb 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 115:87f2f5183dfb 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 115:87f2f5183dfb 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 115:87f2f5183dfb 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 115:87f2f5183dfb 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 115:87f2f5183dfb 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 115:87f2f5183dfb 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 115:87f2f5183dfb 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 115:87f2f5183dfb 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 115:87f2f5183dfb 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 115:87f2f5183dfb 34 *
Kojto 115:87f2f5183dfb 35 ******************************************************************************
Kojto 115:87f2f5183dfb 36 */
Kojto 115:87f2f5183dfb 37
Kojto 115:87f2f5183dfb 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 115:87f2f5183dfb 39 #ifndef __STM32F7xx_HAL_RCC_EX_H
Kojto 115:87f2f5183dfb 40 #define __STM32F7xx_HAL_RCC_EX_H
Kojto 115:87f2f5183dfb 41
Kojto 115:87f2f5183dfb 42 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 43 extern "C" {
Kojto 115:87f2f5183dfb 44 #endif
Kojto 115:87f2f5183dfb 45
Kojto 115:87f2f5183dfb 46 /* Includes ------------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 47 #include "stm32f7xx_hal_def.h"
Kojto 115:87f2f5183dfb 48
Kojto 115:87f2f5183dfb 49 /** @addtogroup STM32F7xx_HAL_Driver
Kojto 115:87f2f5183dfb 50 * @{
Kojto 115:87f2f5183dfb 51 */
Kojto 115:87f2f5183dfb 52
Kojto 115:87f2f5183dfb 53 /** @addtogroup RCCEx
Kojto 115:87f2f5183dfb 54 * @{
Kojto 115:87f2f5183dfb 55 */
Kojto 115:87f2f5183dfb 56
Kojto 115:87f2f5183dfb 57 /* Exported types ------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 115:87f2f5183dfb 59 * @{
Kojto 115:87f2f5183dfb 60 */
Kojto 122:f9eeca106725 61
Kojto 122:f9eeca106725 62 /**
Kojto 122:f9eeca106725 63 * @brief RCC PLL configuration structure definition
Kojto 122:f9eeca106725 64 */
Kojto 122:f9eeca106725 65 typedef struct
Kojto 122:f9eeca106725 66 {
Kojto 122:f9eeca106725 67 uint32_t PLLState; /*!< The new state of the PLL.
Kojto 122:f9eeca106725 68 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 122:f9eeca106725 69
Kojto 122:f9eeca106725 70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto 122:f9eeca106725 71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 122:f9eeca106725 72
Kojto 122:f9eeca106725 73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto 122:f9eeca106725 74 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto 122:f9eeca106725 75
Kojto 122:f9eeca106725 76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto 122:f9eeca106725 77 This parameter must be a number between Min_Data = 50 and Max_Data = 432 */
Kojto 122:f9eeca106725 78
Kojto 122:f9eeca106725 79 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto 122:f9eeca106725 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 122:f9eeca106725 81
Kojto 122:f9eeca106725 82 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
Kojto 122:f9eeca106725 83 This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
Kojto 122:f9eeca106725 84 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 85 uint32_t PLLR; /*!< PLLR: Division factor for DSI clock.
Kojto 122:f9eeca106725 86 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
Kojto 122:f9eeca106725 87 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 88
Kojto 122:f9eeca106725 89 }RCC_PLLInitTypeDef;
Kojto 115:87f2f5183dfb 90
Kojto 115:87f2f5183dfb 91 /**
Kojto 115:87f2f5183dfb 92 * @brief PLLI2S Clock structure definition
Kojto 115:87f2f5183dfb 93 */
Kojto 115:87f2f5183dfb 94 typedef struct
Kojto 115:87f2f5183dfb 95 {
Kojto 115:87f2f5183dfb 96 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 116:c0f6e94411f5 97 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto 115:87f2f5183dfb 98 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 115:87f2f5183dfb 99
Kojto 115:87f2f5183dfb 100 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto 115:87f2f5183dfb 101 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 115:87f2f5183dfb 102 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 115:87f2f5183dfb 103
Kojto 115:87f2f5183dfb 104 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 115:87f2f5183dfb 105 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 115:87f2f5183dfb 106 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 115:87f2f5183dfb 107
Kojto 115:87f2f5183dfb 108 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
Kojto 116:c0f6e94411f5 109 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
Kojto 116:c0f6e94411f5 110 This parameter will be used only when PLLI2S is selected as Clock Source SPDIF-RX */
Kojto 115:87f2f5183dfb 111 }RCC_PLLI2SInitTypeDef;
Kojto 115:87f2f5183dfb 112
Kojto 115:87f2f5183dfb 113 /**
Kojto 115:87f2f5183dfb 114 * @brief PLLSAI Clock structure definition
Kojto 115:87f2f5183dfb 115 */
Kojto 115:87f2f5183dfb 116 typedef struct
Kojto 115:87f2f5183dfb 117 {
Kojto 115:87f2f5183dfb 118 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 116:c0f6e94411f5 119 This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto 115:87f2f5183dfb 120 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 115:87f2f5183dfb 121
Kojto 115:87f2f5183dfb 122 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 115:87f2f5183dfb 123 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 115:87f2f5183dfb 124 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 115:87f2f5183dfb 125
Kojto 115:87f2f5183dfb 126 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
Kojto 115:87f2f5183dfb 127 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 115:87f2f5183dfb 128 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
Kojto 115:87f2f5183dfb 129
Kojto 115:87f2f5183dfb 130 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
Kojto 116:c0f6e94411f5 131 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider
Kojto 115:87f2f5183dfb 132 This parameter will be used only when PLLSAI is disabled */
Kojto 115:87f2f5183dfb 133 }RCC_PLLSAIInitTypeDef;
Kojto 115:87f2f5183dfb 134
Kojto 115:87f2f5183dfb 135 /**
Kojto 115:87f2f5183dfb 136 * @brief RCC extended clocks structure definition
Kojto 115:87f2f5183dfb 137 */
Kojto 115:87f2f5183dfb 138 typedef struct
Kojto 115:87f2f5183dfb 139 {
Kojto 115:87f2f5183dfb 140 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 115:87f2f5183dfb 141 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 115:87f2f5183dfb 142
Kojto 115:87f2f5183dfb 143 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto 115:87f2f5183dfb 144 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 115:87f2f5183dfb 145
Kojto 115:87f2f5183dfb 146 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto 115:87f2f5183dfb 147 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto 115:87f2f5183dfb 148
Kojto 115:87f2f5183dfb 149 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 115:87f2f5183dfb 150 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 115:87f2f5183dfb 151 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 115:87f2f5183dfb 152
Kojto 115:87f2f5183dfb 153 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 115:87f2f5183dfb 154 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 115:87f2f5183dfb 155 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto 115:87f2f5183dfb 156
Kojto 115:87f2f5183dfb 157 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
Kojto 115:87f2f5183dfb 158 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
Kojto 115:87f2f5183dfb 159
Kojto 115:87f2f5183dfb 160 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
Kojto 115:87f2f5183dfb 161 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 115:87f2f5183dfb 162
Kojto 115:87f2f5183dfb 163 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
Kojto 115:87f2f5183dfb 164 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 115:87f2f5183dfb 165
Kojto 115:87f2f5183dfb 166 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
Kojto 115:87f2f5183dfb 167 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
Kojto 115:87f2f5183dfb 168
Kojto 115:87f2f5183dfb 169 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
Kojto 115:87f2f5183dfb 170 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto 115:87f2f5183dfb 171
Kojto 115:87f2f5183dfb 172 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
Kojto 115:87f2f5183dfb 173 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto 115:87f2f5183dfb 174
Kojto 115:87f2f5183dfb 175 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 115:87f2f5183dfb 176 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 115:87f2f5183dfb 177
Kojto 115:87f2f5183dfb 178 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 115:87f2f5183dfb 179 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 115:87f2f5183dfb 180
Kojto 115:87f2f5183dfb 181 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 115:87f2f5183dfb 182 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto 115:87f2f5183dfb 183
Kojto 115:87f2f5183dfb 184 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 115:87f2f5183dfb 185 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 115:87f2f5183dfb 186
Kojto 115:87f2f5183dfb 187 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 115:87f2f5183dfb 188 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 115:87f2f5183dfb 189
Kojto 115:87f2f5183dfb 190 uint32_t Usart6ClockSelection; /*!< USART6 clock source
Kojto 115:87f2f5183dfb 191 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
Kojto 115:87f2f5183dfb 192
Kojto 115:87f2f5183dfb 193 uint32_t Uart7ClockSelection; /*!< UART7 clock source
Kojto 115:87f2f5183dfb 194 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
Kojto 115:87f2f5183dfb 195
Kojto 115:87f2f5183dfb 196 uint32_t Uart8ClockSelection; /*!< UART8 clock source
Kojto 115:87f2f5183dfb 197 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
Kojto 115:87f2f5183dfb 198
Kojto 115:87f2f5183dfb 199 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 115:87f2f5183dfb 200 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto 115:87f2f5183dfb 201
Kojto 115:87f2f5183dfb 202 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 115:87f2f5183dfb 203 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 115:87f2f5183dfb 204
Kojto 115:87f2f5183dfb 205 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 115:87f2f5183dfb 206 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 115:87f2f5183dfb 207
Kojto 115:87f2f5183dfb 208 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
Kojto 115:87f2f5183dfb 209 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
Kojto 115:87f2f5183dfb 210
Kojto 115:87f2f5183dfb 211 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
Kojto 115:87f2f5183dfb 212 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto 115:87f2f5183dfb 213
Kojto 115:87f2f5183dfb 214 uint32_t CecClockSelection; /*!< CEC clock source
Kojto 115:87f2f5183dfb 215 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 115:87f2f5183dfb 216
Kojto 115:87f2f5183dfb 217 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
Kojto 115:87f2f5183dfb 218 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto 115:87f2f5183dfb 219
Kojto 115:87f2f5183dfb 220 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
Kojto 115:87f2f5183dfb 221 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
Kojto 122:f9eeca106725 222
Kojto 122:f9eeca106725 223 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 224 uint32_t Sdmmc2ClockSelection; /*!< SDMMC2 clock source
Kojto 122:f9eeca106725 225 This parameter can be a value of @ref RCCEx_SDMMC2_Clock_Source */
Kojto 122:f9eeca106725 226
Kojto 122:f9eeca106725 227 uint32_t Dfsdm1ClockSelection; /*!< DFSDM1 clock source
Kojto 122:f9eeca106725 228 This parameter can be a value of @ref RCCEx_DFSDM1_Kernel_Clock_Source */
Kojto 122:f9eeca106725 229
Kojto 122:f9eeca106725 230 uint32_t Dfsdm1AudioClockSelection; /*!< DFSDM1 clock source
Kojto 122:f9eeca106725 231 This parameter can be a value of @ref RCCEx_DFSDM1_AUDIO_Clock_Source */
Kojto 122:f9eeca106725 232 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 233 }RCC_PeriphCLKInitTypeDef;
Kojto 115:87f2f5183dfb 234 /**
Kojto 115:87f2f5183dfb 235 * @}
Kojto 115:87f2f5183dfb 236 */
Kojto 115:87f2f5183dfb 237
Kojto 115:87f2f5183dfb 238 /* Exported constants --------------------------------------------------------*/
Kojto 115:87f2f5183dfb 239 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 115:87f2f5183dfb 240 * @{
Kojto 115:87f2f5183dfb 241 */
Kojto 115:87f2f5183dfb 242
Kojto 115:87f2f5183dfb 243 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
Kojto 115:87f2f5183dfb 244 * @{
Kojto 115:87f2f5183dfb 245 */
Kojto 122:f9eeca106725 246 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 247 #if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 248 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008U)
Kojto 122:f9eeca106725 249 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 250 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010U)
Kojto 122:f9eeca106725 251 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020U)
Kojto 122:f9eeca106725 252 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040U)
Kojto 122:f9eeca106725 253 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080U)
Kojto 122:f9eeca106725 254 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100U)
Kojto 122:f9eeca106725 255 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200U)
Kojto 122:f9eeca106725 256 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400U)
Kojto 122:f9eeca106725 257 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800U)
Kojto 122:f9eeca106725 258 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000U)
Kojto 122:f9eeca106725 259 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000U)
Kojto 122:f9eeca106725 260 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000U)
Kojto 122:f9eeca106725 261 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000U)
Kojto 122:f9eeca106725 262 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000U)
Kojto 122:f9eeca106725 263 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000U)
Kojto 122:f9eeca106725 264 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000U)
Kojto 122:f9eeca106725 265 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000U)
Kojto 122:f9eeca106725 266 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000U)
Kojto 122:f9eeca106725 267 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000U)
Kojto 122:f9eeca106725 268 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000U)
Kojto 122:f9eeca106725 269 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000U)
Kojto 122:f9eeca106725 270 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000U)
Kojto 122:f9eeca106725 271 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000U)
Kojto 122:f9eeca106725 272 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 273 #define RCC_PERIPHCLK_SDMMC2 ((uint32_t)0x04000000U)
Kojto 122:f9eeca106725 274 #define RCC_PERIPHCLK_DFSDM1 ((uint32_t)0x08000000U)
Kojto 122:f9eeca106725 275 #define RCC_PERIPHCLK_DFSDM1_AUDIO ((uint32_t)0x10000000U)
Kojto 122:f9eeca106725 276 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 277
Kojto 116:c0f6e94411f5 278 /**
Kojto 116:c0f6e94411f5 279 * @}
Kojto 116:c0f6e94411f5 280 */
Kojto 115:87f2f5183dfb 281
Kojto 116:c0f6e94411f5 282 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCCEx PLLI2SP Clock Divider
Kojto 116:c0f6e94411f5 283 * @{
Kojto 116:c0f6e94411f5 284 */
Kojto 122:f9eeca106725 285 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 286 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 287 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 288 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000003U)
Kojto 115:87f2f5183dfb 289 /**
Kojto 115:87f2f5183dfb 290 * @}
Kojto 115:87f2f5183dfb 291 */
Kojto 115:87f2f5183dfb 292
Kojto 115:87f2f5183dfb 293 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
Kojto 115:87f2f5183dfb 294 * @{
Kojto 115:87f2f5183dfb 295 */
Kojto 122:f9eeca106725 296 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 297 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001U)
Kojto 122:f9eeca106725 298 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002U)
Kojto 122:f9eeca106725 299 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003U)
Kojto 115:87f2f5183dfb 300 /**
Kojto 115:87f2f5183dfb 301 * @}
Kojto 115:87f2f5183dfb 302 */
Kojto 115:87f2f5183dfb 303
Kojto 115:87f2f5183dfb 304 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
Kojto 115:87f2f5183dfb 305 * @{
Kojto 115:87f2f5183dfb 306 */
Kojto 122:f9eeca106725 307 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 308 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
Kojto 115:87f2f5183dfb 309 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
Kojto 115:87f2f5183dfb 310 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
Kojto 115:87f2f5183dfb 311 /**
Kojto 115:87f2f5183dfb 312 * @}
Kojto 115:87f2f5183dfb 313 */
Kojto 115:87f2f5183dfb 314
Kojto 115:87f2f5183dfb 315 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
Kojto 115:87f2f5183dfb 316 * @{
Kojto 115:87f2f5183dfb 317 */
Kojto 122:f9eeca106725 318 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 319 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
Kojto 115:87f2f5183dfb 320
Kojto 115:87f2f5183dfb 321 /**
Kojto 115:87f2f5183dfb 322 * @}
Kojto 115:87f2f5183dfb 323 */
Kojto 115:87f2f5183dfb 324
Kojto 115:87f2f5183dfb 325
Kojto 115:87f2f5183dfb 326 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
Kojto 115:87f2f5183dfb 327 * @{
Kojto 115:87f2f5183dfb 328 */
Kojto 122:f9eeca106725 329 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 330 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
Kojto 115:87f2f5183dfb 331 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
Kojto 122:f9eeca106725 332 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 333 #define RCC_SAI1CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI1SEL
Kojto 122:f9eeca106725 334 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 335 /**
Kojto 115:87f2f5183dfb 336 * @}
Kojto 115:87f2f5183dfb 337 */
Kojto 115:87f2f5183dfb 338
Kojto 115:87f2f5183dfb 339 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
Kojto 115:87f2f5183dfb 340 * @{
Kojto 115:87f2f5183dfb 341 */
Kojto 122:f9eeca106725 342 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 343 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
Kojto 115:87f2f5183dfb 344 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
Kojto 122:f9eeca106725 345 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 346 #define RCC_SAI2CLKSOURCE_PLLSRC RCC_DCKCFGR1_SAI2SEL
Kojto 122:f9eeca106725 347 #endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 348 /**
Kojto 115:87f2f5183dfb 349 * @}
Kojto 115:87f2f5183dfb 350 */
Kojto 115:87f2f5183dfb 351
Kojto 115:87f2f5183dfb 352 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
Kojto 115:87f2f5183dfb 353 * @{
Kojto 115:87f2f5183dfb 354 */
Kojto 122:f9eeca106725 355 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 356 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
Kojto 115:87f2f5183dfb 357 /**
Kojto 115:87f2f5183dfb 358 * @}
Kojto 115:87f2f5183dfb 359 */
Kojto 115:87f2f5183dfb 360
Kojto 115:87f2f5183dfb 361 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
Kojto 115:87f2f5183dfb 362 * @{
Kojto 115:87f2f5183dfb 363 */
Kojto 122:f9eeca106725 364 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 365 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
Kojto 115:87f2f5183dfb 366 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
Kojto 115:87f2f5183dfb 367 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
Kojto 115:87f2f5183dfb 368 /**
Kojto 115:87f2f5183dfb 369 * @}
Kojto 115:87f2f5183dfb 370 */
Kojto 115:87f2f5183dfb 371
Kojto 115:87f2f5183dfb 372 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
Kojto 115:87f2f5183dfb 373 * @{
Kojto 115:87f2f5183dfb 374 */
Kojto 122:f9eeca106725 375 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 376 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
Kojto 115:87f2f5183dfb 377 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
Kojto 115:87f2f5183dfb 378 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
Kojto 115:87f2f5183dfb 379 /**
Kojto 115:87f2f5183dfb 380 * @}
Kojto 115:87f2f5183dfb 381 */
Kojto 115:87f2f5183dfb 382
Kojto 115:87f2f5183dfb 383 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
Kojto 115:87f2f5183dfb 384 * @{
Kojto 115:87f2f5183dfb 385 */
Kojto 122:f9eeca106725 386 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 387 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
Kojto 115:87f2f5183dfb 388 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
Kojto 115:87f2f5183dfb 389 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
Kojto 115:87f2f5183dfb 390 /**
Kojto 115:87f2f5183dfb 391 * @}
Kojto 115:87f2f5183dfb 392 */
Kojto 115:87f2f5183dfb 393
Kojto 115:87f2f5183dfb 394 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
Kojto 115:87f2f5183dfb 395 * @{
Kojto 115:87f2f5183dfb 396 */
Kojto 122:f9eeca106725 397 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 398 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
Kojto 115:87f2f5183dfb 399 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
Kojto 115:87f2f5183dfb 400 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
Kojto 115:87f2f5183dfb 401 /**
Kojto 115:87f2f5183dfb 402 * @}
Kojto 115:87f2f5183dfb 403 */
Kojto 115:87f2f5183dfb 404
Kojto 115:87f2f5183dfb 405 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
Kojto 115:87f2f5183dfb 406 * @{
Kojto 115:87f2f5183dfb 407 */
Kojto 122:f9eeca106725 408 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 409 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
Kojto 115:87f2f5183dfb 410 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
Kojto 115:87f2f5183dfb 411 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
Kojto 115:87f2f5183dfb 412 /**
Kojto 115:87f2f5183dfb 413 * @}
Kojto 115:87f2f5183dfb 414 */
Kojto 115:87f2f5183dfb 415
Kojto 115:87f2f5183dfb 416 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
Kojto 115:87f2f5183dfb 417 * @{
Kojto 115:87f2f5183dfb 418 */
Kojto 122:f9eeca106725 419 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 420 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
Kojto 115:87f2f5183dfb 421 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
Kojto 115:87f2f5183dfb 422 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
Kojto 115:87f2f5183dfb 423 /**
Kojto 115:87f2f5183dfb 424 * @}
Kojto 115:87f2f5183dfb 425 */
Kojto 115:87f2f5183dfb 426
Kojto 115:87f2f5183dfb 427 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
Kojto 115:87f2f5183dfb 428 * @{
Kojto 115:87f2f5183dfb 429 */
Kojto 122:f9eeca106725 430 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 431 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
Kojto 115:87f2f5183dfb 432 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
Kojto 115:87f2f5183dfb 433 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
Kojto 115:87f2f5183dfb 434 /**
Kojto 115:87f2f5183dfb 435 * @}
Kojto 115:87f2f5183dfb 436 */
Kojto 115:87f2f5183dfb 437
Kojto 115:87f2f5183dfb 438 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
Kojto 115:87f2f5183dfb 439 * @{
Kojto 115:87f2f5183dfb 440 */
Kojto 122:f9eeca106725 441 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 442 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
Kojto 115:87f2f5183dfb 443 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
Kojto 115:87f2f5183dfb 444 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
Kojto 115:87f2f5183dfb 445 /**
Kojto 115:87f2f5183dfb 446 * @}
Kojto 115:87f2f5183dfb 447 */
Kojto 115:87f2f5183dfb 448
Kojto 115:87f2f5183dfb 449 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
Kojto 115:87f2f5183dfb 450 * @{
Kojto 115:87f2f5183dfb 451 */
Kojto 122:f9eeca106725 452 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 453 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
Kojto 115:87f2f5183dfb 454 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
Kojto 115:87f2f5183dfb 455 /**
Kojto 115:87f2f5183dfb 456 * @}
Kojto 115:87f2f5183dfb 457 */
Kojto 115:87f2f5183dfb 458
Kojto 115:87f2f5183dfb 459 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
Kojto 115:87f2f5183dfb 460 * @{
Kojto 115:87f2f5183dfb 461 */
Kojto 122:f9eeca106725 462 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 463 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
Kojto 115:87f2f5183dfb 464 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
Kojto 115:87f2f5183dfb 465
Kojto 115:87f2f5183dfb 466 /**
Kojto 115:87f2f5183dfb 467 * @}
Kojto 115:87f2f5183dfb 468 */
Kojto 115:87f2f5183dfb 469
Kojto 115:87f2f5183dfb 470 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
Kojto 115:87f2f5183dfb 471 * @{
Kojto 115:87f2f5183dfb 472 */
Kojto 122:f9eeca106725 473 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 474 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
Kojto 115:87f2f5183dfb 475 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
Kojto 115:87f2f5183dfb 476 /**
Kojto 115:87f2f5183dfb 477 * @}
Kojto 115:87f2f5183dfb 478 */
Kojto 115:87f2f5183dfb 479
Kojto 115:87f2f5183dfb 480 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
Kojto 115:87f2f5183dfb 481 * @{
Kojto 115:87f2f5183dfb 482 */
Kojto 122:f9eeca106725 483 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 484 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
Kojto 115:87f2f5183dfb 485 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
Kojto 115:87f2f5183dfb 486 /**
Kojto 115:87f2f5183dfb 487 * @}
Kojto 115:87f2f5183dfb 488 */
Kojto 115:87f2f5183dfb 489
Kojto 115:87f2f5183dfb 490 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
Kojto 115:87f2f5183dfb 491 * @{
Kojto 115:87f2f5183dfb 492 */
Kojto 122:f9eeca106725 493 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 494 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
Kojto 115:87f2f5183dfb 495 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
Kojto 115:87f2f5183dfb 496 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
Kojto 115:87f2f5183dfb 497
Kojto 115:87f2f5183dfb 498 /**
Kojto 115:87f2f5183dfb 499 * @}
Kojto 115:87f2f5183dfb 500 */
Kojto 115:87f2f5183dfb 501
Kojto 115:87f2f5183dfb 502 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
Kojto 115:87f2f5183dfb 503 * @{
Kojto 115:87f2f5183dfb 504 */
Kojto 122:f9eeca106725 505 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 506 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
Kojto 115:87f2f5183dfb 507 /**
Kojto 115:87f2f5183dfb 508 * @}
Kojto 115:87f2f5183dfb 509 */
Kojto 115:87f2f5183dfb 510
Kojto 115:87f2f5183dfb 511 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
Kojto 115:87f2f5183dfb 512 * @{
Kojto 115:87f2f5183dfb 513 */
Kojto 122:f9eeca106725 514 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000U)
Kojto 115:87f2f5183dfb 515 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
Kojto 116:c0f6e94411f5 516 /**
Kojto 116:c0f6e94411f5 517 * @}
Kojto 116:c0f6e94411f5 518 */
Kojto 115:87f2f5183dfb 519
Kojto 116:c0f6e94411f5 520 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
Kojto 116:c0f6e94411f5 521 * @{
Kojto 116:c0f6e94411f5 522 */
Kojto 122:f9eeca106725 523 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
Kojto 116:c0f6e94411f5 524 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
Kojto 115:87f2f5183dfb 525 /**
Kojto 115:87f2f5183dfb 526 * @}
Kojto 115:87f2f5183dfb 527 */
Kojto 115:87f2f5183dfb 528
Kojto 122:f9eeca106725 529 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 530 /** @defgroup RCCEx_SDMMC2_Clock_Source RCCEx SDMMC2 Clock Source
Kojto 122:f9eeca106725 531 * @{
Kojto 122:f9eeca106725 532 */
Kojto 122:f9eeca106725 533 #define RCC_SDMMC2CLKSOURCE_CLK48 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 534 #define RCC_SDMMC2CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC2SEL
Kojto 122:f9eeca106725 535 /**
Kojto 122:f9eeca106725 536 * @}
Kojto 122:f9eeca106725 537 */
Kojto 122:f9eeca106725 538
Kojto 122:f9eeca106725 539 /** @defgroup RCCEx_DFSDM1_Kernel_Clock_Source RCCEx DFSDM1 Kernel Clock Source
Kojto 122:f9eeca106725 540 * @{
Kojto 122:f9eeca106725 541 */
Kojto 122:f9eeca106725 542 #define RCC_DFSDM1CLKSOURCE_PCLK ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 543 #define RCC_DFSDM1CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL
Kojto 122:f9eeca106725 544 /**
Kojto 122:f9eeca106725 545 * @}
Kojto 122:f9eeca106725 546 */
Kojto 122:f9eeca106725 547
Kojto 122:f9eeca106725 548 /** @defgroup RCCEx_DFSDM1_AUDIO_Clock_Source RCCEx DFSDM1 AUDIO Clock Source
Kojto 122:f9eeca106725 549 * @{
Kojto 122:f9eeca106725 550 */
Kojto 122:f9eeca106725 551 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI1 ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 552 #define RCC_DFSDM1AUDIOCLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL
Kojto 122:f9eeca106725 553 /**
Kojto 122:f9eeca106725 554 * @}
Kojto 122:f9eeca106725 555 */
Kojto 122:f9eeca106725 556 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 557
Kojto 122:f9eeca106725 558 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 559 /** @defgroup RCCEx_DSI_Clock_Source RCC DSI Clock Source
Kojto 122:f9eeca106725 560 * @{
Kojto 122:f9eeca106725 561 */
Kojto 122:f9eeca106725 562 #define RCC_DSICLKSOURCE_DSIPHY ((uint32_t)0x00000000U)
Kojto 122:f9eeca106725 563 #define RCC_DSICLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR2_DSISEL)
Kojto 122:f9eeca106725 564 /**
Kojto 122:f9eeca106725 565 * @}
Kojto 122:f9eeca106725 566 */
Kojto 122:f9eeca106725 567 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 568
Kojto 115:87f2f5183dfb 569 /**
Kojto 115:87f2f5183dfb 570 * @}
Kojto 115:87f2f5183dfb 571 */
Kojto 115:87f2f5183dfb 572
Kojto 115:87f2f5183dfb 573 /* Exported macro ------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 574 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 115:87f2f5183dfb 575 * @{
Kojto 115:87f2f5183dfb 576 */
Kojto 115:87f2f5183dfb 577 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto 115:87f2f5183dfb 578 * @brief Enables or disables the AHB/APB peripheral clock.
Kojto 115:87f2f5183dfb 579 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 580 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 581 * using it.
Kojto 115:87f2f5183dfb 582 * @{
Kojto 115:87f2f5183dfb 583 */
Kojto 115:87f2f5183dfb 584
Kojto 115:87f2f5183dfb 585 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 115:87f2f5183dfb 586 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 587 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 588 * using it.
Kojto 115:87f2f5183dfb 589 */
Kojto 115:87f2f5183dfb 590 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 591 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 592 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 115:87f2f5183dfb 593 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 594 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 115:87f2f5183dfb 595 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 596 } while(0)
Kojto 122:f9eeca106725 597
Kojto 115:87f2f5183dfb 598 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 599 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 600 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
Kojto 115:87f2f5183dfb 601 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 602 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
Kojto 115:87f2f5183dfb 603 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 604 } while(0)
Kojto 122:f9eeca106725 605
Kojto 115:87f2f5183dfb 606 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 607 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 608 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 115:87f2f5183dfb 609 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 610 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 115:87f2f5183dfb 611 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 612 } while(0)
Kojto 115:87f2f5183dfb 613
Kojto 115:87f2f5183dfb 614 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 615 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 616 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto 115:87f2f5183dfb 617 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 618 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto 115:87f2f5183dfb 619 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 620 } while(0)
Kojto 115:87f2f5183dfb 621
Kojto 115:87f2f5183dfb 622 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 623 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 624 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 115:87f2f5183dfb 625 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 626 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 115:87f2f5183dfb 627 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 628 } while(0)
Kojto 115:87f2f5183dfb 629
Kojto 115:87f2f5183dfb 630 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 631 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 632 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 115:87f2f5183dfb 633 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 634 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 115:87f2f5183dfb 635 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 636 } while(0)
Kojto 115:87f2f5183dfb 637
Kojto 115:87f2f5183dfb 638 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 639 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 640 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 115:87f2f5183dfb 641 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 642 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 115:87f2f5183dfb 643 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 644 } while(0)
Kojto 115:87f2f5183dfb 645
Kojto 115:87f2f5183dfb 646 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 647 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 648 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 115:87f2f5183dfb 649 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 650 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 115:87f2f5183dfb 651 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 652 } while(0)
Kojto 115:87f2f5183dfb 653
Kojto 115:87f2f5183dfb 654 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 655 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 115:87f2f5183dfb 657 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 658 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 115:87f2f5183dfb 659 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 660 } while(0)
Kojto 115:87f2f5183dfb 661
Kojto 115:87f2f5183dfb 662 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 663 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 664 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 115:87f2f5183dfb 665 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 666 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 115:87f2f5183dfb 667 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 668 } while(0)
Kojto 115:87f2f5183dfb 669
Kojto 115:87f2f5183dfb 670 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 671 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 672 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 115:87f2f5183dfb 673 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 674 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 115:87f2f5183dfb 675 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 676 } while(0)
Kojto 115:87f2f5183dfb 677
Kojto 115:87f2f5183dfb 678 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 679 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 680 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 115:87f2f5183dfb 681 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 682 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 115:87f2f5183dfb 683 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 684 } while(0)
Kojto 115:87f2f5183dfb 685
Kojto 115:87f2f5183dfb 686 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 687 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 688 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 115:87f2f5183dfb 689 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 690 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 115:87f2f5183dfb 691 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 692 } while(0)
Kojto 115:87f2f5183dfb 693
Kojto 115:87f2f5183dfb 694 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 695 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 696 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 115:87f2f5183dfb 697 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 698 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 115:87f2f5183dfb 699 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 700 } while(0)
Kojto 115:87f2f5183dfb 701
Kojto 115:87f2f5183dfb 702 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 703 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 704 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 115:87f2f5183dfb 705 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 706 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 115:87f2f5183dfb 707 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 708 } while(0)
Kojto 115:87f2f5183dfb 709
Kojto 115:87f2f5183dfb 710 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 711 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 712 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto 115:87f2f5183dfb 713 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 714 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto 115:87f2f5183dfb 715 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 716 } while(0)
Kojto 115:87f2f5183dfb 717
Kojto 115:87f2f5183dfb 718 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 719 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 720 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto 115:87f2f5183dfb 721 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 722 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto 115:87f2f5183dfb 723 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 724 } while(0)
Kojto 115:87f2f5183dfb 725
Kojto 115:87f2f5183dfb 726 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto 115:87f2f5183dfb 727 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
Kojto 115:87f2f5183dfb 728 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 115:87f2f5183dfb 729 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto 115:87f2f5183dfb 730 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 115:87f2f5183dfb 731 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 115:87f2f5183dfb 732 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 115:87f2f5183dfb 733 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 115:87f2f5183dfb 734 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 115:87f2f5183dfb 735 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto 115:87f2f5183dfb 736 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto 115:87f2f5183dfb 737 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 115:87f2f5183dfb 738 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 115:87f2f5183dfb 739 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 115:87f2f5183dfb 740 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 115:87f2f5183dfb 741 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto 115:87f2f5183dfb 742 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto 115:87f2f5183dfb 743 /**
Kojto 115:87f2f5183dfb 744 * @brief Enable ETHERNET clock.
Kojto 115:87f2f5183dfb 745 */
Kojto 115:87f2f5183dfb 746 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 747 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 748 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 115:87f2f5183dfb 749 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 750 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 115:87f2f5183dfb 751 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 752 } while(0)
Kojto 115:87f2f5183dfb 753
Kojto 115:87f2f5183dfb 754 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 755 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 756 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 115:87f2f5183dfb 757 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 758 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 115:87f2f5183dfb 759 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 760 } while(0)
Kojto 115:87f2f5183dfb 761
Kojto 115:87f2f5183dfb 762 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 763 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 764 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 115:87f2f5183dfb 765 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 766 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 115:87f2f5183dfb 767 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 768 } while(0)
Kojto 115:87f2f5183dfb 769
Kojto 115:87f2f5183dfb 770 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 771 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 772 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 115:87f2f5183dfb 773 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 774 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 115:87f2f5183dfb 775 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 776 } while(0)
Kojto 122:f9eeca106725 777
Kojto 115:87f2f5183dfb 778 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto 115:87f2f5183dfb 779 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto 115:87f2f5183dfb 780 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto 115:87f2f5183dfb 781 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto 115:87f2f5183dfb 782 } while(0)
Kojto 115:87f2f5183dfb 783 /**
Kojto 115:87f2f5183dfb 784 * @brief Disable ETHERNET clock.
Kojto 115:87f2f5183dfb 785 */
Kojto 115:87f2f5183dfb 786 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 115:87f2f5183dfb 787 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 115:87f2f5183dfb 788 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 115:87f2f5183dfb 789 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto 115:87f2f5183dfb 790 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto 115:87f2f5183dfb 791 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto 115:87f2f5183dfb 792 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto 115:87f2f5183dfb 793 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto 115:87f2f5183dfb 794 } while(0)
Kojto 115:87f2f5183dfb 795
Kojto 115:87f2f5183dfb 796 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 115:87f2f5183dfb 797 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 798 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 799 * using it.
Kojto 115:87f2f5183dfb 800 */
Kojto 115:87f2f5183dfb 801 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 802 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 803 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 115:87f2f5183dfb 804 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 805 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 115:87f2f5183dfb 806 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 807 } while(0)
Kojto 115:87f2f5183dfb 808
Kojto 122:f9eeca106725 809 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 810 #define __HAL_RCC_JPEG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 811 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 812 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
Kojto 122:f9eeca106725 813 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 814 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_JPEGEN);\
Kojto 122:f9eeca106725 815 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 816 } while(0)
Kojto 122:f9eeca106725 817 #define __HAL_RCC_JPEG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_JPEGEN))
Kojto 122:f9eeca106725 818 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 819
Kojto 115:87f2f5183dfb 820 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 821 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 822 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto 115:87f2f5183dfb 823 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 824 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto 115:87f2f5183dfb 825 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 826 } while(0)
Kojto 115:87f2f5183dfb 827
Kojto 115:87f2f5183dfb 828 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 829 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 830 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
Kojto 115:87f2f5183dfb 831 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 832 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
Kojto 115:87f2f5183dfb 833 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 834 __HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto 115:87f2f5183dfb 835 } while(0)
Kojto 122:f9eeca106725 836
Kojto 116:c0f6e94411f5 837 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 115:87f2f5183dfb 838 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto 115:87f2f5183dfb 839
Kojto 116:c0f6e94411f5 840 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN))
Kojto 122:f9eeca106725 841 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 842 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 843 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 844 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 115:87f2f5183dfb 845 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 846 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 115:87f2f5183dfb 847 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 848 } while(0)
Kojto 115:87f2f5183dfb 849
Kojto 115:87f2f5183dfb 850 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 851 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 852 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 115:87f2f5183dfb 853 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 854 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 115:87f2f5183dfb 855 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 856 } while(0)
Kojto 122:f9eeca106725 857
Kojto 115:87f2f5183dfb 858 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto 115:87f2f5183dfb 859 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 122:f9eeca106725 860 #endif /* STM32F756x || STM32F777xx || STM32F779xx */
Kojto 116:c0f6e94411f5 861
Kojto 115:87f2f5183dfb 862 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 115:87f2f5183dfb 863 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 864 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 865 * using it.
Kojto 115:87f2f5183dfb 866 */
Kojto 115:87f2f5183dfb 867 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 868 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 869 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 115:87f2f5183dfb 870 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 871 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 115:87f2f5183dfb 872 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 873 } while(0)
Kojto 115:87f2f5183dfb 874
Kojto 115:87f2f5183dfb 875 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 876 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 877 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto 115:87f2f5183dfb 878 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 879 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto 115:87f2f5183dfb 880 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 881 } while(0)
Kojto 115:87f2f5183dfb 882
Kojto 115:87f2f5183dfb 883 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto 115:87f2f5183dfb 884 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto 115:87f2f5183dfb 885
Kojto 115:87f2f5183dfb 886 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 115:87f2f5183dfb 887 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 888 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 889 * using it.
Kojto 115:87f2f5183dfb 890 */
Kojto 115:87f2f5183dfb 891 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 892 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 893 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 115:87f2f5183dfb 894 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 895 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 115:87f2f5183dfb 896 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 897 } while(0)
Kojto 115:87f2f5183dfb 898
Kojto 115:87f2f5183dfb 899 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 900 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 901 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 115:87f2f5183dfb 902 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 903 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 115:87f2f5183dfb 904 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 905 } while(0)
Kojto 115:87f2f5183dfb 906
Kojto 115:87f2f5183dfb 907 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 908 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 909 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 115:87f2f5183dfb 910 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 911 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 115:87f2f5183dfb 912 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 913 } while(0)
Kojto 115:87f2f5183dfb 914
Kojto 115:87f2f5183dfb 915 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 916 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 917 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 115:87f2f5183dfb 918 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 919 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 115:87f2f5183dfb 920 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 921 } while(0)
Kojto 115:87f2f5183dfb 922
Kojto 115:87f2f5183dfb 923 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 924 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 925 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 115:87f2f5183dfb 926 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 927 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 115:87f2f5183dfb 928 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 929 } while(0)
Kojto 115:87f2f5183dfb 930
Kojto 115:87f2f5183dfb 931 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 932 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 933 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 115:87f2f5183dfb 934 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 935 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 115:87f2f5183dfb 936 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 937 } while(0)
Kojto 115:87f2f5183dfb 938
Kojto 115:87f2f5183dfb 939 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 940 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 941 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 115:87f2f5183dfb 942 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 943 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 115:87f2f5183dfb 944 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 945 } while(0)
Kojto 115:87f2f5183dfb 946
Kojto 115:87f2f5183dfb 947 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 948 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 949 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 115:87f2f5183dfb 950 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 951 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 115:87f2f5183dfb 952 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 953 } while(0)
Kojto 115:87f2f5183dfb 954
Kojto 115:87f2f5183dfb 955 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 956 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 957 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 115:87f2f5183dfb 958 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 959 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 115:87f2f5183dfb 960 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 961 } while(0)
Kojto 115:87f2f5183dfb 962
Kojto 115:87f2f5183dfb 963 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 964 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 965 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto 115:87f2f5183dfb 966 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 967 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto 115:87f2f5183dfb 968 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 969 } while(0)
Kojto 115:87f2f5183dfb 970
Kojto 122:f9eeca106725 971 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 972 #define __HAL_RCC_RTC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 973 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 974 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
Kojto 122:f9eeca106725 975 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 976 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_RTCEN);\
Kojto 122:f9eeca106725 977 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 978 } while(0)
Kojto 122:f9eeca106725 979
Kojto 122:f9eeca106725 980 #define __HAL_RCC_CAN3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 981 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 982 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
Kojto 122:f9eeca106725 983 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 984 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN3EN);\
Kojto 122:f9eeca106725 985 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 986 } while(0)
Kojto 122:f9eeca106725 987 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 988
Kojto 115:87f2f5183dfb 989 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 990 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 991 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 115:87f2f5183dfb 992 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 993 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 115:87f2f5183dfb 994 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 995 } while(0)
Kojto 115:87f2f5183dfb 996
Kojto 115:87f2f5183dfb 997 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 998 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 999 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 115:87f2f5183dfb 1000 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1001 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 115:87f2f5183dfb 1002 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1003 } while(0)
Kojto 115:87f2f5183dfb 1004
Kojto 115:87f2f5183dfb 1005 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1006 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1007 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto 115:87f2f5183dfb 1008 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1009 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto 115:87f2f5183dfb 1010 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1011 } while(0)
Kojto 115:87f2f5183dfb 1012
Kojto 115:87f2f5183dfb 1013 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1014 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1015 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 115:87f2f5183dfb 1016 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1017 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 115:87f2f5183dfb 1018 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1019 } while(0)
Kojto 115:87f2f5183dfb 1020
Kojto 115:87f2f5183dfb 1021 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1022 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1023 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 115:87f2f5183dfb 1024 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1025 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 115:87f2f5183dfb 1026 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1027 } while(0)
Kojto 115:87f2f5183dfb 1028
Kojto 115:87f2f5183dfb 1029 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1030 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1031 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 115:87f2f5183dfb 1032 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1033 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 115:87f2f5183dfb 1034 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1035 } while(0)
Kojto 115:87f2f5183dfb 1036
Kojto 115:87f2f5183dfb 1037 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1038 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1039 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 115:87f2f5183dfb 1040 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1041 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 115:87f2f5183dfb 1042 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1043 } while(0)
Kojto 115:87f2f5183dfb 1044
Kojto 115:87f2f5183dfb 1045 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1046 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1047 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 115:87f2f5183dfb 1048 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1049 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 115:87f2f5183dfb 1050 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1051 } while(0)
Kojto 115:87f2f5183dfb 1052
Kojto 115:87f2f5183dfb 1053 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1054 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1055 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 115:87f2f5183dfb 1056 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1057 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 115:87f2f5183dfb 1058 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1059 } while(0)
Kojto 115:87f2f5183dfb 1060
Kojto 115:87f2f5183dfb 1061 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1062 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1063 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 115:87f2f5183dfb 1064 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1065 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 115:87f2f5183dfb 1066 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1067 } while(0)
Kojto 115:87f2f5183dfb 1068
Kojto 115:87f2f5183dfb 1069 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1070 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1071 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
Kojto 115:87f2f5183dfb 1072 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1073 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
Kojto 115:87f2f5183dfb 1074 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1075 } while(0)
Kojto 115:87f2f5183dfb 1076
Kojto 115:87f2f5183dfb 1077 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1078 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1079 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 115:87f2f5183dfb 1080 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1081 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 115:87f2f5183dfb 1082 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1083 } while(0)
Kojto 115:87f2f5183dfb 1084
Kojto 115:87f2f5183dfb 1085 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1086 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1087 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 115:87f2f5183dfb 1088 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1089 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 115:87f2f5183dfb 1090 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1091 } while(0)
Kojto 115:87f2f5183dfb 1092
Kojto 115:87f2f5183dfb 1093 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1094 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1095 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 115:87f2f5183dfb 1096 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1097 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 115:87f2f5183dfb 1098 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1099 } while(0)
Kojto 115:87f2f5183dfb 1100
Kojto 115:87f2f5183dfb 1101 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1102 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1103 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 115:87f2f5183dfb 1104 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1105 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 115:87f2f5183dfb 1106 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1107 } while(0)
Kojto 115:87f2f5183dfb 1108
Kojto 115:87f2f5183dfb 1109 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1110 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1111 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto 115:87f2f5183dfb 1112 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1113 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto 115:87f2f5183dfb 1114 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1115 } while(0)
Kojto 115:87f2f5183dfb 1116
Kojto 115:87f2f5183dfb 1117 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1118 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1119 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto 115:87f2f5183dfb 1120 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1121 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto 115:87f2f5183dfb 1122 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1123 } while(0)
Kojto 115:87f2f5183dfb 1124
Kojto 115:87f2f5183dfb 1125 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 115:87f2f5183dfb 1126 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 115:87f2f5183dfb 1127 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 115:87f2f5183dfb 1128 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 115:87f2f5183dfb 1129 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 115:87f2f5183dfb 1130 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 115:87f2f5183dfb 1131 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 115:87f2f5183dfb 1132 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 115:87f2f5183dfb 1133 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 115:87f2f5183dfb 1134 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
Kojto 122:f9eeca106725 1135 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1136 #define __HAL_RCC_RTC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_RTCEN))
Kojto 122:f9eeca106725 1137 #define __HAL_RCC_CAN3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN3EN))
Kojto 122:f9eeca106725 1138 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1139 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 115:87f2f5183dfb 1140 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 115:87f2f5183dfb 1141 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto 115:87f2f5183dfb 1142 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 115:87f2f5183dfb 1143 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 115:87f2f5183dfb 1144 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 115:87f2f5183dfb 1145 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 115:87f2f5183dfb 1146 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 115:87f2f5183dfb 1147 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 115:87f2f5183dfb 1148 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto 115:87f2f5183dfb 1149 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
Kojto 115:87f2f5183dfb 1150 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 115:87f2f5183dfb 1151 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 115:87f2f5183dfb 1152 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto 115:87f2f5183dfb 1153 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 115:87f2f5183dfb 1154 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto 115:87f2f5183dfb 1155 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto 115:87f2f5183dfb 1156
Kojto 115:87f2f5183dfb 1157 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 115:87f2f5183dfb 1158 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 1159 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 1160 * using it.
Kojto 115:87f2f5183dfb 1161 */
Kojto 115:87f2f5183dfb 1162 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1163 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1164 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 115:87f2f5183dfb 1165 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1166 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 115:87f2f5183dfb 1167 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1168 } while(0)
Kojto 115:87f2f5183dfb 1169
Kojto 115:87f2f5183dfb 1170 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1171 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1172 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 115:87f2f5183dfb 1173 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1174 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 115:87f2f5183dfb 1175 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1176 } while(0)
Kojto 115:87f2f5183dfb 1177
Kojto 115:87f2f5183dfb 1178 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1179 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1180 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 115:87f2f5183dfb 1181 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1182 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 115:87f2f5183dfb 1183 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1184 } while(0)
Kojto 115:87f2f5183dfb 1185
Kojto 115:87f2f5183dfb 1186 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1187 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1188 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 115:87f2f5183dfb 1189 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1190 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 115:87f2f5183dfb 1191 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1192 } while(0)
Kojto 115:87f2f5183dfb 1193
Kojto 122:f9eeca106725 1194 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1195 #define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1196 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1197 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
Kojto 122:f9eeca106725 1198 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1199 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC2EN);\
Kojto 122:f9eeca106725 1200 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1201 } while(0)
Kojto 122:f9eeca106725 1202 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1203
Kojto 115:87f2f5183dfb 1204 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1205 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1206 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 115:87f2f5183dfb 1207 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1208 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 115:87f2f5183dfb 1209 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1210 } while(0)
Kojto 115:87f2f5183dfb 1211
Kojto 115:87f2f5183dfb 1212 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1213 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1214 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 115:87f2f5183dfb 1215 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1216 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 115:87f2f5183dfb 1217 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1218 } while(0)
Kojto 115:87f2f5183dfb 1219
Kojto 115:87f2f5183dfb 1220 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1221 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1222 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 115:87f2f5183dfb 1223 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1224 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 115:87f2f5183dfb 1225 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1226 } while(0)
Kojto 115:87f2f5183dfb 1227
Kojto 115:87f2f5183dfb 1228 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1229 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1230 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
Kojto 115:87f2f5183dfb 1231 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1232 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
Kojto 115:87f2f5183dfb 1233 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1234 } while(0)
Kojto 115:87f2f5183dfb 1235
Kojto 115:87f2f5183dfb 1236 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1237 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1238 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 115:87f2f5183dfb 1239 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1240 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 115:87f2f5183dfb 1241 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1242 } while(0)
Kojto 115:87f2f5183dfb 1243
Kojto 115:87f2f5183dfb 1244 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1245 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1246 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 115:87f2f5183dfb 1247 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1248 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 115:87f2f5183dfb 1249 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1250 } while(0)
Kojto 115:87f2f5183dfb 1251
Kojto 115:87f2f5183dfb 1252 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1253 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1254 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 115:87f2f5183dfb 1255 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1256 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 115:87f2f5183dfb 1257 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1258 } while(0)
Kojto 115:87f2f5183dfb 1259
Kojto 115:87f2f5183dfb 1260 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1261 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1262 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 115:87f2f5183dfb 1263 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1264 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 115:87f2f5183dfb 1265 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1266 } while(0)
Kojto 115:87f2f5183dfb 1267
Kojto 115:87f2f5183dfb 1268 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1269 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1270 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 115:87f2f5183dfb 1271 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1272 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 115:87f2f5183dfb 1273 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1274 } while(0)
Kojto 115:87f2f5183dfb 1275
Kojto 115:87f2f5183dfb 1276 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1277 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1278 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 115:87f2f5183dfb 1279 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1280 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 115:87f2f5183dfb 1281 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1282 } while(0)
Kojto 115:87f2f5183dfb 1283
Kojto 115:87f2f5183dfb 1284 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1285 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1286 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto 115:87f2f5183dfb 1287 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1288 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto 115:87f2f5183dfb 1289 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1290 } while(0)
Kojto 115:87f2f5183dfb 1291
Kojto 115:87f2f5183dfb 1292 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1293 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1294 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 115:87f2f5183dfb 1295 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1296 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 115:87f2f5183dfb 1297 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1298 } while(0)
Kojto 115:87f2f5183dfb 1299
Kojto 115:87f2f5183dfb 1300 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1301 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1302 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto 115:87f2f5183dfb 1303 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1304 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto 115:87f2f5183dfb 1305 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1306 } while(0)
Kojto 115:87f2f5183dfb 1307
Kojto 122:f9eeca106725 1308 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1309 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1310 __IO uint32_t tmpreg; \
Kojto 115:87f2f5183dfb 1311 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto 115:87f2f5183dfb 1312 /* Delay after an RCC peripheral clock enabling */ \
Kojto 115:87f2f5183dfb 1313 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto 115:87f2f5183dfb 1314 UNUSED(tmpreg); \
Kojto 115:87f2f5183dfb 1315 } while(0)
Kojto 122:f9eeca106725 1316 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1317
Kojto 122:f9eeca106725 1318 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1319 #define __HAL_RCC_DSI_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1320 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1321 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto 122:f9eeca106725 1322 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1323 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIEN);\
Kojto 122:f9eeca106725 1324 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1325 } while(0)
Kojto 122:f9eeca106725 1326 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 1327
Kojto 122:f9eeca106725 1328 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1329 #define __HAL_RCC_DFSDM1_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1330 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1331 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
Kojto 122:f9eeca106725 1332 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1333 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\
Kojto 122:f9eeca106725 1334 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1335 } while(0)
Kojto 122:f9eeca106725 1336
Kojto 122:f9eeca106725 1337 #define __HAL_RCC_MDIO_CLK_ENABLE() do { \
Kojto 122:f9eeca106725 1338 __IO uint32_t tmpreg; \
Kojto 122:f9eeca106725 1339 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
Kojto 122:f9eeca106725 1340 /* Delay after an RCC peripheral clock enabling */ \
Kojto 122:f9eeca106725 1341 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_MDIOEN);\
Kojto 122:f9eeca106725 1342 UNUSED(tmpreg); \
Kojto 122:f9eeca106725 1343 } while(0)
Kojto 122:f9eeca106725 1344 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 116:c0f6e94411f5 1345
Kojto 115:87f2f5183dfb 1346 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 115:87f2f5183dfb 1347 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 115:87f2f5183dfb 1348 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 115:87f2f5183dfb 1349 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 122:f9eeca106725 1350 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1351 #define __HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC2EN))
Kojto 122:f9eeca106725 1352 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1353 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 115:87f2f5183dfb 1354 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 115:87f2f5183dfb 1355 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 116:c0f6e94411f5 1356 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
Kojto 115:87f2f5183dfb 1357 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 115:87f2f5183dfb 1358 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto 115:87f2f5183dfb 1359 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 115:87f2f5183dfb 1360 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto 115:87f2f5183dfb 1361 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 115:87f2f5183dfb 1362 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 115:87f2f5183dfb 1363 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto 115:87f2f5183dfb 1364 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto 115:87f2f5183dfb 1365 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto 122:f9eeca106725 1366 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1367 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto 122:f9eeca106725 1368 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1369 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1370 #define __HAL_RCC_DSI_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DSIEN))
Kojto 122:f9eeca106725 1371 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 1372 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1373 #define __HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DFSDM1EN))
Kojto 122:f9eeca106725 1374 #define __HAL_RCC_MDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_MDIOEN))
Kojto 122:f9eeca106725 1375 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1376
Kojto 115:87f2f5183dfb 1377 /**
Kojto 115:87f2f5183dfb 1378 * @}
Kojto 115:87f2f5183dfb 1379 */
Kojto 115:87f2f5183dfb 1380
Kojto 115:87f2f5183dfb 1381
Kojto 115:87f2f5183dfb 1382 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
Kojto 115:87f2f5183dfb 1383 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
Kojto 115:87f2f5183dfb 1384 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 1385 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 1386 * using it.
Kojto 115:87f2f5183dfb 1387 * @{
Kojto 115:87f2f5183dfb 1388 */
Kojto 115:87f2f5183dfb 1389
Kojto 115:87f2f5183dfb 1390 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto 115:87f2f5183dfb 1391 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 1392 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 1393 * using it.
Kojto 115:87f2f5183dfb 1394 */
Kojto 115:87f2f5183dfb 1395 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto 115:87f2f5183dfb 1396 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
Kojto 115:87f2f5183dfb 1397 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
Kojto 115:87f2f5183dfb 1398 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
Kojto 115:87f2f5183dfb 1399 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto 115:87f2f5183dfb 1400 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto 115:87f2f5183dfb 1401 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
Kojto 115:87f2f5183dfb 1402 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
Kojto 115:87f2f5183dfb 1403 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
Kojto 115:87f2f5183dfb 1404 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto 115:87f2f5183dfb 1405 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto 115:87f2f5183dfb 1406 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto 115:87f2f5183dfb 1407 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto 115:87f2f5183dfb 1408 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
Kojto 115:87f2f5183dfb 1409 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
Kojto 115:87f2f5183dfb 1410 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
Kojto 115:87f2f5183dfb 1411 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
Kojto 115:87f2f5183dfb 1412
Kojto 115:87f2f5183dfb 1413 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto 115:87f2f5183dfb 1414 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
Kojto 115:87f2f5183dfb 1415 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
Kojto 115:87f2f5183dfb 1416 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
Kojto 115:87f2f5183dfb 1417 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto 115:87f2f5183dfb 1418 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
Kojto 115:87f2f5183dfb 1419 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
Kojto 115:87f2f5183dfb 1420 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
Kojto 115:87f2f5183dfb 1421 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
Kojto 115:87f2f5183dfb 1422 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto 115:87f2f5183dfb 1423 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto 115:87f2f5183dfb 1424 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto 115:87f2f5183dfb 1425 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto 115:87f2f5183dfb 1426 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
Kojto 115:87f2f5183dfb 1427 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
Kojto 115:87f2f5183dfb 1428 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
Kojto 115:87f2f5183dfb 1429 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
Kojto 115:87f2f5183dfb 1430 /**
Kojto 115:87f2f5183dfb 1431 * @brief Enable ETHERNET clock.
Kojto 115:87f2f5183dfb 1432 */
Kojto 115:87f2f5183dfb 1433 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Kojto 115:87f2f5183dfb 1434 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
Kojto 115:87f2f5183dfb 1435 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
Kojto 115:87f2f5183dfb 1436 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
Kojto 115:87f2f5183dfb 1437 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
Kojto 115:87f2f5183dfb 1438 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
Kojto 122:f9eeca106725 1439 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
Kojto 115:87f2f5183dfb 1440
Kojto 115:87f2f5183dfb 1441 /**
Kojto 115:87f2f5183dfb 1442 * @brief Disable ETHERNET clock.
Kojto 115:87f2f5183dfb 1443 */
Kojto 115:87f2f5183dfb 1444 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Kojto 115:87f2f5183dfb 1445 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
Kojto 115:87f2f5183dfb 1446 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
Kojto 115:87f2f5183dfb 1447 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
Kojto 115:87f2f5183dfb 1448 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
Kojto 115:87f2f5183dfb 1449 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
Kojto 122:f9eeca106725 1450 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
Kojto 115:87f2f5183dfb 1451
Kojto 115:87f2f5183dfb 1452 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto 115:87f2f5183dfb 1453 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 1454 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 1455 * using it.
Kojto 115:87f2f5183dfb 1456 */
Kojto 115:87f2f5183dfb 1457 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto 115:87f2f5183dfb 1458 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto 115:87f2f5183dfb 1459 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto 116:c0f6e94411f5 1460
Kojto 115:87f2f5183dfb 1461 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto 115:87f2f5183dfb 1462 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto 115:87f2f5183dfb 1463 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto 115:87f2f5183dfb 1464
Kojto 122:f9eeca106725 1465 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1466 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
Kojto 115:87f2f5183dfb 1467 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
Kojto 115:87f2f5183dfb 1468 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
Kojto 115:87f2f5183dfb 1469 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
Kojto 122:f9eeca106725 1470 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1471
Kojto 122:f9eeca106725 1472 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1473 #define __HAL_RCC_JPEG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) != RESET)
Kojto 122:f9eeca106725 1474 #define __HAL_RCC_JPEG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_JPEGEN)) == RESET)
Kojto 122:f9eeca106725 1475 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1476
Kojto 115:87f2f5183dfb 1477 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto 115:87f2f5183dfb 1478 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 1479 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 1480 * using it.
Kojto 115:87f2f5183dfb 1481 */
Kojto 115:87f2f5183dfb 1482 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Kojto 115:87f2f5183dfb 1483 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto 115:87f2f5183dfb 1484
Kojto 115:87f2f5183dfb 1485 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Kojto 115:87f2f5183dfb 1486 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto 115:87f2f5183dfb 1487
Kojto 115:87f2f5183dfb 1488 /** @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 115:87f2f5183dfb 1489 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 1490 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 1491 * using it.
Kojto 115:87f2f5183dfb 1492 */
Kojto 115:87f2f5183dfb 1493 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto 115:87f2f5183dfb 1494 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto 115:87f2f5183dfb 1495 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto 115:87f2f5183dfb 1496 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 115:87f2f5183dfb 1497 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto 115:87f2f5183dfb 1498 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto 115:87f2f5183dfb 1499 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto 115:87f2f5183dfb 1500 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto 115:87f2f5183dfb 1501 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto 115:87f2f5183dfb 1502 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
Kojto 122:f9eeca106725 1503 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1504 #define __HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) != RESET)
Kojto 122:f9eeca106725 1505 #define __HAL_RCC_CAN3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) != RESET)
Kojto 122:f9eeca106725 1506 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1507 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 115:87f2f5183dfb 1508 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 115:87f2f5183dfb 1509 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
Kojto 115:87f2f5183dfb 1510 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto 115:87f2f5183dfb 1511 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto 115:87f2f5183dfb 1512 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto 115:87f2f5183dfb 1513 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto 115:87f2f5183dfb 1514 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto 115:87f2f5183dfb 1515 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 115:87f2f5183dfb 1516 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto 115:87f2f5183dfb 1517 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
Kojto 115:87f2f5183dfb 1518 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto 115:87f2f5183dfb 1519 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto 115:87f2f5183dfb 1520 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto 115:87f2f5183dfb 1521 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto 115:87f2f5183dfb 1522 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
Kojto 115:87f2f5183dfb 1523 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
Kojto 115:87f2f5183dfb 1524
Kojto 115:87f2f5183dfb 1525 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto 115:87f2f5183dfb 1526 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto 115:87f2f5183dfb 1527 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto 115:87f2f5183dfb 1528 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 115:87f2f5183dfb 1529 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto 115:87f2f5183dfb 1530 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto 115:87f2f5183dfb 1531 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto 115:87f2f5183dfb 1532 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto 115:87f2f5183dfb 1533 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto 115:87f2f5183dfb 1534 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
Kojto 122:f9eeca106725 1535 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1536 #define __HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_RTCEN)) == RESET)
Kojto 122:f9eeca106725 1537 #define __HAL_RCC_CAN3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN3EN)) == RESET)
Kojto 122:f9eeca106725 1538 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1539 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 115:87f2f5183dfb 1540 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 115:87f2f5183dfb 1541 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
Kojto 115:87f2f5183dfb 1542 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto 115:87f2f5183dfb 1543 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto 115:87f2f5183dfb 1544 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto 115:87f2f5183dfb 1545 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto 115:87f2f5183dfb 1546 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto 115:87f2f5183dfb 1547 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 115:87f2f5183dfb 1548 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto 115:87f2f5183dfb 1549 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
Kojto 115:87f2f5183dfb 1550 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto 115:87f2f5183dfb 1551 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto 115:87f2f5183dfb 1552 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto 115:87f2f5183dfb 1553 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto 115:87f2f5183dfb 1554 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
Kojto 115:87f2f5183dfb 1555 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
Kojto 115:87f2f5183dfb 1556
Kojto 115:87f2f5183dfb 1557 /** @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 115:87f2f5183dfb 1558 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 115:87f2f5183dfb 1559 * is disabled and the application software has to enable this clock before
Kojto 115:87f2f5183dfb 1560 * using it.
Kojto 115:87f2f5183dfb 1561 */
Kojto 115:87f2f5183dfb 1562 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 115:87f2f5183dfb 1563 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto 115:87f2f5183dfb 1564 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto 115:87f2f5183dfb 1565 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto 115:87f2f5183dfb 1566 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 115:87f2f5183dfb 1567 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto 115:87f2f5183dfb 1568 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto 115:87f2f5183dfb 1569 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
Kojto 115:87f2f5183dfb 1570 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 115:87f2f5183dfb 1571 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto 115:87f2f5183dfb 1572 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Kojto 115:87f2f5183dfb 1573 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto 115:87f2f5183dfb 1574 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Kojto 115:87f2f5183dfb 1575 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto 115:87f2f5183dfb 1576 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
Kojto 115:87f2f5183dfb 1577 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
Kojto 115:87f2f5183dfb 1578 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
Kojto 122:f9eeca106725 1579 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1580 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
Kojto 122:f9eeca106725 1581 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1582 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1583 #define __HAL_RCC_DSI_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) != RESET)
Kojto 122:f9eeca106725 1584 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 1585 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1586 #define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) != RESET)
Kojto 122:f9eeca106725 1587 #define __HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) != RESET)
Kojto 122:f9eeca106725 1588 #define __HAL_RCC_MDIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) != RESET)
Kojto 122:f9eeca106725 1589 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1590 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 115:87f2f5183dfb 1591 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto 115:87f2f5183dfb 1592 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto 115:87f2f5183dfb 1593 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto 115:87f2f5183dfb 1594 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 115:87f2f5183dfb 1595 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto 115:87f2f5183dfb 1596 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto 115:87f2f5183dfb 1597 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
Kojto 115:87f2f5183dfb 1598 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 115:87f2f5183dfb 1599 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto 115:87f2f5183dfb 1600 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Kojto 115:87f2f5183dfb 1601 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto 115:87f2f5183dfb 1602 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Kojto 115:87f2f5183dfb 1603 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto 115:87f2f5183dfb 1604 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
Kojto 115:87f2f5183dfb 1605 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
Kojto 115:87f2f5183dfb 1606 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
Kojto 122:f9eeca106725 1607 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1608 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
Kojto 122:f9eeca106725 1609 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1610 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1611 #define __HAL_RCC_DSI_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DSIEN)) == RESET)
Kojto 122:f9eeca106725 1612 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 1613 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1614 #define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC2EN)) == RESET)
Kojto 122:f9eeca106725 1615 #define __HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_DFSDM1EN)) == RESET)
Kojto 122:f9eeca106725 1616 #define __HAL_RCC_MDIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_MDIOEN)) == RESET)
Kojto 122:f9eeca106725 1617 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1618 /**
Kojto 115:87f2f5183dfb 1619 * @}
Kojto 115:87f2f5183dfb 1620 */
Kojto 115:87f2f5183dfb 1621
Kojto 115:87f2f5183dfb 1622 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto 115:87f2f5183dfb 1623 * @brief Forces or releases AHB/APB peripheral reset.
Kojto 115:87f2f5183dfb 1624 * @{
Kojto 115:87f2f5183dfb 1625 */
Kojto 115:87f2f5183dfb 1626
Kojto 115:87f2f5183dfb 1627 /** @brief Force or release AHB1 peripheral reset.
Kojto 115:87f2f5183dfb 1628 */
Kojto 115:87f2f5183dfb 1629 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Kojto 115:87f2f5183dfb 1630 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
Kojto 115:87f2f5183dfb 1631 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
Kojto 115:87f2f5183dfb 1632 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 115:87f2f5183dfb 1633 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 115:87f2f5183dfb 1634 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 115:87f2f5183dfb 1635 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 115:87f2f5183dfb 1636 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
Kojto 115:87f2f5183dfb 1637 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
Kojto 115:87f2f5183dfb 1638 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 115:87f2f5183dfb 1639 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 115:87f2f5183dfb 1640 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 115:87f2f5183dfb 1641 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
Kojto 115:87f2f5183dfb 1642 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
Kojto 115:87f2f5183dfb 1643 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
Kojto 115:87f2f5183dfb 1644
Kojto 115:87f2f5183dfb 1645 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 115:87f2f5183dfb 1646 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto 115:87f2f5183dfb 1647 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto 115:87f2f5183dfb 1648 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 115:87f2f5183dfb 1649 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 115:87f2f5183dfb 1650 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 115:87f2f5183dfb 1651 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 115:87f2f5183dfb 1652 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto 115:87f2f5183dfb 1653 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto 115:87f2f5183dfb 1654 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 115:87f2f5183dfb 1655 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 115:87f2f5183dfb 1656 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 115:87f2f5183dfb 1657 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 115:87f2f5183dfb 1658 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto 115:87f2f5183dfb 1659 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto 115:87f2f5183dfb 1660
Kojto 115:87f2f5183dfb 1661 /** @brief Force or release AHB2 peripheral reset.
Kojto 115:87f2f5183dfb 1662 */
Kojto 122:f9eeca106725 1663 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFFU)
Kojto 115:87f2f5183dfb 1664 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 115:87f2f5183dfb 1665 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
Kojto 115:87f2f5183dfb 1666 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
Kojto 115:87f2f5183dfb 1667
Kojto 122:f9eeca106725 1668 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)
Kojto 115:87f2f5183dfb 1669 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 115:87f2f5183dfb 1670 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto 115:87f2f5183dfb 1671 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto 115:87f2f5183dfb 1672
Kojto 122:f9eeca106725 1673 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1674 #define __HAL_RCC_JPEG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_JPEGRST))
Kojto 122:f9eeca106725 1675 #define __HAL_RCC_JPEG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_JPEGRST))
Kojto 122:f9eeca106725 1676 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1677
Kojto 122:f9eeca106725 1678 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1679 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
Kojto 115:87f2f5183dfb 1680 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
Kojto 115:87f2f5183dfb 1681 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto 115:87f2f5183dfb 1682 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto 122:f9eeca106725 1683 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1684
Kojto 115:87f2f5183dfb 1685 /** @brief Force or release AHB3 peripheral reset
Kojto 115:87f2f5183dfb 1686 */
Kojto 122:f9eeca106725 1687 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFFU)
Kojto 115:87f2f5183dfb 1688 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
Kojto 115:87f2f5183dfb 1689 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
Kojto 115:87f2f5183dfb 1690
Kojto 122:f9eeca106725 1691 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00U)
Kojto 115:87f2f5183dfb 1692 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto 115:87f2f5183dfb 1693 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto 115:87f2f5183dfb 1694
Kojto 115:87f2f5183dfb 1695 /** @brief Force or release APB1 peripheral reset.
Kojto 115:87f2f5183dfb 1696 */
Kojto 115:87f2f5183dfb 1697 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 115:87f2f5183dfb 1698 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 115:87f2f5183dfb 1699 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 115:87f2f5183dfb 1700 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 115:87f2f5183dfb 1701 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 115:87f2f5183dfb 1702 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 115:87f2f5183dfb 1703 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 115:87f2f5183dfb 1704 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 115:87f2f5183dfb 1705 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 115:87f2f5183dfb 1706 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
Kojto 122:f9eeca106725 1707 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1708 #define __HAL_RCC_CAN3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN3RST))
Kojto 122:f9eeca106725 1709 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1710 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 115:87f2f5183dfb 1711 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 115:87f2f5183dfb 1712 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
Kojto 115:87f2f5183dfb 1713 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 115:87f2f5183dfb 1714 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 115:87f2f5183dfb 1715 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 115:87f2f5183dfb 1716 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 115:87f2f5183dfb 1717 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 115:87f2f5183dfb 1718 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 115:87f2f5183dfb 1719 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 115:87f2f5183dfb 1720 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
Kojto 115:87f2f5183dfb 1721 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 115:87f2f5183dfb 1722 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 115:87f2f5183dfb 1723 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 115:87f2f5183dfb 1724 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 115:87f2f5183dfb 1725 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
Kojto 115:87f2f5183dfb 1726 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
Kojto 115:87f2f5183dfb 1727
Kojto 115:87f2f5183dfb 1728 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 115:87f2f5183dfb 1729 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 115:87f2f5183dfb 1730 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 115:87f2f5183dfb 1731 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 115:87f2f5183dfb 1732 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 115:87f2f5183dfb 1733 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 115:87f2f5183dfb 1734 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 115:87f2f5183dfb 1735 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 115:87f2f5183dfb 1736 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 115:87f2f5183dfb 1737 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
Kojto 122:f9eeca106725 1738 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1739 #define __HAL_RCC_CAN3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN3RST))
Kojto 122:f9eeca106725 1740 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1741 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 115:87f2f5183dfb 1742 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 115:87f2f5183dfb 1743 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto 115:87f2f5183dfb 1744 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 115:87f2f5183dfb 1745 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 115:87f2f5183dfb 1746 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 115:87f2f5183dfb 1747 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 115:87f2f5183dfb 1748 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 115:87f2f5183dfb 1749 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 115:87f2f5183dfb 1750 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto 115:87f2f5183dfb 1751 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
Kojto 115:87f2f5183dfb 1752 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 115:87f2f5183dfb 1753 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 115:87f2f5183dfb 1754 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto 115:87f2f5183dfb 1755 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 115:87f2f5183dfb 1756 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto 115:87f2f5183dfb 1757 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto 115:87f2f5183dfb 1758
Kojto 115:87f2f5183dfb 1759 /** @brief Force or release APB2 peripheral reset.
Kojto 115:87f2f5183dfb 1760 */
Kojto 115:87f2f5183dfb 1761 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 115:87f2f5183dfb 1762 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 115:87f2f5183dfb 1763 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 115:87f2f5183dfb 1764 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 115:87f2f5183dfb 1765 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 115:87f2f5183dfb 1766 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
Kojto 115:87f2f5183dfb 1767 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 115:87f2f5183dfb 1768 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
Kojto 115:87f2f5183dfb 1769 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 115:87f2f5183dfb 1770 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
Kojto 115:87f2f5183dfb 1771 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Kojto 115:87f2f5183dfb 1772 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 115:87f2f5183dfb 1773 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
Kojto 115:87f2f5183dfb 1774 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
Kojto 115:87f2f5183dfb 1775 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
Kojto 122:f9eeca106725 1776 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1777 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
Kojto 122:f9eeca106725 1778 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1779
Kojto 115:87f2f5183dfb 1780 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 115:87f2f5183dfb 1781 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 115:87f2f5183dfb 1782 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 115:87f2f5183dfb 1783 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 115:87f2f5183dfb 1784 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 115:87f2f5183dfb 1785 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
Kojto 115:87f2f5183dfb 1786 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 115:87f2f5183dfb 1787 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto 115:87f2f5183dfb 1788 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 115:87f2f5183dfb 1789 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto 115:87f2f5183dfb 1790 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 115:87f2f5183dfb 1791 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 115:87f2f5183dfb 1792 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto 115:87f2f5183dfb 1793 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto 115:87f2f5183dfb 1794 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto 122:f9eeca106725 1795 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1796 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto 122:f9eeca106725 1797 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1798
Kojto 122:f9eeca106725 1799 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1800 #define __HAL_RCC_DSI_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DSIRST))
Kojto 122:f9eeca106725 1801 #define __HAL_RCC_DSI_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DSIRST))
Kojto 122:f9eeca106725 1802 #endif /* STM32F769xx || STM32F779xx */
Kojto 116:c0f6e94411f5 1803
Kojto 122:f9eeca106725 1804 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1805 #define __HAL_RCC_SDMMC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC2RST))
Kojto 122:f9eeca106725 1806 #define __HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DFSDM1RST))
Kojto 122:f9eeca106725 1807 #define __HAL_RCC_MDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_MDIORST))
Kojto 122:f9eeca106725 1808
Kojto 122:f9eeca106725 1809 #define __HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC2RST))
Kojto 122:f9eeca106725 1810 #define __HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DFSDM1RST))
Kojto 122:f9eeca106725 1811 #define __HAL_RCC_MDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_MDIORST))
Kojto 122:f9eeca106725 1812 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1813 /**
Kojto 115:87f2f5183dfb 1814 * @}
Kojto 115:87f2f5183dfb 1815 */
Kojto 115:87f2f5183dfb 1816
Kojto 115:87f2f5183dfb 1817 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
Kojto 115:87f2f5183dfb 1818 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 1819 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 1820 * power consumption.
Kojto 115:87f2f5183dfb 1821 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 1822 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 1823 * @{
Kojto 115:87f2f5183dfb 1824 */
Kojto 115:87f2f5183dfb 1825
Kojto 115:87f2f5183dfb 1826 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 1827 */
Kojto 115:87f2f5183dfb 1828 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
Kojto 115:87f2f5183dfb 1829 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
Kojto 115:87f2f5183dfb 1830 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto 115:87f2f5183dfb 1831 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 115:87f2f5183dfb 1832 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 115:87f2f5183dfb 1833 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
Kojto 115:87f2f5183dfb 1834 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
Kojto 115:87f2f5183dfb 1835 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto 115:87f2f5183dfb 1836 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto 115:87f2f5183dfb 1837 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 115:87f2f5183dfb 1838 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 115:87f2f5183dfb 1839 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 115:87f2f5183dfb 1840 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 115:87f2f5183dfb 1841 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 115:87f2f5183dfb 1842 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 115:87f2f5183dfb 1843 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 115:87f2f5183dfb 1844 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 115:87f2f5183dfb 1845 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
Kojto 115:87f2f5183dfb 1846 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
Kojto 115:87f2f5183dfb 1847 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 115:87f2f5183dfb 1848 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 115:87f2f5183dfb 1849 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 115:87f2f5183dfb 1850 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
Kojto 115:87f2f5183dfb 1851 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto 115:87f2f5183dfb 1852 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto 115:87f2f5183dfb 1853
Kojto 115:87f2f5183dfb 1854 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto 115:87f2f5183dfb 1855 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
Kojto 115:87f2f5183dfb 1856 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto 115:87f2f5183dfb 1857 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 115:87f2f5183dfb 1858 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 115:87f2f5183dfb 1859 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
Kojto 115:87f2f5183dfb 1860 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 115:87f2f5183dfb 1861 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto 115:87f2f5183dfb 1862 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto 115:87f2f5183dfb 1863 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 115:87f2f5183dfb 1864 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 115:87f2f5183dfb 1865 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 115:87f2f5183dfb 1866 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 115:87f2f5183dfb 1867 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 115:87f2f5183dfb 1868 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 115:87f2f5183dfb 1869 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 115:87f2f5183dfb 1870 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 115:87f2f5183dfb 1871 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto 115:87f2f5183dfb 1872 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto 115:87f2f5183dfb 1873 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 115:87f2f5183dfb 1874 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 115:87f2f5183dfb 1875 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 115:87f2f5183dfb 1876 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto 115:87f2f5183dfb 1877 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto 115:87f2f5183dfb 1878 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto 115:87f2f5183dfb 1879
Kojto 115:87f2f5183dfb 1880 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 1881 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 1882 * power consumption.
Kojto 115:87f2f5183dfb 1883 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 1884 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 1885 */
Kojto 115:87f2f5183dfb 1886 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 115:87f2f5183dfb 1887 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 116:c0f6e94411f5 1888
Kojto 122:f9eeca106725 1889 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1890 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_JPEGLPEN))
Kojto 122:f9eeca106725 1891 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_JPEGLPEN))
Kojto 122:f9eeca106725 1892 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 1893
Kojto 115:87f2f5183dfb 1894 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
Kojto 115:87f2f5183dfb 1895 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto 115:87f2f5183dfb 1896
Kojto 115:87f2f5183dfb 1897 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto 115:87f2f5183dfb 1898 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto 115:87f2f5183dfb 1899
Kojto 122:f9eeca106725 1900 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 1901 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
Kojto 115:87f2f5183dfb 1902 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
Kojto 115:87f2f5183dfb 1903
Kojto 115:87f2f5183dfb 1904 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto 115:87f2f5183dfb 1905 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 122:f9eeca106725 1906 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1907
Kojto 115:87f2f5183dfb 1908 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 1909 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 1910 * power consumption.
Kojto 115:87f2f5183dfb 1911 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 1912 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 1913 */
Kojto 115:87f2f5183dfb 1914 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Kojto 115:87f2f5183dfb 1915 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto 115:87f2f5183dfb 1916
Kojto 115:87f2f5183dfb 1917 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
Kojto 115:87f2f5183dfb 1918 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto 115:87f2f5183dfb 1919
Kojto 115:87f2f5183dfb 1920 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 1921 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 1922 * power consumption.
Kojto 115:87f2f5183dfb 1923 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 1924 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 1925 */
Kojto 115:87f2f5183dfb 1926 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
Kojto 115:87f2f5183dfb 1927 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
Kojto 115:87f2f5183dfb 1928 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
Kojto 115:87f2f5183dfb 1929 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 115:87f2f5183dfb 1930 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 115:87f2f5183dfb 1931 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 115:87f2f5183dfb 1932 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 115:87f2f5183dfb 1933 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 115:87f2f5183dfb 1934 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 115:87f2f5183dfb 1935 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
Kojto 122:f9eeca106725 1936 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1937 #define __HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_RTCLPEN))
Kojto 122:f9eeca106725 1938 #define __HAL_RCC_CAN3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN3LPEN))
Kojto 122:f9eeca106725 1939 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1940 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 115:87f2f5183dfb 1941 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
Kojto 115:87f2f5183dfb 1942 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto 115:87f2f5183dfb 1943 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 115:87f2f5183dfb 1944 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 115:87f2f5183dfb 1945 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 115:87f2f5183dfb 1946 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 115:87f2f5183dfb 1947 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 115:87f2f5183dfb 1948 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 115:87f2f5183dfb 1949 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
Kojto 115:87f2f5183dfb 1950 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
Kojto 115:87f2f5183dfb 1951 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 115:87f2f5183dfb 1952 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 115:87f2f5183dfb 1953 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
Kojto 115:87f2f5183dfb 1954 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 115:87f2f5183dfb 1955 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
Kojto 115:87f2f5183dfb 1956 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
Kojto 115:87f2f5183dfb 1957
Kojto 115:87f2f5183dfb 1958 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto 115:87f2f5183dfb 1959 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto 115:87f2f5183dfb 1960 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto 115:87f2f5183dfb 1961 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 115:87f2f5183dfb 1962 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 115:87f2f5183dfb 1963 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 115:87f2f5183dfb 1964 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 115:87f2f5183dfb 1965 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 115:87f2f5183dfb 1966 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 115:87f2f5183dfb 1967 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
Kojto 122:f9eeca106725 1968 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 1969 #define __HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_RTCLPEN))
Kojto 122:f9eeca106725 1970 #define __HAL_RCC_CAN3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN3LPEN))
Kojto 122:f9eeca106725 1971 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 1972 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 115:87f2f5183dfb 1973 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto 115:87f2f5183dfb 1974 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto 115:87f2f5183dfb 1975 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 115:87f2f5183dfb 1976 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 115:87f2f5183dfb 1977 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 115:87f2f5183dfb 1978 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 115:87f2f5183dfb 1979 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 115:87f2f5183dfb 1980 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 115:87f2f5183dfb 1981 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto 115:87f2f5183dfb 1982 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
Kojto 115:87f2f5183dfb 1983 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 115:87f2f5183dfb 1984 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 115:87f2f5183dfb 1985 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto 115:87f2f5183dfb 1986 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 116:c0f6e94411f5 1987 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto 116:c0f6e94411f5 1988 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto 115:87f2f5183dfb 1989
Kojto 115:87f2f5183dfb 1990 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 1991 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 1992 * power consumption.
Kojto 115:87f2f5183dfb 1993 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 1994 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 1995 */
Kojto 115:87f2f5183dfb 1996 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 115:87f2f5183dfb 1997 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 115:87f2f5183dfb 1998 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 115:87f2f5183dfb 1999 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 115:87f2f5183dfb 2000 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 115:87f2f5183dfb 2001 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 115:87f2f5183dfb 2002 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 115:87f2f5183dfb 2003 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
Kojto 115:87f2f5183dfb 2004 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 115:87f2f5183dfb 2005 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
Kojto 115:87f2f5183dfb 2006 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 115:87f2f5183dfb 2007 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
Kojto 115:87f2f5183dfb 2008 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
Kojto 115:87f2f5183dfb 2009 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
Kojto 115:87f2f5183dfb 2010 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
Kojto 115:87f2f5183dfb 2011 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
Kojto 115:87f2f5183dfb 2012 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
Kojto 122:f9eeca106725 2013 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 2014 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
Kojto 122:f9eeca106725 2015 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2016
Kojto 115:87f2f5183dfb 2017 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 115:87f2f5183dfb 2018 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 115:87f2f5183dfb 2019 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 115:87f2f5183dfb 2020 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 115:87f2f5183dfb 2021 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 115:87f2f5183dfb 2022 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 115:87f2f5183dfb 2023 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 115:87f2f5183dfb 2024 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
Kojto 115:87f2f5183dfb 2025 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 115:87f2f5183dfb 2026 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto 115:87f2f5183dfb 2027 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 115:87f2f5183dfb 2028 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto 115:87f2f5183dfb 2029 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 115:87f2f5183dfb 2030 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto 115:87f2f5183dfb 2031 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto 115:87f2f5183dfb 2032 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto 115:87f2f5183dfb 2033 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto 122:f9eeca106725 2034 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 2035 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto 122:f9eeca106725 2036 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 2037 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2038 #define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DSILPEN))
Kojto 122:f9eeca106725 2039 #define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DSILPEN))
Kojto 122:f9eeca106725 2040 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 2041 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2042 #define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC2LPEN))
Kojto 122:f9eeca106725 2043 #define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_DFSDM1LPEN))
Kojto 122:f9eeca106725 2044 #define __HAL_RCC_MDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_MDIOLPEN))
Kojto 116:c0f6e94411f5 2045
Kojto 122:f9eeca106725 2046 #define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC2LPEN))
Kojto 122:f9eeca106725 2047 #define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_DFSDM1LPEN))
Kojto 122:f9eeca106725 2048 #define __HAL_RCC_MDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_MDIOLPEN))
Kojto 122:f9eeca106725 2049 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2050 /**
Kojto 115:87f2f5183dfb 2051 * @}
Kojto 115:87f2f5183dfb 2052 */
Kojto 115:87f2f5183dfb 2053
Kojto 115:87f2f5183dfb 2054 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
Kojto 115:87f2f5183dfb 2055 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 2056 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 2057 * power consumption.
Kojto 115:87f2f5183dfb 2058 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 2059 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 2060 * @{
Kojto 115:87f2f5183dfb 2061 */
Kojto 115:87f2f5183dfb 2062
Kojto 115:87f2f5183dfb 2063 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 2064 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 2065 * power consumption.
Kojto 115:87f2f5183dfb 2066 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 2067 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 2068 */
Kojto 115:87f2f5183dfb 2069 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2070 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
Kojto 115:87f2f5183dfb 2071 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2072 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2073 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2074 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2075 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2076 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2077 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2078 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2079 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2080 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2081 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2082 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
Kojto 115:87f2f5183dfb 2083 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
Kojto 115:87f2f5183dfb 2084 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2085 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2086 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2087 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
Kojto 115:87f2f5183dfb 2088 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2089 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2090 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2091 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
Kojto 115:87f2f5183dfb 2092 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2093 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2094
Kojto 115:87f2f5183dfb 2095 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2096 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
Kojto 115:87f2f5183dfb 2097 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2098 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2099 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2100 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2101 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2102 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2103 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2104 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2105 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2106 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2107 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2108 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
Kojto 115:87f2f5183dfb 2109 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
Kojto 115:87f2f5183dfb 2110 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2111 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2112 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2113 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
Kojto 115:87f2f5183dfb 2114 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2115 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2116 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2117 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
Kojto 115:87f2f5183dfb 2118 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2119 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2120
Kojto 115:87f2f5183dfb 2121 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 2122 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 2123 * power consumption.
Kojto 115:87f2f5183dfb 2124 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 2125 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 2126 */
Kojto 115:87f2f5183dfb 2127 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
Kojto 115:87f2f5183dfb 2128 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
Kojto 116:c0f6e94411f5 2129
Kojto 122:f9eeca106725 2130 #if defined(STM32F767xx) || defined(STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2131 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) != RESET)
Kojto 122:f9eeca106725 2132 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_JPEGLPEN)) == RESET)
Kojto 122:f9eeca106725 2133 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 2134
Kojto 115:87f2f5183dfb 2135 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2136 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2137
Kojto 115:87f2f5183dfb 2138 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2139 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2140
Kojto 122:f9eeca106725 2141 #if defined(STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 2142 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2143 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2144
Kojto 115:87f2f5183dfb 2145 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2146 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
Kojto 122:f9eeca106725 2147 #endif /* STM32F756xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2148
Kojto 115:87f2f5183dfb 2149 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 2150 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 2151 * power consumption.
Kojto 115:87f2f5183dfb 2152 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 2153 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 2154 */
Kojto 115:87f2f5183dfb 2155 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2156 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2157
Kojto 115:87f2f5183dfb 2158 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
Kojto 115:87f2f5183dfb 2159 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
Kojto 115:87f2f5183dfb 2160
Kojto 115:87f2f5183dfb 2161 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 2162 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 2163 * power consumption.
Kojto 115:87f2f5183dfb 2164 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 2165 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 2166 */
Kojto 115:87f2f5183dfb 2167 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2168 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2169 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2170 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2171 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2172 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2173 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2174 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2175 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2176 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
Kojto 122:f9eeca106725 2177 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2178 #define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) != RESET)
Kojto 122:f9eeca106725 2179 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) != RESET)
Kojto 122:f9eeca106725 2180 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2181 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2182 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2183 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2184 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2185 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2186 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2187 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2188 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2189 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2190 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2191 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2192 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2193 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2194 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2195 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
Kojto 115:87f2f5183dfb 2196 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2197 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2198
Kojto 115:87f2f5183dfb 2199 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2200 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2201 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2202 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2203 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2204 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2205 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2206 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2207 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2208 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
Kojto 122:f9eeca106725 2209 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2210 #define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_RTCLPEN)) == RESET)
Kojto 122:f9eeca106725 2211 #define __HAL_RCC_CAN3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN3LPEN)) == RESET)
Kojto 122:f9eeca106725 2212 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2213 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2214 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2215 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2216 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2217 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2218 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2219 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2220 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2221 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2222 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2223 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2224 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2225 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2226 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2227 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
Kojto 115:87f2f5183dfb 2228 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2229 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2230
Kojto 115:87f2f5183dfb 2231 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 115:87f2f5183dfb 2232 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 115:87f2f5183dfb 2233 * power consumption.
Kojto 115:87f2f5183dfb 2234 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 115:87f2f5183dfb 2235 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 115:87f2f5183dfb 2236 */
Kojto 115:87f2f5183dfb 2237 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2238 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2239 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2240 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2241 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2242 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2243 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2244 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2245 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2246 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2247 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2248 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2249 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2250 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2251 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2252 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
Kojto 115:87f2f5183dfb 2253 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
Kojto 122:f9eeca106725 2254 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 2255 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
Kojto 122:f9eeca106725 2256 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 2257 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2258 #define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) != RESET)
Kojto 122:f9eeca106725 2259 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 2260 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2261 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) != RESET)
Kojto 122:f9eeca106725 2262 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != RESET)
Kojto 122:f9eeca106725 2263 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) != RESET)
Kojto 122:f9eeca106725 2264 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2265
Kojto 115:87f2f5183dfb 2266 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2267 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2268 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2269 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2270 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2271 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2272 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2273 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2274 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2275 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2276 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2277 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2278 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2279 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2280 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2281 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
Kojto 115:87f2f5183dfb 2282 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
Kojto 122:f9eeca106725 2283 #if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 115:87f2f5183dfb 2284 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
Kojto 122:f9eeca106725 2285 #endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 2286 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2287 #define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DSILPEN)) == RESET)
Kojto 122:f9eeca106725 2288 #endif /* STM32F769xx || STM32F779xx */
Kojto 122:f9eeca106725 2289 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2290 #define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC2LPEN)) == RESET)
Kojto 122:f9eeca106725 2291 #define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == RESET)
Kojto 122:f9eeca106725 2292 #define __HAL_RCC_MDIO_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_MDIOLPEN)) == RESET)
Kojto 122:f9eeca106725 2293 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2294 /**
Kojto 115:87f2f5183dfb 2295 * @}
Kojto 115:87f2f5183dfb 2296 */
Kojto 116:c0f6e94411f5 2297
Kojto 122:f9eeca106725 2298 /*------------------------------- PLL Configuration --------------------------*/
Kojto 122:f9eeca106725 2299 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2300 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 122:f9eeca106725 2301 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 2302 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 122:f9eeca106725 2303 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2304 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 2305 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 2306 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto 122:f9eeca106725 2307 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 122:f9eeca106725 2308 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 122:f9eeca106725 2309 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 122:f9eeca106725 2310 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 122:f9eeca106725 2311 * of 2 MHz to limit PLL jitter.
Kojto 122:f9eeca106725 2312 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto 122:f9eeca106725 2313 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto 122:f9eeca106725 2314 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 2315 * output frequency is between 100 and 432 MHz.
Kojto 122:f9eeca106725 2316 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto 122:f9eeca106725 2317 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 122:f9eeca106725 2318 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
Kojto 122:f9eeca106725 2319 * the System clock frequency.
Kojto 122:f9eeca106725 2320 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
Kojto 122:f9eeca106725 2321 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 122:f9eeca106725 2322 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 122:f9eeca106725 2323 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 122:f9eeca106725 2324 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 122:f9eeca106725 2325 * correctly.
Kojto 122:f9eeca106725 2326 * @param __PLLR__: specifies the division factor for DSI clock
Kojto 122:f9eeca106725 2327 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 122:f9eeca106725 2328 */
Kojto 122:f9eeca106725 2329 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto 122:f9eeca106725 2330 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
Kojto 122:f9eeca106725 2331 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
Kojto 122:f9eeca106725 2332 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
Kojto 122:f9eeca106725 2333 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
Kojto 122:f9eeca106725 2334 ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto 122:f9eeca106725 2335 #else
Kojto 122:f9eeca106725 2336 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 122:f9eeca106725 2337 * @note This function must be used only when the main PLL is disabled.
Kojto 122:f9eeca106725 2338 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 122:f9eeca106725 2339 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2340 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 2341 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 122:f9eeca106725 2342 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto 122:f9eeca106725 2343 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 122:f9eeca106725 2344 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 122:f9eeca106725 2345 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 122:f9eeca106725 2346 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 122:f9eeca106725 2347 * of 2 MHz to limit PLL jitter.
Kojto 122:f9eeca106725 2348 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto 122:f9eeca106725 2349 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto 122:f9eeca106725 2350 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 122:f9eeca106725 2351 * output frequency is between 100 and 432 MHz.
Kojto 122:f9eeca106725 2352 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto 122:f9eeca106725 2353 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 122:f9eeca106725 2354 * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
Kojto 122:f9eeca106725 2355 * the System clock frequency.
Kojto 122:f9eeca106725 2356 * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
Kojto 122:f9eeca106725 2357 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 122:f9eeca106725 2358 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 122:f9eeca106725 2359 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 122:f9eeca106725 2360 * the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 122:f9eeca106725 2361 * correctly.
Kojto 122:f9eeca106725 2362 */
Kojto 122:f9eeca106725 2363 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto 122:f9eeca106725 2364 (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
Kojto 122:f9eeca106725 2365 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
Kojto 122:f9eeca106725 2366 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
Kojto 122:f9eeca106725 2367 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto 122:f9eeca106725 2368 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2369 /*---------------------------------------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 2370
Kojto 115:87f2f5183dfb 2371 /** @brief Macro to configure the Timers clocks prescalers
Kojto 115:87f2f5183dfb 2372 * @param __PRESC__ : specifies the Timers clocks prescalers selection
Kojto 115:87f2f5183dfb 2373 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2374 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
Kojto 115:87f2f5183dfb 2375 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
Kojto 115:87f2f5183dfb 2376 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
Kojto 115:87f2f5183dfb 2377 * division by 4 or more.
Kojto 115:87f2f5183dfb 2378 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
Kojto 115:87f2f5183dfb 2379 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
Kojto 115:87f2f5183dfb 2380 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
Kojto 115:87f2f5183dfb 2381 * to division by 8 or more.
Kojto 115:87f2f5183dfb 2382 */
Kojto 115:87f2f5183dfb 2383 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
Kojto 116:c0f6e94411f5 2384 RCC->DCKCFGR1 |= (__PRESC__); \
Kojto 116:c0f6e94411f5 2385 }while(0)
Kojto 115:87f2f5183dfb 2386
Kojto 115:87f2f5183dfb 2387 /** @brief Macros to Enable or Disable the PLLISAI.
Kojto 115:87f2f5183dfb 2388 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto 115:87f2f5183dfb 2389 */
Kojto 115:87f2f5183dfb 2390 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
Kojto 115:87f2f5183dfb 2391 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
Kojto 115:87f2f5183dfb 2392
Kojto 115:87f2f5183dfb 2393 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto 115:87f2f5183dfb 2394 * @note This function must be used only when the PLLSAI is disabled.
Kojto 115:87f2f5183dfb 2395 * @note PLLSAI clock source is common with the main PLL (configured in
Kojto 115:87f2f5183dfb 2396 * RCC_PLLConfig function )
Kojto 115:87f2f5183dfb 2397 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto 116:c0f6e94411f5 2398 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto 115:87f2f5183dfb 2399 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto 116:c0f6e94411f5 2400 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto 116:c0f6e94411f5 2401 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
Kojto 116:c0f6e94411f5 2402 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
Kojto 115:87f2f5183dfb 2403 * @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto 115:87f2f5183dfb 2404 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 115:87f2f5183dfb 2405 * @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto 115:87f2f5183dfb 2406 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 115:87f2f5183dfb 2407 */
Kojto 116:c0f6e94411f5 2408 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto 116:c0f6e94411f5 2409 (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
Kojto 116:c0f6e94411f5 2410 ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
Kojto 116:c0f6e94411f5 2411 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
Kojto 116:c0f6e94411f5 2412 ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
Kojto 115:87f2f5183dfb 2413
Kojto 116:c0f6e94411f5 2414 /** @brief Macro to configure the PLLI2S clock multiplication and division factors.
Kojto 115:87f2f5183dfb 2415 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 115:87f2f5183dfb 2416 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 115:87f2f5183dfb 2417 * HAL_RCC_ClockConfig() API)
Kojto 115:87f2f5183dfb 2418 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 116:c0f6e94411f5 2419 * This parameter must be a number between Min_Data = 50 and Max_Data = 432.
Kojto 115:87f2f5183dfb 2420 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 116:c0f6e94411f5 2421 * output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
Kojto 116:c0f6e94411f5 2422 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
Kojto 116:c0f6e94411f5 2423 * This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
Kojto 115:87f2f5183dfb 2424 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
Kojto 115:87f2f5183dfb 2425 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 115:87f2f5183dfb 2426 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 115:87f2f5183dfb 2427 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 115:87f2f5183dfb 2428 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 116:c0f6e94411f5 2429 * on the I2S clock frequency.
Kojto 115:87f2f5183dfb 2430 */
Kojto 116:c0f6e94411f5 2431 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto 116:c0f6e94411f5 2432 (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
Kojto 116:c0f6e94411f5 2433 ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
Kojto 116:c0f6e94411f5 2434 ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
Kojto 116:c0f6e94411f5 2435 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
Kojto 115:87f2f5183dfb 2436
Kojto 115:87f2f5183dfb 2437 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto 115:87f2f5183dfb 2438 * @note This function must be called before enabling the PLLI2S.
Kojto 115:87f2f5183dfb 2439 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
Kojto 115:87f2f5183dfb 2440 * This parameter must be a number between 1 and 32.
Kojto 115:87f2f5183dfb 2441 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto 115:87f2f5183dfb 2442 */
Kojto 115:87f2f5183dfb 2443 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto 115:87f2f5183dfb 2444
Kojto 115:87f2f5183dfb 2445 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto 115:87f2f5183dfb 2446 * @note This function must be called before enabling the PLLSAI.
Kojto 115:87f2f5183dfb 2447 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto 115:87f2f5183dfb 2448 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto 115:87f2f5183dfb 2449 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto 115:87f2f5183dfb 2450 */
Kojto 115:87f2f5183dfb 2451 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto 115:87f2f5183dfb 2452
Kojto 115:87f2f5183dfb 2453 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto 115:87f2f5183dfb 2454 *
Kojto 115:87f2f5183dfb 2455 * @note This function must be called before enabling the PLLSAI.
Kojto 115:87f2f5183dfb 2456 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto 116:c0f6e94411f5 2457 * This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
Kojto 115:87f2f5183dfb 2458 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto 115:87f2f5183dfb 2459 */
Kojto 115:87f2f5183dfb 2460 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
Kojto 115:87f2f5183dfb 2461 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
Kojto 115:87f2f5183dfb 2462
Kojto 115:87f2f5183dfb 2463 /** @brief Macro to configure SAI1 clock source selection.
Kojto 115:87f2f5183dfb 2464 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 115:87f2f5183dfb 2465 * the SAI clock.
Kojto 115:87f2f5183dfb 2466 * @param __SOURCE__: specifies the SAI1 clock source.
Kojto 115:87f2f5183dfb 2467 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2468 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 115:87f2f5183dfb 2469 * as SAI1 clock.
Kojto 115:87f2f5183dfb 2470 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 115:87f2f5183dfb 2471 * as SAI1 clock.
Kojto 115:87f2f5183dfb 2472 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 115:87f2f5183dfb 2473 * used as SAI1 clock.
Kojto 122:f9eeca106725 2474 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
Kojto 122:f9eeca106725 2475 * used as SAI1 clock.
Kojto 122:f9eeca106725 2476 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Kojto 115:87f2f5183dfb 2477 */
Kojto 115:87f2f5183dfb 2478 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
Kojto 115:87f2f5183dfb 2479 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
Kojto 115:87f2f5183dfb 2480
Kojto 115:87f2f5183dfb 2481 /** @brief Macro to get the SAI1 clock source.
Kojto 115:87f2f5183dfb 2482 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2483 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 115:87f2f5183dfb 2484 * as SAI1 clock.
Kojto 115:87f2f5183dfb 2485 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 115:87f2f5183dfb 2486 * as SAI1 clock.
Kojto 115:87f2f5183dfb 2487 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 115:87f2f5183dfb 2488 * used as SAI1 clock.
Kojto 122:f9eeca106725 2489 * @arg RCC_SAI1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
Kojto 122:f9eeca106725 2490 * used as SAI1 clock.
Kojto 122:f9eeca106725 2491 * @note The RCC_SAI1CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Kojto 115:87f2f5183dfb 2492 */
Kojto 115:87f2f5183dfb 2493 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
Kojto 115:87f2f5183dfb 2494
Kojto 115:87f2f5183dfb 2495
Kojto 115:87f2f5183dfb 2496 /** @brief Macro to configure SAI2 clock source selection.
Kojto 115:87f2f5183dfb 2497 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 115:87f2f5183dfb 2498 * the SAI clock.
Kojto 115:87f2f5183dfb 2499 * @param __SOURCE__: specifies the SAI2 clock source.
Kojto 115:87f2f5183dfb 2500 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2501 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 115:87f2f5183dfb 2502 * as SAI2 clock.
Kojto 115:87f2f5183dfb 2503 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 115:87f2f5183dfb 2504 * as SAI2 clock.
Kojto 115:87f2f5183dfb 2505 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 115:87f2f5183dfb 2506 * used as SAI2 clock.
Kojto 122:f9eeca106725 2507 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
Kojto 122:f9eeca106725 2508 * used as SAI2 clock.
Kojto 122:f9eeca106725 2509 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Kojto 115:87f2f5183dfb 2510 */
Kojto 115:87f2f5183dfb 2511 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
Kojto 115:87f2f5183dfb 2512 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
Kojto 115:87f2f5183dfb 2513
Kojto 115:87f2f5183dfb 2514
Kojto 115:87f2f5183dfb 2515 /** @brief Macro to get the SAI2 clock source.
Kojto 115:87f2f5183dfb 2516 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2517 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 115:87f2f5183dfb 2518 * as SAI2 clock.
Kojto 115:87f2f5183dfb 2519 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 115:87f2f5183dfb 2520 * as SAI2 clock.
Kojto 115:87f2f5183dfb 2521 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 115:87f2f5183dfb 2522 * used as SAI2 clock.
Kojto 122:f9eeca106725 2523 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock
Kojto 122:f9eeca106725 2524 * used as SAI2 clock.
Kojto 122:f9eeca106725 2525 * @note The RCC_SAI2CLKSOURCE_PLLSRC value is only available with STM32F767/769/777/779xx Devices
Kojto 115:87f2f5183dfb 2526 */
Kojto 115:87f2f5183dfb 2527 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
Kojto 115:87f2f5183dfb 2528
Kojto 115:87f2f5183dfb 2529
Kojto 115:87f2f5183dfb 2530 /** @brief Enable PLLSAI_RDY interrupt.
Kojto 115:87f2f5183dfb 2531 */
Kojto 115:87f2f5183dfb 2532 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
Kojto 115:87f2f5183dfb 2533
Kojto 115:87f2f5183dfb 2534 /** @brief Disable PLLSAI_RDY interrupt.
Kojto 115:87f2f5183dfb 2535 */
Kojto 115:87f2f5183dfb 2536 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Kojto 115:87f2f5183dfb 2537
Kojto 115:87f2f5183dfb 2538 /** @brief Clear the PLLSAI RDY interrupt pending bits.
Kojto 115:87f2f5183dfb 2539 */
Kojto 115:87f2f5183dfb 2540 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
Kojto 115:87f2f5183dfb 2541
Kojto 115:87f2f5183dfb 2542 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
Kojto 115:87f2f5183dfb 2543 * @retval The new state (TRUE or FALSE).
Kojto 115:87f2f5183dfb 2544 */
Kojto 115:87f2f5183dfb 2545 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Kojto 115:87f2f5183dfb 2546
Kojto 115:87f2f5183dfb 2547 /** @brief Check PLLSAI RDY flag is set or not.
Kojto 115:87f2f5183dfb 2548 * @retval The new state (TRUE or FALSE).
Kojto 115:87f2f5183dfb 2549 */
Kojto 115:87f2f5183dfb 2550 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Kojto 115:87f2f5183dfb 2551
Kojto 115:87f2f5183dfb 2552 /** @brief Macro to Get I2S clock source selection.
Kojto 115:87f2f5183dfb 2553 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2554 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto 115:87f2f5183dfb 2555 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
Kojto 115:87f2f5183dfb 2556 */
Kojto 115:87f2f5183dfb 2557 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
Kojto 115:87f2f5183dfb 2558
Kojto 115:87f2f5183dfb 2559 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 115:87f2f5183dfb 2560 *
Kojto 115:87f2f5183dfb 2561 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
Kojto 115:87f2f5183dfb 2562 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2563 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 115:87f2f5183dfb 2564 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 115:87f2f5183dfb 2565 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 115:87f2f5183dfb 2566 */
Kojto 115:87f2f5183dfb 2567 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2568 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2569
Kojto 115:87f2f5183dfb 2570 /** @brief Macro to get the I2C1 clock source.
Kojto 115:87f2f5183dfb 2571 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2572 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 115:87f2f5183dfb 2573 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 115:87f2f5183dfb 2574 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 115:87f2f5183dfb 2575 */
Kojto 115:87f2f5183dfb 2576 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
Kojto 115:87f2f5183dfb 2577
Kojto 115:87f2f5183dfb 2578 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 115:87f2f5183dfb 2579 *
Kojto 115:87f2f5183dfb 2580 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
Kojto 115:87f2f5183dfb 2581 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2582 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto 115:87f2f5183dfb 2583 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 115:87f2f5183dfb 2584 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 115:87f2f5183dfb 2585 */
Kojto 115:87f2f5183dfb 2586 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2587 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2588
Kojto 115:87f2f5183dfb 2589 /** @brief Macro to get the I2C2 clock source.
Kojto 115:87f2f5183dfb 2590 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2591 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto 115:87f2f5183dfb 2592 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 115:87f2f5183dfb 2593 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 115:87f2f5183dfb 2594 */
Kojto 115:87f2f5183dfb 2595 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
Kojto 115:87f2f5183dfb 2596
Kojto 115:87f2f5183dfb 2597 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 115:87f2f5183dfb 2598 *
Kojto 115:87f2f5183dfb 2599 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
Kojto 115:87f2f5183dfb 2600 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2601 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 115:87f2f5183dfb 2602 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 115:87f2f5183dfb 2603 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 115:87f2f5183dfb 2604 */
Kojto 115:87f2f5183dfb 2605 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2606 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2607
Kojto 115:87f2f5183dfb 2608 /** @brief macro to get the I2C3 clock source.
Kojto 115:87f2f5183dfb 2609 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2610 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 115:87f2f5183dfb 2611 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 115:87f2f5183dfb 2612 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 115:87f2f5183dfb 2613 */
Kojto 115:87f2f5183dfb 2614 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
Kojto 115:87f2f5183dfb 2615
Kojto 115:87f2f5183dfb 2616 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
Kojto 115:87f2f5183dfb 2617 *
Kojto 115:87f2f5183dfb 2618 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
Kojto 115:87f2f5183dfb 2619 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2620 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
Kojto 115:87f2f5183dfb 2621 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
Kojto 115:87f2f5183dfb 2622 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Kojto 115:87f2f5183dfb 2623 */
Kojto 115:87f2f5183dfb 2624 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2625 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2626
Kojto 115:87f2f5183dfb 2627 /** @brief macro to get the I2C4 clock source.
Kojto 115:87f2f5183dfb 2628 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2629 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
Kojto 115:87f2f5183dfb 2630 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
Kojto 115:87f2f5183dfb 2631 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Kojto 115:87f2f5183dfb 2632 */
Kojto 115:87f2f5183dfb 2633 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
Kojto 115:87f2f5183dfb 2634
Kojto 115:87f2f5183dfb 2635 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 115:87f2f5183dfb 2636 *
Kojto 115:87f2f5183dfb 2637 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
Kojto 115:87f2f5183dfb 2638 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2639 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 115:87f2f5183dfb 2640 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 115:87f2f5183dfb 2641 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 115:87f2f5183dfb 2642 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 115:87f2f5183dfb 2643 */
Kojto 115:87f2f5183dfb 2644 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2645 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2646
Kojto 115:87f2f5183dfb 2647 /** @brief macro to get the USART1 clock source.
Kojto 115:87f2f5183dfb 2648 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2649 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 115:87f2f5183dfb 2650 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 115:87f2f5183dfb 2651 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 115:87f2f5183dfb 2652 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 115:87f2f5183dfb 2653 */
Kojto 115:87f2f5183dfb 2654 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
Kojto 115:87f2f5183dfb 2655
Kojto 115:87f2f5183dfb 2656 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 115:87f2f5183dfb 2657 *
Kojto 115:87f2f5183dfb 2658 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
Kojto 115:87f2f5183dfb 2659 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2660 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 115:87f2f5183dfb 2661 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 115:87f2f5183dfb 2662 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 115:87f2f5183dfb 2663 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 115:87f2f5183dfb 2664 */
Kojto 115:87f2f5183dfb 2665 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2666 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2667
Kojto 115:87f2f5183dfb 2668 /** @brief macro to get the USART2 clock source.
Kojto 115:87f2f5183dfb 2669 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2670 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 115:87f2f5183dfb 2671 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 115:87f2f5183dfb 2672 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 115:87f2f5183dfb 2673 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 115:87f2f5183dfb 2674 */
Kojto 115:87f2f5183dfb 2675 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
Kojto 115:87f2f5183dfb 2676
Kojto 115:87f2f5183dfb 2677 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 115:87f2f5183dfb 2678 *
Kojto 115:87f2f5183dfb 2679 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
Kojto 115:87f2f5183dfb 2680 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2681 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 115:87f2f5183dfb 2682 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 115:87f2f5183dfb 2683 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 115:87f2f5183dfb 2684 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 115:87f2f5183dfb 2685 */
Kojto 115:87f2f5183dfb 2686 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2687 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2688
Kojto 115:87f2f5183dfb 2689 /** @brief macro to get the USART3 clock source.
Kojto 115:87f2f5183dfb 2690 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2691 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 115:87f2f5183dfb 2692 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 115:87f2f5183dfb 2693 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 115:87f2f5183dfb 2694 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 115:87f2f5183dfb 2695 */
Kojto 115:87f2f5183dfb 2696 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
Kojto 115:87f2f5183dfb 2697
Kojto 115:87f2f5183dfb 2698 /** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto 115:87f2f5183dfb 2699 *
Kojto 115:87f2f5183dfb 2700 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
Kojto 115:87f2f5183dfb 2701 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2702 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 115:87f2f5183dfb 2703 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 115:87f2f5183dfb 2704 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 115:87f2f5183dfb 2705 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 115:87f2f5183dfb 2706 */
Kojto 115:87f2f5183dfb 2707 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2708 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2709
Kojto 115:87f2f5183dfb 2710 /** @brief macro to get the UART4 clock source.
Kojto 115:87f2f5183dfb 2711 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2712 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 115:87f2f5183dfb 2713 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 115:87f2f5183dfb 2714 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 115:87f2f5183dfb 2715 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 115:87f2f5183dfb 2716 */
Kojto 115:87f2f5183dfb 2717 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
Kojto 115:87f2f5183dfb 2718
Kojto 115:87f2f5183dfb 2719 /** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto 115:87f2f5183dfb 2720 *
Kojto 115:87f2f5183dfb 2721 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
Kojto 115:87f2f5183dfb 2722 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2723 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 115:87f2f5183dfb 2724 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 115:87f2f5183dfb 2725 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 115:87f2f5183dfb 2726 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 115:87f2f5183dfb 2727 */
Kojto 115:87f2f5183dfb 2728 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2729 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2730
Kojto 115:87f2f5183dfb 2731 /** @brief macro to get the UART5 clock source.
Kojto 115:87f2f5183dfb 2732 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2733 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 115:87f2f5183dfb 2734 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 115:87f2f5183dfb 2735 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 115:87f2f5183dfb 2736 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 115:87f2f5183dfb 2737 */
Kojto 115:87f2f5183dfb 2738 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
Kojto 115:87f2f5183dfb 2739
Kojto 115:87f2f5183dfb 2740 /** @brief Macro to configure the USART6 clock (USART6CLK).
Kojto 115:87f2f5183dfb 2741 *
Kojto 115:87f2f5183dfb 2742 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
Kojto 115:87f2f5183dfb 2743 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2744 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
Kojto 115:87f2f5183dfb 2745 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
Kojto 115:87f2f5183dfb 2746 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
Kojto 115:87f2f5183dfb 2747 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Kojto 115:87f2f5183dfb 2748 */
Kojto 115:87f2f5183dfb 2749 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2750 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2751
Kojto 115:87f2f5183dfb 2752 /** @brief macro to get the USART6 clock source.
Kojto 115:87f2f5183dfb 2753 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2754 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
Kojto 115:87f2f5183dfb 2755 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
Kojto 115:87f2f5183dfb 2756 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
Kojto 115:87f2f5183dfb 2757 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Kojto 115:87f2f5183dfb 2758 */
Kojto 115:87f2f5183dfb 2759 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
Kojto 115:87f2f5183dfb 2760
Kojto 115:87f2f5183dfb 2761 /** @brief Macro to configure the UART7 clock (UART7CLK).
Kojto 115:87f2f5183dfb 2762 *
Kojto 115:87f2f5183dfb 2763 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
Kojto 115:87f2f5183dfb 2764 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2765 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
Kojto 115:87f2f5183dfb 2766 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
Kojto 115:87f2f5183dfb 2767 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
Kojto 115:87f2f5183dfb 2768 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Kojto 115:87f2f5183dfb 2769 */
Kojto 115:87f2f5183dfb 2770 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2771 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2772
Kojto 115:87f2f5183dfb 2773 /** @brief macro to get the UART7 clock source.
Kojto 115:87f2f5183dfb 2774 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2775 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
Kojto 115:87f2f5183dfb 2776 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
Kojto 115:87f2f5183dfb 2777 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
Kojto 115:87f2f5183dfb 2778 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Kojto 115:87f2f5183dfb 2779 */
Kojto 115:87f2f5183dfb 2780 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
Kojto 115:87f2f5183dfb 2781
Kojto 115:87f2f5183dfb 2782 /** @brief Macro to configure the UART8 clock (UART8CLK).
Kojto 115:87f2f5183dfb 2783 *
Kojto 115:87f2f5183dfb 2784 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
Kojto 115:87f2f5183dfb 2785 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2786 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
Kojto 115:87f2f5183dfb 2787 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
Kojto 115:87f2f5183dfb 2788 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
Kojto 115:87f2f5183dfb 2789 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Kojto 115:87f2f5183dfb 2790 */
Kojto 115:87f2f5183dfb 2791 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2792 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2793
Kojto 115:87f2f5183dfb 2794 /** @brief macro to get the UART8 clock source.
Kojto 115:87f2f5183dfb 2795 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2796 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
Kojto 115:87f2f5183dfb 2797 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
Kojto 115:87f2f5183dfb 2798 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
Kojto 115:87f2f5183dfb 2799 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Kojto 115:87f2f5183dfb 2800 */
Kojto 115:87f2f5183dfb 2801 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
Kojto 115:87f2f5183dfb 2802
Kojto 115:87f2f5183dfb 2803 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
Kojto 115:87f2f5183dfb 2804 *
Kojto 115:87f2f5183dfb 2805 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
Kojto 115:87f2f5183dfb 2806 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2807 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2808 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2809 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2810 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2811 */
Kojto 115:87f2f5183dfb 2812 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2813 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2814
Kojto 115:87f2f5183dfb 2815 /** @brief macro to get the LPTIM1 clock source.
Kojto 115:87f2f5183dfb 2816 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2817 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2818 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2819 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2820 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto 115:87f2f5183dfb 2821 */
Kojto 115:87f2f5183dfb 2822 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
Kojto 115:87f2f5183dfb 2823
Kojto 115:87f2f5183dfb 2824 /** @brief Macro to configure the CEC clock (CECCLK).
Kojto 115:87f2f5183dfb 2825 *
Kojto 115:87f2f5183dfb 2826 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
Kojto 115:87f2f5183dfb 2827 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2828 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 116:c0f6e94411f5 2829 * @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
Kojto 115:87f2f5183dfb 2830 */
Kojto 115:87f2f5183dfb 2831 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2832 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2833
Kojto 115:87f2f5183dfb 2834 /** @brief macro to get the CEC clock source.
Kojto 115:87f2f5183dfb 2835 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2836 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 115:87f2f5183dfb 2837 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 115:87f2f5183dfb 2838 */
Kojto 115:87f2f5183dfb 2839 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
Kojto 115:87f2f5183dfb 2840
Kojto 115:87f2f5183dfb 2841 /** @brief Macro to configure the CLK48 source (CLK48CLK).
Kojto 115:87f2f5183dfb 2842 *
Kojto 115:87f2f5183dfb 2843 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
Kojto 115:87f2f5183dfb 2844 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2845 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
Kojto 116:c0f6e94411f5 2846 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
Kojto 115:87f2f5183dfb 2847 */
Kojto 115:87f2f5183dfb 2848 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
Kojto 115:87f2f5183dfb 2849 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
Kojto 115:87f2f5183dfb 2850
Kojto 115:87f2f5183dfb 2851 /** @brief macro to get the CLK48 source.
Kojto 115:87f2f5183dfb 2852 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2853 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
Kojto 116:c0f6e94411f5 2854 * @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP used as CLK48 source
Kojto 115:87f2f5183dfb 2855 */
Kojto 115:87f2f5183dfb 2856 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
Kojto 115:87f2f5183dfb 2857
Kojto 115:87f2f5183dfb 2858 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
Kojto 115:87f2f5183dfb 2859 *
Kojto 115:87f2f5183dfb 2860 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
Kojto 115:87f2f5183dfb 2861 * This parameter can be one of the following values:
Kojto 115:87f2f5183dfb 2862 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
Kojto 115:87f2f5183dfb 2863 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
Kojto 115:87f2f5183dfb 2864 */
Kojto 115:87f2f5183dfb 2865 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
Kojto 115:87f2f5183dfb 2866 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Kojto 115:87f2f5183dfb 2867
Kojto 115:87f2f5183dfb 2868 /** @brief macro to get the SDMMC1 clock source.
Kojto 115:87f2f5183dfb 2869 * @retval The clock source can be one of the following values:
Kojto 115:87f2f5183dfb 2870 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
Kojto 115:87f2f5183dfb 2871 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
Kojto 115:87f2f5183dfb 2872 */
Kojto 115:87f2f5183dfb 2873 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
Kojto 115:87f2f5183dfb 2874
Kojto 122:f9eeca106725 2875 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2876 /** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
Kojto 122:f9eeca106725 2877 * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
Kojto 122:f9eeca106725 2878 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2879 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
Kojto 122:f9eeca106725 2880 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
Kojto 122:f9eeca106725 2881 */
Kojto 122:f9eeca106725 2882 #define __HAL_RCC_SDMMC2_CONFIG(__SDMMC2_CLKSOURCE__) \
Kojto 122:f9eeca106725 2883 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL, (uint32_t)(__SDMMC2_CLKSOURCE__))
Kojto 122:f9eeca106725 2884
Kojto 122:f9eeca106725 2885 /** @brief macro to get the SDMMC2 clock source.
Kojto 122:f9eeca106725 2886 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 2887 * @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
Kojto 122:f9eeca106725 2888 * @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
Kojto 122:f9eeca106725 2889 */
Kojto 122:f9eeca106725 2890 #define __HAL_RCC_GET_SDMMC2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC2SEL)))
Kojto 122:f9eeca106725 2891
Kojto 122:f9eeca106725 2892 /** @brief Macro to configure the DFSDM1 clock
Kojto 122:f9eeca106725 2893 * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
Kojto 122:f9eeca106725 2894 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2895 * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM clock
Kojto 122:f9eeca106725 2896 * @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
Kojto 122:f9eeca106725 2897 */
Kojto 122:f9eeca106725 2898 #define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1_CLKSOURCE__) \
Kojto 122:f9eeca106725 2899 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, (uint32_t)(__DFSDM1_CLKSOURCE__))
Kojto 122:f9eeca106725 2900
Kojto 122:f9eeca106725 2901 /** @brief Macro to get the DFSDM1 clock source.
Kojto 122:f9eeca106725 2902 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 2903 * @arg RCC_DFSDM1CLKSOURCE_PCLK: PCLK2 Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 2904 * @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System Clock selected as DFSDM1 clock
Kojto 122:f9eeca106725 2905 */
Kojto 122:f9eeca106725 2906 #define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
Kojto 122:f9eeca106725 2907
Kojto 122:f9eeca106725 2908 /** @brief Macro to configure the DFSDM1 Audio clock
Kojto 122:f9eeca106725 2909 * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
Kojto 122:f9eeca106725 2910 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2911 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
Kojto 122:f9eeca106725 2912 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
Kojto 122:f9eeca106725 2913 */
Kojto 122:f9eeca106725 2914 #define __HAL_RCC_DFSDM1AUDIO_CONFIG(__DFSDM1AUDIO_CLKSOURCE__) \
Kojto 122:f9eeca106725 2915 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, (uint32_t)(__DFSDM1AUDIO_CLKSOURCE__))
Kojto 122:f9eeca106725 2916
Kojto 122:f9eeca106725 2917 /** @brief Macro to get the DFSDM1 Audio clock source.
Kojto 122:f9eeca106725 2918 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 2919 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
Kojto 122:f9eeca106725 2920 * @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
Kojto 122:f9eeca106725 2921 */
Kojto 122:f9eeca106725 2922 #define __HAL_RCC_GET_DFSDM1AUDIO_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL)))
Kojto 122:f9eeca106725 2923 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 2924
Kojto 122:f9eeca106725 2925 #if defined (STM32F769xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 2926 /** @brief Macro to configure the DSI clock.
Kojto 122:f9eeca106725 2927 * @param __DSI_CLKSOURCE__: specifies the DSI clock source.
Kojto 122:f9eeca106725 2928 * This parameter can be one of the following values:
Kojto 122:f9eeca106725 2929 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto 122:f9eeca106725 2930 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto 122:f9eeca106725 2931 */
Kojto 122:f9eeca106725 2932 #define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, (uint32_t)(__DSI_CLKSOURCE__)))
Kojto 122:f9eeca106725 2933
Kojto 122:f9eeca106725 2934 /** @brief Macro to Get the DSI clock.
Kojto 122:f9eeca106725 2935 * @retval The clock source can be one of the following values:
Kojto 122:f9eeca106725 2936 * @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
Kojto 122:f9eeca106725 2937 * @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
Kojto 122:f9eeca106725 2938 */
Kojto 122:f9eeca106725 2939 #define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL))
Kojto 122:f9eeca106725 2940 #endif /* STM32F769xx || STM32F779xx */
Kojto 115:87f2f5183dfb 2941 /**
Kojto 115:87f2f5183dfb 2942 * @}
Kojto 115:87f2f5183dfb 2943 */
Kojto 116:c0f6e94411f5 2944
Kojto 115:87f2f5183dfb 2945 /* Exported functions --------------------------------------------------------*/
Kojto 115:87f2f5183dfb 2946 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 115:87f2f5183dfb 2947 * @{
Kojto 115:87f2f5183dfb 2948 */
Kojto 115:87f2f5183dfb 2949 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 115:87f2f5183dfb 2950 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 115:87f2f5183dfb 2951 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 115:87f2f5183dfb 2952
Kojto 115:87f2f5183dfb 2953 /**
Kojto 115:87f2f5183dfb 2954 * @}
Kojto 115:87f2f5183dfb 2955 */
Kojto 115:87f2f5183dfb 2956 /* Private macros ------------------------------------------------------------*/
Kojto 115:87f2f5183dfb 2957 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto 115:87f2f5183dfb 2958 * @{
Kojto 115:87f2f5183dfb 2959 */
Kojto 115:87f2f5183dfb 2960 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 115:87f2f5183dfb 2961 * @{
Kojto 115:87f2f5183dfb 2962 */
Kojto 115:87f2f5183dfb 2963 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 115:87f2f5183dfb 2964 #define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto 116:c0f6e94411f5 2965 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
Kojto 115:87f2f5183dfb 2966 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
Kojto 115:87f2f5183dfb 2967 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
Kojto 115:87f2f5183dfb 2968 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 115:87f2f5183dfb 2969 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 115:87f2f5183dfb 2970 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 115:87f2f5183dfb 2971 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 115:87f2f5183dfb 2972 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 115:87f2f5183dfb 2973 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
Kojto 115:87f2f5183dfb 2974 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
Kojto 115:87f2f5183dfb 2975 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
Kojto 115:87f2f5183dfb 2976 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 115:87f2f5183dfb 2977 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 115:87f2f5183dfb 2978 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 115:87f2f5183dfb 2979 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
Kojto 115:87f2f5183dfb 2980 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 115:87f2f5183dfb 2981 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 115:87f2f5183dfb 2982 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 115:87f2f5183dfb 2983 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
Kojto 115:87f2f5183dfb 2984 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
Kojto 116:c0f6e94411f5 2985 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
Kojto 116:c0f6e94411f5 2986 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
Kojto 115:87f2f5183dfb 2987 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto 115:87f2f5183dfb 2988 #elif defined(STM32F745xx)
Kojto 115:87f2f5183dfb 2989 #define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto 116:c0f6e94411f5 2990 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
Kojto 115:87f2f5183dfb 2991 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
Kojto 115:87f2f5183dfb 2992 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 115:87f2f5183dfb 2993 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 115:87f2f5183dfb 2994 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 115:87f2f5183dfb 2995 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 115:87f2f5183dfb 2996 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 115:87f2f5183dfb 2997 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
Kojto 115:87f2f5183dfb 2998 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
Kojto 115:87f2f5183dfb 2999 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
Kojto 115:87f2f5183dfb 3000 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 115:87f2f5183dfb 3001 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 115:87f2f5183dfb 3002 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 115:87f2f5183dfb 3003 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
Kojto 115:87f2f5183dfb 3004 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 115:87f2f5183dfb 3005 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 115:87f2f5183dfb 3006 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 115:87f2f5183dfb 3007 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
Kojto 115:87f2f5183dfb 3008 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
Kojto 116:c0f6e94411f5 3009 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
Kojto 116:c0f6e94411f5 3010 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
Kojto 115:87f2f5183dfb 3011 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 3012 #elif defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 3013 #define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto 122:f9eeca106725 3014 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
Kojto 122:f9eeca106725 3015 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
Kojto 122:f9eeca106725 3016 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
Kojto 122:f9eeca106725 3017 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 3018 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 3019 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 3020 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 122:f9eeca106725 3021 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 122:f9eeca106725 3022 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
Kojto 122:f9eeca106725 3023 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
Kojto 122:f9eeca106725 3024 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
Kojto 122:f9eeca106725 3025 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 3026 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 3027 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 3028 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
Kojto 122:f9eeca106725 3029 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 3030 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 3031 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 122:f9eeca106725 3032 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
Kojto 122:f9eeca106725 3033 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
Kojto 122:f9eeca106725 3034 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
Kojto 122:f9eeca106725 3035 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
Kojto 122:f9eeca106725 3036 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
Kojto 122:f9eeca106725 3037 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
Kojto 122:f9eeca106725 3038 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
Kojto 122:f9eeca106725 3039 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto 122:f9eeca106725 3040 #elif defined (STM32F765xx)
Kojto 122:f9eeca106725 3041 #define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto 122:f9eeca106725 3042 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
Kojto 122:f9eeca106725 3043 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
Kojto 122:f9eeca106725 3044 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 122:f9eeca106725 3045 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 122:f9eeca106725 3046 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 122:f9eeca106725 3047 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 122:f9eeca106725 3048 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 122:f9eeca106725 3049 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
Kojto 122:f9eeca106725 3050 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
Kojto 122:f9eeca106725 3051 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
Kojto 122:f9eeca106725 3052 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 122:f9eeca106725 3053 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 122:f9eeca106725 3054 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 122:f9eeca106725 3055 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
Kojto 122:f9eeca106725 3056 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 122:f9eeca106725 3057 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 122:f9eeca106725 3058 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 122:f9eeca106725 3059 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
Kojto 122:f9eeca106725 3060 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
Kojto 122:f9eeca106725 3061 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
Kojto 122:f9eeca106725 3062 (((SELECTION) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2) || \
Kojto 122:f9eeca106725 3063 (((SELECTION) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1) || \
Kojto 122:f9eeca106725 3064 (((SELECTION) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO) || \
Kojto 122:f9eeca106725 3065 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
Kojto 122:f9eeca106725 3066 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto 116:c0f6e94411f5 3067 #endif /* STM32F746xx || STM32F756xx */
Kojto 116:c0f6e94411f5 3068 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
Kojto 116:c0f6e94411f5 3069 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
Kojto 116:c0f6e94411f5 3070 ((VALUE) == RCC_PLLI2SP_DIV4) ||\
Kojto 116:c0f6e94411f5 3071 ((VALUE) == RCC_PLLI2SP_DIV6) ||\
Kojto 116:c0f6e94411f5 3072 ((VALUE) == RCC_PLLI2SP_DIV8))
Kojto 115:87f2f5183dfb 3073 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 115:87f2f5183dfb 3074 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 115:87f2f5183dfb 3075
Kojto 116:c0f6e94411f5 3076 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((50 <= (VALUE)) && ((VALUE) <= 432))
Kojto 116:c0f6e94411f5 3077 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
Kojto 116:c0f6e94411f5 3078 ((VALUE) == RCC_PLLSAIP_DIV4) ||\
Kojto 116:c0f6e94411f5 3079 ((VALUE) == RCC_PLLSAIP_DIV6) ||\
Kojto 116:c0f6e94411f5 3080 ((VALUE) == RCC_PLLSAIP_DIV8))
Kojto 115:87f2f5183dfb 3081 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 115:87f2f5183dfb 3082 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 115:87f2f5183dfb 3083
Kojto 115:87f2f5183dfb 3084 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 115:87f2f5183dfb 3085
Kojto 115:87f2f5183dfb 3086 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 115:87f2f5183dfb 3087
Kojto 115:87f2f5183dfb 3088 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
Kojto 116:c0f6e94411f5 3089 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
Kojto 116:c0f6e94411f5 3090 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
Kojto 115:87f2f5183dfb 3091 ((VALUE) == RCC_PLLSAIDIVR_16))
Kojto 115:87f2f5183dfb 3092 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
Kojto 116:c0f6e94411f5 3093 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 115:87f2f5183dfb 3094
Kojto 116:c0f6e94411f5 3095 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
Kojto 116:c0f6e94411f5 3096 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
Kojto 115:87f2f5183dfb 3097
Kojto 115:87f2f5183dfb 3098 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
Kojto 115:87f2f5183dfb 3099 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto 115:87f2f5183dfb 3100 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3101 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 115:87f2f5183dfb 3102 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3103 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3104 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3105
Kojto 115:87f2f5183dfb 3106 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3107 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3108 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3109 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3110 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3111 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3112 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3113 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3114 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3115 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3116
Kojto 115:87f2f5183dfb 3117 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3118 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3119 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3120 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3121 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3122
Kojto 115:87f2f5183dfb 3123 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3124 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3125 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3126 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3127 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3128
Kojto 115:87f2f5183dfb 3129 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3130 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
Kojto 115:87f2f5183dfb 3131 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3132 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3133 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3134
Kojto 115:87f2f5183dfb 3135 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3136 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3137 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3138 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3139 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3140
Kojto 115:87f2f5183dfb 3141 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3142 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3143 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
Kojto 115:87f2f5183dfb 3144 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
Kojto 115:87f2f5183dfb 3145 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3146 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3147 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3148 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
Kojto 115:87f2f5183dfb 3149 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3150 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3151 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3152 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
Kojto 115:87f2f5183dfb 3153 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3154
Kojto 115:87f2f5183dfb 3155 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3156 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3157 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
Kojto 115:87f2f5183dfb 3158 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3159 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3160 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
Kojto 115:87f2f5183dfb 3161 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
Kojto 115:87f2f5183dfb 3162 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
Kojto 115:87f2f5183dfb 3163 #define IS_RCC_LPTIM1CLK(SOURCE) \
Kojto 115:87f2f5183dfb 3164 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
Kojto 115:87f2f5183dfb 3165 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
Kojto 115:87f2f5183dfb 3166 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
Kojto 115:87f2f5183dfb 3167 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto 115:87f2f5183dfb 3168 #define IS_RCC_CLK48SOURCE(SOURCE) \
Kojto 115:87f2f5183dfb 3169 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
Kojto 115:87f2f5183dfb 3170 ((SOURCE) == RCC_CLK48SOURCE_PLL))
Kojto 115:87f2f5183dfb 3171 #define IS_RCC_TIMPRES(VALUE) \
Kojto 115:87f2f5183dfb 3172 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
Kojto 115:87f2f5183dfb 3173 ((VALUE) == RCC_TIMPRES_ACTIVATED))
Kojto 116:c0f6e94411f5 3174
Kojto 116:c0f6e94411f5 3175 #if defined (STM32F745xx) || defined (STM32F746xx) || defined (STM32F756xx)
Kojto 116:c0f6e94411f5 3176 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
Kojto 116:c0f6e94411f5 3177 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
Kojto 116:c0f6e94411f5 3178 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
Kojto 116:c0f6e94411f5 3179 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
Kojto 116:c0f6e94411f5 3180 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
Kojto 116:c0f6e94411f5 3181 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
Kojto 116:c0f6e94411f5 3182 #endif /* STM32F745xx || STM32F746xx || STM32F756xx */
Kojto 116:c0f6e94411f5 3183
Kojto 122:f9eeca106725 3184 #if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 3185 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 122:f9eeca106725 3186
Kojto 122:f9eeca106725 3187 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
Kojto 122:f9eeca106725 3188 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
Kojto 122:f9eeca106725 3189 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN) || \
Kojto 122:f9eeca106725 3190 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLSRC))
Kojto 122:f9eeca106725 3191
Kojto 122:f9eeca106725 3192 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
Kojto 122:f9eeca106725 3193 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
Kojto 122:f9eeca106725 3194 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN) || \
Kojto 122:f9eeca106725 3195 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto 122:f9eeca106725 3196
Kojto 122:f9eeca106725 3197 #define IS_RCC_SDMMC2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC2CLKSOURCE_SYSCLK) || \
Kojto 122:f9eeca106725 3198 ((SOURCE) == RCC_SDMMC2CLKSOURCE_CLK48))
Kojto 122:f9eeca106725 3199
Kojto 122:f9eeca106725 3200 #define IS_RCC_DFSDM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1CLKSOURCE_PCLK) || \
Kojto 122:f9eeca106725 3201 ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYSCLK))
Kojto 122:f9eeca106725 3202
Kojto 122:f9eeca106725 3203 #define IS_RCC_DFSDM1AUDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI1) || \
Kojto 122:f9eeca106725 3204 ((SOURCE) == RCC_DFSDM1AUDIOCLKSOURCE_SAI2))
Kojto 122:f9eeca106725 3205 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 3206
Kojto 122:f9eeca106725 3207 #if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
Kojto 122:f9eeca106725 3208 #define IS_RCC_DSIBYTELANECLKSOURCE(SOURCE) (((SOURCE) == RCC_DSICLKSOURCE_PLLR) ||\
Kojto 122:f9eeca106725 3209 ((SOURCE) == RCC_DSICLKSOURCE_DSIPHY))
Kojto 122:f9eeca106725 3210 #endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
Kojto 122:f9eeca106725 3211
Kojto 115:87f2f5183dfb 3212 /**
Kojto 115:87f2f5183dfb 3213 * @}
Kojto 115:87f2f5183dfb 3214 */
Kojto 115:87f2f5183dfb 3215
Kojto 115:87f2f5183dfb 3216 /**
Kojto 115:87f2f5183dfb 3217 * @}
Kojto 115:87f2f5183dfb 3218 */
Kojto 115:87f2f5183dfb 3219
Kojto 115:87f2f5183dfb 3220 /**
Kojto 115:87f2f5183dfb 3221 * @}
Kojto 115:87f2f5183dfb 3222 */
Kojto 115:87f2f5183dfb 3223
Kojto 115:87f2f5183dfb 3224 /**
Kojto 115:87f2f5183dfb 3225 * @}
Kojto 115:87f2f5183dfb 3226 */
Kojto 115:87f2f5183dfb 3227 #ifdef __cplusplus
Kojto 115:87f2f5183dfb 3228 }
Kojto 115:87f2f5183dfb 3229 #endif
Kojto 115:87f2f5183dfb 3230
Kojto 115:87f2f5183dfb 3231 #endif /* __STM32F7xx_HAL_RCC_EX_H */
Kojto 115:87f2f5183dfb 3232
Kojto 115:87f2f5183dfb 3233 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/