Diff: TARGET_NUCLEO_F103RB/stm32f1xx_hal_dma.h

Revision:

120:7c328cabac7e

Parent:

96:487b796308b0

--- a/TARGET_NUCLEO_F103RB/stm32f1xx_hal_dma.h	Wed Apr 27 12:10:56 2016 -0500
+++ b/TARGET_NUCLEO_F103RB/stm32f1xx_hal_dma.h	Tue May 10 12:23:43 2016 -0500
@@ -2,13 +2,13 @@
   ******************************************************************************
   * @file    stm32f1xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    15-December-2014
+  * @version V1.0.4
+  * @date    29-April-2016
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -54,13 +54,14 @@
   * @{
   */ 
 
-/* Exported types ------------------------------------------------------------*/ 
+/* Exported types ------------------------------------------------------------*/
+
 /** @defgroup DMA_Exported_Types DMA Exported Types
   * @{
   */
-
+   
 /** 
-  * @brief  DMA Configuration Structure definition  
+  * @brief  DMA Configuration Structure definition
   */
 typedef struct
 {
@@ -87,11 +88,10 @@
 
   uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
                                             This parameter can be a value of @ref DMA_Priority_level */
-
 } DMA_InitTypeDef;
 
 /** 
-  * @brief DMA Configuration enumeration values definition 
+  * @brief DMA Configuration enumeration values definition
   */  
 typedef enum 
 {
@@ -105,37 +105,35 @@
   */
 typedef enum
 {
-  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */  
-  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use   */
+  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */
+  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA initialized and ready for use   */
   HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
-  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */     
-  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */  
+  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */
+  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */
   HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
-                                                                        
 }HAL_DMA_StateTypeDef;
 
 /** 
-  * @brief  HAL DMA Error Code structure definition  
-  */ 
+  * @brief  HAL DMA Error Code structure definition
+  */
 typedef enum
 {
   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
   HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
 
-}HAL_DMA_LevelCompleteTypeDef;
-                                                                        
 /** 
-  * @brief  DMA handle Structure definition  
-  */ 
+  * @brief  DMA handle Structure definition
+  */
 typedef struct __DMA_HandleTypeDef
-{  
-  DMA_Channel_TypeDef   *Instance;                                                    /*!< Register base address                  */
+{
+  DMA_Channel_TypeDef   *Instance;                       /*!< Register base address                  */
   
-  DMA_InitTypeDef       Init;                                                         /*!< DMA communication parameters           */ 
+  DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */ 
   
-  HAL_LockTypeDef       Lock;                                                         /*!< DMA locking object                     */  
+  HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */  
   
-  HAL_DMA_StateTypeDef  State;                                                        /*!< DMA transfer state                     */
+  HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
   
   void                  *Parent;                                                      /*!< Parent object state                    */  
   
@@ -146,18 +144,18 @@
   void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
   
   __IO uint32_t         ErrorCode;                                                    /*!< DMA Error code                         */
-  
 } DMA_HandleTypeDef;    
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
+
 /** @defgroup DMA_Exported_Constants DMA Exported Constants
   * @{
   */
 
-/** @defgroup DMA_Error_Codes DMA Error Codes
+/** @defgroup DMA_Error_Code DMA Error Code
   * @{
   */
  #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00)    /*!< No error             */
@@ -168,38 +166,22 @@
   * @}
   */
 
-
-
 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
   * @{
   */ 
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction     */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)      /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)     /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction     */
 
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
 /**
   * @}
   */
 
-/** @defgroup DMA_Data_buffer_size DMA Data buffer size
-  * @{
-  */ 
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/**
-  * @}
-  */     
-    
 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
   * @{
   */ 
-#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
 /**
   * @}
   */ 
@@ -207,11 +189,8 @@
 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
   * @{
   */ 
-#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)   /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)     /*!< Memory increment mode Disable */
 /**
   * @}
   */
@@ -219,28 +198,19 @@
 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
   * @{
   */ 
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
-#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Peripheral data alignment: Byte     */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)   /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)   /*!< Peripheral data alignment: Word     */
 /**
   * @}
   */ 
 
-
 /** @defgroup DMA_Memory_data_size DMA Memory data size
   * @{ 
   */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
-#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)        /*!< Memory data alignment: Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)   /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)   /*!< Memory data alignment: Word     */
 /**
   * @}
   */
@@ -248,11 +218,8 @@
 /** @defgroup DMA_mode DMA mode
   * @{
   */ 
-#define DMA_NORMAL         ((uint32_t)0x00000000)      /*!< Normal Mode                  */
-#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR)) 
+#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
+#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
 /**
   * @}
   */
@@ -260,15 +227,10 @@
 /** @defgroup DMA_Priority_level DMA Priority level
   * @{
   */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
-#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
-#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
-#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)     /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)   /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)   /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)     /*!< Priority level : Very_High */
 /**
   * @}
   */ 
@@ -277,11 +239,9 @@
 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
   * @{
   */
-
 #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
 #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
 #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
-
 /**
   * @}
   */
@@ -289,7 +249,6 @@
 /** @defgroup DMA_flag_definitions DMA flag definitions
   * @{
   */ 
-
 #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
 #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
 #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
@@ -318,8 +277,6 @@
 #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
 #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
 #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
-
-
 /**
   * @}
   */
@@ -327,8 +284,9 @@
 /**
   * @}
   */
+ 
 
-/* Exported macros -----------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
 /** @defgroup DMA_Exported_Macros DMA Exported Macros
   * @{
   */
@@ -371,7 +329,7 @@
 /**
   * @brief  Disables the specified DMA Channel interrupts.
   * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
   *          This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -381,7 +339,7 @@
 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
 
 /**
-  * @brief  Checks whether the specified DMA Channel interrupt has occurred or not.
+  * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
   * @param  __HANDLE__: DMA handle
   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
   *          This parameter can be one of the following values:
@@ -393,6 +351,14 @@
 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /**
+  * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
+  * @param  __HANDLE__: DMA handle
+  *   
+  * @retval The number of remaining data units in the current DMA Channel transfer.
+  */
+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR)
+
+/**
   * @}
   */
 
@@ -422,7 +388,7 @@
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
@@ -441,6 +407,62 @@
   * @}
   */
 
+/* Private Constants -------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @brief    DMA private defines and constants 
+  * @{
+  */
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @brief    DMA private macros 
+  * @{
+  */
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR)) 
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
+
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @brief    DMA private  functions 
+  * @{
+  */
+/**
+  * @}
+  */
+
 /**
   * @}
   */